Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 77
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.74 88.74 100.00 100.00 91.67 91.67 100.00 100.00 82.14 82.14 95.83 95.83 62.79 62.79 /workspace/coverage/default/4.prim_async_alert.800810996
91.87 3.13 100.00 0.00 91.67 0.00 100.00 0.00 89.29 7.14 95.83 0.00 74.42 11.63 /workspace/coverage/sync_alert/18.prim_sync_alert.1273504293
93.72 1.86 100.00 0.00 95.83 4.17 100.00 0.00 89.29 0.00 95.83 0.00 81.40 6.98 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2511341564
94.50 0.78 100.00 0.00 95.83 0.00 100.00 0.00 89.29 0.00 95.83 0.00 86.05 4.65 /workspace/coverage/default/10.prim_async_alert.2195264998
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3961489441
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/1.prim_sync_alert.3266433018

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3209964021
/workspace/coverage/default/1.prim_async_alert.1794703141
/workspace/coverage/default/11.prim_async_alert.3363069457
/workspace/coverage/default/12.prim_async_alert.3972110810
/workspace/coverage/default/13.prim_async_alert.3772133215
/workspace/coverage/default/14.prim_async_alert.664118455
/workspace/coverage/default/15.prim_async_alert.3940383229
/workspace/coverage/default/17.prim_async_alert.893111990
/workspace/coverage/default/18.prim_async_alert.1385839990
/workspace/coverage/default/2.prim_async_alert.488099868
/workspace/coverage/default/3.prim_async_alert.772795441
/workspace/coverage/default/5.prim_async_alert.2827210156
/workspace/coverage/default/6.prim_async_alert.3030202155
/workspace/coverage/default/7.prim_async_alert.1983951916
/workspace/coverage/default/8.prim_async_alert.3748537578
/workspace/coverage/default/9.prim_async_alert.1100125565
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3993107246
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1915583391
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2148508193
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1122617610
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.43317141
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1754523425
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1402575165
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3348869665
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3975342613
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2233206376
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2955060744
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.458978957
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1223573683
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1517286335
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.203297781
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4283701090
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3931085158
/workspace/coverage/sync_alert/0.prim_sync_alert.3862749511
/workspace/coverage/sync_alert/10.prim_sync_alert.1242569327
/workspace/coverage/sync_alert/11.prim_sync_alert.2839890160
/workspace/coverage/sync_alert/12.prim_sync_alert.2865890758
/workspace/coverage/sync_alert/13.prim_sync_alert.3583651752
/workspace/coverage/sync_alert/14.prim_sync_alert.704562038
/workspace/coverage/sync_alert/15.prim_sync_alert.1188925205
/workspace/coverage/sync_alert/16.prim_sync_alert.3439510273
/workspace/coverage/sync_alert/17.prim_sync_alert.4096149888
/workspace/coverage/sync_alert/19.prim_sync_alert.1593109368
/workspace/coverage/sync_alert/2.prim_sync_alert.3333960941
/workspace/coverage/sync_alert/3.prim_sync_alert.1266334169
/workspace/coverage/sync_alert/4.prim_sync_alert.5671196
/workspace/coverage/sync_alert/5.prim_sync_alert.1434916918
/workspace/coverage/sync_alert/6.prim_sync_alert.2310606334
/workspace/coverage/sync_alert/7.prim_sync_alert.2680460450
/workspace/coverage/sync_alert/8.prim_sync_alert.4209234159
/workspace/coverage/sync_alert/9.prim_sync_alert.129871238
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3143312172
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1665914362
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3412343243
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3926754311
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2010051183
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.248344860
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3441358228
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2145289617
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3431897083
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2859052505
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3782333108
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1219047356
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4157575508
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2288606756
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3286209622
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.433476266
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2122222046
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.402776199
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1810819506
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1686257682



Total test records in report: 77
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/12.prim_async_alert.3972110810 Dec 31 12:45:33 PM PST 23 Dec 31 12:45:34 PM PST 23 10930227 ps
T2 /workspace/coverage/default/2.prim_async_alert.488099868 Dec 31 12:45:30 PM PST 23 Dec 31 12:45:32 PM PST 23 11588547 ps
T3 /workspace/coverage/default/8.prim_async_alert.3748537578 Dec 31 12:45:16 PM PST 23 Dec 31 12:45:21 PM PST 23 11093812 ps
T10 /workspace/coverage/default/15.prim_async_alert.3940383229 Dec 31 12:45:10 PM PST 23 Dec 31 12:45:20 PM PST 23 11496742 ps
T12 /workspace/coverage/default/14.prim_async_alert.664118455 Dec 31 12:45:25 PM PST 23 Dec 31 12:45:26 PM PST 23 11543292 ps
T7 /workspace/coverage/default/17.prim_async_alert.893111990 Dec 31 12:45:24 PM PST 23 Dec 31 12:45:26 PM PST 23 11882153 ps
T16 /workspace/coverage/default/10.prim_async_alert.2195264998 Dec 31 12:45:38 PM PST 23 Dec 31 12:45:39 PM PST 23 10799249 ps
T8 /workspace/coverage/default/5.prim_async_alert.2827210156 Dec 31 12:45:29 PM PST 23 Dec 31 12:45:31 PM PST 23 10597188 ps
T13 /workspace/coverage/default/4.prim_async_alert.800810996 Dec 31 12:45:12 PM PST 23 Dec 31 12:45:14 PM PST 23 12260941 ps
T18 /workspace/coverage/default/6.prim_async_alert.3030202155 Dec 31 12:45:25 PM PST 23 Dec 31 12:45:26 PM PST 23 10327861 ps
T9 /workspace/coverage/default/9.prim_async_alert.1100125565 Dec 31 12:45:10 PM PST 23 Dec 31 12:45:12 PM PST 23 11632986 ps
T44 /workspace/coverage/default/13.prim_async_alert.3772133215 Dec 31 12:45:17 PM PST 23 Dec 31 12:45:21 PM PST 23 11640849 ps
T19 /workspace/coverage/default/7.prim_async_alert.1983951916 Dec 31 12:45:22 PM PST 23 Dec 31 12:45:25 PM PST 23 11107918 ps
T20 /workspace/coverage/default/18.prim_async_alert.1385839990 Dec 31 12:45:18 PM PST 23 Dec 31 12:45:21 PM PST 23 11135145 ps
T15 /workspace/coverage/default/1.prim_async_alert.1794703141 Dec 31 12:45:28 PM PST 23 Dec 31 12:45:29 PM PST 23 11346658 ps
T17 /workspace/coverage/default/11.prim_async_alert.3363069457 Dec 31 12:45:08 PM PST 23 Dec 31 12:45:10 PM PST 23 10930118 ps
T21 /workspace/coverage/default/0.prim_async_alert.3209964021 Dec 31 12:45:27 PM PST 23 Dec 31 12:45:28 PM PST 23 10938047 ps
T14 /workspace/coverage/default/3.prim_async_alert.772795441 Dec 31 12:45:32 PM PST 23 Dec 31 12:45:43 PM PST 23 12062475 ps
T36 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.43317141 Dec 31 12:44:53 PM PST 23 Dec 31 12:44:57 PM PST 23 27892219 ps
T37 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4283701090 Dec 31 12:44:29 PM PST 23 Dec 31 12:44:35 PM PST 23 31014159 ps
T22 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1754523425 Dec 31 12:44:35 PM PST 23 Dec 31 12:44:41 PM PST 23 30035603 ps
T38 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2955060744 Dec 31 12:44:33 PM PST 23 Dec 31 12:44:39 PM PST 23 29810837 ps
T39 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1122617610 Dec 31 12:45:08 PM PST 23 Dec 31 12:45:10 PM PST 23 30724241 ps
T40 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.458978957 Dec 31 12:44:45 PM PST 23 Dec 31 12:44:49 PM PST 23 30604013 ps
T41 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2233206376 Dec 31 12:44:53 PM PST 23 Dec 31 12:44:57 PM PST 23 30166022 ps
T42 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2511341564 Dec 31 12:44:36 PM PST 23 Dec 31 12:44:45 PM PST 23 28579748 ps
T4 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3961489441 Dec 31 12:45:06 PM PST 23 Dec 31 12:45:09 PM PST 23 31562448 ps
T43 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2148508193 Dec 31 12:44:27 PM PST 23 Dec 31 12:44:31 PM PST 23 29943570 ps
T45 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1915583391 Dec 31 12:44:33 PM PST 23 Dec 31 12:44:39 PM PST 23 30267265 ps
T46 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1517286335 Dec 31 12:44:43 PM PST 23 Dec 31 12:44:48 PM PST 23 30997608 ps
T47 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.203297781 Dec 31 12:44:43 PM PST 23 Dec 31 12:44:48 PM PST 23 30187970 ps
T48 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1402575165 Dec 31 12:44:15 PM PST 23 Dec 31 12:44:20 PM PST 23 28502680 ps
T49 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3993107246 Dec 31 12:45:03 PM PST 23 Dec 31 12:45:05 PM PST 23 29723883 ps
T35 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3975342613 Dec 31 12:44:28 PM PST 23 Dec 31 12:44:35 PM PST 23 30280085 ps
T50 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1223573683 Dec 31 12:44:49 PM PST 23 Dec 31 12:44:53 PM PST 23 28761291 ps
T51 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3931085158 Dec 31 12:45:07 PM PST 23 Dec 31 12:45:14 PM PST 23 28955531 ps
T52 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3348869665 Dec 31 12:44:27 PM PST 23 Dec 31 12:44:31 PM PST 23 29460336 ps
T32 /workspace/coverage/sync_alert/5.prim_sync_alert.1434916918 Dec 31 12:49:16 PM PST 23 Dec 31 12:49:18 PM PST 23 9220005 ps
T33 /workspace/coverage/sync_alert/8.prim_sync_alert.4209234159 Dec 31 12:49:14 PM PST 23 Dec 31 12:49:16 PM PST 23 8474956 ps
T23 /workspace/coverage/sync_alert/0.prim_sync_alert.3862749511 Dec 31 12:49:09 PM PST 23 Dec 31 12:49:10 PM PST 23 8171435 ps
T34 /workspace/coverage/sync_alert/6.prim_sync_alert.2310606334 Dec 31 12:49:04 PM PST 23 Dec 31 12:49:08 PM PST 23 8963486 ps
T24 /workspace/coverage/sync_alert/18.prim_sync_alert.1273504293 Dec 31 12:48:43 PM PST 23 Dec 31 12:48:45 PM PST 23 11212271 ps
T25 /workspace/coverage/sync_alert/11.prim_sync_alert.2839890160 Dec 31 12:49:16 PM PST 23 Dec 31 12:49:18 PM PST 23 8379456 ps
T26 /workspace/coverage/sync_alert/12.prim_sync_alert.2865890758 Dec 31 12:49:19 PM PST 23 Dec 31 12:49:21 PM PST 23 9688858 ps
T27 /workspace/coverage/sync_alert/3.prim_sync_alert.1266334169 Dec 31 12:48:57 PM PST 23 Dec 31 12:48:58 PM PST 23 9302627 ps
T28 /workspace/coverage/sync_alert/14.prim_sync_alert.704562038 Dec 31 12:48:55 PM PST 23 Dec 31 12:48:57 PM PST 23 9662113 ps
T29 /workspace/coverage/sync_alert/17.prim_sync_alert.4096149888 Dec 31 12:48:52 PM PST 23 Dec 31 12:48:53 PM PST 23 9250106 ps
T30 /workspace/coverage/sync_alert/16.prim_sync_alert.3439510273 Dec 31 12:49:18 PM PST 23 Dec 31 12:49:20 PM PST 23 9169143 ps
T31 /workspace/coverage/sync_alert/4.prim_sync_alert.5671196 Dec 31 12:49:12 PM PST 23 Dec 31 12:49:14 PM PST 23 8119294 ps
T53 /workspace/coverage/sync_alert/19.prim_sync_alert.1593109368 Dec 31 12:48:20 PM PST 23 Dec 31 12:48:27 PM PST 23 9328710 ps
T54 /workspace/coverage/sync_alert/7.prim_sync_alert.2680460450 Dec 31 12:49:17 PM PST 23 Dec 31 12:49:19 PM PST 23 9060847 ps
T55 /workspace/coverage/sync_alert/9.prim_sync_alert.129871238 Dec 31 12:49:16 PM PST 23 Dec 31 12:49:18 PM PST 23 9908112 ps
T56 /workspace/coverage/sync_alert/13.prim_sync_alert.3583651752 Dec 31 12:49:11 PM PST 23 Dec 31 12:49:12 PM PST 23 8688305 ps
T57 /workspace/coverage/sync_alert/2.prim_sync_alert.3333960941 Dec 31 12:49:06 PM PST 23 Dec 31 12:49:07 PM PST 23 9523685 ps
T58 /workspace/coverage/sync_alert/15.prim_sync_alert.1188925205 Dec 31 12:49:15 PM PST 23 Dec 31 12:49:16 PM PST 23 10076552 ps
T11 /workspace/coverage/sync_alert/1.prim_sync_alert.3266433018 Dec 31 12:48:23 PM PST 23 Dec 31 12:48:28 PM PST 23 8476447 ps
T59 /workspace/coverage/sync_alert/10.prim_sync_alert.1242569327 Dec 31 12:49:18 PM PST 23 Dec 31 12:49:21 PM PST 23 11058218 ps
T60 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4157575508 Dec 31 12:48:57 PM PST 23 Dec 31 12:48:59 PM PST 23 26918833 ps
T5 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2010051183 Dec 31 12:48:06 PM PST 23 Dec 31 12:48:09 PM PST 23 28785456 ps
T61 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2145289617 Dec 31 12:48:18 PM PST 23 Dec 31 12:48:23 PM PST 23 24923174 ps
T62 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1810819506 Dec 31 12:48:43 PM PST 23 Dec 31 12:48:45 PM PST 23 26102771 ps
T63 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.248344860 Dec 31 12:48:34 PM PST 23 Dec 31 12:48:37 PM PST 23 28083848 ps
T64 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1686257682 Dec 31 12:48:15 PM PST 23 Dec 31 12:48:22 PM PST 23 29542696 ps
T65 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.433476266 Dec 31 12:47:57 PM PST 23 Dec 31 12:47:59 PM PST 23 27681230 ps
T66 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1219047356 Dec 31 12:48:52 PM PST 23 Dec 31 12:48:53 PM PST 23 26337984 ps
T67 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3441358228 Dec 31 12:48:41 PM PST 23 Dec 31 12:48:44 PM PST 23 27029289 ps
T68 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1665914362 Dec 31 12:48:52 PM PST 23 Dec 31 12:48:53 PM PST 23 26205425 ps
T69 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3412343243 Dec 31 12:48:22 PM PST 23 Dec 31 12:48:27 PM PST 23 28545010 ps
T6 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2288606756 Dec 31 12:48:40 PM PST 23 Dec 31 12:48:43 PM PST 23 28387094 ps
T70 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3286209622 Dec 31 12:48:41 PM PST 23 Dec 31 12:48:43 PM PST 23 28920790 ps
T71 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3431897083 Dec 31 12:48:24 PM PST 23 Dec 31 12:48:28 PM PST 23 29051564 ps
T72 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3143312172 Dec 31 12:48:26 PM PST 23 Dec 31 12:48:29 PM PST 23 29747535 ps
T73 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2859052505 Dec 31 12:48:39 PM PST 23 Dec 31 12:48:41 PM PST 23 27568303 ps
T74 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3782333108 Dec 31 12:48:46 PM PST 23 Dec 31 12:48:47 PM PST 23 24385935 ps
T75 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2122222046 Dec 31 12:48:23 PM PST 23 Dec 31 12:48:28 PM PST 23 29097687 ps
T76 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3926754311 Dec 31 12:48:41 PM PST 23 Dec 31 12:48:44 PM PST 23 27525057 ps
T77 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.402776199 Dec 31 12:48:46 PM PST 23 Dec 31 12:48:47 PM PST 23 27231251 ps

Test location /workspace/coverage/default/4.prim_async_alert.800810996
Short name T13
Test name
Test status
Simulation time 12260941 ps
CPU time 0.38 seconds
Started Dec 31 12:45:12 PM PST 23
Finished Dec 31 12:45:14 PM PST 23
Peak memory 145388 kb
Host smart-e3b161c5-07dc-4de0-b4cf-db3ad5cf080a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800810996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.800810996
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1273504293
Short name T24
Test name
Test status
Simulation time 11212271 ps
CPU time 0.37 seconds
Started Dec 31 12:48:43 PM PST 23
Finished Dec 31 12:48:45 PM PST 23
Peak memory 144904 kb
Host smart-2d118532-055f-4603-8752-c0b33a748db4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1273504293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1273504293
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2511341564
Short name T42
Test name
Test status
Simulation time 28579748 ps
CPU time 0.39 seconds
Started Dec 31 12:44:36 PM PST 23
Finished Dec 31 12:44:45 PM PST 23
Peak memory 145492 kb
Host smart-fd79a6cf-5f2a-4e12-9b40-a28583475467
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2511341564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2511341564
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2195264998
Short name T16
Test name
Test status
Simulation time 10799249 ps
CPU time 0.38 seconds
Started Dec 31 12:45:38 PM PST 23
Finished Dec 31 12:45:39 PM PST 23
Peak memory 145356 kb
Host smart-d0900417-e206-41bd-b102-1837d1b2b161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195264998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2195264998
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3961489441
Short name T4
Test name
Test status
Simulation time 31562448 ps
CPU time 0.4 seconds
Started Dec 31 12:45:06 PM PST 23
Finished Dec 31 12:45:09 PM PST 23
Peak memory 145412 kb
Host smart-d8043f26-5940-40af-b6d5-cc6c3ad13555
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3961489441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3961489441
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3266433018
Short name T11
Test name
Test status
Simulation time 8476447 ps
CPU time 0.38 seconds
Started Dec 31 12:48:23 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 144976 kb
Host smart-bde7ecb9-0242-4e3c-aeaf-b98fa49e1fce
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3266433018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3266433018
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3209964021
Short name T21
Test name
Test status
Simulation time 10938047 ps
CPU time 0.38 seconds
Started Dec 31 12:45:27 PM PST 23
Finished Dec 31 12:45:28 PM PST 23
Peak memory 145444 kb
Host smart-948e315c-127e-474b-bb57-ce9c9c92489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209964021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3209964021
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1794703141
Short name T15
Test name
Test status
Simulation time 11346658 ps
CPU time 0.38 seconds
Started Dec 31 12:45:28 PM PST 23
Finished Dec 31 12:45:29 PM PST 23
Peak memory 145324 kb
Host smart-374c9680-c7ea-4575-a5eb-c35c4e98f3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794703141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1794703141
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3363069457
Short name T17
Test name
Test status
Simulation time 10930118 ps
CPU time 0.38 seconds
Started Dec 31 12:45:08 PM PST 23
Finished Dec 31 12:45:10 PM PST 23
Peak memory 145380 kb
Host smart-fd2bc58c-200e-44af-bf81-02f99c83919b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363069457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3363069457
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.3972110810
Short name T1
Test name
Test status
Simulation time 10930227 ps
CPU time 0.37 seconds
Started Dec 31 12:45:33 PM PST 23
Finished Dec 31 12:45:34 PM PST 23
Peak memory 145324 kb
Host smart-f2f231e9-079a-4fa8-b7e0-e7bcd0bdca4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972110810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3972110810
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3772133215
Short name T44
Test name
Test status
Simulation time 11640849 ps
CPU time 0.37 seconds
Started Dec 31 12:45:17 PM PST 23
Finished Dec 31 12:45:21 PM PST 23
Peak memory 145344 kb
Host smart-38211f6e-8792-41ca-a33d-fa63d4dd131d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772133215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3772133215
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.664118455
Short name T12
Test name
Test status
Simulation time 11543292 ps
CPU time 0.38 seconds
Started Dec 31 12:45:25 PM PST 23
Finished Dec 31 12:45:26 PM PST 23
Peak memory 145324 kb
Host smart-f10b170f-e1d3-42c4-a07d-2596f2d39d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664118455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.664118455
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.3940383229
Short name T10
Test name
Test status
Simulation time 11496742 ps
CPU time 0.37 seconds
Started Dec 31 12:45:10 PM PST 23
Finished Dec 31 12:45:20 PM PST 23
Peak memory 145324 kb
Host smart-ff22fd24-a360-4ce7-a563-1c4aed3d0ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940383229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3940383229
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.893111990
Short name T7
Test name
Test status
Simulation time 11882153 ps
CPU time 0.39 seconds
Started Dec 31 12:45:24 PM PST 23
Finished Dec 31 12:45:26 PM PST 23
Peak memory 145364 kb
Host smart-81445e0b-0626-475f-97fa-afd2658fbcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893111990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.893111990
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1385839990
Short name T20
Test name
Test status
Simulation time 11135145 ps
CPU time 0.39 seconds
Started Dec 31 12:45:18 PM PST 23
Finished Dec 31 12:45:21 PM PST 23
Peak memory 145432 kb
Host smart-89df1ffb-db7e-4c4f-8640-adfefc3d17ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385839990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1385839990
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.488099868
Short name T2
Test name
Test status
Simulation time 11588547 ps
CPU time 0.38 seconds
Started Dec 31 12:45:30 PM PST 23
Finished Dec 31 12:45:32 PM PST 23
Peak memory 145324 kb
Host smart-b72db7bc-c7d5-45c0-aea5-103d9e999cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488099868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.488099868
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.772795441
Short name T14
Test name
Test status
Simulation time 12062475 ps
CPU time 0.39 seconds
Started Dec 31 12:45:32 PM PST 23
Finished Dec 31 12:45:43 PM PST 23
Peak memory 145408 kb
Host smart-9b58e4fa-0f6a-47c2-a7f6-b6264af01985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772795441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.772795441
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2827210156
Short name T8
Test name
Test status
Simulation time 10597188 ps
CPU time 0.38 seconds
Started Dec 31 12:45:29 PM PST 23
Finished Dec 31 12:45:31 PM PST 23
Peak memory 145324 kb
Host smart-bd0bdb1f-77ed-47f8-bf71-66c717adaf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827210156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2827210156
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3030202155
Short name T18
Test name
Test status
Simulation time 10327861 ps
CPU time 0.44 seconds
Started Dec 31 12:45:25 PM PST 23
Finished Dec 31 12:45:26 PM PST 23
Peak memory 145376 kb
Host smart-2d4c8135-9512-46fd-a91d-34f5b62b41e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030202155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3030202155
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1983951916
Short name T19
Test name
Test status
Simulation time 11107918 ps
CPU time 0.38 seconds
Started Dec 31 12:45:22 PM PST 23
Finished Dec 31 12:45:25 PM PST 23
Peak memory 145364 kb
Host smart-bccc6178-4cb3-4f8d-89bf-c6801772da97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983951916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1983951916
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3748537578
Short name T3
Test name
Test status
Simulation time 11093812 ps
CPU time 0.37 seconds
Started Dec 31 12:45:16 PM PST 23
Finished Dec 31 12:45:21 PM PST 23
Peak memory 145364 kb
Host smart-08697dae-d4f2-4368-bdca-7c8106e2a2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748537578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3748537578
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1100125565
Short name T9
Test name
Test status
Simulation time 11632986 ps
CPU time 0.37 seconds
Started Dec 31 12:45:10 PM PST 23
Finished Dec 31 12:45:12 PM PST 23
Peak memory 145324 kb
Host smart-a72543d7-c088-4a0f-861a-116f90421469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100125565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1100125565
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3993107246
Short name T49
Test name
Test status
Simulation time 29723883 ps
CPU time 0.39 seconds
Started Dec 31 12:45:03 PM PST 23
Finished Dec 31 12:45:05 PM PST 23
Peak memory 145412 kb
Host smart-e7822364-319a-4bb9-b258-e289c206239f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3993107246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3993107246
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1915583391
Short name T45
Test name
Test status
Simulation time 30267265 ps
CPU time 0.4 seconds
Started Dec 31 12:44:33 PM PST 23
Finished Dec 31 12:44:39 PM PST 23
Peak memory 145444 kb
Host smart-066ee5a1-fdb9-4d48-bc85-79dd813ce364
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1915583391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1915583391
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2148508193
Short name T43
Test name
Test status
Simulation time 29943570 ps
CPU time 0.39 seconds
Started Dec 31 12:44:27 PM PST 23
Finished Dec 31 12:44:31 PM PST 23
Peak memory 145408 kb
Host smart-a67b6534-ac0b-43f5-8026-4287d6492974
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2148508193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2148508193
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1122617610
Short name T39
Test name
Test status
Simulation time 30724241 ps
CPU time 0.4 seconds
Started Dec 31 12:45:08 PM PST 23
Finished Dec 31 12:45:10 PM PST 23
Peak memory 145476 kb
Host smart-e101a72a-ac73-47b9-bbf3-ffba1bcf23e6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1122617610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1122617610
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.43317141
Short name T36
Test name
Test status
Simulation time 27892219 ps
CPU time 0.4 seconds
Started Dec 31 12:44:53 PM PST 23
Finished Dec 31 12:44:57 PM PST 23
Peak memory 145572 kb
Host smart-b658d167-5635-4b42-a43a-6b3398689697
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=43317141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.43317141
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1754523425
Short name T22
Test name
Test status
Simulation time 30035603 ps
CPU time 0.4 seconds
Started Dec 31 12:44:35 PM PST 23
Finished Dec 31 12:44:41 PM PST 23
Peak memory 145432 kb
Host smart-5c458dc0-db0e-4d49-8fb5-5e5dd20d29d4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1754523425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1754523425
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1402575165
Short name T48
Test name
Test status
Simulation time 28502680 ps
CPU time 0.42 seconds
Started Dec 31 12:44:15 PM PST 23
Finished Dec 31 12:44:20 PM PST 23
Peak memory 145440 kb
Host smart-90d46a89-21a9-4c98-9af5-fc60e2914ad0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1402575165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1402575165
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3348869665
Short name T52
Test name
Test status
Simulation time 29460336 ps
CPU time 0.4 seconds
Started Dec 31 12:44:27 PM PST 23
Finished Dec 31 12:44:31 PM PST 23
Peak memory 145452 kb
Host smart-e2ec0943-8857-4957-bd95-dcb0724e714f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3348869665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3348869665
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3975342613
Short name T35
Test name
Test status
Simulation time 30280085 ps
CPU time 0.39 seconds
Started Dec 31 12:44:28 PM PST 23
Finished Dec 31 12:44:35 PM PST 23
Peak memory 145432 kb
Host smart-09cd20b9-b1a2-463d-a966-8c03887408bd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3975342613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3975342613
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2233206376
Short name T41
Test name
Test status
Simulation time 30166022 ps
CPU time 0.4 seconds
Started Dec 31 12:44:53 PM PST 23
Finished Dec 31 12:44:57 PM PST 23
Peak memory 145448 kb
Host smart-e4831998-f4ba-441d-93ae-e915573e571f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2233206376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2233206376
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2955060744
Short name T38
Test name
Test status
Simulation time 29810837 ps
CPU time 0.39 seconds
Started Dec 31 12:44:33 PM PST 23
Finished Dec 31 12:44:39 PM PST 23
Peak memory 145444 kb
Host smart-c6acfa46-d413-4d0f-8e91-fe2b046f14e1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2955060744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2955060744
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.458978957
Short name T40
Test name
Test status
Simulation time 30604013 ps
CPU time 0.41 seconds
Started Dec 31 12:44:45 PM PST 23
Finished Dec 31 12:44:49 PM PST 23
Peak memory 145752 kb
Host smart-f7073fa6-f9dc-46e0-ba82-4d30b59b01f6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=458978957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.458978957
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1223573683
Short name T50
Test name
Test status
Simulation time 28761291 ps
CPU time 0.4 seconds
Started Dec 31 12:44:49 PM PST 23
Finished Dec 31 12:44:53 PM PST 23
Peak memory 145540 kb
Host smart-1a7e8ce9-7a71-4e18-b559-e7c2bd808b92
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1223573683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1223573683
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1517286335
Short name T46
Test name
Test status
Simulation time 30997608 ps
CPU time 0.4 seconds
Started Dec 31 12:44:43 PM PST 23
Finished Dec 31 12:44:48 PM PST 23
Peak memory 145480 kb
Host smart-84b7004c-22a7-4467-8cc0-fd0384b85bbf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1517286335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1517286335
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.203297781
Short name T47
Test name
Test status
Simulation time 30187970 ps
CPU time 0.39 seconds
Started Dec 31 12:44:43 PM PST 23
Finished Dec 31 12:44:48 PM PST 23
Peak memory 145456 kb
Host smart-219663be-cdc3-4224-81df-15f7ac920d47
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=203297781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.203297781
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4283701090
Short name T37
Test name
Test status
Simulation time 31014159 ps
CPU time 0.4 seconds
Started Dec 31 12:44:29 PM PST 23
Finished Dec 31 12:44:35 PM PST 23
Peak memory 145532 kb
Host smart-c0753669-b7ac-4de9-b3c7-a0f6ac0bf9cf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4283701090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.4283701090
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3931085158
Short name T51
Test name
Test status
Simulation time 28955531 ps
CPU time 0.39 seconds
Started Dec 31 12:45:07 PM PST 23
Finished Dec 31 12:45:14 PM PST 23
Peak memory 145480 kb
Host smart-5ace0305-6bfe-4a0a-8172-8dea6a5a0daa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3931085158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3931085158
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3862749511
Short name T23
Test name
Test status
Simulation time 8171435 ps
CPU time 0.36 seconds
Started Dec 31 12:49:09 PM PST 23
Finished Dec 31 12:49:10 PM PST 23
Peak memory 144996 kb
Host smart-0d5201d0-acfe-4883-a770-a95dcefeed87
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3862749511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3862749511
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1242569327
Short name T59
Test name
Test status
Simulation time 11058218 ps
CPU time 0.38 seconds
Started Dec 31 12:49:18 PM PST 23
Finished Dec 31 12:49:21 PM PST 23
Peak memory 144944 kb
Host smart-6d9abde0-bd05-47ec-9b3c-6c13cc3d1a37
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1242569327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1242569327
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2839890160
Short name T25
Test name
Test status
Simulation time 8379456 ps
CPU time 0.37 seconds
Started Dec 31 12:49:16 PM PST 23
Finished Dec 31 12:49:18 PM PST 23
Peak memory 144924 kb
Host smart-aee54c66-6d8b-491a-bbea-ce84b574bd49
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2839890160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2839890160
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2865890758
Short name T26
Test name
Test status
Simulation time 9688858 ps
CPU time 0.37 seconds
Started Dec 31 12:49:19 PM PST 23
Finished Dec 31 12:49:21 PM PST 23
Peak memory 144932 kb
Host smart-08ee3459-75b6-4c65-bc40-655e41f84ded
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2865890758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2865890758
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3583651752
Short name T56
Test name
Test status
Simulation time 8688305 ps
CPU time 0.38 seconds
Started Dec 31 12:49:11 PM PST 23
Finished Dec 31 12:49:12 PM PST 23
Peak memory 144920 kb
Host smart-f403fb79-f0c5-4c48-9698-1ec4f3352a2a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3583651752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3583651752
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.704562038
Short name T28
Test name
Test status
Simulation time 9662113 ps
CPU time 0.37 seconds
Started Dec 31 12:48:55 PM PST 23
Finished Dec 31 12:48:57 PM PST 23
Peak memory 144992 kb
Host smart-ad7ed643-039d-4a3a-9c86-3519805df5d1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=704562038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.704562038
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1188925205
Short name T58
Test name
Test status
Simulation time 10076552 ps
CPU time 0.36 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:49:16 PM PST 23
Peak memory 144940 kb
Host smart-bcec043b-820b-4ed5-bd5e-ec5c7ad220d3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1188925205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1188925205
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3439510273
Short name T30
Test name
Test status
Simulation time 9169143 ps
CPU time 0.39 seconds
Started Dec 31 12:49:18 PM PST 23
Finished Dec 31 12:49:20 PM PST 23
Peak memory 144984 kb
Host smart-30c87b1e-008a-467c-a6f4-dcd132478849
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3439510273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3439510273
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.4096149888
Short name T29
Test name
Test status
Simulation time 9250106 ps
CPU time 0.37 seconds
Started Dec 31 12:48:52 PM PST 23
Finished Dec 31 12:48:53 PM PST 23
Peak memory 145004 kb
Host smart-fbfd2265-9272-42e3-8549-3703adaba3c3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4096149888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.4096149888
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1593109368
Short name T53
Test name
Test status
Simulation time 9328710 ps
CPU time 0.38 seconds
Started Dec 31 12:48:20 PM PST 23
Finished Dec 31 12:48:27 PM PST 23
Peak memory 144992 kb
Host smart-d45cfca7-9729-4596-913b-c12c7154f60d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1593109368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1593109368
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3333960941
Short name T57
Test name
Test status
Simulation time 9523685 ps
CPU time 0.39 seconds
Started Dec 31 12:49:06 PM PST 23
Finished Dec 31 12:49:07 PM PST 23
Peak memory 144896 kb
Host smart-8973f539-f84f-494c-a8d7-f179fa4d90f6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3333960941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3333960941
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1266334169
Short name T27
Test name
Test status
Simulation time 9302627 ps
CPU time 0.37 seconds
Started Dec 31 12:48:57 PM PST 23
Finished Dec 31 12:48:58 PM PST 23
Peak memory 144944 kb
Host smart-350d5803-1132-4801-80fc-c59058485bc4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1266334169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1266334169
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.5671196
Short name T31
Test name
Test status
Simulation time 8119294 ps
CPU time 0.37 seconds
Started Dec 31 12:49:12 PM PST 23
Finished Dec 31 12:49:14 PM PST 23
Peak memory 144916 kb
Host smart-a2318476-e3cc-4934-965c-2cf140ba3326
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=5671196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.5671196
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1434916918
Short name T32
Test name
Test status
Simulation time 9220005 ps
CPU time 0.38 seconds
Started Dec 31 12:49:16 PM PST 23
Finished Dec 31 12:49:18 PM PST 23
Peak memory 144956 kb
Host smart-78e49264-74f6-4d0f-b465-d2637ceab904
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1434916918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1434916918
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2310606334
Short name T34
Test name
Test status
Simulation time 8963486 ps
CPU time 0.37 seconds
Started Dec 31 12:49:04 PM PST 23
Finished Dec 31 12:49:08 PM PST 23
Peak memory 144920 kb
Host smart-20c00ce0-4940-4e72-a35f-0e718cf4f775
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2310606334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2310606334
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2680460450
Short name T54
Test name
Test status
Simulation time 9060847 ps
CPU time 0.37 seconds
Started Dec 31 12:49:17 PM PST 23
Finished Dec 31 12:49:19 PM PST 23
Peak memory 144940 kb
Host smart-08023bdc-6a26-4cd4-9e82-4abe39132b1a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2680460450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2680460450
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.4209234159
Short name T33
Test name
Test status
Simulation time 8474956 ps
CPU time 0.38 seconds
Started Dec 31 12:49:14 PM PST 23
Finished Dec 31 12:49:16 PM PST 23
Peak memory 144992 kb
Host smart-6fe65680-aed0-40de-b97d-4cf5e8c8951c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4209234159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.4209234159
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.129871238
Short name T55
Test name
Test status
Simulation time 9908112 ps
CPU time 0.37 seconds
Started Dec 31 12:49:16 PM PST 23
Finished Dec 31 12:49:18 PM PST 23
Peak memory 145008 kb
Host smart-dc3f0ef1-3548-465b-8a45-39d63a4e6e1d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=129871238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.129871238
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3143312172
Short name T72
Test name
Test status
Simulation time 29747535 ps
CPU time 0.4 seconds
Started Dec 31 12:48:26 PM PST 23
Finished Dec 31 12:48:29 PM PST 23
Peak memory 144996 kb
Host smart-27b93887-bf6a-4e11-ba4d-16f32690563f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3143312172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3143312172
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1665914362
Short name T68
Test name
Test status
Simulation time 26205425 ps
CPU time 0.38 seconds
Started Dec 31 12:48:52 PM PST 23
Finished Dec 31 12:48:53 PM PST 23
Peak memory 144952 kb
Host smart-a8a58f8f-eefa-4b8d-b216-0aacca8bc90e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1665914362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1665914362
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3412343243
Short name T69
Test name
Test status
Simulation time 28545010 ps
CPU time 0.4 seconds
Started Dec 31 12:48:22 PM PST 23
Finished Dec 31 12:48:27 PM PST 23
Peak memory 145024 kb
Host smart-29244c05-882b-446e-8491-578a9126191d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3412343243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3412343243
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3926754311
Short name T76
Test name
Test status
Simulation time 27525057 ps
CPU time 0.39 seconds
Started Dec 31 12:48:41 PM PST 23
Finished Dec 31 12:48:44 PM PST 23
Peak memory 144920 kb
Host smart-d976eb19-5726-47a7-8a75-a99de2dbac69
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3926754311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3926754311
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2010051183
Short name T5
Test name
Test status
Simulation time 28785456 ps
CPU time 0.38 seconds
Started Dec 31 12:48:06 PM PST 23
Finished Dec 31 12:48:09 PM PST 23
Peak memory 145024 kb
Host smart-ca798de6-d267-4630-bf6f-aed96e06846f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2010051183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2010051183
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.248344860
Short name T63
Test name
Test status
Simulation time 28083848 ps
CPU time 0.41 seconds
Started Dec 31 12:48:34 PM PST 23
Finished Dec 31 12:48:37 PM PST 23
Peak memory 145000 kb
Host smart-054e13ab-0db6-45f5-a173-8ce6f285d1ac
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=248344860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.248344860
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3441358228
Short name T67
Test name
Test status
Simulation time 27029289 ps
CPU time 0.38 seconds
Started Dec 31 12:48:41 PM PST 23
Finished Dec 31 12:48:44 PM PST 23
Peak memory 144956 kb
Host smart-9961b430-5fa4-4555-9d4a-a686e5ed1824
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3441358228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3441358228
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2145289617
Short name T61
Test name
Test status
Simulation time 24923174 ps
CPU time 0.38 seconds
Started Dec 31 12:48:18 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 145016 kb
Host smart-2a9d342c-a901-4e57-a36a-b01bfe9ee7e8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2145289617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2145289617
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3431897083
Short name T71
Test name
Test status
Simulation time 29051564 ps
CPU time 0.39 seconds
Started Dec 31 12:48:24 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 144936 kb
Host smart-5b8ff55a-ac78-43aa-8411-aab465e2d338
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3431897083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3431897083
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2859052505
Short name T73
Test name
Test status
Simulation time 27568303 ps
CPU time 0.4 seconds
Started Dec 31 12:48:39 PM PST 23
Finished Dec 31 12:48:41 PM PST 23
Peak memory 144904 kb
Host smart-9ef881ee-a521-4643-8cf7-2265dc244049
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2859052505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2859052505
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3782333108
Short name T74
Test name
Test status
Simulation time 24385935 ps
CPU time 0.38 seconds
Started Dec 31 12:48:46 PM PST 23
Finished Dec 31 12:48:47 PM PST 23
Peak memory 144948 kb
Host smart-5e57a96f-571b-471d-8181-d51ffcd4fffb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3782333108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3782333108
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1219047356
Short name T66
Test name
Test status
Simulation time 26337984 ps
CPU time 0.39 seconds
Started Dec 31 12:48:52 PM PST 23
Finished Dec 31 12:48:53 PM PST 23
Peak memory 145036 kb
Host smart-3553290e-678a-4a60-a70b-619148e591e0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1219047356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1219047356
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4157575508
Short name T60
Test name
Test status
Simulation time 26918833 ps
CPU time 0.39 seconds
Started Dec 31 12:48:57 PM PST 23
Finished Dec 31 12:48:59 PM PST 23
Peak memory 144892 kb
Host smart-4892ec96-024f-4a21-9932-f0ac97ea1344
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4157575508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.4157575508
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2288606756
Short name T6
Test name
Test status
Simulation time 28387094 ps
CPU time 0.39 seconds
Started Dec 31 12:48:40 PM PST 23
Finished Dec 31 12:48:43 PM PST 23
Peak memory 145024 kb
Host smart-955915a1-ce3b-4993-a08f-5800b3c95ff7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2288606756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2288606756
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3286209622
Short name T70
Test name
Test status
Simulation time 28920790 ps
CPU time 0.4 seconds
Started Dec 31 12:48:41 PM PST 23
Finished Dec 31 12:48:43 PM PST 23
Peak memory 144932 kb
Host smart-e8c81ece-07e4-41aa-953b-024539fc2d51
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3286209622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3286209622
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.433476266
Short name T65
Test name
Test status
Simulation time 27681230 ps
CPU time 0.4 seconds
Started Dec 31 12:47:57 PM PST 23
Finished Dec 31 12:47:59 PM PST 23
Peak memory 144952 kb
Host smart-835dbc46-a005-4e24-a01d-446ed2fb8a1a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=433476266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.433476266
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2122222046
Short name T75
Test name
Test status
Simulation time 29097687 ps
CPU time 0.39 seconds
Started Dec 31 12:48:23 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 144944 kb
Host smart-6a0c0c7e-6f44-4c75-a720-e3ebab773fb7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2122222046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2122222046
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.402776199
Short name T77
Test name
Test status
Simulation time 27231251 ps
CPU time 0.39 seconds
Started Dec 31 12:48:46 PM PST 23
Finished Dec 31 12:48:47 PM PST 23
Peak memory 144952 kb
Host smart-bd24cdb1-a47b-4d4a-9603-e6af03c89d7b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=402776199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.402776199
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1810819506
Short name T62
Test name
Test status
Simulation time 26102771 ps
CPU time 0.41 seconds
Started Dec 31 12:48:43 PM PST 23
Finished Dec 31 12:48:45 PM PST 23
Peak memory 145008 kb
Host smart-5d76dc7b-1d17-48a7-a926-e485e6dc03c6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1810819506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1810819506
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1686257682
Short name T64
Test name
Test status
Simulation time 29542696 ps
CPU time 0.4 seconds
Started Dec 31 12:48:15 PM PST 23
Finished Dec 31 12:48:22 PM PST 23
Peak memory 144912 kb
Host smart-35509fd2-93e8-43f4-b3c6-59cb2db1d93b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1686257682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1686257682
Directory /workspace/9.prim_sync_fatal_alert/latest
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