| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.92 | 88.92 | 100.00 | 100.00 | 91.67 | 91.67 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/19.prim_async_alert.705788711 |
| 92.39 | 3.48 | 100.00 | 0.00 | 93.75 | 2.08 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/8.prim_sync_alert.1928083575 |
| 94.50 | 2.11 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.220120058 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.429457586 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1194960675 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.1263923652 |
| /workspace/coverage/default/1.prim_async_alert.943410846 |
| /workspace/coverage/default/10.prim_async_alert.615978678 |
| /workspace/coverage/default/11.prim_async_alert.4177645108 |
| /workspace/coverage/default/12.prim_async_alert.3941295704 |
| /workspace/coverage/default/13.prim_async_alert.1793709017 |
| /workspace/coverage/default/14.prim_async_alert.1413532978 |
| /workspace/coverage/default/15.prim_async_alert.1757254456 |
| /workspace/coverage/default/17.prim_async_alert.1570445130 |
| /workspace/coverage/default/18.prim_async_alert.2662492574 |
| /workspace/coverage/default/2.prim_async_alert.1167714501 |
| /workspace/coverage/default/3.prim_async_alert.1525711580 |
| /workspace/coverage/default/4.prim_async_alert.3223846738 |
| /workspace/coverage/default/6.prim_async_alert.2009435684 |
| /workspace/coverage/default/7.prim_async_alert.2101515118 |
| /workspace/coverage/default/9.prim_async_alert.3760944722 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2419233507 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2070682922 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1270380000 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2703110481 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4263177416 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.88401729 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.435162697 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1693585096 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3519567878 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3958605993 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1432798492 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3051510858 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2912883205 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.1216707723 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1305912832 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.1438925911 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.598719058 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.3822507518 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.3601096496 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.477287953 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.973549062 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.353279613 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.3680880166 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1213962252 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.2479480590 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1577309775 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3142239830 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2914096384 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1799750281 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.611937266 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3675229956 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3762604339 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1031506852 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2601660480 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3542983933 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.495307094 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3055324535 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3904732779 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3655700592 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_async_alert.2662492574 | Jan 07 12:34:05 PM PST 24 | Jan 07 12:35:26 PM PST 24 | 11931061 ps | ||
| T2 | /workspace/coverage/default/19.prim_async_alert.705788711 | Jan 07 12:33:51 PM PST 24 | Jan 07 12:35:29 PM PST 24 | 12160931 ps | ||
| T3 | /workspace/coverage/default/0.prim_async_alert.1263923652 | Jan 07 12:33:47 PM PST 24 | Jan 07 12:34:53 PM PST 24 | 10740926 ps | ||
| T8 | /workspace/coverage/default/9.prim_async_alert.3760944722 | Jan 07 12:33:56 PM PST 24 | Jan 07 12:35:08 PM PST 24 | 12698856 ps | ||
| T18 | /workspace/coverage/default/11.prim_async_alert.4177645108 | Jan 07 12:34:59 PM PST 24 | Jan 07 12:36:26 PM PST 24 | 10974578 ps | ||
| T5 | /workspace/coverage/default/13.prim_async_alert.1793709017 | Jan 07 12:33:49 PM PST 24 | Jan 07 12:36:03 PM PST 24 | 11199434 ps | ||
| T19 | /workspace/coverage/default/17.prim_async_alert.1570445130 | Jan 07 12:33:30 PM PST 24 | Jan 07 12:34:30 PM PST 24 | 10964385 ps | ||
| T15 | /workspace/coverage/default/15.prim_async_alert.1757254456 | Jan 07 12:34:17 PM PST 24 | Jan 07 12:35:34 PM PST 24 | 10726263 ps | ||
| T20 | /workspace/coverage/default/2.prim_async_alert.1167714501 | Jan 07 12:35:18 PM PST 24 | Jan 07 12:36:47 PM PST 24 | 11176256 ps | ||
| T9 | /workspace/coverage/default/10.prim_async_alert.615978678 | Jan 07 12:33:56 PM PST 24 | Jan 07 12:35:24 PM PST 24 | 12113786 ps | ||
| T6 | /workspace/coverage/default/14.prim_async_alert.1413532978 | Jan 07 12:34:15 PM PST 24 | Jan 07 12:35:39 PM PST 24 | 11213581 ps | ||
| T7 | /workspace/coverage/default/1.prim_async_alert.943410846 | Jan 07 12:33:41 PM PST 24 | Jan 07 12:34:42 PM PST 24 | 11355289 ps | ||
| T21 | /workspace/coverage/default/6.prim_async_alert.2009435684 | Jan 07 12:33:41 PM PST 24 | Jan 07 12:35:25 PM PST 24 | 11865466 ps | ||
| T13 | /workspace/coverage/default/12.prim_async_alert.3941295704 | Jan 07 12:35:40 PM PST 24 | Jan 07 12:37:19 PM PST 24 | 12137152 ps | ||
| T16 | /workspace/coverage/default/7.prim_async_alert.2101515118 | Jan 07 12:34:10 PM PST 24 | Jan 07 12:35:25 PM PST 24 | 11290203 ps | ||
| T17 | /workspace/coverage/default/3.prim_async_alert.1525711580 | Jan 07 12:34:17 PM PST 24 | Jan 07 12:35:54 PM PST 24 | 11230103 ps | ||
| T43 | /workspace/coverage/default/4.prim_async_alert.3223846738 | Jan 07 12:33:58 PM PST 24 | Jan 07 12:35:18 PM PST 24 | 11736261 ps | ||
| T36 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2703110481 | Jan 07 12:35:54 PM PST 24 | Jan 07 12:37:29 PM PST 24 | 30389861 ps | ||
| T11 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2070682922 | Jan 07 12:34:03 PM PST 24 | Jan 07 12:35:33 PM PST 24 | 30696311 ps | ||
| T37 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2912883205 | Jan 07 12:34:06 PM PST 24 | Jan 07 12:35:51 PM PST 24 | 31525990 ps | ||
| T38 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3051510858 | Jan 07 12:34:26 PM PST 24 | Jan 07 12:35:41 PM PST 24 | 29528935 ps | ||
| T39 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1693585096 | Jan 07 12:33:41 PM PST 24 | Jan 07 12:35:03 PM PST 24 | 29416807 ps | ||
| T14 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2419233507 | Jan 07 12:33:40 PM PST 24 | Jan 07 12:35:10 PM PST 24 | 28274870 ps | ||
| T12 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.220120058 | Jan 07 12:34:19 PM PST 24 | Jan 07 12:36:07 PM PST 24 | 29313289 ps | ||
| T40 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1432798492 | Jan 07 12:34:28 PM PST 24 | Jan 07 12:35:58 PM PST 24 | 28274230 ps | ||
| T41 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1270380000 | Jan 07 12:34:22 PM PST 24 | Jan 07 12:35:49 PM PST 24 | 29148129 ps | ||
| T42 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3958605993 | Jan 07 12:33:58 PM PST 24 | Jan 07 12:35:29 PM PST 24 | 30058902 ps | ||
| T44 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.435162697 | Jan 07 12:33:39 PM PST 24 | Jan 07 12:34:53 PM PST 24 | 29638754 ps | ||
| T45 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3519567878 | Jan 07 12:33:42 PM PST 24 | Jan 07 12:34:47 PM PST 24 | 31040857 ps | ||
| T4 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.429457586 | Jan 07 12:34:04 PM PST 24 | Jan 07 12:35:46 PM PST 24 | 28411399 ps | ||
| T46 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4263177416 | Jan 07 12:33:41 PM PST 24 | Jan 07 12:35:09 PM PST 24 | 29396462 ps | ||
| T47 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.88401729 | Jan 07 12:34:24 PM PST 24 | Jan 07 12:35:54 PM PST 24 | 29115942 ps | ||
| T22 | /workspace/coverage/sync_alert/12.prim_sync_alert.1438925911 | Jan 07 12:36:35 PM PST 24 | Jan 07 12:38:09 PM PST 24 | 10172894 ps | ||
| T23 | /workspace/coverage/sync_alert/18.prim_sync_alert.353279613 | Jan 07 12:34:30 PM PST 24 | Jan 07 12:36:04 PM PST 24 | 10616096 ps | ||
| T24 | /workspace/coverage/sync_alert/13.prim_sync_alert.598719058 | Jan 07 12:33:38 PM PST 24 | Jan 07 12:35:15 PM PST 24 | 9044185 ps | ||
| T25 | /workspace/coverage/sync_alert/16.prim_sync_alert.477287953 | Jan 07 12:34:23 PM PST 24 | Jan 07 12:35:48 PM PST 24 | 10048257 ps | ||
| T26 | /workspace/coverage/sync_alert/11.prim_sync_alert.1305912832 | Jan 07 12:33:59 PM PST 24 | Jan 07 12:35:07 PM PST 24 | 9325095 ps | ||
| T27 | /workspace/coverage/sync_alert/19.prim_sync_alert.3680880166 | Jan 07 12:33:42 PM PST 24 | Jan 07 12:35:05 PM PST 24 | 8265469 ps | ||
| T32 | /workspace/coverage/sync_alert/14.prim_sync_alert.3822507518 | Jan 07 12:35:42 PM PST 24 | Jan 07 12:36:49 PM PST 24 | 9459980 ps | ||
| T33 | /workspace/coverage/sync_alert/7.prim_sync_alert.2479480590 | Jan 07 12:34:16 PM PST 24 | Jan 07 12:35:45 PM PST 24 | 8803960 ps | ||
| T34 | /workspace/coverage/sync_alert/6.prim_sync_alert.1213962252 | Jan 07 12:34:01 PM PST 24 | Jan 07 12:35:18 PM PST 24 | 8199051 ps | ||
| T35 | /workspace/coverage/sync_alert/8.prim_sync_alert.1928083575 | Jan 07 12:36:16 PM PST 24 | Jan 07 12:37:34 PM PST 24 | 8935501 ps | ||
| T48 | /workspace/coverage/sync_alert/17.prim_sync_alert.973549062 | Jan 07 12:33:41 PM PST 24 | Jan 07 12:35:09 PM PST 24 | 8364488 ps | ||
| T49 | /workspace/coverage/sync_alert/15.prim_sync_alert.3601096496 | Jan 07 12:33:57 PM PST 24 | Jan 07 12:35:41 PM PST 24 | 9008418 ps | ||
| T28 | /workspace/coverage/sync_alert/0.prim_sync_alert.1216707723 | Jan 07 12:34:11 PM PST 24 | Jan 07 12:36:07 PM PST 24 | 9443125 ps | ||
| T29 | /workspace/coverage/sync_alert/9.prim_sync_alert.1577309775 | Jan 07 12:34:16 PM PST 24 | Jan 07 12:35:55 PM PST 24 | 9665001 ps | ||
| T50 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1799750281 | Jan 07 12:34:53 PM PST 24 | Jan 07 12:36:45 PM PST 24 | 27716308 ps | ||
| T30 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3904732779 | Jan 07 12:34:10 PM PST 24 | Jan 07 12:35:54 PM PST 24 | 28800009 ps | ||
| T51 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1031506852 | Jan 07 12:34:53 PM PST 24 | Jan 07 12:36:45 PM PST 24 | 26871835 ps | ||
| T31 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3142239830 | Jan 07 12:33:58 PM PST 24 | Jan 07 12:35:29 PM PST 24 | 26567481 ps | ||
| T52 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3542983933 | Jan 07 12:33:56 PM PST 24 | Jan 07 12:35:57 PM PST 24 | 26811865 ps | ||
| T53 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3055324535 | Jan 07 12:34:13 PM PST 24 | Jan 07 12:35:39 PM PST 24 | 26922708 ps | ||
| T54 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3762604339 | Jan 07 12:33:57 PM PST 24 | Jan 07 12:35:03 PM PST 24 | 26611279 ps | ||
| T55 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3655700592 | Jan 07 12:33:55 PM PST 24 | Jan 07 12:35:17 PM PST 24 | 28647653 ps | ||
| T56 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3675229956 | Jan 07 12:34:33 PM PST 24 | Jan 07 12:36:26 PM PST 24 | 27923284 ps | ||
| T10 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1194960675 | Jan 07 12:34:47 PM PST 24 | Jan 07 12:36:43 PM PST 24 | 26537934 ps | ||
| T57 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.495307094 | Jan 07 12:33:50 PM PST 24 | Jan 07 12:35:25 PM PST 24 | 28471868 ps | ||
| T58 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2601660480 | Jan 07 12:34:10 PM PST 24 | Jan 07 12:35:45 PM PST 24 | 28090778 ps | ||
| T59 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2914096384 | Jan 07 12:35:17 PM PST 24 | Jan 07 12:36:56 PM PST 24 | 27544806 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.611937266 | Jan 07 12:34:05 PM PST 24 | Jan 07 12:35:43 PM PST 24 | 28694338 ps |
| Test location | /workspace/coverage/default/19.prim_async_alert.705788711 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12160931 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:33:51 PM PST 24 |
| Finished | Jan 07 12:35:29 PM PST 24 |
| Peak memory | 145404 kb |
| Host | smart-2e7d95bb-201b-4748-8861-9ed6031f9ece |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=705788711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.705788711 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1928083575 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8935501 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:36:16 PM PST 24 |
| Finished | Jan 07 12:37:34 PM PST 24 |
| Peak memory | 144676 kb |
| Host | smart-054e58e2-ee91-4d21-911d-e8dafa350b14 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1928083575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1928083575 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.220120058 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 29313289 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:34:19 PM PST 24 |
| Finished | Jan 07 12:36:07 PM PST 24 |
| Peak memory | 145472 kb |
| Host | smart-263ea881-fff0-4584-b1d6-09dd2dd89d4f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=220120058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.220120058 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.429457586 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28411399 ps |
| CPU time | 0.4 seconds |
| Started | Jan 07 12:34:04 PM PST 24 |
| Finished | Jan 07 12:35:46 PM PST 24 |
| Peak memory | 145532 kb |
| Host | smart-3ab5956a-0033-4510-b7fe-44643fa69bda |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=429457586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.429457586 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1194960675 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 26537934 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:34:47 PM PST 24 |
| Finished | Jan 07 12:36:43 PM PST 24 |
| Peak memory | 144924 kb |
| Host | smart-f4f5c5fc-4376-4207-b60a-287220a393a6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1194960675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1194960675 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.1263923652 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10740926 ps |
| CPU time | 0.36 seconds |
| Started | Jan 07 12:33:47 PM PST 24 |
| Finished | Jan 07 12:34:53 PM PST 24 |
| Peak memory | 145412 kb |
| Host | smart-9cb78e1d-9f4b-483e-bece-a6091ea94af5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1263923652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1263923652 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.943410846 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11355289 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:33:41 PM PST 24 |
| Finished | Jan 07 12:34:42 PM PST 24 |
| Peak memory | 145304 kb |
| Host | smart-63634da8-628e-4db0-adf1-83da4218b2f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943410846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.943410846 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.615978678 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12113786 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:33:56 PM PST 24 |
| Finished | Jan 07 12:35:24 PM PST 24 |
| Peak memory | 145204 kb |
| Host | smart-8db04028-f5b6-4761-9580-0e5c6d2b48be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=615978678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.615978678 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.4177645108 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10974578 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:34:59 PM PST 24 |
| Finished | Jan 07 12:36:26 PM PST 24 |
| Peak memory | 145448 kb |
| Host | smart-7683591c-a36c-4f2f-8efe-d148eecb9b3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177645108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4177645108 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3941295704 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12137152 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:35:40 PM PST 24 |
| Finished | Jan 07 12:37:19 PM PST 24 |
| Peak memory | 144952 kb |
| Host | smart-809407d9-0179-4c60-a5c6-fc16446582fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3941295704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3941295704 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1793709017 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11199434 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:33:49 PM PST 24 |
| Finished | Jan 07 12:36:03 PM PST 24 |
| Peak memory | 145412 kb |
| Host | smart-f611a98b-82f3-4f5d-82fd-b8c1619d0030 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793709017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1793709017 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1413532978 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11213581 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:34:15 PM PST 24 |
| Finished | Jan 07 12:35:39 PM PST 24 |
| Peak memory | 145364 kb |
| Host | smart-8641e031-d5e4-4bf1-a7a1-c1fef8d20c81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413532978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1413532978 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1757254456 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10726263 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:34:17 PM PST 24 |
| Finished | Jan 07 12:35:34 PM PST 24 |
| Peak memory | 145476 kb |
| Host | smart-38e324a2-e815-4876-b4be-c1ec5c11e8b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1757254456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1757254456 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1570445130 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10964385 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:33:30 PM PST 24 |
| Finished | Jan 07 12:34:30 PM PST 24 |
| Peak memory | 145368 kb |
| Host | smart-784eb6f3-00cf-4b2b-a195-049a0dd09fc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570445130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1570445130 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.2662492574 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11931061 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:34:05 PM PST 24 |
| Finished | Jan 07 12:35:26 PM PST 24 |
| Peak memory | 145504 kb |
| Host | smart-497fa478-12a5-4d90-9f9d-f732960613fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662492574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2662492574 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.1167714501 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11176256 ps |
| CPU time | 0.42 seconds |
| Started | Jan 07 12:35:18 PM PST 24 |
| Finished | Jan 07 12:36:47 PM PST 24 |
| Peak memory | 145116 kb |
| Host | smart-c09c08c2-39b8-40e7-b9d0-3fe0a67dce83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1167714501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1167714501 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.1525711580 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11230103 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:34:17 PM PST 24 |
| Finished | Jan 07 12:35:54 PM PST 24 |
| Peak memory | 145424 kb |
| Host | smart-dad51a85-d71f-4760-83f6-07128b864901 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525711580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1525711580 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.3223846738 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11736261 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:33:58 PM PST 24 |
| Finished | Jan 07 12:35:18 PM PST 24 |
| Peak memory | 145360 kb |
| Host | smart-64f16b30-3a85-4055-87d3-99985ee9b92b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223846738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3223846738 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2009435684 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11865466 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:33:41 PM PST 24 |
| Finished | Jan 07 12:35:25 PM PST 24 |
| Peak memory | 145312 kb |
| Host | smart-bf3f128c-1b8f-415b-9296-9a4fd38da983 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2009435684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2009435684 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.2101515118 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11290203 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:34:10 PM PST 24 |
| Finished | Jan 07 12:35:25 PM PST 24 |
| Peak memory | 145504 kb |
| Host | smart-36c632fe-3c1d-4dbd-958c-cb3954ab2588 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2101515118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2101515118 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.3760944722 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12698856 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:33:56 PM PST 24 |
| Finished | Jan 07 12:35:08 PM PST 24 |
| Peak memory | 145356 kb |
| Host | smart-b92729ec-494d-4958-addd-d6ccb2ca0ce6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760944722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3760944722 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2419233507 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 28274870 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:33:40 PM PST 24 |
| Finished | Jan 07 12:35:10 PM PST 24 |
| Peak memory | 145496 kb |
| Host | smart-0ce04339-3540-4dff-a961-60e1f5a8fdcd |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2419233507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2419233507 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2070682922 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 30696311 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:34:03 PM PST 24 |
| Finished | Jan 07 12:35:33 PM PST 24 |
| Peak memory | 145476 kb |
| Host | smart-e1da3f97-e851-454f-bbc9-9f7e7991156f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2070682922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2070682922 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1270380000 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29148129 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:34:22 PM PST 24 |
| Finished | Jan 07 12:35:49 PM PST 24 |
| Peak memory | 145448 kb |
| Host | smart-c8a66521-9d0d-4ab2-b770-ba94679ee1f6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1270380000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1270380000 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2703110481 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 30389861 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:35:54 PM PST 24 |
| Finished | Jan 07 12:37:29 PM PST 24 |
| Peak memory | 145140 kb |
| Host | smart-c680495a-7f43-4815-8c31-088365174c13 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2703110481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2703110481 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4263177416 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29396462 ps |
| CPU time | 0.4 seconds |
| Started | Jan 07 12:33:41 PM PST 24 |
| Finished | Jan 07 12:35:09 PM PST 24 |
| Peak memory | 145536 kb |
| Host | smart-52f477b3-05ef-4943-9f35-2d876527f2c4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4263177416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.4263177416 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.88401729 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 29115942 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:34:24 PM PST 24 |
| Finished | Jan 07 12:35:54 PM PST 24 |
| Peak memory | 145496 kb |
| Host | smart-3c5a0676-63d4-48a9-aaf0-704aed51e946 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=88401729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.88401729 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.435162697 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 29638754 ps |
| CPU time | 0.42 seconds |
| Started | Jan 07 12:33:39 PM PST 24 |
| Finished | Jan 07 12:34:53 PM PST 24 |
| Peak memory | 145544 kb |
| Host | smart-8725572b-503e-409e-a43a-ab7aec8dd2ef |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=435162697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.435162697 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1693585096 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 29416807 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:33:41 PM PST 24 |
| Finished | Jan 07 12:35:03 PM PST 24 |
| Peak memory | 145488 kb |
| Host | smart-f51e282f-a8f9-4378-9093-ed07644f368c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1693585096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1693585096 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3519567878 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 31040857 ps |
| CPU time | 0.4 seconds |
| Started | Jan 07 12:33:42 PM PST 24 |
| Finished | Jan 07 12:34:47 PM PST 24 |
| Peak memory | 145504 kb |
| Host | smart-a2851fbd-68a2-4507-9a63-a7686917c74c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3519567878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3519567878 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3958605993 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30058902 ps |
| CPU time | 0.43 seconds |
| Started | Jan 07 12:33:58 PM PST 24 |
| Finished | Jan 07 12:35:29 PM PST 24 |
| Peak memory | 145428 kb |
| Host | smart-8758b745-9b17-4e0a-aafb-e9efbb935ed8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3958605993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3958605993 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1432798492 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 28274230 ps |
| CPU time | 0.4 seconds |
| Started | Jan 07 12:34:28 PM PST 24 |
| Finished | Jan 07 12:35:58 PM PST 24 |
| Peak memory | 145456 kb |
| Host | smart-0e6c1fc7-e0c0-4910-8772-62c34879eaa5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1432798492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1432798492 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3051510858 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 29528935 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:34:26 PM PST 24 |
| Finished | Jan 07 12:35:41 PM PST 24 |
| Peak memory | 145596 kb |
| Host | smart-cd0eced2-2165-4c81-8109-cd1e745a848e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3051510858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3051510858 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2912883205 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 31525990 ps |
| CPU time | 0.4 seconds |
| Started | Jan 07 12:34:06 PM PST 24 |
| Finished | Jan 07 12:35:51 PM PST 24 |
| Peak memory | 145428 kb |
| Host | smart-a0e35891-1fb5-412f-ab04-fe9672430e59 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2912883205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2912883205 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.1216707723 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9443125 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:34:11 PM PST 24 |
| Finished | Jan 07 12:36:07 PM PST 24 |
| Peak memory | 144916 kb |
| Host | smart-f611941d-9d6d-4c79-a402-ecd3c64376bd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1216707723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1216707723 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1305912832 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9325095 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:33:59 PM PST 24 |
| Finished | Jan 07 12:35:07 PM PST 24 |
| Peak memory | 144920 kb |
| Host | smart-2b5dd02f-55a9-4bd5-a16e-3ac439e65976 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1305912832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1305912832 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.1438925911 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10172894 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:36:35 PM PST 24 |
| Finished | Jan 07 12:38:09 PM PST 24 |
| Peak memory | 144644 kb |
| Host | smart-f045d279-8403-4c24-bc4d-d3faae1aa6c9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1438925911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1438925911 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.598719058 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9044185 ps |
| CPU time | 0.36 seconds |
| Started | Jan 07 12:33:38 PM PST 24 |
| Finished | Jan 07 12:35:15 PM PST 24 |
| Peak memory | 144860 kb |
| Host | smart-0f2f07c1-58a1-4c09-9d7b-daab0dfb01a0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=598719058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.598719058 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.3822507518 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9459980 ps |
| CPU time | 0.36 seconds |
| Started | Jan 07 12:35:42 PM PST 24 |
| Finished | Jan 07 12:36:49 PM PST 24 |
| Peak memory | 144440 kb |
| Host | smart-00eb337c-e1f6-40e8-ac43-f65d8c38cf66 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3822507518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3822507518 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3601096496 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9008418 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:33:57 PM PST 24 |
| Finished | Jan 07 12:35:41 PM PST 24 |
| Peak memory | 144988 kb |
| Host | smart-3cd8efab-218b-4952-82ef-20319864eed4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3601096496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3601096496 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.477287953 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10048257 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:34:23 PM PST 24 |
| Finished | Jan 07 12:35:48 PM PST 24 |
| Peak memory | 144880 kb |
| Host | smart-9f88fdca-9096-482d-8b0a-da99c12a9fff |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=477287953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.477287953 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.973549062 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8364488 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:33:41 PM PST 24 |
| Finished | Jan 07 12:35:09 PM PST 24 |
| Peak memory | 144904 kb |
| Host | smart-e74d04ff-bc4a-44eb-a77c-ef6d7004b5f6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=973549062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.973549062 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.353279613 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10616096 ps |
| CPU time | 0.36 seconds |
| Started | Jan 07 12:34:30 PM PST 24 |
| Finished | Jan 07 12:36:04 PM PST 24 |
| Peak memory | 144896 kb |
| Host | smart-87cf1bb2-1772-4029-9078-8ebe1543ab26 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=353279613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.353279613 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.3680880166 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8265469 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:33:42 PM PST 24 |
| Finished | Jan 07 12:35:05 PM PST 24 |
| Peak memory | 144888 kb |
| Host | smart-62d977aa-c2fb-43dc-b654-dd4724dcd6d8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3680880166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3680880166 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1213962252 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8199051 ps |
| CPU time | 0.36 seconds |
| Started | Jan 07 12:34:01 PM PST 24 |
| Finished | Jan 07 12:35:18 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-7ae79cdb-7c12-4146-a509-58246554f315 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1213962252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1213962252 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.2479480590 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8803960 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:34:16 PM PST 24 |
| Finished | Jan 07 12:35:45 PM PST 24 |
| Peak memory | 144856 kb |
| Host | smart-12cf3eb9-d375-4a06-90de-bad06443f679 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2479480590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2479480590 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1577309775 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9665001 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:34:16 PM PST 24 |
| Finished | Jan 07 12:35:55 PM PST 24 |
| Peak memory | 145020 kb |
| Host | smart-fb479292-e55c-47e6-af45-389ca68fad20 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1577309775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1577309775 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3142239830 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 26567481 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:33:58 PM PST 24 |
| Finished | Jan 07 12:35:29 PM PST 24 |
| Peak memory | 144904 kb |
| Host | smart-afdce3d1-fc0d-4269-988d-6788d87598de |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3142239830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3142239830 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2914096384 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 27544806 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:35:17 PM PST 24 |
| Finished | Jan 07 12:36:56 PM PST 24 |
| Peak memory | 144440 kb |
| Host | smart-25ee1bd2-f081-4d2b-a7c2-f29718d1a539 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2914096384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2914096384 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1799750281 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 27716308 ps |
| CPU time | 0.44 seconds |
| Started | Jan 07 12:34:53 PM PST 24 |
| Finished | Jan 07 12:36:45 PM PST 24 |
| Peak memory | 144376 kb |
| Host | smart-09df415c-b330-4a4d-a858-3ef4ddfd4513 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1799750281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1799750281 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.611937266 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 28694338 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:34:05 PM PST 24 |
| Finished | Jan 07 12:35:43 PM PST 24 |
| Peak memory | 144940 kb |
| Host | smart-a1d187c9-b9d5-4794-9a92-694d9bf67cd1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=611937266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.611937266 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3675229956 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 27923284 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:34:33 PM PST 24 |
| Finished | Jan 07 12:36:26 PM PST 24 |
| Peak memory | 144960 kb |
| Host | smart-19ff3bb0-416c-4591-b027-146cbd46e0ed |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3675229956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3675229956 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3762604339 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 26611279 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:33:57 PM PST 24 |
| Finished | Jan 07 12:35:03 PM PST 24 |
| Peak memory | 144936 kb |
| Host | smart-c959d71f-5a35-470b-8423-59c02b67cb53 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3762604339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3762604339 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1031506852 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 26871835 ps |
| CPU time | 0.43 seconds |
| Started | Jan 07 12:34:53 PM PST 24 |
| Finished | Jan 07 12:36:45 PM PST 24 |
| Peak memory | 144520 kb |
| Host | smart-2a02d81c-a6cf-4660-a01c-d33091f757fc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1031506852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1031506852 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2601660480 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 28090778 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:34:10 PM PST 24 |
| Finished | Jan 07 12:35:45 PM PST 24 |
| Peak memory | 144916 kb |
| Host | smart-ac4555b1-0eb6-4645-b05c-2df9ea76e777 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2601660480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2601660480 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3542983933 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 26811865 ps |
| CPU time | 0.42 seconds |
| Started | Jan 07 12:33:56 PM PST 24 |
| Finished | Jan 07 12:35:57 PM PST 24 |
| Peak memory | 145004 kb |
| Host | smart-2bcf66d0-47bb-43d5-bdb2-53e0f591eb57 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3542983933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3542983933 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.495307094 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 28471868 ps |
| CPU time | 0.43 seconds |
| Started | Jan 07 12:33:50 PM PST 24 |
| Finished | Jan 07 12:35:25 PM PST 24 |
| Peak memory | 144948 kb |
| Host | smart-63380a1c-621f-4d49-a56c-45072f61144e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=495307094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.495307094 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3055324535 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 26922708 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:34:13 PM PST 24 |
| Finished | Jan 07 12:35:39 PM PST 24 |
| Peak memory | 144972 kb |
| Host | smart-45df06ee-764b-4a34-9ed3-29648aeba880 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3055324535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3055324535 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3904732779 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 28800009 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:34:10 PM PST 24 |
| Finished | Jan 07 12:35:54 PM PST 24 |
| Peak memory | 144924 kb |
| Host | smart-4aaacb27-642e-4cfd-8a35-def52539990a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3904732779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3904732779 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3655700592 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 28647653 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:33:55 PM PST 24 |
| Finished | Jan 07 12:35:17 PM PST 24 |
| Peak memory | 145004 kb |
| Host | smart-1f4518ef-6b88-46bc-8892-47bc76248ed4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3655700592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3655700592 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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