Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 76
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/7.prim_async_alert.3774973966
92.39 3.72 100.00 0.00 93.75 0.00 100.00 0.00 85.71 10.71 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/1.prim_sync_alert.1613238999
93.90 1.51 100.00 0.00 95.83 2.08 100.00 0.00 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3945662636
94.85 0.94 100.00 0.00 97.92 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2914965247
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/10.prim_sync_alert.365425594

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3322956517
/workspace/coverage/default/1.prim_async_alert.3492103829
/workspace/coverage/default/10.prim_async_alert.4102202845
/workspace/coverage/default/11.prim_async_alert.3979983240
/workspace/coverage/default/12.prim_async_alert.182310491
/workspace/coverage/default/13.prim_async_alert.2064994892
/workspace/coverage/default/16.prim_async_alert.3276936502
/workspace/coverage/default/17.prim_async_alert.3051510325
/workspace/coverage/default/18.prim_async_alert.1844947462
/workspace/coverage/default/19.prim_async_alert.2896115995
/workspace/coverage/default/2.prim_async_alert.528561910
/workspace/coverage/default/3.prim_async_alert.3290590401
/workspace/coverage/default/4.prim_async_alert.2901710768
/workspace/coverage/default/5.prim_async_alert.2426764099
/workspace/coverage/default/6.prim_async_alert.3785000763
/workspace/coverage/default/8.prim_async_alert.13188317
/workspace/coverage/default/9.prim_async_alert.3715691267
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.305496361
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1767606409
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2916876927
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.667519995
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2038382274
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2946527966
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3106643274
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2931480875
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.49034672
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2007049914
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2874024853
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.819558840
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2667230238
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4076112199
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1176420612
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2360970418
/workspace/coverage/sync_alert/0.prim_sync_alert.1387729372
/workspace/coverage/sync_alert/11.prim_sync_alert.3311854517
/workspace/coverage/sync_alert/12.prim_sync_alert.2311311489
/workspace/coverage/sync_alert/13.prim_sync_alert.1090319543
/workspace/coverage/sync_alert/14.prim_sync_alert.2105649912
/workspace/coverage/sync_alert/15.prim_sync_alert.2771696548
/workspace/coverage/sync_alert/16.prim_sync_alert.4287424969
/workspace/coverage/sync_alert/17.prim_sync_alert.113765563
/workspace/coverage/sync_alert/18.prim_sync_alert.2108056431
/workspace/coverage/sync_alert/19.prim_sync_alert.2516854914
/workspace/coverage/sync_alert/2.prim_sync_alert.156114124
/workspace/coverage/sync_alert/3.prim_sync_alert.1611480200
/workspace/coverage/sync_alert/4.prim_sync_alert.2836262492
/workspace/coverage/sync_alert/5.prim_sync_alert.3984964520
/workspace/coverage/sync_alert/6.prim_sync_alert.2021194592
/workspace/coverage/sync_alert/7.prim_sync_alert.4236819607
/workspace/coverage/sync_alert/8.prim_sync_alert.2312718634
/workspace/coverage/sync_alert/9.prim_sync_alert.1920927301
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2624034285
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4023048602
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2781146574
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3548080277
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3082518097
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2060153935
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2222564968
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3751155041
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1712069902
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2032773156
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2949447414
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3918074262
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3517901238
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3671059808
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3528881552
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4178607638
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.793969759
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.947857934
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3889599649
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1188692650



Total test records in report: 76
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/18.prim_async_alert.1844947462 Jan 10 12:27:07 PM PST 24 Jan 10 12:27:14 PM PST 24 11414440 ps
T2 /workspace/coverage/default/10.prim_async_alert.4102202845 Jan 10 12:24:51 PM PST 24 Jan 10 12:24:52 PM PST 24 10675513 ps
T3 /workspace/coverage/default/3.prim_async_alert.3290590401 Jan 10 12:32:01 PM PST 24 Jan 10 12:32:48 PM PST 24 10549237 ps
T9 /workspace/coverage/default/19.prim_async_alert.2896115995 Jan 10 12:27:33 PM PST 24 Jan 10 12:27:39 PM PST 24 11698761 ps
T10 /workspace/coverage/default/7.prim_async_alert.3774973966 Jan 10 12:30:20 PM PST 24 Jan 10 12:31:01 PM PST 24 11578754 ps
T18 /workspace/coverage/default/13.prim_async_alert.2064994892 Jan 10 12:28:02 PM PST 24 Jan 10 12:28:18 PM PST 24 10937026 ps
T7 /workspace/coverage/default/9.prim_async_alert.3715691267 Jan 10 12:21:39 PM PST 24 Jan 10 12:21:41 PM PST 24 11106709 ps
T19 /workspace/coverage/default/16.prim_async_alert.3276936502 Jan 10 12:21:55 PM PST 24 Jan 10 12:21:57 PM PST 24 10406233 ps
T20 /workspace/coverage/default/8.prim_async_alert.13188317 Jan 10 12:26:12 PM PST 24 Jan 10 12:26:17 PM PST 24 11617772 ps
T12 /workspace/coverage/default/4.prim_async_alert.2901710768 Jan 10 12:32:18 PM PST 24 Jan 10 12:32:58 PM PST 24 12248287 ps
T8 /workspace/coverage/default/17.prim_async_alert.3051510325 Jan 10 12:28:06 PM PST 24 Jan 10 12:28:22 PM PST 24 11269627 ps
T21 /workspace/coverage/default/2.prim_async_alert.528561910 Jan 10 12:27:16 PM PST 24 Jan 10 12:27:23 PM PST 24 10589641 ps
T26 /workspace/coverage/default/6.prim_async_alert.3785000763 Jan 10 12:28:09 PM PST 24 Jan 10 12:28:24 PM PST 24 11216412 ps
T27 /workspace/coverage/default/11.prim_async_alert.3979983240 Jan 10 12:31:30 PM PST 24 Jan 10 12:32:20 PM PST 24 11313240 ps
T16 /workspace/coverage/default/12.prim_async_alert.182310491 Jan 10 12:21:39 PM PST 24 Jan 10 12:21:41 PM PST 24 12056837 ps
T22 /workspace/coverage/default/1.prim_async_alert.3492103829 Jan 10 12:28:05 PM PST 24 Jan 10 12:28:21 PM PST 24 11193847 ps
T14 /workspace/coverage/default/0.prim_async_alert.3322956517 Jan 10 12:28:54 PM PST 24 Jan 10 12:29:12 PM PST 24 11618330 ps
T13 /workspace/coverage/default/5.prim_async_alert.2426764099 Jan 10 12:28:54 PM PST 24 Jan 10 12:29:13 PM PST 24 11679882 ps
T23 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2874024853 Jan 10 12:20:34 PM PST 24 Jan 10 12:20:50 PM PST 24 31308272 ps
T42 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2360970418 Jan 10 12:20:55 PM PST 24 Jan 10 12:21:01 PM PST 24 31423971 ps
T28 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2667230238 Jan 10 12:21:03 PM PST 24 Jan 10 12:21:06 PM PST 24 28994538 ps
T43 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3945662636 Jan 10 12:20:35 PM PST 24 Jan 10 12:20:50 PM PST 24 29736278 ps
T17 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2007049914 Jan 10 12:20:35 PM PST 24 Jan 10 12:20:50 PM PST 24 30755390 ps
T24 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1767606409 Jan 10 12:20:35 PM PST 24 Jan 10 12:20:50 PM PST 24 29364199 ps
T25 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2946527966 Jan 10 12:20:34 PM PST 24 Jan 10 12:20:50 PM PST 24 30715583 ps
T44 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.667519995 Jan 10 12:20:35 PM PST 24 Jan 10 12:20:51 PM PST 24 32417363 ps
T45 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2931480875 Jan 10 12:20:32 PM PST 24 Jan 10 12:20:48 PM PST 24 31263786 ps
T46 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1176420612 Jan 10 12:20:35 PM PST 24 Jan 10 12:20:51 PM PST 24 29476706 ps
T15 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3106643274 Jan 10 12:20:56 PM PST 24 Jan 10 12:21:01 PM PST 24 31081898 ps
T47 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4076112199 Jan 10 12:20:36 PM PST 24 Jan 10 12:20:52 PM PST 24 29388376 ps
T4 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2914965247 Jan 10 12:20:35 PM PST 24 Jan 10 12:20:50 PM PST 24 30737956 ps
T48 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2038382274 Jan 10 12:20:35 PM PST 24 Jan 10 12:20:51 PM PST 24 30240130 ps
T5 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.49034672 Jan 10 12:20:55 PM PST 24 Jan 10 12:21:00 PM PST 24 30490415 ps
T49 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.305496361 Jan 10 12:20:33 PM PST 24 Jan 10 12:20:49 PM PST 24 30344673 ps
T50 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.819558840 Jan 10 12:20:34 PM PST 24 Jan 10 12:20:49 PM PST 24 30831212 ps
T51 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2916876927 Jan 10 12:20:36 PM PST 24 Jan 10 12:20:52 PM PST 24 31496082 ps
T11 /workspace/coverage/sync_alert/10.prim_sync_alert.365425594 Jan 10 12:54:30 PM PST 24 Jan 10 12:55:34 PM PST 24 8542821 ps
T38 /workspace/coverage/sync_alert/5.prim_sync_alert.3984964520 Jan 10 12:54:18 PM PST 24 Jan 10 12:55:25 PM PST 24 8764048 ps
T39 /workspace/coverage/sync_alert/13.prim_sync_alert.1090319543 Jan 10 12:54:30 PM PST 24 Jan 10 12:55:34 PM PST 24 8363783 ps
T29 /workspace/coverage/sync_alert/1.prim_sync_alert.1613238999 Jan 10 12:54:20 PM PST 24 Jan 10 12:55:27 PM PST 24 9792317 ps
T40 /workspace/coverage/sync_alert/4.prim_sync_alert.2836262492 Jan 10 12:54:18 PM PST 24 Jan 10 12:55:25 PM PST 24 8866498 ps
T41 /workspace/coverage/sync_alert/12.prim_sync_alert.2311311489 Jan 10 12:54:28 PM PST 24 Jan 10 12:55:32 PM PST 24 8120616 ps
T30 /workspace/coverage/sync_alert/18.prim_sync_alert.2108056431 Jan 10 12:54:31 PM PST 24 Jan 10 12:55:35 PM PST 24 9306069 ps
T31 /workspace/coverage/sync_alert/11.prim_sync_alert.3311854517 Jan 10 12:54:28 PM PST 24 Jan 10 12:55:32 PM PST 24 10040406 ps
T32 /workspace/coverage/sync_alert/0.prim_sync_alert.1387729372 Jan 10 12:54:19 PM PST 24 Jan 10 12:55:25 PM PST 24 8572021 ps
T33 /workspace/coverage/sync_alert/7.prim_sync_alert.4236819607 Jan 10 12:54:20 PM PST 24 Jan 10 12:55:27 PM PST 24 9471134 ps
T34 /workspace/coverage/sync_alert/8.prim_sync_alert.2312718634 Jan 10 12:54:18 PM PST 24 Jan 10 12:55:25 PM PST 24 9573573 ps
T35 /workspace/coverage/sync_alert/17.prim_sync_alert.113765563 Jan 10 12:54:32 PM PST 24 Jan 10 12:55:37 PM PST 24 9255641 ps
T36 /workspace/coverage/sync_alert/19.prim_sync_alert.2516854914 Jan 10 12:54:28 PM PST 24 Jan 10 12:55:33 PM PST 24 10104345 ps
T37 /workspace/coverage/sync_alert/6.prim_sync_alert.2021194592 Jan 10 12:54:20 PM PST 24 Jan 10 12:55:26 PM PST 24 8276926 ps
T52 /workspace/coverage/sync_alert/2.prim_sync_alert.156114124 Jan 10 12:54:19 PM PST 24 Jan 10 12:55:25 PM PST 24 9260572 ps
T53 /workspace/coverage/sync_alert/16.prim_sync_alert.4287424969 Jan 10 12:54:31 PM PST 24 Jan 10 12:55:35 PM PST 24 9780152 ps
T54 /workspace/coverage/sync_alert/15.prim_sync_alert.2771696548 Jan 10 12:54:29 PM PST 24 Jan 10 12:55:34 PM PST 24 9097447 ps
T55 /workspace/coverage/sync_alert/9.prim_sync_alert.1920927301 Jan 10 12:54:27 PM PST 24 Jan 10 12:55:32 PM PST 24 9069879 ps
T56 /workspace/coverage/sync_alert/14.prim_sync_alert.2105649912 Jan 10 12:54:28 PM PST 24 Jan 10 12:55:32 PM PST 24 8930855 ps
T57 /workspace/coverage/sync_alert/3.prim_sync_alert.1611480200 Jan 10 12:54:19 PM PST 24 Jan 10 12:55:25 PM PST 24 9091368 ps
T58 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3082518097 Jan 10 12:20:54 PM PST 24 Jan 10 12:21:00 PM PST 24 25766847 ps
T6 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2781146574 Jan 10 12:20:42 PM PST 24 Jan 10 12:20:54 PM PST 24 28507005 ps
T59 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.947857934 Jan 10 12:20:55 PM PST 24 Jan 10 12:21:01 PM PST 24 29713987 ps
T60 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2222564968 Jan 10 12:20:43 PM PST 24 Jan 10 12:20:55 PM PST 24 27495008 ps
T61 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3889599649 Jan 10 12:20:42 PM PST 24 Jan 10 12:20:54 PM PST 24 28106860 ps
T62 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3751155041 Jan 10 12:20:42 PM PST 24 Jan 10 12:20:54 PM PST 24 26620956 ps
T63 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4178607638 Jan 10 12:20:54 PM PST 24 Jan 10 12:21:00 PM PST 24 27623288 ps
T64 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3517901238 Jan 10 12:20:56 PM PST 24 Jan 10 12:21:01 PM PST 24 25547078 ps
T65 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1712069902 Jan 10 12:20:55 PM PST 24 Jan 10 12:21:01 PM PST 24 26554512 ps
T66 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2060153935 Jan 10 12:20:42 PM PST 24 Jan 10 12:20:54 PM PST 24 25038890 ps
T67 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3528881552 Jan 10 12:20:42 PM PST 24 Jan 10 12:20:54 PM PST 24 27270082 ps
T68 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2032773156 Jan 10 12:20:55 PM PST 24 Jan 10 12:21:01 PM PST 24 27463439 ps
T69 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3548080277 Jan 10 12:20:43 PM PST 24 Jan 10 12:20:55 PM PST 24 26186879 ps
T70 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2949447414 Jan 10 12:20:35 PM PST 24 Jan 10 12:20:51 PM PST 24 27718755 ps
T71 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.793969759 Jan 10 12:20:56 PM PST 24 Jan 10 12:21:01 PM PST 24 27678578 ps
T72 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3671059808 Jan 10 12:20:42 PM PST 24 Jan 10 12:20:54 PM PST 24 28902739 ps
T73 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1188692650 Jan 10 12:20:34 PM PST 24 Jan 10 12:20:50 PM PST 24 25480523 ps
T74 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3918074262 Jan 10 12:20:42 PM PST 24 Jan 10 12:20:54 PM PST 24 29102008 ps
T75 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4023048602 Jan 10 12:20:34 PM PST 24 Jan 10 12:20:50 PM PST 24 27926976 ps
T76 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2624034285 Jan 10 12:20:35 PM PST 24 Jan 10 12:20:51 PM PST 24 27993608 ps

Test location /workspace/coverage/default/7.prim_async_alert.3774973966
Short name T10
Test name
Test status
Simulation time 11578754 ps
CPU time 0.42 seconds
Started Jan 10 12:30:20 PM PST 24
Finished Jan 10 12:31:01 PM PST 24
Peak memory 145148 kb
Host smart-008c6455-af85-49e8-8578-eb7d8d8c28d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774973966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3774973966
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1613238999
Short name T29
Test name
Test status
Simulation time 9792317 ps
CPU time 0.37 seconds
Started Jan 10 12:54:20 PM PST 24
Finished Jan 10 12:55:27 PM PST 24
Peak memory 144960 kb
Host smart-d113b5dd-b695-49e6-baba-65fc2a944ca9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1613238999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1613238999
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3945662636
Short name T43
Test name
Test status
Simulation time 29736278 ps
CPU time 0.4 seconds
Started Jan 10 12:20:35 PM PST 24
Finished Jan 10 12:20:50 PM PST 24
Peak memory 145096 kb
Host smart-f06bfd03-1344-4451-a59a-b0fa7529a044
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3945662636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3945662636
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2914965247
Short name T4
Test name
Test status
Simulation time 30737956 ps
CPU time 0.4 seconds
Started Jan 10 12:20:35 PM PST 24
Finished Jan 10 12:20:50 PM PST 24
Peak memory 145728 kb
Host smart-28004d8d-e429-4284-8773-ba11bb0ed34b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2914965247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2914965247
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.365425594
Short name T11
Test name
Test status
Simulation time 8542821 ps
CPU time 0.38 seconds
Started Jan 10 12:54:30 PM PST 24
Finished Jan 10 12:55:34 PM PST 24
Peak memory 144876 kb
Host smart-6a6d4249-e739-425c-a4af-7a2c9fb244e7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=365425594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.365425594
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3322956517
Short name T14
Test name
Test status
Simulation time 11618330 ps
CPU time 0.39 seconds
Started Jan 10 12:28:54 PM PST 24
Finished Jan 10 12:29:12 PM PST 24
Peak memory 145336 kb
Host smart-ae2d4322-7299-46ae-ae5b-bc8c5bcd61e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322956517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3322956517
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3492103829
Short name T22
Test name
Test status
Simulation time 11193847 ps
CPU time 0.38 seconds
Started Jan 10 12:28:05 PM PST 24
Finished Jan 10 12:28:21 PM PST 24
Peak memory 145352 kb
Host smart-d09f9c49-a14d-4944-acb3-120ed9c42bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492103829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3492103829
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.4102202845
Short name T2
Test name
Test status
Simulation time 10675513 ps
CPU time 0.4 seconds
Started Jan 10 12:24:51 PM PST 24
Finished Jan 10 12:24:52 PM PST 24
Peak memory 145384 kb
Host smart-1ed7f5cd-7250-4143-8f9c-0d5bf6bdd735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102202845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.4102202845
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3979983240
Short name T27
Test name
Test status
Simulation time 11313240 ps
CPU time 0.43 seconds
Started Jan 10 12:31:30 PM PST 24
Finished Jan 10 12:32:20 PM PST 24
Peak memory 145144 kb
Host smart-a10f9ba6-07f8-47d1-83c5-83b37ac72bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979983240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3979983240
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.182310491
Short name T16
Test name
Test status
Simulation time 12056837 ps
CPU time 0.43 seconds
Started Jan 10 12:21:39 PM PST 24
Finished Jan 10 12:21:41 PM PST 24
Peak memory 143800 kb
Host smart-69e7a6d2-2300-40bb-bbff-4041f7f2a3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182310491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.182310491
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2064994892
Short name T18
Test name
Test status
Simulation time 10937026 ps
CPU time 0.42 seconds
Started Jan 10 12:28:02 PM PST 24
Finished Jan 10 12:28:18 PM PST 24
Peak memory 145528 kb
Host smart-9c93fc07-1b3d-4c5c-8cbc-184898d59bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064994892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2064994892
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3276936502
Short name T19
Test name
Test status
Simulation time 10406233 ps
CPU time 0.39 seconds
Started Jan 10 12:21:55 PM PST 24
Finished Jan 10 12:21:57 PM PST 24
Peak memory 145528 kb
Host smart-033bf427-12ca-40a4-8f04-05f373b54bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276936502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3276936502
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3051510325
Short name T8
Test name
Test status
Simulation time 11269627 ps
CPU time 0.38 seconds
Started Jan 10 12:28:06 PM PST 24
Finished Jan 10 12:28:22 PM PST 24
Peak memory 145404 kb
Host smart-0699a91d-06ff-405d-8100-ba160b93c7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051510325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3051510325
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1844947462
Short name T1
Test name
Test status
Simulation time 11414440 ps
CPU time 0.39 seconds
Started Jan 10 12:27:07 PM PST 24
Finished Jan 10 12:27:14 PM PST 24
Peak memory 145332 kb
Host smart-b567dd5f-6091-48b6-a611-651b06daa930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844947462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1844947462
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2896115995
Short name T9
Test name
Test status
Simulation time 11698761 ps
CPU time 0.37 seconds
Started Jan 10 12:27:33 PM PST 24
Finished Jan 10 12:27:39 PM PST 24
Peak memory 145336 kb
Host smart-9e730156-efbb-43a1-b288-0e4ca6e311e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896115995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2896115995
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.528561910
Short name T21
Test name
Test status
Simulation time 10589641 ps
CPU time 0.38 seconds
Started Jan 10 12:27:16 PM PST 24
Finished Jan 10 12:27:23 PM PST 24
Peak memory 145384 kb
Host smart-a39f886d-3aef-480f-867d-04cbac0fb09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528561910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.528561910
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3290590401
Short name T3
Test name
Test status
Simulation time 10549237 ps
CPU time 0.37 seconds
Started Jan 10 12:32:01 PM PST 24
Finished Jan 10 12:32:48 PM PST 24
Peak memory 145144 kb
Host smart-901cd2d0-4301-4c6c-b346-1bb383ffeb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290590401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3290590401
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2901710768
Short name T12
Test name
Test status
Simulation time 12248287 ps
CPU time 0.37 seconds
Started Jan 10 12:32:18 PM PST 24
Finished Jan 10 12:32:58 PM PST 24
Peak memory 145144 kb
Host smart-cbd103a2-6c49-4214-9026-d0ab665347f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901710768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2901710768
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2426764099
Short name T13
Test name
Test status
Simulation time 11679882 ps
CPU time 0.47 seconds
Started Jan 10 12:28:54 PM PST 24
Finished Jan 10 12:29:13 PM PST 24
Peak memory 145340 kb
Host smart-9bd14e26-40e7-4da7-8651-c7e71362de70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426764099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2426764099
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3785000763
Short name T26
Test name
Test status
Simulation time 11216412 ps
CPU time 0.38 seconds
Started Jan 10 12:28:09 PM PST 24
Finished Jan 10 12:28:24 PM PST 24
Peak memory 145428 kb
Host smart-357c861b-7576-4489-8bc4-e81f89d57ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785000763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3785000763
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.13188317
Short name T20
Test name
Test status
Simulation time 11617772 ps
CPU time 0.38 seconds
Started Jan 10 12:26:12 PM PST 24
Finished Jan 10 12:26:17 PM PST 24
Peak memory 145444 kb
Host smart-8820d978-13fc-4598-b404-ac6a91c9c51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13188317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.13188317
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3715691267
Short name T7
Test name
Test status
Simulation time 11106709 ps
CPU time 0.41 seconds
Started Jan 10 12:21:39 PM PST 24
Finished Jan 10 12:21:41 PM PST 24
Peak memory 143748 kb
Host smart-ef092aa2-49a2-4370-9135-4bf68b0657e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715691267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3715691267
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.305496361
Short name T49
Test name
Test status
Simulation time 30344673 ps
CPU time 0.4 seconds
Started Jan 10 12:20:33 PM PST 24
Finished Jan 10 12:20:49 PM PST 24
Peak memory 145720 kb
Host smart-e6f4e428-16cd-498d-99b5-59509841c774
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=305496361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.305496361
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1767606409
Short name T24
Test name
Test status
Simulation time 29364199 ps
CPU time 0.4 seconds
Started Jan 10 12:20:35 PM PST 24
Finished Jan 10 12:20:50 PM PST 24
Peak memory 145624 kb
Host smart-f4a2c248-9e03-439d-bda1-ab20340d11c1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1767606409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1767606409
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2916876927
Short name T51
Test name
Test status
Simulation time 31496082 ps
CPU time 0.39 seconds
Started Jan 10 12:20:36 PM PST 24
Finished Jan 10 12:20:52 PM PST 24
Peak memory 145028 kb
Host smart-3b3fedfc-936d-496e-bcbf-a5474e711a7a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2916876927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2916876927
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.667519995
Short name T44
Test name
Test status
Simulation time 32417363 ps
CPU time 0.4 seconds
Started Jan 10 12:20:35 PM PST 24
Finished Jan 10 12:20:51 PM PST 24
Peak memory 145176 kb
Host smart-8e9c9fd6-ae7c-43cd-a263-f71cfaab33c2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=667519995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.667519995
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2038382274
Short name T48
Test name
Test status
Simulation time 30240130 ps
CPU time 0.4 seconds
Started Jan 10 12:20:35 PM PST 24
Finished Jan 10 12:20:51 PM PST 24
Peak memory 144996 kb
Host smart-a6ff59a8-7384-4e2c-b94e-d37ceec9295b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2038382274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2038382274
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2946527966
Short name T25
Test name
Test status
Simulation time 30715583 ps
CPU time 0.45 seconds
Started Jan 10 12:20:34 PM PST 24
Finished Jan 10 12:20:50 PM PST 24
Peak memory 145388 kb
Host smart-557032ab-b9fa-4439-be16-950631db995b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2946527966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2946527966
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3106643274
Short name T15
Test name
Test status
Simulation time 31081898 ps
CPU time 0.41 seconds
Started Jan 10 12:20:56 PM PST 24
Finished Jan 10 12:21:01 PM PST 24
Peak memory 145048 kb
Host smart-a115f53a-f744-45e4-b28c-e332eed2190c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3106643274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3106643274
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2931480875
Short name T45
Test name
Test status
Simulation time 31263786 ps
CPU time 0.39 seconds
Started Jan 10 12:20:32 PM PST 24
Finished Jan 10 12:20:48 PM PST 24
Peak memory 145624 kb
Host smart-000e1d7e-355b-4f59-bc01-9ef82b5a9436
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2931480875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2931480875
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.49034672
Short name T5
Test name
Test status
Simulation time 30490415 ps
CPU time 0.42 seconds
Started Jan 10 12:20:55 PM PST 24
Finished Jan 10 12:21:00 PM PST 24
Peak memory 145472 kb
Host smart-a3d460e2-31ac-4732-9a94-2468c4b3cb48
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=49034672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.49034672
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2007049914
Short name T17
Test name
Test status
Simulation time 30755390 ps
CPU time 0.4 seconds
Started Jan 10 12:20:35 PM PST 24
Finished Jan 10 12:20:50 PM PST 24
Peak memory 145088 kb
Host smart-c8f7a310-8f47-479d-a981-40d91b1c2aa9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2007049914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2007049914
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2874024853
Short name T23
Test name
Test status
Simulation time 31308272 ps
CPU time 0.4 seconds
Started Jan 10 12:20:34 PM PST 24
Finished Jan 10 12:20:50 PM PST 24
Peak memory 145728 kb
Host smart-db4e3cee-663b-4c52-b5ba-d2637fe9cb30
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2874024853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2874024853
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.819558840
Short name T50
Test name
Test status
Simulation time 30831212 ps
CPU time 0.39 seconds
Started Jan 10 12:20:34 PM PST 24
Finished Jan 10 12:20:49 PM PST 24
Peak memory 145632 kb
Host smart-b1d0c54c-c76b-45f3-9967-7d5edbd35255
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=819558840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.819558840
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2667230238
Short name T28
Test name
Test status
Simulation time 28994538 ps
CPU time 0.46 seconds
Started Jan 10 12:21:03 PM PST 24
Finished Jan 10 12:21:06 PM PST 24
Peak memory 144996 kb
Host smart-79869e44-1561-4756-8e4f-f7d34604c7b3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2667230238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2667230238
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4076112199
Short name T47
Test name
Test status
Simulation time 29388376 ps
CPU time 0.41 seconds
Started Jan 10 12:20:36 PM PST 24
Finished Jan 10 12:20:52 PM PST 24
Peak memory 145132 kb
Host smart-9d6be601-a984-43c3-a03a-ccb1f53d1472
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4076112199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.4076112199
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1176420612
Short name T46
Test name
Test status
Simulation time 29476706 ps
CPU time 0.4 seconds
Started Jan 10 12:20:35 PM PST 24
Finished Jan 10 12:20:51 PM PST 24
Peak memory 145348 kb
Host smart-7b9a08a7-6047-4894-8d9c-d5d08ac0fadb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1176420612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1176420612
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2360970418
Short name T42
Test name
Test status
Simulation time 31423971 ps
CPU time 0.38 seconds
Started Jan 10 12:20:55 PM PST 24
Finished Jan 10 12:21:01 PM PST 24
Peak memory 144976 kb
Host smart-d900f8c2-4bcf-4374-afa5-adb7e24edcbc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2360970418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2360970418
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1387729372
Short name T32
Test name
Test status
Simulation time 8572021 ps
CPU time 0.38 seconds
Started Jan 10 12:54:19 PM PST 24
Finished Jan 10 12:55:25 PM PST 24
Peak memory 144924 kb
Host smart-69bbe0e9-c429-49c7-b005-5da50ddd441a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1387729372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1387729372
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3311854517
Short name T31
Test name
Test status
Simulation time 10040406 ps
CPU time 0.38 seconds
Started Jan 10 12:54:28 PM PST 24
Finished Jan 10 12:55:32 PM PST 24
Peak memory 144928 kb
Host smart-e6d1d15e-72e7-44a9-99e2-30c1858df7e6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3311854517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3311854517
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2311311489
Short name T41
Test name
Test status
Simulation time 8120616 ps
CPU time 0.38 seconds
Started Jan 10 12:54:28 PM PST 24
Finished Jan 10 12:55:32 PM PST 24
Peak memory 144928 kb
Host smart-8c312897-0dd6-4351-a1b1-b74316151227
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2311311489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2311311489
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1090319543
Short name T39
Test name
Test status
Simulation time 8363783 ps
CPU time 0.38 seconds
Started Jan 10 12:54:30 PM PST 24
Finished Jan 10 12:55:34 PM PST 24
Peak memory 144892 kb
Host smart-51011a11-01c4-4459-a3c4-700e1f2fef33
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1090319543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1090319543
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2105649912
Short name T56
Test name
Test status
Simulation time 8930855 ps
CPU time 0.4 seconds
Started Jan 10 12:54:28 PM PST 24
Finished Jan 10 12:55:32 PM PST 24
Peak memory 144988 kb
Host smart-8309239b-0318-4630-8387-b5e0c23c6e19
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2105649912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2105649912
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2771696548
Short name T54
Test name
Test status
Simulation time 9097447 ps
CPU time 0.38 seconds
Started Jan 10 12:54:29 PM PST 24
Finished Jan 10 12:55:34 PM PST 24
Peak memory 144932 kb
Host smart-f79ac790-d425-49e2-a80a-3dce8e5ce914
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2771696548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2771696548
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.4287424969
Short name T53
Test name
Test status
Simulation time 9780152 ps
CPU time 0.37 seconds
Started Jan 10 12:54:31 PM PST 24
Finished Jan 10 12:55:35 PM PST 24
Peak memory 144920 kb
Host smart-8f436cf8-48a7-4559-a619-59a3b6447625
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4287424969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.4287424969
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.113765563
Short name T35
Test name
Test status
Simulation time 9255641 ps
CPU time 0.39 seconds
Started Jan 10 12:54:32 PM PST 24
Finished Jan 10 12:55:37 PM PST 24
Peak memory 144888 kb
Host smart-08f3fdfb-85e1-4243-bd82-518112dab276
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=113765563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.113765563
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2108056431
Short name T30
Test name
Test status
Simulation time 9306069 ps
CPU time 0.4 seconds
Started Jan 10 12:54:31 PM PST 24
Finished Jan 10 12:55:35 PM PST 24
Peak memory 145000 kb
Host smart-b4e13fc3-1f28-4608-b697-bd9c5849cc5d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2108056431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2108056431
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2516854914
Short name T36
Test name
Test status
Simulation time 10104345 ps
CPU time 0.39 seconds
Started Jan 10 12:54:28 PM PST 24
Finished Jan 10 12:55:33 PM PST 24
Peak memory 144992 kb
Host smart-db89dd8b-2ac0-41ed-a286-2a88373d815f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2516854914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2516854914
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.156114124
Short name T52
Test name
Test status
Simulation time 9260572 ps
CPU time 0.41 seconds
Started Jan 10 12:54:19 PM PST 24
Finished Jan 10 12:55:25 PM PST 24
Peak memory 144948 kb
Host smart-d931c386-f7fe-4fd8-971c-0774b18ac101
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=156114124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.156114124
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1611480200
Short name T57
Test name
Test status
Simulation time 9091368 ps
CPU time 0.38 seconds
Started Jan 10 12:54:19 PM PST 24
Finished Jan 10 12:55:25 PM PST 24
Peak memory 144836 kb
Host smart-fac4410c-3752-4b71-8998-02ca743b1e4b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1611480200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1611480200
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2836262492
Short name T40
Test name
Test status
Simulation time 8866498 ps
CPU time 0.38 seconds
Started Jan 10 12:54:18 PM PST 24
Finished Jan 10 12:55:25 PM PST 24
Peak memory 144956 kb
Host smart-13e724c3-7a3c-4b5f-a0a6-09417b0fbb33
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2836262492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2836262492
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3984964520
Short name T38
Test name
Test status
Simulation time 8764048 ps
CPU time 0.39 seconds
Started Jan 10 12:54:18 PM PST 24
Finished Jan 10 12:55:25 PM PST 24
Peak memory 145004 kb
Host smart-0a449520-030f-4004-a97c-b66b90c6cdc3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3984964520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3984964520
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2021194592
Short name T37
Test name
Test status
Simulation time 8276926 ps
CPU time 0.38 seconds
Started Jan 10 12:54:20 PM PST 24
Finished Jan 10 12:55:26 PM PST 24
Peak memory 144856 kb
Host smart-d1e9dbf8-9c36-41a8-a564-4b48687f181c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2021194592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2021194592
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.4236819607
Short name T33
Test name
Test status
Simulation time 9471134 ps
CPU time 0.38 seconds
Started Jan 10 12:54:20 PM PST 24
Finished Jan 10 12:55:27 PM PST 24
Peak memory 145004 kb
Host smart-11a742d8-7345-4980-813e-3f20a82e84a5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4236819607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.4236819607
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2312718634
Short name T34
Test name
Test status
Simulation time 9573573 ps
CPU time 0.38 seconds
Started Jan 10 12:54:18 PM PST 24
Finished Jan 10 12:55:25 PM PST 24
Peak memory 144964 kb
Host smart-ef3321d6-e19a-4701-b58f-6307ee12d566
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2312718634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2312718634
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1920927301
Short name T55
Test name
Test status
Simulation time 9069879 ps
CPU time 0.38 seconds
Started Jan 10 12:54:27 PM PST 24
Finished Jan 10 12:55:32 PM PST 24
Peak memory 144972 kb
Host smart-79860e69-ca0d-42c6-9c8c-3009cefdf53c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1920927301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1920927301
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2624034285
Short name T76
Test name
Test status
Simulation time 27993608 ps
CPU time 0.39 seconds
Started Jan 10 12:20:35 PM PST 24
Finished Jan 10 12:20:51 PM PST 24
Peak memory 144432 kb
Host smart-8282e1cc-e8a4-4482-b82c-927d12731a8d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2624034285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2624034285
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4023048602
Short name T75
Test name
Test status
Simulation time 27926976 ps
CPU time 0.4 seconds
Started Jan 10 12:20:34 PM PST 24
Finished Jan 10 12:20:50 PM PST 24
Peak memory 144112 kb
Host smart-07352e7b-ec12-49d8-8c76-eecc5ad7a7e2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4023048602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.4023048602
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2781146574
Short name T6
Test name
Test status
Simulation time 28507005 ps
CPU time 0.41 seconds
Started Jan 10 12:20:42 PM PST 24
Finished Jan 10 12:20:54 PM PST 24
Peak memory 145096 kb
Host smart-abe89201-3a41-4131-b751-94bb496be846
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2781146574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2781146574
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3548080277
Short name T69
Test name
Test status
Simulation time 26186879 ps
CPU time 0.41 seconds
Started Jan 10 12:20:43 PM PST 24
Finished Jan 10 12:20:55 PM PST 24
Peak memory 145092 kb
Host smart-78bc881e-dd0a-452e-b580-448ed40ec70b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3548080277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3548080277
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3082518097
Short name T58
Test name
Test status
Simulation time 25766847 ps
CPU time 0.42 seconds
Started Jan 10 12:20:54 PM PST 24
Finished Jan 10 12:21:00 PM PST 24
Peak memory 144356 kb
Host smart-5ef3d070-5d6b-4ec9-8016-ea242f37b605
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3082518097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3082518097
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2060153935
Short name T66
Test name
Test status
Simulation time 25038890 ps
CPU time 0.4 seconds
Started Jan 10 12:20:42 PM PST 24
Finished Jan 10 12:20:54 PM PST 24
Peak memory 145096 kb
Host smart-4c9cd64e-f9bc-4b05-bbf9-7fc0a477eb2d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2060153935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2060153935
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2222564968
Short name T60
Test name
Test status
Simulation time 27495008 ps
CPU time 0.39 seconds
Started Jan 10 12:20:43 PM PST 24
Finished Jan 10 12:20:55 PM PST 24
Peak memory 145092 kb
Host smart-cfcb6835-5a08-42d9-9230-6f8e674baf33
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2222564968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2222564968
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3751155041
Short name T62
Test name
Test status
Simulation time 26620956 ps
CPU time 0.4 seconds
Started Jan 10 12:20:42 PM PST 24
Finished Jan 10 12:20:54 PM PST 24
Peak memory 145096 kb
Host smart-e1830503-454c-4f20-9dd0-4fe4e2bc9c54
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3751155041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3751155041
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1712069902
Short name T65
Test name
Test status
Simulation time 26554512 ps
CPU time 0.38 seconds
Started Jan 10 12:20:55 PM PST 24
Finished Jan 10 12:21:01 PM PST 24
Peak memory 144400 kb
Host smart-a5822843-0d23-41f9-812f-d493855b55a5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1712069902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1712069902
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2032773156
Short name T68
Test name
Test status
Simulation time 27463439 ps
CPU time 0.37 seconds
Started Jan 10 12:20:55 PM PST 24
Finished Jan 10 12:21:01 PM PST 24
Peak memory 144420 kb
Host smart-b7c7e54f-1c1a-4517-bd4b-5c6cd32237bc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2032773156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2032773156
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2949447414
Short name T70
Test name
Test status
Simulation time 27718755 ps
CPU time 0.4 seconds
Started Jan 10 12:20:35 PM PST 24
Finished Jan 10 12:20:51 PM PST 24
Peak memory 145068 kb
Host smart-9e663f11-3015-40cc-8f7f-5d72862cc5ac
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2949447414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2949447414
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3918074262
Short name T74
Test name
Test status
Simulation time 29102008 ps
CPU time 0.41 seconds
Started Jan 10 12:20:42 PM PST 24
Finished Jan 10 12:20:54 PM PST 24
Peak memory 145096 kb
Host smart-5c8bfac3-d35d-4cf5-9a1f-72d255f3ff72
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3918074262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3918074262
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3517901238
Short name T64
Test name
Test status
Simulation time 25547078 ps
CPU time 0.4 seconds
Started Jan 10 12:20:56 PM PST 24
Finished Jan 10 12:21:01 PM PST 24
Peak memory 144432 kb
Host smart-9d9e290a-8ecc-4380-8db8-4bf55e153cf0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3517901238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3517901238
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3671059808
Short name T72
Test name
Test status
Simulation time 28902739 ps
CPU time 0.4 seconds
Started Jan 10 12:20:42 PM PST 24
Finished Jan 10 12:20:54 PM PST 24
Peak memory 145108 kb
Host smart-c2b77458-8424-48fc-87af-d7e9400801ea
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3671059808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3671059808
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3528881552
Short name T67
Test name
Test status
Simulation time 27270082 ps
CPU time 0.39 seconds
Started Jan 10 12:20:42 PM PST 24
Finished Jan 10 12:20:54 PM PST 24
Peak memory 145108 kb
Host smart-ede50c56-1d13-4f74-b6b4-d3cd01f80ece
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3528881552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3528881552
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4178607638
Short name T63
Test name
Test status
Simulation time 27623288 ps
CPU time 0.41 seconds
Started Jan 10 12:20:54 PM PST 24
Finished Jan 10 12:21:00 PM PST 24
Peak memory 144644 kb
Host smart-caac9293-4d19-4dc7-8056-a833b839f3cb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4178607638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.4178607638
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.793969759
Short name T71
Test name
Test status
Simulation time 27678578 ps
CPU time 0.39 seconds
Started Jan 10 12:20:56 PM PST 24
Finished Jan 10 12:21:01 PM PST 24
Peak memory 144432 kb
Host smart-35e2f24b-cf14-4517-8f8d-c472505e5d43
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=793969759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.793969759
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.947857934
Short name T59
Test name
Test status
Simulation time 29713987 ps
CPU time 0.38 seconds
Started Jan 10 12:20:55 PM PST 24
Finished Jan 10 12:21:01 PM PST 24
Peak memory 144420 kb
Host smart-6e21b475-eeeb-4bbb-9137-638385571ded
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=947857934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.947857934
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3889599649
Short name T61
Test name
Test status
Simulation time 28106860 ps
CPU time 0.41 seconds
Started Jan 10 12:20:42 PM PST 24
Finished Jan 10 12:20:54 PM PST 24
Peak memory 145108 kb
Host smart-5f8a4252-d8e9-4845-9e61-cb50ca6d2427
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3889599649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3889599649
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1188692650
Short name T73
Test name
Test status
Simulation time 25480523 ps
CPU time 0.43 seconds
Started Jan 10 12:20:34 PM PST 24
Finished Jan 10 12:20:50 PM PST 24
Peak memory 143572 kb
Host smart-00f28caa-e7fd-40d9-b3bb-9a86209ded93
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1188692650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1188692650
Directory /workspace/9.prim_sync_fatal_alert/latest
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