Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.42 88.42 100.00 100.00 95.83 95.83 96.43 96.43 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/5.prim_async_alert.3275918156
92.15 3.72 100.00 0.00 95.83 0.00 96.43 0.00 85.71 10.71 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/12.prim_sync_alert.2453928868
94.25 2.11 100.00 0.00 97.92 2.08 100.00 3.57 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3862467354
94.85 0.60 100.00 0.00 97.92 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/19.prim_async_alert.3037385165

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1465939209
/workspace/coverage/default/1.prim_async_alert.2450270526
/workspace/coverage/default/10.prim_async_alert.3409189081
/workspace/coverage/default/11.prim_async_alert.4016516265
/workspace/coverage/default/12.prim_async_alert.2642423037
/workspace/coverage/default/13.prim_async_alert.639241449
/workspace/coverage/default/14.prim_async_alert.1650622875
/workspace/coverage/default/15.prim_async_alert.1473971251
/workspace/coverage/default/16.prim_async_alert.2780642117
/workspace/coverage/default/17.prim_async_alert.2091723263
/workspace/coverage/default/18.prim_async_alert.317374040
/workspace/coverage/default/2.prim_async_alert.4096643896
/workspace/coverage/default/3.prim_async_alert.2403132978
/workspace/coverage/default/4.prim_async_alert.1072467236
/workspace/coverage/default/6.prim_async_alert.3798826228
/workspace/coverage/default/7.prim_async_alert.1041896254
/workspace/coverage/default/8.prim_async_alert.4061613008
/workspace/coverage/default/9.prim_async_alert.2995121455
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1022789255
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3341081535
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2244450974
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1244303480
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1631216387
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2900443379
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.221469284
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2238370828
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1236548518
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4211255422
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.796925510
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4047317923
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.840887687
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.674136121
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.152728423
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.960876949
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1403137212
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2678279387
/workspace/coverage/sync_alert/0.prim_sync_alert.4064730785
/workspace/coverage/sync_alert/1.prim_sync_alert.1681993918
/workspace/coverage/sync_alert/10.prim_sync_alert.2597061314
/workspace/coverage/sync_alert/11.prim_sync_alert.2086319477
/workspace/coverage/sync_alert/13.prim_sync_alert.2049376875
/workspace/coverage/sync_alert/14.prim_sync_alert.2871226960
/workspace/coverage/sync_alert/15.prim_sync_alert.2781433859
/workspace/coverage/sync_alert/16.prim_sync_alert.4117891125
/workspace/coverage/sync_alert/17.prim_sync_alert.937645479
/workspace/coverage/sync_alert/18.prim_sync_alert.1348004342
/workspace/coverage/sync_alert/19.prim_sync_alert.3239997428
/workspace/coverage/sync_alert/2.prim_sync_alert.3916792332
/workspace/coverage/sync_alert/3.prim_sync_alert.1452852111
/workspace/coverage/sync_alert/4.prim_sync_alert.2679238165
/workspace/coverage/sync_alert/5.prim_sync_alert.2515039427
/workspace/coverage/sync_alert/6.prim_sync_alert.4271204560
/workspace/coverage/sync_alert/7.prim_sync_alert.3658532686
/workspace/coverage/sync_alert/8.prim_sync_alert.1824968206
/workspace/coverage/sync_alert/9.prim_sync_alert.2821001384
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2278237092
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4065319674
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4227056228
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2676152453
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1347992827
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.356645980
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1139165794
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4269215539
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1118187234
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.269496242
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1974665378
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3712728259
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2560067582
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3543990152
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2950275532
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2344949592
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.619151658
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3300817746
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3521599150
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.444516877



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/16.prim_async_alert.2780642117 Jan 14 12:54:00 PM PST 24 Jan 14 12:54:01 PM PST 24 11099257 ps
T2 /workspace/coverage/default/19.prim_async_alert.3037385165 Jan 14 12:54:13 PM PST 24 Jan 14 12:54:14 PM PST 24 11985904 ps
T3 /workspace/coverage/default/15.prim_async_alert.1473971251 Jan 14 12:53:58 PM PST 24 Jan 14 12:53:59 PM PST 24 11215168 ps
T7 /workspace/coverage/default/5.prim_async_alert.3275918156 Jan 14 12:53:46 PM PST 24 Jan 14 12:53:47 PM PST 24 11531653 ps
T8 /workspace/coverage/default/2.prim_async_alert.4096643896 Jan 14 12:53:37 PM PST 24 Jan 14 12:53:38 PM PST 24 11638812 ps
T19 /workspace/coverage/default/4.prim_async_alert.1072467236 Jan 14 12:53:45 PM PST 24 Jan 14 12:53:46 PM PST 24 11555055 ps
T9 /workspace/coverage/default/3.prim_async_alert.2403132978 Jan 14 12:53:46 PM PST 24 Jan 14 12:53:47 PM PST 24 12139733 ps
T20 /workspace/coverage/default/13.prim_async_alert.639241449 Jan 14 12:54:02 PM PST 24 Jan 14 12:54:04 PM PST 24 11555823 ps
T21 /workspace/coverage/default/18.prim_async_alert.317374040 Jan 14 12:54:12 PM PST 24 Jan 14 12:54:13 PM PST 24 11066821 ps
T16 /workspace/coverage/default/8.prim_async_alert.4061613008 Jan 14 12:53:52 PM PST 24 Jan 14 12:53:53 PM PST 24 10908643 ps
T42 /workspace/coverage/default/11.prim_async_alert.4016516265 Jan 14 12:54:03 PM PST 24 Jan 14 12:54:04 PM PST 24 10835412 ps
T13 /workspace/coverage/default/1.prim_async_alert.2450270526 Jan 14 12:53:37 PM PST 24 Jan 14 12:53:38 PM PST 24 11271418 ps
T43 /workspace/coverage/default/14.prim_async_alert.1650622875 Jan 14 12:54:00 PM PST 24 Jan 14 12:54:01 PM PST 24 11571230 ps
T44 /workspace/coverage/default/9.prim_async_alert.2995121455 Jan 14 12:53:54 PM PST 24 Jan 14 12:53:55 PM PST 24 11602498 ps
T36 /workspace/coverage/default/0.prim_async_alert.1465939209 Jan 14 12:53:36 PM PST 24 Jan 14 12:53:37 PM PST 24 10637841 ps
T17 /workspace/coverage/default/7.prim_async_alert.1041896254 Jan 14 12:53:52 PM PST 24 Jan 14 12:53:53 PM PST 24 11254780 ps
T45 /workspace/coverage/default/10.prim_async_alert.3409189081 Jan 14 12:53:52 PM PST 24 Jan 14 12:53:53 PM PST 24 10489683 ps
T22 /workspace/coverage/default/12.prim_async_alert.2642423037 Jan 14 12:54:00 PM PST 24 Jan 14 12:54:01 PM PST 24 10588721 ps
T18 /workspace/coverage/default/17.prim_async_alert.2091723263 Jan 14 12:54:10 PM PST 24 Jan 14 12:54:11 PM PST 24 11774765 ps
T46 /workspace/coverage/default/6.prim_async_alert.3798826228 Jan 14 12:53:53 PM PST 24 Jan 14 12:53:54 PM PST 24 10667686 ps
T10 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2238370828 Jan 14 12:54:18 PM PST 24 Jan 14 12:54:23 PM PST 24 29901995 ps
T14 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2900443379 Jan 14 12:54:18 PM PST 24 Jan 14 12:54:23 PM PST 24 30524452 ps
T15 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4047317923 Jan 14 12:54:28 PM PST 24 Jan 14 12:54:32 PM PST 24 30728189 ps
T37 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2244450974 Jan 14 12:54:10 PM PST 24 Jan 14 12:54:11 PM PST 24 31181201 ps
T4 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3862467354 Jan 14 12:54:09 PM PST 24 Jan 14 12:54:10 PM PST 24 29657046 ps
T38 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.221469284 Jan 14 12:54:15 PM PST 24 Jan 14 12:54:17 PM PST 24 29065310 ps
T39 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1244303480 Jan 14 12:54:17 PM PST 24 Jan 14 12:54:22 PM PST 24 30541830 ps
T40 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2678279387 Jan 14 12:54:10 PM PST 24 Jan 14 12:54:11 PM PST 24 28962642 ps
T41 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1403137212 Jan 14 12:54:12 PM PST 24 Jan 14 12:54:13 PM PST 24 29588480 ps
T11 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1236548518 Jan 14 12:54:18 PM PST 24 Jan 14 12:54:23 PM PST 24 31367546 ps
T47 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1022789255 Jan 14 12:54:12 PM PST 24 Jan 14 12:54:13 PM PST 24 28985704 ps
T48 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.796925510 Jan 14 12:54:27 PM PST 24 Jan 14 12:54:31 PM PST 24 28685177 ps
T49 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.960876949 Jan 14 12:54:09 PM PST 24 Jan 14 12:54:10 PM PST 24 29456752 ps
T12 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4211255422 Jan 14 12:54:27 PM PST 24 Jan 14 12:54:31 PM PST 24 30371110 ps
T50 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3341081535 Jan 14 12:54:12 PM PST 24 Jan 14 12:54:13 PM PST 24 30728073 ps
T51 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1631216387 Jan 14 12:54:17 PM PST 24 Jan 14 12:54:18 PM PST 24 31470644 ps
T52 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.152728423 Jan 14 12:54:09 PM PST 24 Jan 14 12:54:10 PM PST 24 30325980 ps
T53 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.674136121 Jan 14 12:54:14 PM PST 24 Jan 14 12:54:15 PM PST 24 28536656 ps
T54 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.840887687 Jan 14 12:54:13 PM PST 24 Jan 14 12:54:14 PM PST 24 31137975 ps
T23 /workspace/coverage/sync_alert/11.prim_sync_alert.2086319477 Jan 14 12:58:30 PM PST 24 Jan 14 12:58:31 PM PST 24 8980931 ps
T33 /workspace/coverage/sync_alert/4.prim_sync_alert.2679238165 Jan 14 12:58:18 PM PST 24 Jan 14 12:58:19 PM PST 24 10012080 ps
T34 /workspace/coverage/sync_alert/19.prim_sync_alert.3239997428 Jan 14 12:58:26 PM PST 24 Jan 14 12:58:27 PM PST 24 8999575 ps
T35 /workspace/coverage/sync_alert/12.prim_sync_alert.2453928868 Jan 14 12:58:30 PM PST 24 Jan 14 12:58:31 PM PST 24 10023477 ps
T24 /workspace/coverage/sync_alert/6.prim_sync_alert.4271204560 Jan 14 12:58:19 PM PST 24 Jan 14 12:58:20 PM PST 24 9267083 ps
T25 /workspace/coverage/sync_alert/3.prim_sync_alert.1452852111 Jan 14 12:58:14 PM PST 24 Jan 14 12:58:14 PM PST 24 9393257 ps
T26 /workspace/coverage/sync_alert/2.prim_sync_alert.3916792332 Jan 14 12:58:16 PM PST 24 Jan 14 12:58:17 PM PST 24 8688212 ps
T27 /workspace/coverage/sync_alert/14.prim_sync_alert.2871226960 Jan 14 12:58:27 PM PST 24 Jan 14 12:58:28 PM PST 24 9408343 ps
T28 /workspace/coverage/sync_alert/15.prim_sync_alert.2781433859 Jan 14 12:58:26 PM PST 24 Jan 14 12:58:27 PM PST 24 8797251 ps
T29 /workspace/coverage/sync_alert/13.prim_sync_alert.2049376875 Jan 14 12:58:26 PM PST 24 Jan 14 12:58:27 PM PST 24 9695854 ps
T30 /workspace/coverage/sync_alert/0.prim_sync_alert.4064730785 Jan 14 12:58:12 PM PST 24 Jan 14 12:58:13 PM PST 24 9244041 ps
T31 /workspace/coverage/sync_alert/17.prim_sync_alert.937645479 Jan 14 12:58:27 PM PST 24 Jan 14 12:58:29 PM PST 24 9939223 ps
T32 /workspace/coverage/sync_alert/7.prim_sync_alert.3658532686 Jan 14 12:58:26 PM PST 24 Jan 14 12:58:27 PM PST 24 9391468 ps
T55 /workspace/coverage/sync_alert/8.prim_sync_alert.1824968206 Jan 14 12:58:26 PM PST 24 Jan 14 12:58:28 PM PST 24 10099096 ps
T56 /workspace/coverage/sync_alert/16.prim_sync_alert.4117891125 Jan 14 12:58:26 PM PST 24 Jan 14 12:58:27 PM PST 24 9157235 ps
T57 /workspace/coverage/sync_alert/10.prim_sync_alert.2597061314 Jan 14 12:58:28 PM PST 24 Jan 14 12:58:29 PM PST 24 9543594 ps
T58 /workspace/coverage/sync_alert/18.prim_sync_alert.1348004342 Jan 14 12:58:29 PM PST 24 Jan 14 12:58:30 PM PST 24 10143813 ps
T59 /workspace/coverage/sync_alert/1.prim_sync_alert.1681993918 Jan 14 12:58:13 PM PST 24 Jan 14 12:58:14 PM PST 24 10141744 ps
T60 /workspace/coverage/sync_alert/5.prim_sync_alert.2515039427 Jan 14 12:58:19 PM PST 24 Jan 14 12:58:20 PM PST 24 10183748 ps
T61 /workspace/coverage/sync_alert/9.prim_sync_alert.2821001384 Jan 14 12:58:26 PM PST 24 Jan 14 12:58:27 PM PST 24 10217338 ps
T62 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.444516877 Jan 14 12:58:08 PM PST 24 Jan 14 12:58:09 PM PST 24 27135977 ps
T63 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1118187234 Jan 14 12:58:12 PM PST 24 Jan 14 12:58:13 PM PST 24 26163262 ps
T64 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2560067582 Jan 14 12:58:06 PM PST 24 Jan 14 12:58:07 PM PST 24 25900592 ps
T65 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.356645980 Jan 14 12:58:05 PM PST 24 Jan 14 12:58:06 PM PST 24 27537792 ps
T66 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2344949592 Jan 14 12:58:05 PM PST 24 Jan 14 12:58:06 PM PST 24 27586153 ps
T67 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.619151658 Jan 14 12:58:06 PM PST 24 Jan 14 12:58:07 PM PST 24 28590894 ps
T5 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4065319674 Jan 14 12:58:07 PM PST 24 Jan 14 12:58:08 PM PST 24 25514473 ps
T68 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2950275532 Jan 14 12:58:08 PM PST 24 Jan 14 12:58:09 PM PST 24 28989745 ps
T69 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.269496242 Jan 14 12:58:10 PM PST 24 Jan 14 12:58:10 PM PST 24 27785334 ps
T70 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1974665378 Jan 14 12:58:11 PM PST 24 Jan 14 12:58:12 PM PST 24 27990043 ps
T71 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2278237092 Jan 14 12:58:07 PM PST 24 Jan 14 12:58:07 PM PST 24 26753469 ps
T6 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1139165794 Jan 14 12:58:09 PM PST 24 Jan 14 12:58:10 PM PST 24 28034414 ps
T72 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3300817746 Jan 14 12:58:08 PM PST 24 Jan 14 12:58:09 PM PST 24 24547025 ps
T73 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1347992827 Jan 14 12:58:07 PM PST 24 Jan 14 12:58:07 PM PST 24 28747726 ps
T74 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4269215539 Jan 14 12:58:11 PM PST 24 Jan 14 12:58:12 PM PST 24 26436875 ps
T75 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3521599150 Jan 14 12:58:11 PM PST 24 Jan 14 12:58:12 PM PST 24 27185848 ps
T76 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3712728259 Jan 14 12:58:08 PM PST 24 Jan 14 12:58:09 PM PST 24 27871710 ps
T77 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2676152453 Jan 14 12:58:08 PM PST 24 Jan 14 12:58:09 PM PST 24 26648893 ps
T78 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4227056228 Jan 14 12:58:12 PM PST 24 Jan 14 12:58:13 PM PST 24 28257585 ps
T79 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3543990152 Jan 14 12:58:08 PM PST 24 Jan 14 12:58:09 PM PST 24 28095347 ps

Test location /workspace/coverage/default/5.prim_async_alert.3275918156
Short name T7
Test name
Test status
Simulation time 11531653 ps
CPU time 0.39 seconds
Started Jan 14 12:53:46 PM PST 24
Finished Jan 14 12:53:47 PM PST 24
Peak memory 145452 kb
Host smart-7464d9c8-69d0-45a8-aba9-c876a32ca541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275918156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3275918156
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2453928868
Short name T35
Test name
Test status
Simulation time 10023477 ps
CPU time 0.39 seconds
Started Jan 14 12:58:30 PM PST 24
Finished Jan 14 12:58:31 PM PST 24
Peak memory 144364 kb
Host smart-828c804c-b09b-47be-8fb0-4ac927e40ce7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2453928868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2453928868
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3862467354
Short name T4
Test name
Test status
Simulation time 29657046 ps
CPU time 0.4 seconds
Started Jan 14 12:54:09 PM PST 24
Finished Jan 14 12:54:10 PM PST 24
Peak memory 145500 kb
Host smart-465f7915-4fa6-4317-a2e0-28ddfb0b7411
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3862467354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3862467354
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3037385165
Short name T2
Test name
Test status
Simulation time 11985904 ps
CPU time 0.39 seconds
Started Jan 14 12:54:13 PM PST 24
Finished Jan 14 12:54:14 PM PST 24
Peak memory 145436 kb
Host smart-f2b90704-9860-478a-b0bd-817f789937c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037385165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3037385165
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1465939209
Short name T36
Test name
Test status
Simulation time 10637841 ps
CPU time 0.4 seconds
Started Jan 14 12:53:36 PM PST 24
Finished Jan 14 12:53:37 PM PST 24
Peak memory 145428 kb
Host smart-39b50689-2ece-4a92-a5ce-55bdadf3a235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465939209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1465939209
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2450270526
Short name T13
Test name
Test status
Simulation time 11271418 ps
CPU time 0.4 seconds
Started Jan 14 12:53:37 PM PST 24
Finished Jan 14 12:53:38 PM PST 24
Peak memory 145452 kb
Host smart-7ad4f3c6-1609-41b4-a1ed-af83bc7f4d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450270526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2450270526
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3409189081
Short name T45
Test name
Test status
Simulation time 10489683 ps
CPU time 0.39 seconds
Started Jan 14 12:53:52 PM PST 24
Finished Jan 14 12:53:53 PM PST 24
Peak memory 145376 kb
Host smart-f4079e35-06d0-40cf-8db1-64bec731f912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409189081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3409189081
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.4016516265
Short name T42
Test name
Test status
Simulation time 10835412 ps
CPU time 0.4 seconds
Started Jan 14 12:54:03 PM PST 24
Finished Jan 14 12:54:04 PM PST 24
Peak memory 145376 kb
Host smart-1d42e28a-8f53-4575-b9d3-af07f6137706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016516265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4016516265
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2642423037
Short name T22
Test name
Test status
Simulation time 10588721 ps
CPU time 0.38 seconds
Started Jan 14 12:54:00 PM PST 24
Finished Jan 14 12:54:01 PM PST 24
Peak memory 145400 kb
Host smart-82017c2d-dc9a-4b04-aef9-508fd6a88437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642423037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2642423037
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.639241449
Short name T20
Test name
Test status
Simulation time 11555823 ps
CPU time 0.39 seconds
Started Jan 14 12:54:02 PM PST 24
Finished Jan 14 12:54:04 PM PST 24
Peak memory 145424 kb
Host smart-642567f1-0acf-4c89-9edb-603e55eb834c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639241449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.639241449
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1650622875
Short name T43
Test name
Test status
Simulation time 11571230 ps
CPU time 0.39 seconds
Started Jan 14 12:54:00 PM PST 24
Finished Jan 14 12:54:01 PM PST 24
Peak memory 145432 kb
Host smart-9c1ff1bb-ccb5-44ef-8820-8878d0a275e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650622875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1650622875
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1473971251
Short name T3
Test name
Test status
Simulation time 11215168 ps
CPU time 0.39 seconds
Started Jan 14 12:53:58 PM PST 24
Finished Jan 14 12:53:59 PM PST 24
Peak memory 145548 kb
Host smart-bd7b275f-b0ef-4bd9-b5b9-3033ebfe85d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473971251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1473971251
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2780642117
Short name T1
Test name
Test status
Simulation time 11099257 ps
CPU time 0.38 seconds
Started Jan 14 12:54:00 PM PST 24
Finished Jan 14 12:54:01 PM PST 24
Peak memory 145372 kb
Host smart-ce70ada6-9594-4d1d-898b-2dd052da1ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780642117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2780642117
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2091723263
Short name T18
Test name
Test status
Simulation time 11774765 ps
CPU time 0.38 seconds
Started Jan 14 12:54:10 PM PST 24
Finished Jan 14 12:54:11 PM PST 24
Peak memory 145408 kb
Host smart-f98146bb-3150-439f-852a-05979f230f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091723263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2091723263
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.317374040
Short name T21
Test name
Test status
Simulation time 11066821 ps
CPU time 0.42 seconds
Started Jan 14 12:54:12 PM PST 24
Finished Jan 14 12:54:13 PM PST 24
Peak memory 145416 kb
Host smart-abeb08e4-04f8-4c2a-8f77-0cb0e0ebe99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317374040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.317374040
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.4096643896
Short name T8
Test name
Test status
Simulation time 11638812 ps
CPU time 0.39 seconds
Started Jan 14 12:53:37 PM PST 24
Finished Jan 14 12:53:38 PM PST 24
Peak memory 145460 kb
Host smart-dd0f97a9-6a3f-4729-8969-f12776bca2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096643896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.4096643896
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2403132978
Short name T9
Test name
Test status
Simulation time 12139733 ps
CPU time 0.38 seconds
Started Jan 14 12:53:46 PM PST 24
Finished Jan 14 12:53:47 PM PST 24
Peak memory 145464 kb
Host smart-f7921cc2-a53e-4c29-a865-5cf33ae894ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403132978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2403132978
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1072467236
Short name T19
Test name
Test status
Simulation time 11555055 ps
CPU time 0.38 seconds
Started Jan 14 12:53:45 PM PST 24
Finished Jan 14 12:53:46 PM PST 24
Peak memory 145452 kb
Host smart-0f04b9bf-2bae-4049-8bc9-f266272702a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072467236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1072467236
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3798826228
Short name T46
Test name
Test status
Simulation time 10667686 ps
CPU time 0.38 seconds
Started Jan 14 12:53:53 PM PST 24
Finished Jan 14 12:53:54 PM PST 24
Peak memory 145368 kb
Host smart-0821a79f-d5dc-44c6-a4f4-cb45569b0392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798826228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3798826228
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1041896254
Short name T17
Test name
Test status
Simulation time 11254780 ps
CPU time 0.39 seconds
Started Jan 14 12:53:52 PM PST 24
Finished Jan 14 12:53:53 PM PST 24
Peak memory 145452 kb
Host smart-18b4f640-c768-468a-b469-6affb5a92e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041896254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1041896254
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.4061613008
Short name T16
Test name
Test status
Simulation time 10908643 ps
CPU time 0.38 seconds
Started Jan 14 12:53:52 PM PST 24
Finished Jan 14 12:53:53 PM PST 24
Peak memory 145384 kb
Host smart-45ce02e6-c7fa-48a9-9d73-97ef22938ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061613008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.4061613008
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2995121455
Short name T44
Test name
Test status
Simulation time 11602498 ps
CPU time 0.4 seconds
Started Jan 14 12:53:54 PM PST 24
Finished Jan 14 12:53:55 PM PST 24
Peak memory 145408 kb
Host smart-5374e3d4-0a47-4482-b080-816221447bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995121455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2995121455
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1022789255
Short name T47
Test name
Test status
Simulation time 28985704 ps
CPU time 0.41 seconds
Started Jan 14 12:54:12 PM PST 24
Finished Jan 14 12:54:13 PM PST 24
Peak memory 145544 kb
Host smart-16446030-c1a0-48e8-911b-86a5ba1d0303
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1022789255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1022789255
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3341081535
Short name T50
Test name
Test status
Simulation time 30728073 ps
CPU time 0.39 seconds
Started Jan 14 12:54:12 PM PST 24
Finished Jan 14 12:54:13 PM PST 24
Peak memory 145576 kb
Host smart-d509567c-3fa0-4a5f-98bb-68a119d6eb99
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3341081535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3341081535
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2244450974
Short name T37
Test name
Test status
Simulation time 31181201 ps
CPU time 0.4 seconds
Started Jan 14 12:54:10 PM PST 24
Finished Jan 14 12:54:11 PM PST 24
Peak memory 145496 kb
Host smart-2b03187c-2a85-48b2-8279-b301d1780bef
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2244450974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2244450974
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1244303480
Short name T39
Test name
Test status
Simulation time 30541830 ps
CPU time 0.4 seconds
Started Jan 14 12:54:17 PM PST 24
Finished Jan 14 12:54:22 PM PST 24
Peak memory 145516 kb
Host smart-b4ac48b5-b77e-4bd6-90d9-e61484e905e1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1244303480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1244303480
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1631216387
Short name T51
Test name
Test status
Simulation time 31470644 ps
CPU time 0.4 seconds
Started Jan 14 12:54:17 PM PST 24
Finished Jan 14 12:54:18 PM PST 24
Peak memory 145556 kb
Host smart-29f4c07a-a596-4311-a07c-7849e74a172e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1631216387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1631216387
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2900443379
Short name T14
Test name
Test status
Simulation time 30524452 ps
CPU time 0.4 seconds
Started Jan 14 12:54:18 PM PST 24
Finished Jan 14 12:54:23 PM PST 24
Peak memory 145612 kb
Host smart-1b85a38c-3f0d-44ac-9ef5-2b394ca90776
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2900443379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2900443379
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.221469284
Short name T38
Test name
Test status
Simulation time 29065310 ps
CPU time 0.41 seconds
Started Jan 14 12:54:15 PM PST 24
Finished Jan 14 12:54:17 PM PST 24
Peak memory 145548 kb
Host smart-1ff06fa8-13ad-40ae-8709-c68286d7aa82
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=221469284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.221469284
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2238370828
Short name T10
Test name
Test status
Simulation time 29901995 ps
CPU time 0.41 seconds
Started Jan 14 12:54:18 PM PST 24
Finished Jan 14 12:54:23 PM PST 24
Peak memory 145516 kb
Host smart-5fa4b9d5-0a50-4e4f-b6fa-17ad6c3f0940
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2238370828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2238370828
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1236548518
Short name T11
Test name
Test status
Simulation time 31367546 ps
CPU time 0.4 seconds
Started Jan 14 12:54:18 PM PST 24
Finished Jan 14 12:54:23 PM PST 24
Peak memory 145544 kb
Host smart-28b67d93-2aae-4079-baac-aad71bf05496
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1236548518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1236548518
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4211255422
Short name T12
Test name
Test status
Simulation time 30371110 ps
CPU time 0.41 seconds
Started Jan 14 12:54:27 PM PST 24
Finished Jan 14 12:54:31 PM PST 24
Peak memory 145600 kb
Host smart-f314638e-917d-4802-93ee-5bbd748e582a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4211255422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.4211255422
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.796925510
Short name T48
Test name
Test status
Simulation time 28685177 ps
CPU time 0.4 seconds
Started Jan 14 12:54:27 PM PST 24
Finished Jan 14 12:54:31 PM PST 24
Peak memory 145540 kb
Host smart-b9877eb2-a8a0-4f45-8be4-9ee6971b8cc8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=796925510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.796925510
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4047317923
Short name T15
Test name
Test status
Simulation time 30728189 ps
CPU time 0.41 seconds
Started Jan 14 12:54:28 PM PST 24
Finished Jan 14 12:54:32 PM PST 24
Peak memory 145560 kb
Host smart-5bf45cf8-5ab2-4a3e-9abd-b095b67b6f9f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4047317923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.4047317923
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.840887687
Short name T54
Test name
Test status
Simulation time 31137975 ps
CPU time 0.4 seconds
Started Jan 14 12:54:13 PM PST 24
Finished Jan 14 12:54:14 PM PST 24
Peak memory 145540 kb
Host smart-2f27be0c-0779-464d-bb71-40a0943cd7fd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=840887687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.840887687
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.674136121
Short name T53
Test name
Test status
Simulation time 28536656 ps
CPU time 0.4 seconds
Started Jan 14 12:54:14 PM PST 24
Finished Jan 14 12:54:15 PM PST 24
Peak memory 145580 kb
Host smart-c8e6faea-47d5-4aef-81c4-602d9bcc473d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=674136121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.674136121
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.152728423
Short name T52
Test name
Test status
Simulation time 30325980 ps
CPU time 0.39 seconds
Started Jan 14 12:54:09 PM PST 24
Finished Jan 14 12:54:10 PM PST 24
Peak memory 145540 kb
Host smart-b33a4917-f402-44fb-9de1-242f646565fd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=152728423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.152728423
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.960876949
Short name T49
Test name
Test status
Simulation time 29456752 ps
CPU time 0.4 seconds
Started Jan 14 12:54:09 PM PST 24
Finished Jan 14 12:54:10 PM PST 24
Peak memory 145512 kb
Host smart-7c3a4ff8-e630-467c-b319-3de8ca706d56
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=960876949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.960876949
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1403137212
Short name T41
Test name
Test status
Simulation time 29588480 ps
CPU time 0.41 seconds
Started Jan 14 12:54:12 PM PST 24
Finished Jan 14 12:54:13 PM PST 24
Peak memory 145616 kb
Host smart-791243e4-b377-4b23-b453-4cc877af9a0b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1403137212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1403137212
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2678279387
Short name T40
Test name
Test status
Simulation time 28962642 ps
CPU time 0.39 seconds
Started Jan 14 12:54:10 PM PST 24
Finished Jan 14 12:54:11 PM PST 24
Peak memory 145504 kb
Host smart-9d751b6d-4536-499e-ae8f-e400d0d91de1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2678279387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2678279387
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.4064730785
Short name T30
Test name
Test status
Simulation time 9244041 ps
CPU time 0.37 seconds
Started Jan 14 12:58:12 PM PST 24
Finished Jan 14 12:58:13 PM PST 24
Peak memory 145032 kb
Host smart-3b7e7305-f646-4a23-a777-53556f5a7209
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4064730785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4064730785
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1681993918
Short name T59
Test name
Test status
Simulation time 10141744 ps
CPU time 0.44 seconds
Started Jan 14 12:58:13 PM PST 24
Finished Jan 14 12:58:14 PM PST 24
Peak memory 144888 kb
Host smart-75bff771-8c78-4cd1-84da-49bbea3b05d0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1681993918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1681993918
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2597061314
Short name T57
Test name
Test status
Simulation time 9543594 ps
CPU time 0.39 seconds
Started Jan 14 12:58:28 PM PST 24
Finished Jan 14 12:58:29 PM PST 24
Peak memory 144892 kb
Host smart-0dd316ac-e33e-4ae0-a874-af64413fc2e1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2597061314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2597061314
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2086319477
Short name T23
Test name
Test status
Simulation time 8980931 ps
CPU time 0.39 seconds
Started Jan 14 12:58:30 PM PST 24
Finished Jan 14 12:58:31 PM PST 24
Peak memory 145200 kb
Host smart-6fc6ab4b-66a3-48e8-86c7-edb5aaa3b44e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2086319477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2086319477
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2049376875
Short name T29
Test name
Test status
Simulation time 9695854 ps
CPU time 0.39 seconds
Started Jan 14 12:58:26 PM PST 24
Finished Jan 14 12:58:27 PM PST 24
Peak memory 144940 kb
Host smart-e9628398-c516-46d6-823c-788713210d7e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2049376875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2049376875
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2871226960
Short name T27
Test name
Test status
Simulation time 9408343 ps
CPU time 0.39 seconds
Started Jan 14 12:58:27 PM PST 24
Finished Jan 14 12:58:28 PM PST 24
Peak memory 144924 kb
Host smart-f47ecb75-7c8e-4e75-8567-683878de50d9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2871226960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2871226960
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2781433859
Short name T28
Test name
Test status
Simulation time 8797251 ps
CPU time 0.38 seconds
Started Jan 14 12:58:26 PM PST 24
Finished Jan 14 12:58:27 PM PST 24
Peak memory 144916 kb
Host smart-8f7c2027-ecfe-405a-be3d-361d42a874ac
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2781433859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2781433859
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.4117891125
Short name T56
Test name
Test status
Simulation time 9157235 ps
CPU time 0.38 seconds
Started Jan 14 12:58:26 PM PST 24
Finished Jan 14 12:58:27 PM PST 24
Peak memory 144868 kb
Host smart-1c332940-4443-446c-a8f5-d9cdd75e25b5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4117891125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.4117891125
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.937645479
Short name T31
Test name
Test status
Simulation time 9939223 ps
CPU time 0.42 seconds
Started Jan 14 12:58:27 PM PST 24
Finished Jan 14 12:58:29 PM PST 24
Peak memory 144900 kb
Host smart-3022ea16-fd53-484f-8180-9286b907ba04
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=937645479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.937645479
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1348004342
Short name T58
Test name
Test status
Simulation time 10143813 ps
CPU time 0.39 seconds
Started Jan 14 12:58:29 PM PST 24
Finished Jan 14 12:58:30 PM PST 24
Peak memory 144852 kb
Host smart-cff67b94-aa8a-4164-9565-c64ff5144f2c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1348004342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1348004342
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3239997428
Short name T34
Test name
Test status
Simulation time 8999575 ps
CPU time 0.38 seconds
Started Jan 14 12:58:26 PM PST 24
Finished Jan 14 12:58:27 PM PST 24
Peak memory 145020 kb
Host smart-d4c1197e-7c0d-427d-b9db-78947ec86e0d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3239997428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3239997428
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3916792332
Short name T26
Test name
Test status
Simulation time 8688212 ps
CPU time 0.39 seconds
Started Jan 14 12:58:16 PM PST 24
Finished Jan 14 12:58:17 PM PST 24
Peak memory 144988 kb
Host smart-1fe73723-55c1-4093-b120-d47f30ad7461
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3916792332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3916792332
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1452852111
Short name T25
Test name
Test status
Simulation time 9393257 ps
CPU time 0.39 seconds
Started Jan 14 12:58:14 PM PST 24
Finished Jan 14 12:58:14 PM PST 24
Peak memory 144888 kb
Host smart-23370dea-46ba-426f-9ab8-1795289481fb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1452852111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1452852111
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2679238165
Short name T33
Test name
Test status
Simulation time 10012080 ps
CPU time 0.38 seconds
Started Jan 14 12:58:18 PM PST 24
Finished Jan 14 12:58:19 PM PST 24
Peak memory 144896 kb
Host smart-bf1b35b9-3bbf-4dc0-86cb-c20eff691ff6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2679238165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2679238165
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2515039427
Short name T60
Test name
Test status
Simulation time 10183748 ps
CPU time 0.38 seconds
Started Jan 14 12:58:19 PM PST 24
Finished Jan 14 12:58:20 PM PST 24
Peak memory 144800 kb
Host smart-88d8a9f6-157e-4413-b7f9-d2e879e5b8f3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2515039427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2515039427
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.4271204560
Short name T24
Test name
Test status
Simulation time 9267083 ps
CPU time 0.38 seconds
Started Jan 14 12:58:19 PM PST 24
Finished Jan 14 12:58:20 PM PST 24
Peak memory 144900 kb
Host smart-ef3e8056-d677-471e-810c-91d9de8d9017
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4271204560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.4271204560
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3658532686
Short name T32
Test name
Test status
Simulation time 9391468 ps
CPU time 0.37 seconds
Started Jan 14 12:58:26 PM PST 24
Finished Jan 14 12:58:27 PM PST 24
Peak memory 144968 kb
Host smart-1075a4e1-6993-4cab-82e0-ccdb0bc295bb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3658532686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3658532686
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1824968206
Short name T55
Test name
Test status
Simulation time 10099096 ps
CPU time 0.38 seconds
Started Jan 14 12:58:26 PM PST 24
Finished Jan 14 12:58:28 PM PST 24
Peak memory 144952 kb
Host smart-1f2d7a7d-5ec3-4e77-b671-0e79a61f750a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1824968206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1824968206
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2821001384
Short name T61
Test name
Test status
Simulation time 10217338 ps
CPU time 0.38 seconds
Started Jan 14 12:58:26 PM PST 24
Finished Jan 14 12:58:27 PM PST 24
Peak memory 144968 kb
Host smart-f70b25b0-6e2a-4e6a-b87b-1870ccba84d1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2821001384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2821001384
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2278237092
Short name T71
Test name
Test status
Simulation time 26753469 ps
CPU time 0.39 seconds
Started Jan 14 12:58:07 PM PST 24
Finished Jan 14 12:58:07 PM PST 24
Peak memory 144960 kb
Host smart-2091b7ec-5601-4082-b20d-61c11852d96e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2278237092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2278237092
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4065319674
Short name T5
Test name
Test status
Simulation time 25514473 ps
CPU time 0.39 seconds
Started Jan 14 12:58:07 PM PST 24
Finished Jan 14 12:58:08 PM PST 24
Peak memory 145032 kb
Host smart-b19ee16e-5868-4ae9-8d96-6a81180482f7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4065319674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.4065319674
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4227056228
Short name T78
Test name
Test status
Simulation time 28257585 ps
CPU time 0.44 seconds
Started Jan 14 12:58:12 PM PST 24
Finished Jan 14 12:58:13 PM PST 24
Peak memory 145052 kb
Host smart-5949e40f-9400-4cb7-9aa7-178297351cf5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4227056228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.4227056228
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2676152453
Short name T77
Test name
Test status
Simulation time 26648893 ps
CPU time 0.4 seconds
Started Jan 14 12:58:08 PM PST 24
Finished Jan 14 12:58:09 PM PST 24
Peak memory 144924 kb
Host smart-82a63634-03d7-4911-a130-2ce36ced9b31
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2676152453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2676152453
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1347992827
Short name T73
Test name
Test status
Simulation time 28747726 ps
CPU time 0.44 seconds
Started Jan 14 12:58:07 PM PST 24
Finished Jan 14 12:58:07 PM PST 24
Peak memory 144968 kb
Host smart-d92ae7c7-607e-4b87-a5ac-d45ed93763f1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1347992827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1347992827
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.356645980
Short name T65
Test name
Test status
Simulation time 27537792 ps
CPU time 0.39 seconds
Started Jan 14 12:58:05 PM PST 24
Finished Jan 14 12:58:06 PM PST 24
Peak memory 144824 kb
Host smart-6948252f-8671-4196-b1bc-9c1d6ce24b00
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=356645980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.356645980
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1139165794
Short name T6
Test name
Test status
Simulation time 28034414 ps
CPU time 0.39 seconds
Started Jan 14 12:58:09 PM PST 24
Finished Jan 14 12:58:10 PM PST 24
Peak memory 145032 kb
Host smart-b1f1c303-186b-49b9-9f82-01952279a194
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1139165794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1139165794
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4269215539
Short name T74
Test name
Test status
Simulation time 26436875 ps
CPU time 0.4 seconds
Started Jan 14 12:58:11 PM PST 24
Finished Jan 14 12:58:12 PM PST 24
Peak memory 144992 kb
Host smart-546d5fec-96b3-4d5c-b0a9-c7534a5af6ab
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4269215539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.4269215539
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1118187234
Short name T63
Test name
Test status
Simulation time 26163262 ps
CPU time 0.4 seconds
Started Jan 14 12:58:12 PM PST 24
Finished Jan 14 12:58:13 PM PST 24
Peak memory 145052 kb
Host smart-38935c80-c1ae-4d0e-9c9b-bb99632508be
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1118187234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1118187234
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.269496242
Short name T69
Test name
Test status
Simulation time 27785334 ps
CPU time 0.4 seconds
Started Jan 14 12:58:10 PM PST 24
Finished Jan 14 12:58:10 PM PST 24
Peak memory 145024 kb
Host smart-01016c53-2c49-4e0f-9b1b-f5435d5ca86c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=269496242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.269496242
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1974665378
Short name T70
Test name
Test status
Simulation time 27990043 ps
CPU time 0.39 seconds
Started Jan 14 12:58:11 PM PST 24
Finished Jan 14 12:58:12 PM PST 24
Peak memory 144864 kb
Host smart-49ba500b-2029-4a43-89f9-2bcd63a3d830
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1974665378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1974665378
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3712728259
Short name T76
Test name
Test status
Simulation time 27871710 ps
CPU time 0.41 seconds
Started Jan 14 12:58:08 PM PST 24
Finished Jan 14 12:58:09 PM PST 24
Peak memory 144936 kb
Host smart-0bb0f733-2599-445d-858d-73d57b91b2ff
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3712728259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3712728259
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2560067582
Short name T64
Test name
Test status
Simulation time 25900592 ps
CPU time 0.4 seconds
Started Jan 14 12:58:06 PM PST 24
Finished Jan 14 12:58:07 PM PST 24
Peak memory 145032 kb
Host smart-74364316-8ac3-4892-b7b9-c6b6af89c866
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2560067582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2560067582
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3543990152
Short name T79
Test name
Test status
Simulation time 28095347 ps
CPU time 0.42 seconds
Started Jan 14 12:58:08 PM PST 24
Finished Jan 14 12:58:09 PM PST 24
Peak memory 144960 kb
Host smart-ed805d0e-aa07-4662-816b-6944ff6f2e4f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3543990152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3543990152
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2950275532
Short name T68
Test name
Test status
Simulation time 28989745 ps
CPU time 0.38 seconds
Started Jan 14 12:58:08 PM PST 24
Finished Jan 14 12:58:09 PM PST 24
Peak memory 145008 kb
Host smart-d105c4af-03ba-43bb-941c-131cb0fdd8c0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2950275532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2950275532
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2344949592
Short name T66
Test name
Test status
Simulation time 27586153 ps
CPU time 0.42 seconds
Started Jan 14 12:58:05 PM PST 24
Finished Jan 14 12:58:06 PM PST 24
Peak memory 144976 kb
Host smart-700768a7-45e2-4c65-82ac-84df3f7a8521
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2344949592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2344949592
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.619151658
Short name T67
Test name
Test status
Simulation time 28590894 ps
CPU time 0.4 seconds
Started Jan 14 12:58:06 PM PST 24
Finished Jan 14 12:58:07 PM PST 24
Peak memory 145036 kb
Host smart-56d1433c-2703-4ce1-b05b-58a5ac93f363
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=619151658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.619151658
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3300817746
Short name T72
Test name
Test status
Simulation time 24547025 ps
CPU time 0.39 seconds
Started Jan 14 12:58:08 PM PST 24
Finished Jan 14 12:58:09 PM PST 24
Peak memory 145024 kb
Host smart-ccb8b291-84f6-4b0c-946f-b76159b36935
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3300817746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3300817746
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3521599150
Short name T75
Test name
Test status
Simulation time 27185848 ps
CPU time 0.41 seconds
Started Jan 14 12:58:11 PM PST 24
Finished Jan 14 12:58:12 PM PST 24
Peak memory 144968 kb
Host smart-efcc89a3-6f73-4831-8723-a144928cc1e6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3521599150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3521599150
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.444516877
Short name T62
Test name
Test status
Simulation time 27135977 ps
CPU time 0.39 seconds
Started Jan 14 12:58:08 PM PST 24
Finished Jan 14 12:58:09 PM PST 24
Peak memory 144968 kb
Host smart-1b6b4d9d-ca5c-4a77-9d9d-687594dfdcc6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=444516877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.444516877
Directory /workspace/9.prim_sync_fatal_alert/latest
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