Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 78
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.08 88.08 100.00 100.00 93.75 93.75 96.43 96.43 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/11.prim_async_alert.2470319899
91.20 3.13 100.00 0.00 93.75 0.00 96.43 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/18.prim_sync_alert.2347582472
93.56 2.35 100.00 0.00 93.75 0.00 100.00 3.57 85.71 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.523324395
94.25 0.69 100.00 0.00 97.92 4.17 100.00 0.00 85.71 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.206354067
94.85 0.60 100.00 0.00 97.92 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/7.prim_async_alert.2016047625
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2317687271

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2974944016
/workspace/coverage/default/1.prim_async_alert.3955876817
/workspace/coverage/default/10.prim_async_alert.2316284417
/workspace/coverage/default/12.prim_async_alert.2112943554
/workspace/coverage/default/13.prim_async_alert.4087894049
/workspace/coverage/default/14.prim_async_alert.3615333939
/workspace/coverage/default/15.prim_async_alert.312850372
/workspace/coverage/default/16.prim_async_alert.1945504628
/workspace/coverage/default/17.prim_async_alert.1048866108
/workspace/coverage/default/18.prim_async_alert.3920429662
/workspace/coverage/default/19.prim_async_alert.3126529062
/workspace/coverage/default/2.prim_async_alert.3409531246
/workspace/coverage/default/3.prim_async_alert.2234848686
/workspace/coverage/default/4.prim_async_alert.1521779161
/workspace/coverage/default/5.prim_async_alert.3408050060
/workspace/coverage/default/6.prim_async_alert.619254550
/workspace/coverage/default/8.prim_async_alert.2912406683
/workspace/coverage/default/9.prim_async_alert.1345853516
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2364066815
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.989535574
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.789780205
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2951886372
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1372021394
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1885296058
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2303519812
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.978576640
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.857707444
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1017253692
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.625988352
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.653958711
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.369918211
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2040106765
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3663315875
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1995088609
/workspace/coverage/sync_alert/0.prim_sync_alert.3689135681
/workspace/coverage/sync_alert/1.prim_sync_alert.3204925598
/workspace/coverage/sync_alert/10.prim_sync_alert.3131174307
/workspace/coverage/sync_alert/11.prim_sync_alert.892201493
/workspace/coverage/sync_alert/12.prim_sync_alert.3143762419
/workspace/coverage/sync_alert/13.prim_sync_alert.3769042490
/workspace/coverage/sync_alert/14.prim_sync_alert.1175801201
/workspace/coverage/sync_alert/15.prim_sync_alert.245679454
/workspace/coverage/sync_alert/16.prim_sync_alert.1379098754
/workspace/coverage/sync_alert/17.prim_sync_alert.827008970
/workspace/coverage/sync_alert/19.prim_sync_alert.601482688
/workspace/coverage/sync_alert/2.prim_sync_alert.1200880530
/workspace/coverage/sync_alert/3.prim_sync_alert.1363705134
/workspace/coverage/sync_alert/4.prim_sync_alert.2714073116
/workspace/coverage/sync_alert/5.prim_sync_alert.1332794866
/workspace/coverage/sync_alert/6.prim_sync_alert.1259286637
/workspace/coverage/sync_alert/7.prim_sync_alert.3650400415
/workspace/coverage/sync_alert/8.prim_sync_alert.1320282290
/workspace/coverage/sync_alert/9.prim_sync_alert.3616382783
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3220576006
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.483029533
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1946546769
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2184148189
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1241514612
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3174952586
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3168370715
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3610127457
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.587617240
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1549847649
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.130237965
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1937437909
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.891058274
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.767858005
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3726022459
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.745508113
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3515661867
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3496331088
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3023645866



Total test records in report: 78
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/16.prim_async_alert.1945504628 Jan 21 02:59:45 PM PST 24 Jan 21 02:59:46 PM PST 24 10631144 ps
T2 /workspace/coverage/default/19.prim_async_alert.3126529062 Jan 21 02:59:41 PM PST 24 Jan 21 02:59:42 PM PST 24 10746651 ps
T3 /workspace/coverage/default/15.prim_async_alert.312850372 Jan 21 02:59:38 PM PST 24 Jan 21 02:59:39 PM PST 24 11845821 ps
T7 /workspace/coverage/default/6.prim_async_alert.619254550 Jan 21 02:59:38 PM PST 24 Jan 21 02:59:39 PM PST 24 11746780 ps
T10 /workspace/coverage/default/14.prim_async_alert.3615333939 Jan 21 02:59:45 PM PST 24 Jan 21 02:59:46 PM PST 24 10975244 ps
T22 /workspace/coverage/default/0.prim_async_alert.2974944016 Jan 21 02:59:42 PM PST 24 Jan 21 02:59:43 PM PST 24 11232000 ps
T15 /workspace/coverage/default/4.prim_async_alert.1521779161 Jan 21 02:59:41 PM PST 24 Jan 21 02:59:42 PM PST 24 12128358 ps
T23 /workspace/coverage/default/10.prim_async_alert.2316284417 Jan 21 02:59:43 PM PST 24 Jan 21 02:59:44 PM PST 24 10731144 ps
T8 /workspace/coverage/default/11.prim_async_alert.2470319899 Jan 21 02:59:36 PM PST 24 Jan 21 02:59:37 PM PST 24 11351304 ps
T9 /workspace/coverage/default/1.prim_async_alert.3955876817 Jan 21 02:59:42 PM PST 24 Jan 21 02:59:43 PM PST 24 11323672 ps
T24 /workspace/coverage/default/2.prim_async_alert.3409531246 Jan 21 02:59:38 PM PST 24 Jan 21 02:59:39 PM PST 24 10772215 ps
T11 /workspace/coverage/default/8.prim_async_alert.2912406683 Jan 21 02:59:38 PM PST 24 Jan 21 02:59:39 PM PST 24 11608542 ps
T25 /workspace/coverage/default/12.prim_async_alert.2112943554 Jan 21 02:59:39 PM PST 24 Jan 21 02:59:41 PM PST 24 10285491 ps
T16 /workspace/coverage/default/7.prim_async_alert.2016047625 Jan 21 02:59:39 PM PST 24 Jan 21 02:59:40 PM PST 24 10964960 ps
T26 /workspace/coverage/default/17.prim_async_alert.1048866108 Jan 21 02:59:38 PM PST 24 Jan 21 02:59:40 PM PST 24 10623074 ps
T27 /workspace/coverage/default/18.prim_async_alert.3920429662 Jan 21 02:59:52 PM PST 24 Jan 21 02:59:53 PM PST 24 10911843 ps
T20 /workspace/coverage/default/13.prim_async_alert.4087894049 Jan 21 02:59:39 PM PST 24 Jan 21 02:59:40 PM PST 24 12705938 ps
T21 /workspace/coverage/default/5.prim_async_alert.3408050060 Jan 21 02:59:37 PM PST 24 Jan 21 02:59:38 PM PST 24 11737233 ps
T47 /workspace/coverage/default/9.prim_async_alert.1345853516 Jan 21 02:59:52 PM PST 24 Jan 21 02:59:53 PM PST 24 10826011 ps
T48 /workspace/coverage/default/3.prim_async_alert.2234848686 Jan 21 02:59:43 PM PST 24 Jan 21 02:59:45 PM PST 24 10514910 ps
T28 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.789780205 Jan 21 10:09:45 PM PST 24 Jan 21 10:09:50 PM PST 24 29577310 ps
T42 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1885296058 Jan 21 10:09:57 PM PST 24 Jan 21 10:10:02 PM PST 24 29476965 ps
T18 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1372021394 Jan 21 10:09:54 PM PST 24 Jan 21 10:09:58 PM PST 24 31348380 ps
T4 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1017253692 Jan 21 11:01:11 PM PST 24 Jan 21 11:01:13 PM PST 24 30286724 ps
T43 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.369918211 Jan 21 10:09:44 PM PST 24 Jan 21 10:09:49 PM PST 24 31533992 ps
T44 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.523324395 Jan 21 10:24:40 PM PST 24 Jan 21 10:24:49 PM PST 24 30840180 ps
T45 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.653958711 Jan 21 10:09:43 PM PST 24 Jan 21 10:09:48 PM PST 24 31961525 ps
T40 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2303519812 Jan 21 10:09:59 PM PST 24 Jan 21 10:10:10 PM PST 24 29312568 ps
T46 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.625988352 Jan 21 10:09:44 PM PST 24 Jan 21 10:09:49 PM PST 24 30037879 ps
T19 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2040106765 Jan 21 10:09:51 PM PST 24 Jan 21 10:09:55 PM PST 24 31060208 ps
T49 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1995088609 Jan 21 10:09:45 PM PST 24 Jan 21 10:09:50 PM PST 24 28821159 ps
T50 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.989535574 Jan 21 10:55:37 PM PST 24 Jan 21 10:55:39 PM PST 24 30614483 ps
T5 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.206354067 Jan 21 10:10:01 PM PST 24 Jan 21 10:10:12 PM PST 24 30527393 ps
T51 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3663315875 Jan 21 10:09:45 PM PST 24 Jan 21 10:09:50 PM PST 24 31641870 ps
T6 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.857707444 Jan 21 10:10:01 PM PST 24 Jan 21 10:10:12 PM PST 24 31087253 ps
T41 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2951886372 Jan 21 10:09:52 PM PST 24 Jan 21 10:09:57 PM PST 24 31632608 ps
T52 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2364066815 Jan 21 10:09:41 PM PST 24 Jan 21 10:09:45 PM PST 24 29232459 ps
T53 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.978576640 Jan 21 10:10:00 PM PST 24 Jan 21 10:10:11 PM PST 24 30136498 ps
T38 /workspace/coverage/sync_alert/4.prim_sync_alert.2714073116 Jan 21 07:47:38 PM PST 24 Jan 21 07:47:39 PM PST 24 9237336 ps
T39 /workspace/coverage/sync_alert/18.prim_sync_alert.2347582472 Jan 21 07:47:54 PM PST 24 Jan 21 07:47:55 PM PST 24 9817819 ps
T29 /workspace/coverage/sync_alert/8.prim_sync_alert.1320282290 Jan 21 07:47:59 PM PST 24 Jan 21 07:48:01 PM PST 24 10097779 ps
T30 /workspace/coverage/sync_alert/14.prim_sync_alert.1175801201 Jan 21 07:47:59 PM PST 24 Jan 21 07:48:00 PM PST 24 8343766 ps
T31 /workspace/coverage/sync_alert/7.prim_sync_alert.3650400415 Jan 21 07:47:53 PM PST 24 Jan 21 07:47:55 PM PST 24 9479427 ps
T32 /workspace/coverage/sync_alert/9.prim_sync_alert.3616382783 Jan 21 07:47:55 PM PST 24 Jan 21 07:47:57 PM PST 24 8626760 ps
T33 /workspace/coverage/sync_alert/17.prim_sync_alert.827008970 Jan 21 07:47:56 PM PST 24 Jan 21 07:47:57 PM PST 24 9453427 ps
T34 /workspace/coverage/sync_alert/6.prim_sync_alert.1259286637 Jan 21 07:47:53 PM PST 24 Jan 21 07:47:54 PM PST 24 9320442 ps
T35 /workspace/coverage/sync_alert/3.prim_sync_alert.1363705134 Jan 21 07:47:38 PM PST 24 Jan 21 07:47:40 PM PST 24 10953871 ps
T36 /workspace/coverage/sync_alert/10.prim_sync_alert.3131174307 Jan 21 07:47:56 PM PST 24 Jan 21 07:47:57 PM PST 24 9556649 ps
T37 /workspace/coverage/sync_alert/0.prim_sync_alert.3689135681 Jan 21 07:47:42 PM PST 24 Jan 21 07:47:43 PM PST 24 9097101 ps
T54 /workspace/coverage/sync_alert/16.prim_sync_alert.1379098754 Jan 21 07:47:57 PM PST 24 Jan 21 07:47:59 PM PST 24 9695002 ps
T55 /workspace/coverage/sync_alert/13.prim_sync_alert.3769042490 Jan 21 07:47:52 PM PST 24 Jan 21 07:47:53 PM PST 24 10031289 ps
T56 /workspace/coverage/sync_alert/5.prim_sync_alert.1332794866 Jan 21 07:47:51 PM PST 24 Jan 21 07:47:52 PM PST 24 8245861 ps
T57 /workspace/coverage/sync_alert/19.prim_sync_alert.601482688 Jan 21 07:47:59 PM PST 24 Jan 21 07:48:01 PM PST 24 8620116 ps
T58 /workspace/coverage/sync_alert/11.prim_sync_alert.892201493 Jan 21 07:47:59 PM PST 24 Jan 21 07:48:00 PM PST 24 8060236 ps
T59 /workspace/coverage/sync_alert/2.prim_sync_alert.1200880530 Jan 21 07:47:38 PM PST 24 Jan 21 07:47:39 PM PST 24 10045218 ps
T60 /workspace/coverage/sync_alert/1.prim_sync_alert.3204925598 Jan 21 07:47:38 PM PST 24 Jan 21 07:47:40 PM PST 24 8527044 ps
T61 /workspace/coverage/sync_alert/12.prim_sync_alert.3143762419 Jan 21 07:47:57 PM PST 24 Jan 21 07:47:59 PM PST 24 8887317 ps
T62 /workspace/coverage/sync_alert/15.prim_sync_alert.245679454 Jan 21 07:47:57 PM PST 24 Jan 21 07:47:59 PM PST 24 9448716 ps
T63 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3496331088 Jan 21 10:09:33 PM PST 24 Jan 21 10:09:34 PM PST 24 28710983 ps
T64 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.745508113 Jan 21 10:09:37 PM PST 24 Jan 21 10:09:39 PM PST 24 26308639 ps
T65 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1937437909 Jan 21 10:09:28 PM PST 24 Jan 21 10:09:30 PM PST 24 27813815 ps
T66 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2184148189 Jan 21 10:09:37 PM PST 24 Jan 21 10:09:38 PM PST 24 26043597 ps
T67 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.891058274 Jan 21 10:09:26 PM PST 24 Jan 21 10:09:27 PM PST 24 26458759 ps
T12 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3023645866 Jan 21 10:09:36 PM PST 24 Jan 21 10:09:38 PM PST 24 26385110 ps
T68 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3220576006 Jan 21 10:09:34 PM PST 24 Jan 21 10:09:36 PM PST 24 26535315 ps
T69 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3174952586 Jan 21 10:09:39 PM PST 24 Jan 21 10:09:43 PM PST 24 28448223 ps
T70 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.587617240 Jan 21 10:09:41 PM PST 24 Jan 21 10:09:45 PM PST 24 27830697 ps
T71 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3168370715 Jan 21 10:09:40 PM PST 24 Jan 21 10:09:44 PM PST 24 27747669 ps
T72 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.483029533 Jan 21 10:35:47 PM PST 24 Jan 21 10:35:54 PM PST 24 25108581 ps
T73 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3610127457 Jan 21 10:09:40 PM PST 24 Jan 21 10:09:44 PM PST 24 25473540 ps
T74 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1549847649 Jan 21 10:09:42 PM PST 24 Jan 21 10:09:47 PM PST 24 26403934 ps
T13 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2317687271 Jan 21 10:09:40 PM PST 24 Jan 21 10:09:44 PM PST 24 27835907 ps
T75 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.130237965 Jan 21 10:09:39 PM PST 24 Jan 21 10:09:43 PM PST 24 28846576 ps
T17 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1946546769 Jan 21 10:09:35 PM PST 24 Jan 21 10:09:37 PM PST 24 26736644 ps
T76 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.767858005 Jan 21 10:09:28 PM PST 24 Jan 21 10:09:29 PM PST 24 26965944 ps
T77 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1241514612 Jan 21 10:09:33 PM PST 24 Jan 21 10:09:35 PM PST 24 26587906 ps
T78 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3726022459 Jan 21 10:26:23 PM PST 24 Jan 21 10:26:42 PM PST 24 25725041 ps
T14 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3515661867 Jan 21 10:09:37 PM PST 24 Jan 21 10:09:39 PM PST 24 26137401 ps

Test location /workspace/coverage/default/11.prim_async_alert.2470319899
Short name T8
Test name
Test status
Simulation time 11351304 ps
CPU time 0.39 seconds
Started Jan 21 02:59:36 PM PST 24
Finished Jan 21 02:59:37 PM PST 24
Peak memory 145688 kb
Host smart-1e7b0fd5-4b72-4af3-8afb-a0495634b154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470319899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2470319899
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2347582472
Short name T39
Test name
Test status
Simulation time 9817819 ps
CPU time 0.4 seconds
Started Jan 21 07:47:54 PM PST 24
Finished Jan 21 07:47:55 PM PST 24
Peak memory 144924 kb
Host smart-6f47a852-7f2a-4668-b62f-926ba97fb52f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2347582472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2347582472
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.523324395
Short name T44
Test name
Test status
Simulation time 30840180 ps
CPU time 0.42 seconds
Started Jan 21 10:24:40 PM PST 24
Finished Jan 21 10:24:49 PM PST 24
Peak memory 145752 kb
Host smart-dc462b87-72a6-418c-8948-47cfebd49b39
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=523324395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.523324395
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.206354067
Short name T5
Test name
Test status
Simulation time 30527393 ps
CPU time 0.41 seconds
Started Jan 21 10:10:01 PM PST 24
Finished Jan 21 10:10:12 PM PST 24
Peak memory 145712 kb
Host smart-a7b28c15-c314-4cd2-9ddf-9e72f0938fb2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=206354067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.206354067
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2016047625
Short name T16
Test name
Test status
Simulation time 10964960 ps
CPU time 0.39 seconds
Started Jan 21 02:59:39 PM PST 24
Finished Jan 21 02:59:40 PM PST 24
Peak memory 145800 kb
Host smart-34f86ae2-9466-49ce-83ab-af452a66e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016047625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2016047625
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2317687271
Short name T13
Test name
Test status
Simulation time 27835907 ps
CPU time 0.41 seconds
Started Jan 21 10:09:40 PM PST 24
Finished Jan 21 10:09:44 PM PST 24
Peak memory 145108 kb
Host smart-4dbd49a9-354d-4f57-9115-58367b115cef
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2317687271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2317687271
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2974944016
Short name T22
Test name
Test status
Simulation time 11232000 ps
CPU time 0.4 seconds
Started Jan 21 02:59:42 PM PST 24
Finished Jan 21 02:59:43 PM PST 24
Peak memory 145932 kb
Host smart-8eacda98-1f9b-4493-b802-437310fd3f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974944016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2974944016
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3955876817
Short name T9
Test name
Test status
Simulation time 11323672 ps
CPU time 0.4 seconds
Started Jan 21 02:59:42 PM PST 24
Finished Jan 21 02:59:43 PM PST 24
Peak memory 145852 kb
Host smart-6e1dc3ed-aa8e-411b-abaf-d6eb425320c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955876817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3955876817
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2316284417
Short name T23
Test name
Test status
Simulation time 10731144 ps
CPU time 0.39 seconds
Started Jan 21 02:59:43 PM PST 24
Finished Jan 21 02:59:44 PM PST 24
Peak memory 145760 kb
Host smart-ab394460-3fb2-41af-ab2c-9a467287220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316284417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2316284417
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2112943554
Short name T25
Test name
Test status
Simulation time 10285491 ps
CPU time 0.39 seconds
Started Jan 21 02:59:39 PM PST 24
Finished Jan 21 02:59:41 PM PST 24
Peak memory 145784 kb
Host smart-889d0460-3f78-40ac-81d7-512e0d2c975b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112943554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2112943554
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.4087894049
Short name T20
Test name
Test status
Simulation time 12705938 ps
CPU time 0.4 seconds
Started Jan 21 02:59:39 PM PST 24
Finished Jan 21 02:59:40 PM PST 24
Peak memory 145752 kb
Host smart-c5b14b40-be99-4e9e-b1b1-866f5fd489b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087894049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.4087894049
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3615333939
Short name T10
Test name
Test status
Simulation time 10975244 ps
CPU time 0.39 seconds
Started Jan 21 02:59:45 PM PST 24
Finished Jan 21 02:59:46 PM PST 24
Peak memory 145716 kb
Host smart-33aed1bb-838c-4772-b8a0-c34c014f6d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615333939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3615333939
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.312850372
Short name T3
Test name
Test status
Simulation time 11845821 ps
CPU time 0.39 seconds
Started Jan 21 02:59:38 PM PST 24
Finished Jan 21 02:59:39 PM PST 24
Peak memory 145752 kb
Host smart-769f58b1-1810-4bcc-b29b-54f6b6691006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312850372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.312850372
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1945504628
Short name T1
Test name
Test status
Simulation time 10631144 ps
CPU time 0.41 seconds
Started Jan 21 02:59:45 PM PST 24
Finished Jan 21 02:59:46 PM PST 24
Peak memory 145808 kb
Host smart-071ded2c-1ff2-4c91-b58c-8ff9eb431524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945504628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1945504628
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1048866108
Short name T26
Test name
Test status
Simulation time 10623074 ps
CPU time 0.39 seconds
Started Jan 21 02:59:38 PM PST 24
Finished Jan 21 02:59:40 PM PST 24
Peak memory 145800 kb
Host smart-88b24606-ed0d-4099-8a09-339fe1cddb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048866108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1048866108
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3920429662
Short name T27
Test name
Test status
Simulation time 10911843 ps
CPU time 0.39 seconds
Started Jan 21 02:59:52 PM PST 24
Finished Jan 21 02:59:53 PM PST 24
Peak memory 145684 kb
Host smart-87cc355e-6c74-49c6-8f33-6832eff8ef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920429662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3920429662
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3126529062
Short name T2
Test name
Test status
Simulation time 10746651 ps
CPU time 0.38 seconds
Started Jan 21 02:59:41 PM PST 24
Finished Jan 21 02:59:42 PM PST 24
Peak memory 145788 kb
Host smart-181d2cb4-b87c-4ef3-849e-834e524be47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126529062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3126529062
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3409531246
Short name T24
Test name
Test status
Simulation time 10772215 ps
CPU time 0.4 seconds
Started Jan 21 02:59:38 PM PST 24
Finished Jan 21 02:59:39 PM PST 24
Peak memory 145812 kb
Host smart-7a2dc38c-d6ba-4e58-8800-33136e1bee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409531246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3409531246
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2234848686
Short name T48
Test name
Test status
Simulation time 10514910 ps
CPU time 0.39 seconds
Started Jan 21 02:59:43 PM PST 24
Finished Jan 21 02:59:45 PM PST 24
Peak memory 145764 kb
Host smart-83b7fb03-8f2d-4866-8a51-3c055858a8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234848686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2234848686
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1521779161
Short name T15
Test name
Test status
Simulation time 12128358 ps
CPU time 0.38 seconds
Started Jan 21 02:59:41 PM PST 24
Finished Jan 21 02:59:42 PM PST 24
Peak memory 145796 kb
Host smart-167e990a-c42a-443e-bd10-74bc9409f73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521779161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1521779161
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3408050060
Short name T21
Test name
Test status
Simulation time 11737233 ps
CPU time 0.39 seconds
Started Jan 21 02:59:37 PM PST 24
Finished Jan 21 02:59:38 PM PST 24
Peak memory 145692 kb
Host smart-6e7b3331-a3db-4fb0-be96-c1cff5cc1540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408050060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3408050060
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.619254550
Short name T7
Test name
Test status
Simulation time 11746780 ps
CPU time 0.43 seconds
Started Jan 21 02:59:38 PM PST 24
Finished Jan 21 02:59:39 PM PST 24
Peak memory 145752 kb
Host smart-50e1c814-e39d-40f4-83b3-1724fd59359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619254550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.619254550
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2912406683
Short name T11
Test name
Test status
Simulation time 11608542 ps
CPU time 0.38 seconds
Started Jan 21 02:59:38 PM PST 24
Finished Jan 21 02:59:39 PM PST 24
Peak memory 145788 kb
Host smart-d0de7a5f-4bc4-4c79-9e20-974570b38eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912406683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2912406683
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1345853516
Short name T47
Test name
Test status
Simulation time 10826011 ps
CPU time 0.39 seconds
Started Jan 21 02:59:52 PM PST 24
Finished Jan 21 02:59:53 PM PST 24
Peak memory 145732 kb
Host smart-63b3f3c0-36e2-48b7-afb0-bb55093a2304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345853516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1345853516
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2364066815
Short name T52
Test name
Test status
Simulation time 29232459 ps
CPU time 0.4 seconds
Started Jan 21 10:09:41 PM PST 24
Finished Jan 21 10:09:45 PM PST 24
Peak memory 145704 kb
Host smart-67dfbd16-eb10-44d0-8718-ca615c1ab153
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2364066815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2364066815
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.989535574
Short name T50
Test name
Test status
Simulation time 30614483 ps
CPU time 0.42 seconds
Started Jan 21 10:55:37 PM PST 24
Finished Jan 21 10:55:39 PM PST 24
Peak memory 145736 kb
Host smart-cac7aa8c-5655-4e4d-876c-1073727c4042
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=989535574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.989535574
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.789780205
Short name T28
Test name
Test status
Simulation time 29577310 ps
CPU time 0.4 seconds
Started Jan 21 10:09:45 PM PST 24
Finished Jan 21 10:09:50 PM PST 24
Peak memory 145704 kb
Host smart-57eb107f-c7f1-477d-a912-a702e3f924b5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=789780205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.789780205
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2951886372
Short name T41
Test name
Test status
Simulation time 31632608 ps
CPU time 0.42 seconds
Started Jan 21 10:09:52 PM PST 24
Finished Jan 21 10:09:57 PM PST 24
Peak memory 145728 kb
Host smart-f25734bc-e635-431c-94b5-878bb2c561e5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2951886372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2951886372
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1372021394
Short name T18
Test name
Test status
Simulation time 31348380 ps
CPU time 0.45 seconds
Started Jan 21 10:09:54 PM PST 24
Finished Jan 21 10:09:58 PM PST 24
Peak memory 145720 kb
Host smart-2d6ca296-3fa6-43e9-811d-1eab5a40f23c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1372021394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1372021394
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1885296058
Short name T42
Test name
Test status
Simulation time 29476965 ps
CPU time 0.41 seconds
Started Jan 21 10:09:57 PM PST 24
Finished Jan 21 10:10:02 PM PST 24
Peak memory 145748 kb
Host smart-359c5acb-ee3e-4a91-9f5f-2e230f693011
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1885296058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1885296058
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2303519812
Short name T40
Test name
Test status
Simulation time 29312568 ps
CPU time 0.42 seconds
Started Jan 21 10:09:59 PM PST 24
Finished Jan 21 10:10:10 PM PST 24
Peak memory 145708 kb
Host smart-cb1b1b9e-2860-4dca-8204-bc16e26fcbbe
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2303519812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2303519812
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.978576640
Short name T53
Test name
Test status
Simulation time 30136498 ps
CPU time 0.41 seconds
Started Jan 21 10:10:00 PM PST 24
Finished Jan 21 10:10:11 PM PST 24
Peak memory 145704 kb
Host smart-6173b2db-2a1d-42de-989d-137d3a65ea1e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=978576640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.978576640
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.857707444
Short name T6
Test name
Test status
Simulation time 31087253 ps
CPU time 0.41 seconds
Started Jan 21 10:10:01 PM PST 24
Finished Jan 21 10:10:12 PM PST 24
Peak memory 145748 kb
Host smart-2a7f16bc-6ed3-4dc8-9267-ebbbcd820039
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=857707444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.857707444
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1017253692
Short name T4
Test name
Test status
Simulation time 30286724 ps
CPU time 0.4 seconds
Started Jan 21 11:01:11 PM PST 24
Finished Jan 21 11:01:13 PM PST 24
Peak memory 145736 kb
Host smart-a578e75a-733f-4984-9823-0f41aa057668
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1017253692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1017253692
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.625988352
Short name T46
Test name
Test status
Simulation time 30037879 ps
CPU time 0.41 seconds
Started Jan 21 10:09:44 PM PST 24
Finished Jan 21 10:09:49 PM PST 24
Peak memory 145708 kb
Host smart-c0ee1599-874e-4244-b11b-60b51ae0b8db
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=625988352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.625988352
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.653958711
Short name T45
Test name
Test status
Simulation time 31961525 ps
CPU time 0.44 seconds
Started Jan 21 10:09:43 PM PST 24
Finished Jan 21 10:09:48 PM PST 24
Peak memory 145664 kb
Host smart-a7f058cf-8be0-4613-9235-59ff23c6f242
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=653958711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.653958711
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.369918211
Short name T43
Test name
Test status
Simulation time 31533992 ps
CPU time 0.4 seconds
Started Jan 21 10:09:44 PM PST 24
Finished Jan 21 10:09:49 PM PST 24
Peak memory 145680 kb
Host smart-089a7fe4-fd2a-4f86-adeb-0e5e85dad26b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=369918211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.369918211
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2040106765
Short name T19
Test name
Test status
Simulation time 31060208 ps
CPU time 0.4 seconds
Started Jan 21 10:09:51 PM PST 24
Finished Jan 21 10:09:55 PM PST 24
Peak memory 145704 kb
Host smart-0980bc3a-edcc-4ae3-bb1f-8528042721ce
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2040106765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2040106765
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3663315875
Short name T51
Test name
Test status
Simulation time 31641870 ps
CPU time 0.46 seconds
Started Jan 21 10:09:45 PM PST 24
Finished Jan 21 10:09:50 PM PST 24
Peak memory 145716 kb
Host smart-31c137d3-c2b8-4f3e-a3d2-8c6cb31a2429
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3663315875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3663315875
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1995088609
Short name T49
Test name
Test status
Simulation time 28821159 ps
CPU time 0.44 seconds
Started Jan 21 10:09:45 PM PST 24
Finished Jan 21 10:09:50 PM PST 24
Peak memory 145732 kb
Host smart-a17dd054-99da-413d-b31b-a6cec8d0466d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1995088609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1995088609
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3689135681
Short name T37
Test name
Test status
Simulation time 9097101 ps
CPU time 0.39 seconds
Started Jan 21 07:47:42 PM PST 24
Finished Jan 21 07:47:43 PM PST 24
Peak memory 145008 kb
Host smart-acf3a4b2-dba0-47c3-94ef-522e2f78057d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3689135681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3689135681
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3204925598
Short name T60
Test name
Test status
Simulation time 8527044 ps
CPU time 0.39 seconds
Started Jan 21 07:47:38 PM PST 24
Finished Jan 21 07:47:40 PM PST 24
Peak memory 145100 kb
Host smart-ffa7b493-8d30-4f6a-acd7-25f101b16bae
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3204925598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3204925598
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3131174307
Short name T36
Test name
Test status
Simulation time 9556649 ps
CPU time 0.39 seconds
Started Jan 21 07:47:56 PM PST 24
Finished Jan 21 07:47:57 PM PST 24
Peak memory 145088 kb
Host smart-5da86e6b-3928-4e85-969d-0fcedb02f0c4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3131174307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3131174307
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.892201493
Short name T58
Test name
Test status
Simulation time 8060236 ps
CPU time 0.42 seconds
Started Jan 21 07:47:59 PM PST 24
Finished Jan 21 07:48:00 PM PST 24
Peak memory 145164 kb
Host smart-903f76a5-8527-4c94-9a21-583fb32e4545
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=892201493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.892201493
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3143762419
Short name T61
Test name
Test status
Simulation time 8887317 ps
CPU time 0.39 seconds
Started Jan 21 07:47:57 PM PST 24
Finished Jan 21 07:47:59 PM PST 24
Peak memory 144992 kb
Host smart-0a9513ce-b2d5-4287-b21b-437f27ec06ef
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3143762419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3143762419
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3769042490
Short name T55
Test name
Test status
Simulation time 10031289 ps
CPU time 0.4 seconds
Started Jan 21 07:47:52 PM PST 24
Finished Jan 21 07:47:53 PM PST 24
Peak memory 145076 kb
Host smart-6a989f68-bdfb-414b-9be5-1ded250368a0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3769042490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3769042490
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.1175801201
Short name T30
Test name
Test status
Simulation time 8343766 ps
CPU time 0.45 seconds
Started Jan 21 07:47:59 PM PST 24
Finished Jan 21 07:48:00 PM PST 24
Peak memory 145020 kb
Host smart-3e208960-c38b-4451-bd22-40801ac15f24
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1175801201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1175801201
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.245679454
Short name T62
Test name
Test status
Simulation time 9448716 ps
CPU time 0.44 seconds
Started Jan 21 07:47:57 PM PST 24
Finished Jan 21 07:47:59 PM PST 24
Peak memory 144988 kb
Host smart-dacdd51d-d2b4-4a2c-993e-0affae68c4b1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=245679454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.245679454
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1379098754
Short name T54
Test name
Test status
Simulation time 9695002 ps
CPU time 0.4 seconds
Started Jan 21 07:47:57 PM PST 24
Finished Jan 21 07:47:59 PM PST 24
Peak memory 145076 kb
Host smart-a9a0f691-0ef9-4015-837f-38def25f5f0e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1379098754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1379098754
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.827008970
Short name T33
Test name
Test status
Simulation time 9453427 ps
CPU time 0.42 seconds
Started Jan 21 07:47:56 PM PST 24
Finished Jan 21 07:47:57 PM PST 24
Peak memory 145060 kb
Host smart-84a68b38-1262-4ccf-b7ac-d3797adc7f8f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=827008970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.827008970
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.601482688
Short name T57
Test name
Test status
Simulation time 8620116 ps
CPU time 0.41 seconds
Started Jan 21 07:47:59 PM PST 24
Finished Jan 21 07:48:01 PM PST 24
Peak memory 145044 kb
Host smart-5fa611fe-9a1b-4ac7-ab69-a80fd8e358a9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=601482688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.601482688
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1200880530
Short name T59
Test name
Test status
Simulation time 10045218 ps
CPU time 0.39 seconds
Started Jan 21 07:47:38 PM PST 24
Finished Jan 21 07:47:39 PM PST 24
Peak memory 145088 kb
Host smart-3b34e3da-c97e-4cf8-93d3-52aa55581587
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1200880530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1200880530
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1363705134
Short name T35
Test name
Test status
Simulation time 10953871 ps
CPU time 0.45 seconds
Started Jan 21 07:47:38 PM PST 24
Finished Jan 21 07:47:40 PM PST 24
Peak memory 145020 kb
Host smart-c7577d63-9df9-44c2-8d06-e81ad08b859d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1363705134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1363705134
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2714073116
Short name T38
Test name
Test status
Simulation time 9237336 ps
CPU time 0.39 seconds
Started Jan 21 07:47:38 PM PST 24
Finished Jan 21 07:47:39 PM PST 24
Peak memory 145056 kb
Host smart-27b9dbd5-ac4c-47a9-a672-1ec6714463a7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2714073116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2714073116
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1332794866
Short name T56
Test name
Test status
Simulation time 8245861 ps
CPU time 0.39 seconds
Started Jan 21 07:47:51 PM PST 24
Finished Jan 21 07:47:52 PM PST 24
Peak memory 145080 kb
Host smart-cc423833-cde5-42b6-9d72-d4b520c631a4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1332794866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1332794866
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1259286637
Short name T34
Test name
Test status
Simulation time 9320442 ps
CPU time 0.4 seconds
Started Jan 21 07:47:53 PM PST 24
Finished Jan 21 07:47:54 PM PST 24
Peak memory 145100 kb
Host smart-d10746ab-37ef-45b6-81c1-74146822b3b4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1259286637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1259286637
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3650400415
Short name T31
Test name
Test status
Simulation time 9479427 ps
CPU time 0.4 seconds
Started Jan 21 07:47:53 PM PST 24
Finished Jan 21 07:47:55 PM PST 24
Peak memory 145016 kb
Host smart-64847abb-f7cd-45c6-91e2-a2faadab407f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3650400415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3650400415
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1320282290
Short name T29
Test name
Test status
Simulation time 10097779 ps
CPU time 0.4 seconds
Started Jan 21 07:47:59 PM PST 24
Finished Jan 21 07:48:01 PM PST 24
Peak memory 145048 kb
Host smart-9bf16ec2-ed0e-402b-bc94-9124f688e8df
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1320282290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1320282290
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3616382783
Short name T32
Test name
Test status
Simulation time 8626760 ps
CPU time 0.39 seconds
Started Jan 21 07:47:55 PM PST 24
Finished Jan 21 07:47:57 PM PST 24
Peak memory 145064 kb
Host smart-4c6fce78-5137-464b-a467-4a3400146f25
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3616382783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3616382783
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3220576006
Short name T68
Test name
Test status
Simulation time 26535315 ps
CPU time 0.4 seconds
Started Jan 21 10:09:34 PM PST 24
Finished Jan 21 10:09:36 PM PST 24
Peak memory 145120 kb
Host smart-3d6d86a3-a097-4ef2-9a2e-d59ba85e5a9e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3220576006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3220576006
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.483029533
Short name T72
Test name
Test status
Simulation time 25108581 ps
CPU time 0.4 seconds
Started Jan 21 10:35:47 PM PST 24
Finished Jan 21 10:35:54 PM PST 24
Peak memory 145128 kb
Host smart-4131098b-b5ec-466a-8709-5cc397dc8d85
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=483029533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.483029533
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1946546769
Short name T17
Test name
Test status
Simulation time 26736644 ps
CPU time 0.39 seconds
Started Jan 21 10:09:35 PM PST 24
Finished Jan 21 10:09:37 PM PST 24
Peak memory 145172 kb
Host smart-144b7bd7-2f84-44af-a133-5f330eefa624
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1946546769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1946546769
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2184148189
Short name T66
Test name
Test status
Simulation time 26043597 ps
CPU time 0.4 seconds
Started Jan 21 10:09:37 PM PST 24
Finished Jan 21 10:09:38 PM PST 24
Peak memory 145128 kb
Host smart-530dd3cb-3981-455f-a7e7-f1a377f62633
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2184148189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2184148189
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1241514612
Short name T77
Test name
Test status
Simulation time 26587906 ps
CPU time 0.42 seconds
Started Jan 21 10:09:33 PM PST 24
Finished Jan 21 10:09:35 PM PST 24
Peak memory 145176 kb
Host smart-43fcb362-a602-4435-9795-fd353bcdf94b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1241514612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1241514612
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3174952586
Short name T69
Test name
Test status
Simulation time 28448223 ps
CPU time 0.41 seconds
Started Jan 21 10:09:39 PM PST 24
Finished Jan 21 10:09:43 PM PST 24
Peak memory 145164 kb
Host smart-daf58d08-6613-455b-9112-32f8259ef7df
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3174952586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3174952586
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3168370715
Short name T71
Test name
Test status
Simulation time 27747669 ps
CPU time 0.39 seconds
Started Jan 21 10:09:40 PM PST 24
Finished Jan 21 10:09:44 PM PST 24
Peak memory 145064 kb
Host smart-43a5bff4-07a2-43b4-aa8c-29742e6b67c8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3168370715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3168370715
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3610127457
Short name T73
Test name
Test status
Simulation time 25473540 ps
CPU time 0.4 seconds
Started Jan 21 10:09:40 PM PST 24
Finished Jan 21 10:09:44 PM PST 24
Peak memory 145096 kb
Host smart-84846704-465d-468b-b44b-85b40856e47f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3610127457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3610127457
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.587617240
Short name T70
Test name
Test status
Simulation time 27830697 ps
CPU time 0.41 seconds
Started Jan 21 10:09:41 PM PST 24
Finished Jan 21 10:09:45 PM PST 24
Peak memory 145140 kb
Host smart-94f68a0f-3b70-4547-b1b8-8634232df627
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=587617240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.587617240
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1549847649
Short name T74
Test name
Test status
Simulation time 26403934 ps
CPU time 0.44 seconds
Started Jan 21 10:09:42 PM PST 24
Finished Jan 21 10:09:47 PM PST 24
Peak memory 145168 kb
Host smart-5fe404ef-57cb-496d-b4ec-54d8eb11d778
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1549847649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1549847649
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.130237965
Short name T75
Test name
Test status
Simulation time 28846576 ps
CPU time 0.41 seconds
Started Jan 21 10:09:39 PM PST 24
Finished Jan 21 10:09:43 PM PST 24
Peak memory 145092 kb
Host smart-c06dac01-38ba-487e-8cfc-8b4ef4abe3d0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=130237965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.130237965
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1937437909
Short name T65
Test name
Test status
Simulation time 27813815 ps
CPU time 0.4 seconds
Started Jan 21 10:09:28 PM PST 24
Finished Jan 21 10:09:30 PM PST 24
Peak memory 145088 kb
Host smart-f375f316-da0b-44ee-b72c-d8c187e0295a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1937437909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1937437909
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.891058274
Short name T67
Test name
Test status
Simulation time 26458759 ps
CPU time 0.42 seconds
Started Jan 21 10:09:26 PM PST 24
Finished Jan 21 10:09:27 PM PST 24
Peak memory 145128 kb
Host smart-853f5756-013c-4476-a002-62d001daaddd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=891058274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.891058274
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.767858005
Short name T76
Test name
Test status
Simulation time 26965944 ps
CPU time 0.41 seconds
Started Jan 21 10:09:28 PM PST 24
Finished Jan 21 10:09:29 PM PST 24
Peak memory 145136 kb
Host smart-7bce1b89-26aa-4804-9b82-fb88397d8bb9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=767858005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.767858005
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3726022459
Short name T78
Test name
Test status
Simulation time 25725041 ps
CPU time 0.4 seconds
Started Jan 21 10:26:23 PM PST 24
Finished Jan 21 10:26:42 PM PST 24
Peak memory 145096 kb
Host smart-620f3b45-31e1-4cc4-bd50-d1bd06a5658a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3726022459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3726022459
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.745508113
Short name T64
Test name
Test status
Simulation time 26308639 ps
CPU time 0.4 seconds
Started Jan 21 10:09:37 PM PST 24
Finished Jan 21 10:09:39 PM PST 24
Peak memory 145128 kb
Host smart-e2edebc6-ab23-48a5-97ca-527327226182
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=745508113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.745508113
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3515661867
Short name T14
Test name
Test status
Simulation time 26137401 ps
CPU time 0.41 seconds
Started Jan 21 10:09:37 PM PST 24
Finished Jan 21 10:09:39 PM PST 24
Peak memory 145124 kb
Host smart-8ec46560-94f1-4c7b-961d-a174644ebc31
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3515661867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3515661867
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3496331088
Short name T63
Test name
Test status
Simulation time 28710983 ps
CPU time 0.39 seconds
Started Jan 21 10:09:33 PM PST 24
Finished Jan 21 10:09:34 PM PST 24
Peak memory 145004 kb
Host smart-43c1cd4b-1f9a-467b-8960-bcfc26d73c00
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3496331088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3496331088
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3023645866
Short name T12
Test name
Test status
Simulation time 26385110 ps
CPU time 0.41 seconds
Started Jan 21 10:09:36 PM PST 24
Finished Jan 21 10:09:38 PM PST 24
Peak memory 145116 kb
Host smart-1a34bc7a-4437-4dcd-a29b-a1815daf5429
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3023645866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3023645866
Directory /workspace/9.prim_sync_fatal_alert/latest
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