Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.02 89.02 100.00 100.00 95.83 95.83 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/4.prim_async_alert.698452806
92.74 3.72 100.00 0.00 95.83 0.00 100.00 0.00 85.71 10.71 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/10.prim_sync_alert.2223977265
93.90 1.16 100.00 0.00 95.83 0.00 100.00 0.00 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.273417842
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/19.prim_async_alert.3305923147
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.890465394

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3984915863
/workspace/coverage/default/1.prim_async_alert.14091549
/workspace/coverage/default/10.prim_async_alert.4000935206
/workspace/coverage/default/11.prim_async_alert.1343593033
/workspace/coverage/default/12.prim_async_alert.1539718418
/workspace/coverage/default/13.prim_async_alert.841406220
/workspace/coverage/default/14.prim_async_alert.2380971153
/workspace/coverage/default/15.prim_async_alert.2213415035
/workspace/coverage/default/16.prim_async_alert.722573054
/workspace/coverage/default/17.prim_async_alert.1723794556
/workspace/coverage/default/18.prim_async_alert.3790580121
/workspace/coverage/default/2.prim_async_alert.809743789
/workspace/coverage/default/3.prim_async_alert.2927920780
/workspace/coverage/default/5.prim_async_alert.2687538359
/workspace/coverage/default/6.prim_async_alert.2305731940
/workspace/coverage/default/7.prim_async_alert.1611126783
/workspace/coverage/default/8.prim_async_alert.840021817
/workspace/coverage/default/9.prim_async_alert.3678970816
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.760760652
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1236200185
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2733080939
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4274942662
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.660976496
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.119131656
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1204293366
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.454152101
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3270683836
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.551242336
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.841638173
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3420473833
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.932979859
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.150640703
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2385279229
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4188790132
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1649277323
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1895251704
/workspace/coverage/sync_alert/0.prim_sync_alert.4251746257
/workspace/coverage/sync_alert/1.prim_sync_alert.2878781113
/workspace/coverage/sync_alert/11.prim_sync_alert.667730132
/workspace/coverage/sync_alert/12.prim_sync_alert.359352399
/workspace/coverage/sync_alert/13.prim_sync_alert.2617948553
/workspace/coverage/sync_alert/14.prim_sync_alert.3302297148
/workspace/coverage/sync_alert/15.prim_sync_alert.1181234873
/workspace/coverage/sync_alert/16.prim_sync_alert.2545648813
/workspace/coverage/sync_alert/17.prim_sync_alert.2031113538
/workspace/coverage/sync_alert/18.prim_sync_alert.7596121
/workspace/coverage/sync_alert/19.prim_sync_alert.2169935199
/workspace/coverage/sync_alert/2.prim_sync_alert.3019829459
/workspace/coverage/sync_alert/3.prim_sync_alert.995297868
/workspace/coverage/sync_alert/4.prim_sync_alert.1480836542
/workspace/coverage/sync_alert/5.prim_sync_alert.4085009204
/workspace/coverage/sync_alert/6.prim_sync_alert.2576741607
/workspace/coverage/sync_alert/7.prim_sync_alert.3994930080
/workspace/coverage/sync_alert/8.prim_sync_alert.3035608604
/workspace/coverage/sync_alert/9.prim_sync_alert.1293636695
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1412397910
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3930441842
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3032024473
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1581093580
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2348685791
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.996644494
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.346334577
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3504941443
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1117087485
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.291492709
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.692262046
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4274868737
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.299472479
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1986102629
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1261799140
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3351139582
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1924623626
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.569883407
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1282783971



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/14.prim_async_alert.2380971153 Jan 25 12:23:37 AM PST 24 Jan 25 12:23:38 AM PST 24 11450515 ps
T2 /workspace/coverage/default/8.prim_async_alert.840021817 Jan 24 10:39:50 PM PST 24 Jan 24 10:39:51 PM PST 24 10428168 ps
T3 /workspace/coverage/default/16.prim_async_alert.722573054 Jan 24 10:39:52 PM PST 24 Jan 24 10:39:54 PM PST 24 10687521 ps
T18 /workspace/coverage/default/15.prim_async_alert.2213415035 Jan 24 10:39:52 PM PST 24 Jan 24 10:39:54 PM PST 24 11038913 ps
T7 /workspace/coverage/default/11.prim_async_alert.1343593033 Jan 24 10:52:45 PM PST 24 Jan 24 10:52:50 PM PST 24 12320827 ps
T13 /workspace/coverage/default/5.prim_async_alert.2687538359 Jan 24 10:39:41 PM PST 24 Jan 24 10:39:43 PM PST 24 11048583 ps
T8 /workspace/coverage/default/17.prim_async_alert.1723794556 Jan 24 10:40:07 PM PST 24 Jan 24 10:40:08 PM PST 24 11606729 ps
T9 /workspace/coverage/default/19.prim_async_alert.3305923147 Jan 24 10:40:04 PM PST 24 Jan 24 10:40:06 PM PST 24 12129978 ps
T10 /workspace/coverage/default/7.prim_async_alert.1611126783 Jan 24 10:39:41 PM PST 24 Jan 24 10:39:42 PM PST 24 12140310 ps
T19 /workspace/coverage/default/4.prim_async_alert.698452806 Jan 24 10:39:42 PM PST 24 Jan 24 10:39:43 PM PST 24 12429370 ps
T20 /workspace/coverage/default/0.prim_async_alert.3984915863 Jan 24 10:39:45 PM PST 24 Jan 24 10:39:46 PM PST 24 11503952 ps
T21 /workspace/coverage/default/18.prim_async_alert.3790580121 Jan 24 10:40:06 PM PST 24 Jan 24 10:40:07 PM PST 24 11115771 ps
T11 /workspace/coverage/default/9.prim_async_alert.3678970816 Jan 24 10:39:55 PM PST 24 Jan 24 10:39:56 PM PST 24 11593873 ps
T22 /workspace/coverage/default/13.prim_async_alert.841406220 Jan 24 10:39:51 PM PST 24 Jan 24 10:39:52 PM PST 24 10771987 ps
T45 /workspace/coverage/default/6.prim_async_alert.2305731940 Jan 24 10:39:42 PM PST 24 Jan 24 10:39:43 PM PST 24 10346058 ps
T23 /workspace/coverage/default/10.prim_async_alert.4000935206 Jan 24 10:39:53 PM PST 24 Jan 24 10:39:54 PM PST 24 12400798 ps
T14 /workspace/coverage/default/12.prim_async_alert.1539718418 Jan 24 10:39:54 PM PST 24 Jan 24 10:39:55 PM PST 24 11543715 ps
T46 /workspace/coverage/default/1.prim_async_alert.14091549 Jan 24 10:39:44 PM PST 24 Jan 24 10:39:45 PM PST 24 11307394 ps
T47 /workspace/coverage/default/2.prim_async_alert.809743789 Jan 24 10:39:45 PM PST 24 Jan 24 10:39:46 PM PST 24 10698210 ps
T48 /workspace/coverage/default/3.prim_async_alert.2927920780 Jan 24 10:39:44 PM PST 24 Jan 24 10:39:45 PM PST 24 10906900 ps
T15 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4188790132 Jan 24 12:42:48 PM PST 24 Jan 24 12:43:31 PM PST 24 29327322 ps
T16 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.841638173 Jan 24 12:42:47 PM PST 24 Jan 24 12:43:29 PM PST 24 29066436 ps
T24 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1236200185 Jan 24 12:42:50 PM PST 24 Jan 24 12:43:31 PM PST 24 29298486 ps
T39 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.119131656 Jan 24 12:42:44 PM PST 24 Jan 24 12:43:27 PM PST 24 31589672 ps
T40 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.150640703 Jan 24 12:42:44 PM PST 24 Jan 24 12:43:27 PM PST 24 30394491 ps
T41 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1895251704 Jan 24 12:42:51 PM PST 24 Jan 24 12:43:33 PM PST 24 30741206 ps
T42 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.273417842 Jan 24 12:42:50 PM PST 24 Jan 24 12:43:31 PM PST 24 30158368 ps
T43 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3420473833 Jan 24 12:42:48 PM PST 24 Jan 24 12:43:31 PM PST 24 28882202 ps
T44 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.551242336 Jan 24 12:42:56 PM PST 24 Jan 24 12:43:40 PM PST 24 31621700 ps
T38 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1649277323 Jan 24 12:42:47 PM PST 24 Jan 24 12:43:30 PM PST 24 30814388 ps
T49 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.760760652 Jan 24 12:42:48 PM PST 24 Jan 24 12:43:31 PM PST 24 29334684 ps
T50 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4274942662 Jan 24 12:42:47 PM PST 24 Jan 24 12:43:30 PM PST 24 29213101 ps
T17 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.660976496 Jan 24 12:42:52 PM PST 24 Jan 24 12:43:34 PM PST 24 29751406 ps
T12 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2733080939 Jan 24 12:42:48 PM PST 24 Jan 24 12:43:31 PM PST 24 31006575 ps
T51 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.932979859 Jan 24 12:42:49 PM PST 24 Jan 24 12:43:31 PM PST 24 30423885 ps
T52 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.454152101 Jan 24 12:43:06 PM PST 24 Jan 24 12:43:53 PM PST 24 30579334 ps
T53 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1204293366 Jan 24 12:42:48 PM PST 24 Jan 24 12:43:30 PM PST 24 29785249 ps
T54 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3270683836 Jan 24 12:43:06 PM PST 24 Jan 24 12:43:53 PM PST 24 30404185 ps
T55 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2385279229 Jan 24 12:42:47 PM PST 24 Jan 24 12:43:30 PM PST 24 29484064 ps
T25 /workspace/coverage/sync_alert/15.prim_sync_alert.1181234873 Jan 25 04:57:27 AM PST 24 Jan 25 04:57:29 AM PST 24 10251214 ps
T35 /workspace/coverage/sync_alert/13.prim_sync_alert.2617948553 Jan 25 04:49:51 AM PST 24 Jan 25 04:50:00 AM PST 24 9311934 ps
T36 /workspace/coverage/sync_alert/2.prim_sync_alert.3019829459 Jan 25 04:49:40 AM PST 24 Jan 25 04:49:55 AM PST 24 8974436 ps
T37 /workspace/coverage/sync_alert/17.prim_sync_alert.2031113538 Jan 25 04:49:59 AM PST 24 Jan 25 04:50:08 AM PST 24 9814896 ps
T26 /workspace/coverage/sync_alert/12.prim_sync_alert.359352399 Jan 25 04:49:55 AM PST 24 Jan 25 04:50:05 AM PST 24 9329035 ps
T27 /workspace/coverage/sync_alert/16.prim_sync_alert.2545648813 Jan 25 04:50:01 AM PST 24 Jan 25 04:50:09 AM PST 24 8600238 ps
T28 /workspace/coverage/sync_alert/10.prim_sync_alert.2223977265 Jan 25 04:49:49 AM PST 24 Jan 25 04:49:59 AM PST 24 8562349 ps
T29 /workspace/coverage/sync_alert/5.prim_sync_alert.4085009204 Jan 25 04:49:46 AM PST 24 Jan 25 04:49:57 AM PST 24 8873259 ps
T30 /workspace/coverage/sync_alert/14.prim_sync_alert.3302297148 Jan 25 04:49:51 AM PST 24 Jan 25 04:50:00 AM PST 24 9595971 ps
T31 /workspace/coverage/sync_alert/8.prim_sync_alert.3035608604 Jan 25 05:27:02 AM PST 24 Jan 25 05:27:04 AM PST 24 9528140 ps
T32 /workspace/coverage/sync_alert/3.prim_sync_alert.995297868 Jan 25 05:24:59 AM PST 24 Jan 25 05:25:00 AM PST 24 9423827 ps
T33 /workspace/coverage/sync_alert/19.prim_sync_alert.2169935199 Jan 25 04:49:59 AM PST 24 Jan 25 04:50:08 AM PST 24 10361447 ps
T34 /workspace/coverage/sync_alert/7.prim_sync_alert.3994930080 Jan 25 04:49:39 AM PST 24 Jan 25 04:49:54 AM PST 24 9209550 ps
T56 /workspace/coverage/sync_alert/6.prim_sync_alert.2576741607 Jan 25 05:25:23 AM PST 24 Jan 25 05:25:26 AM PST 24 9971955 ps
T57 /workspace/coverage/sync_alert/9.prim_sync_alert.1293636695 Jan 25 04:49:50 AM PST 24 Jan 25 04:49:59 AM PST 24 9838908 ps
T58 /workspace/coverage/sync_alert/0.prim_sync_alert.4251746257 Jan 25 04:49:41 AM PST 24 Jan 25 04:49:55 AM PST 24 7890632 ps
T59 /workspace/coverage/sync_alert/11.prim_sync_alert.667730132 Jan 25 04:49:51 AM PST 24 Jan 25 04:50:01 AM PST 24 9220192 ps
T60 /workspace/coverage/sync_alert/18.prim_sync_alert.7596121 Jan 25 04:50:03 AM PST 24 Jan 25 04:50:12 AM PST 24 8629707 ps
T61 /workspace/coverage/sync_alert/1.prim_sync_alert.2878781113 Jan 25 06:01:54 AM PST 24 Jan 25 06:01:57 AM PST 24 8741820 ps
T62 /workspace/coverage/sync_alert/4.prim_sync_alert.1480836542 Jan 25 05:08:55 AM PST 24 Jan 25 05:08:57 AM PST 24 8317198 ps
T63 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1282783971 Jan 24 12:42:52 PM PST 24 Jan 24 12:43:34 PM PST 24 27004313 ps
T4 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.890465394 Jan 24 01:04:26 PM PST 24 Jan 24 01:05:08 PM PST 24 27301158 ps
T64 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.291492709 Jan 24 12:42:59 PM PST 24 Jan 24 12:43:43 PM PST 24 27050238 ps
T65 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.299472479 Jan 24 12:42:53 PM PST 24 Jan 24 12:43:34 PM PST 24 27854327 ps
T66 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.346334577 Jan 24 01:03:31 PM PST 24 Jan 24 01:04:06 PM PST 24 26808199 ps
T67 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1117087485 Jan 24 12:42:59 PM PST 24 Jan 24 12:43:43 PM PST 24 27978554 ps
T68 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1581093580 Jan 24 12:42:52 PM PST 24 Jan 24 12:43:34 PM PST 24 31206207 ps
T69 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3930441842 Jan 24 12:49:32 PM PST 24 Jan 24 12:49:52 PM PST 24 28078040 ps
T5 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3504941443 Jan 24 12:42:59 PM PST 24 Jan 24 12:43:43 PM PST 24 26950538 ps
T70 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1412397910 Jan 24 12:43:06 PM PST 24 Jan 24 12:43:53 PM PST 24 30630969 ps
T71 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4274868737 Jan 24 01:03:28 PM PST 24 Jan 24 01:04:00 PM PST 24 26924394 ps
T72 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3351139582 Jan 24 12:42:59 PM PST 24 Jan 24 12:43:43 PM PST 24 26467002 ps
T73 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1924623626 Jan 24 12:43:06 PM PST 24 Jan 24 12:43:53 PM PST 24 26949234 ps
T74 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3032024473 Jan 24 01:25:15 PM PST 24 Jan 24 01:26:00 PM PST 24 28945944 ps
T75 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.692262046 Jan 24 01:05:42 PM PST 24 Jan 24 01:06:33 PM PST 24 27903822 ps
T76 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1986102629 Jan 24 12:42:59 PM PST 24 Jan 24 12:43:43 PM PST 24 27539552 ps
T77 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1261799140 Jan 24 12:43:06 PM PST 24 Jan 24 12:43:53 PM PST 24 27787261 ps
T78 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.569883407 Jan 24 12:42:59 PM PST 24 Jan 24 12:43:43 PM PST 24 28618386 ps
T6 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.996644494 Jan 24 12:56:37 PM PST 24 Jan 24 12:57:07 PM PST 24 28970291 ps
T79 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2348685791 Jan 24 12:53:42 PM PST 24 Jan 24 12:54:03 PM PST 24 27250057 ps

Test location /workspace/coverage/default/4.prim_async_alert.698452806
Short name T19
Test name
Test status
Simulation time 12429370 ps
CPU time 0.39 seconds
Started Jan 24 10:39:42 PM PST 24
Finished Jan 24 10:39:43 PM PST 24
Peak memory 145872 kb
Host smart-46d01910-4b02-4bb1-9d23-a0cf985bc834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698452806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.698452806
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2223977265
Short name T28
Test name
Test status
Simulation time 8562349 ps
CPU time 0.39 seconds
Started Jan 25 04:49:49 AM PST 24
Finished Jan 25 04:49:59 AM PST 24
Peak memory 145100 kb
Host smart-c77f9379-7395-49d4-afb6-605d0839347a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2223977265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2223977265
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.273417842
Short name T42
Test name
Test status
Simulation time 30158368 ps
CPU time 0.41 seconds
Started Jan 24 12:42:50 PM PST 24
Finished Jan 24 12:43:31 PM PST 24
Peak memory 145436 kb
Host smart-b82d9945-e63d-424b-98b7-5677be55c7b6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=273417842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.273417842
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3305923147
Short name T9
Test name
Test status
Simulation time 12129978 ps
CPU time 0.38 seconds
Started Jan 24 10:40:04 PM PST 24
Finished Jan 24 10:40:06 PM PST 24
Peak memory 145880 kb
Host smart-a1de4e32-fb33-499f-a814-e5eb6815402a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305923147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3305923147
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.890465394
Short name T4
Test name
Test status
Simulation time 27301158 ps
CPU time 0.39 seconds
Started Jan 24 01:04:26 PM PST 24
Finished Jan 24 01:05:08 PM PST 24
Peak memory 145076 kb
Host smart-23957251-1729-43b4-9bd5-9c710c206bb2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=890465394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.890465394
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3984915863
Short name T20
Test name
Test status
Simulation time 11503952 ps
CPU time 0.38 seconds
Started Jan 24 10:39:45 PM PST 24
Finished Jan 24 10:39:46 PM PST 24
Peak memory 145880 kb
Host smart-aad5239f-8a17-4151-9e86-1a1526d3e54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984915863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3984915863
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.14091549
Short name T46
Test name
Test status
Simulation time 11307394 ps
CPU time 0.37 seconds
Started Jan 24 10:39:44 PM PST 24
Finished Jan 24 10:39:45 PM PST 24
Peak memory 146308 kb
Host smart-3e2df352-5cc7-4cd6-9a69-11a1b9930403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14091549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.14091549
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.4000935206
Short name T23
Test name
Test status
Simulation time 12400798 ps
CPU time 0.43 seconds
Started Jan 24 10:39:53 PM PST 24
Finished Jan 24 10:39:54 PM PST 24
Peak memory 145844 kb
Host smart-cb22050b-2add-4a0a-be11-5c8672cf3d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000935206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.4000935206
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1343593033
Short name T7
Test name
Test status
Simulation time 12320827 ps
CPU time 0.39 seconds
Started Jan 24 10:52:45 PM PST 24
Finished Jan 24 10:52:50 PM PST 24
Peak memory 145836 kb
Host smart-3b022d54-976e-45bf-b782-451eba13f660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343593033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1343593033
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1539718418
Short name T14
Test name
Test status
Simulation time 11543715 ps
CPU time 0.4 seconds
Started Jan 24 10:39:54 PM PST 24
Finished Jan 24 10:39:55 PM PST 24
Peak memory 145872 kb
Host smart-186f33a0-21cf-48dc-9b53-c5123fb3da40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539718418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1539718418
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.841406220
Short name T22
Test name
Test status
Simulation time 10771987 ps
CPU time 0.38 seconds
Started Jan 24 10:39:51 PM PST 24
Finished Jan 24 10:39:52 PM PST 24
Peak memory 145844 kb
Host smart-2f796337-8a26-47f2-921c-c3e1ac7f5c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841406220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.841406220
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2380971153
Short name T1
Test name
Test status
Simulation time 11450515 ps
CPU time 0.43 seconds
Started Jan 25 12:23:37 AM PST 24
Finished Jan 25 12:23:38 AM PST 24
Peak memory 145840 kb
Host smart-4761e90b-5c15-4b0b-808f-67e5eb625db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380971153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2380971153
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.2213415035
Short name T18
Test name
Test status
Simulation time 11038913 ps
CPU time 0.38 seconds
Started Jan 24 10:39:52 PM PST 24
Finished Jan 24 10:39:54 PM PST 24
Peak memory 145832 kb
Host smart-fec7f43e-e7fa-4c8c-aa88-0d517e8da213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213415035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2213415035
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.722573054
Short name T3
Test name
Test status
Simulation time 10687521 ps
CPU time 0.43 seconds
Started Jan 24 10:39:52 PM PST 24
Finished Jan 24 10:39:54 PM PST 24
Peak memory 145868 kb
Host smart-80f89963-6100-45ff-962d-6b3ee370129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722573054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.722573054
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1723794556
Short name T8
Test name
Test status
Simulation time 11606729 ps
CPU time 0.39 seconds
Started Jan 24 10:40:07 PM PST 24
Finished Jan 24 10:40:08 PM PST 24
Peak memory 145860 kb
Host smart-9be18e2c-08eb-46c6-bef9-451613727b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723794556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1723794556
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3790580121
Short name T21
Test name
Test status
Simulation time 11115771 ps
CPU time 0.39 seconds
Started Jan 24 10:40:06 PM PST 24
Finished Jan 24 10:40:07 PM PST 24
Peak memory 145836 kb
Host smart-f49fc08f-3970-4329-94ed-d81a3a3f8508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790580121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3790580121
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.809743789
Short name T47
Test name
Test status
Simulation time 10698210 ps
CPU time 0.39 seconds
Started Jan 24 10:39:45 PM PST 24
Finished Jan 24 10:39:46 PM PST 24
Peak memory 145876 kb
Host smart-aef4e57d-df1c-4dee-8e47-25e927612d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809743789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.809743789
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2927920780
Short name T48
Test name
Test status
Simulation time 10906900 ps
CPU time 0.38 seconds
Started Jan 24 10:39:44 PM PST 24
Finished Jan 24 10:39:45 PM PST 24
Peak memory 145616 kb
Host smart-c753e179-93ed-4a39-92e8-dec486948a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927920780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2927920780
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2687538359
Short name T13
Test name
Test status
Simulation time 11048583 ps
CPU time 0.4 seconds
Started Jan 24 10:39:41 PM PST 24
Finished Jan 24 10:39:43 PM PST 24
Peak memory 145872 kb
Host smart-e008ddfa-65df-4f70-bc38-f8292a7ea821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687538359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2687538359
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.2305731940
Short name T45
Test name
Test status
Simulation time 10346058 ps
CPU time 0.38 seconds
Started Jan 24 10:39:42 PM PST 24
Finished Jan 24 10:39:43 PM PST 24
Peak memory 145872 kb
Host smart-198debe1-4c63-47f5-ae76-7019dc28390f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305731940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2305731940
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1611126783
Short name T10
Test name
Test status
Simulation time 12140310 ps
CPU time 0.41 seconds
Started Jan 24 10:39:41 PM PST 24
Finished Jan 24 10:39:42 PM PST 24
Peak memory 145876 kb
Host smart-2eb0339f-a0d4-4a13-875c-3742a3b0c25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611126783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1611126783
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.840021817
Short name T2
Test name
Test status
Simulation time 10428168 ps
CPU time 0.38 seconds
Started Jan 24 10:39:50 PM PST 24
Finished Jan 24 10:39:51 PM PST 24
Peak memory 145848 kb
Host smart-b4b90a19-6143-4629-bb86-06627856e495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840021817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.840021817
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3678970816
Short name T11
Test name
Test status
Simulation time 11593873 ps
CPU time 0.4 seconds
Started Jan 24 10:39:55 PM PST 24
Finished Jan 24 10:39:56 PM PST 24
Peak memory 145864 kb
Host smart-f0d5d324-8c6c-41a0-b0f1-8af1aa5e15c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678970816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3678970816
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.760760652
Short name T49
Test name
Test status
Simulation time 29334684 ps
CPU time 0.46 seconds
Started Jan 24 12:42:48 PM PST 24
Finished Jan 24 12:43:31 PM PST 24
Peak memory 144664 kb
Host smart-91e3678b-ca42-4352-9f68-4f5973e937d0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=760760652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.760760652
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1236200185
Short name T24
Test name
Test status
Simulation time 29298486 ps
CPU time 0.42 seconds
Started Jan 24 12:42:50 PM PST 24
Finished Jan 24 12:43:31 PM PST 24
Peak memory 145384 kb
Host smart-bf366076-0e2c-451a-b5cf-2b79f8a3d206
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1236200185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1236200185
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2733080939
Short name T12
Test name
Test status
Simulation time 31006575 ps
CPU time 0.45 seconds
Started Jan 24 12:42:48 PM PST 24
Finished Jan 24 12:43:31 PM PST 24
Peak memory 144740 kb
Host smart-2fd917e3-4e19-4c05-920f-022edb8a6d8c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2733080939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2733080939
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4274942662
Short name T50
Test name
Test status
Simulation time 29213101 ps
CPU time 0.42 seconds
Started Jan 24 12:42:47 PM PST 24
Finished Jan 24 12:43:30 PM PST 24
Peak memory 145524 kb
Host smart-4b20bc23-52a9-4f9a-a016-8c6abf93878d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4274942662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.4274942662
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.660976496
Short name T17
Test name
Test status
Simulation time 29751406 ps
CPU time 0.43 seconds
Started Jan 24 12:42:52 PM PST 24
Finished Jan 24 12:43:34 PM PST 24
Peak memory 145316 kb
Host smart-f7cb1bda-7727-48ee-89cc-92cdc1a42672
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=660976496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.660976496
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.119131656
Short name T39
Test name
Test status
Simulation time 31589672 ps
CPU time 0.46 seconds
Started Jan 24 12:42:44 PM PST 24
Finished Jan 24 12:43:27 PM PST 24
Peak memory 145204 kb
Host smart-92ba2e15-606a-4d39-97c6-762c249322ba
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=119131656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.119131656
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1204293366
Short name T53
Test name
Test status
Simulation time 29785249 ps
CPU time 0.42 seconds
Started Jan 24 12:42:48 PM PST 24
Finished Jan 24 12:43:30 PM PST 24
Peak memory 145548 kb
Host smart-7b9f90bd-bc38-447b-b098-337b310fc986
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1204293366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1204293366
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.454152101
Short name T52
Test name
Test status
Simulation time 30579334 ps
CPU time 0.47 seconds
Started Jan 24 12:43:06 PM PST 24
Finished Jan 24 12:43:53 PM PST 24
Peak memory 144596 kb
Host smart-4cec2bfa-ef42-4345-9019-aebf7e5fcc75
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=454152101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.454152101
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3270683836
Short name T54
Test name
Test status
Simulation time 30404185 ps
CPU time 0.45 seconds
Started Jan 24 12:43:06 PM PST 24
Finished Jan 24 12:43:53 PM PST 24
Peak memory 144204 kb
Host smart-bb6415c5-a912-4c1a-a746-9fb88fe56e5c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3270683836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3270683836
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.551242336
Short name T44
Test name
Test status
Simulation time 31621700 ps
CPU time 0.42 seconds
Started Jan 24 12:42:56 PM PST 24
Finished Jan 24 12:43:40 PM PST 24
Peak memory 145536 kb
Host smart-90b756f0-94b6-4a3c-988a-713342efa31b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=551242336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.551242336
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.841638173
Short name T16
Test name
Test status
Simulation time 29066436 ps
CPU time 0.45 seconds
Started Jan 24 12:42:47 PM PST 24
Finished Jan 24 12:43:29 PM PST 24
Peak memory 145252 kb
Host smart-ca823dcb-98ca-4352-a7ef-d6853b269693
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=841638173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.841638173
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3420473833
Short name T43
Test name
Test status
Simulation time 28882202 ps
CPU time 0.47 seconds
Started Jan 24 12:42:48 PM PST 24
Finished Jan 24 12:43:31 PM PST 24
Peak memory 144784 kb
Host smart-4815d35b-0955-4f48-8c87-058f7ebb694b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3420473833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3420473833
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.932979859
Short name T51
Test name
Test status
Simulation time 30423885 ps
CPU time 0.41 seconds
Started Jan 24 12:42:49 PM PST 24
Finished Jan 24 12:43:31 PM PST 24
Peak memory 145140 kb
Host smart-63d5d9c2-f6d0-43cb-8353-fa288a101550
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=932979859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.932979859
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.150640703
Short name T40
Test name
Test status
Simulation time 30394491 ps
CPU time 0.43 seconds
Started Jan 24 12:42:44 PM PST 24
Finished Jan 24 12:43:27 PM PST 24
Peak memory 145456 kb
Host smart-facbfd58-34ce-48aa-9457-0fcc6cd1fe5c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=150640703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.150640703
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2385279229
Short name T55
Test name
Test status
Simulation time 29484064 ps
CPU time 0.47 seconds
Started Jan 24 12:42:47 PM PST 24
Finished Jan 24 12:43:30 PM PST 24
Peak memory 145284 kb
Host smart-d44b1802-803d-4be3-a9a0-8ace9cba1ea7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2385279229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2385279229
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4188790132
Short name T15
Test name
Test status
Simulation time 29327322 ps
CPU time 0.44 seconds
Started Jan 24 12:42:48 PM PST 24
Finished Jan 24 12:43:31 PM PST 24
Peak memory 145252 kb
Host smart-b8fab7af-41ba-437b-b0fd-ded0f2353636
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4188790132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.4188790132
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1649277323
Short name T38
Test name
Test status
Simulation time 30814388 ps
CPU time 0.42 seconds
Started Jan 24 12:42:47 PM PST 24
Finished Jan 24 12:43:30 PM PST 24
Peak memory 145520 kb
Host smart-f3217405-021c-44e8-8d3a-cbdaf074303d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1649277323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1649277323
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1895251704
Short name T41
Test name
Test status
Simulation time 30741206 ps
CPU time 0.41 seconds
Started Jan 24 12:42:51 PM PST 24
Finished Jan 24 12:43:33 PM PST 24
Peak memory 145584 kb
Host smart-f80685b5-edee-4fd1-8e6a-e8add09b7fa1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1895251704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1895251704
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.4251746257
Short name T58
Test name
Test status
Simulation time 7890632 ps
CPU time 0.39 seconds
Started Jan 25 04:49:41 AM PST 24
Finished Jan 25 04:49:55 AM PST 24
Peak memory 145100 kb
Host smart-5144e548-2af0-4125-afa6-3f681fab9b5c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4251746257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4251746257
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2878781113
Short name T61
Test name
Test status
Simulation time 8741820 ps
CPU time 0.39 seconds
Started Jan 25 06:01:54 AM PST 24
Finished Jan 25 06:01:57 AM PST 24
Peak memory 145092 kb
Host smart-54aabc5b-9af5-4c1d-b785-1e770c826629
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2878781113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2878781113
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.667730132
Short name T59
Test name
Test status
Simulation time 9220192 ps
CPU time 0.4 seconds
Started Jan 25 04:49:51 AM PST 24
Finished Jan 25 04:50:01 AM PST 24
Peak memory 145108 kb
Host smart-18b1928a-3d8a-4994-b97c-4bc7a8dcb950
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=667730132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.667730132
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.359352399
Short name T26
Test name
Test status
Simulation time 9329035 ps
CPU time 0.39 seconds
Started Jan 25 04:49:55 AM PST 24
Finished Jan 25 04:50:05 AM PST 24
Peak memory 145116 kb
Host smart-184ec88e-7fd6-44ef-bee3-884262a98780
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=359352399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.359352399
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2617948553
Short name T35
Test name
Test status
Simulation time 9311934 ps
CPU time 0.4 seconds
Started Jan 25 04:49:51 AM PST 24
Finished Jan 25 04:50:00 AM PST 24
Peak memory 145076 kb
Host smart-e75d665e-af57-4148-a747-404661bbf1dd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2617948553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2617948553
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3302297148
Short name T30
Test name
Test status
Simulation time 9595971 ps
CPU time 0.39 seconds
Started Jan 25 04:49:51 AM PST 24
Finished Jan 25 04:50:00 AM PST 24
Peak memory 145088 kb
Host smart-fb5e1321-5900-42ed-b586-e6e1a71d2558
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3302297148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3302297148
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1181234873
Short name T25
Test name
Test status
Simulation time 10251214 ps
CPU time 0.39 seconds
Started Jan 25 04:57:27 AM PST 24
Finished Jan 25 04:57:29 AM PST 24
Peak memory 145088 kb
Host smart-cb900aa3-8d2c-40d5-a991-480197159a0d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1181234873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1181234873
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2545648813
Short name T27
Test name
Test status
Simulation time 8600238 ps
CPU time 0.4 seconds
Started Jan 25 04:50:01 AM PST 24
Finished Jan 25 04:50:09 AM PST 24
Peak memory 145088 kb
Host smart-53e5939d-6426-4799-b32a-aa32827583fa
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2545648813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2545648813
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2031113538
Short name T37
Test name
Test status
Simulation time 9814896 ps
CPU time 0.38 seconds
Started Jan 25 04:49:59 AM PST 24
Finished Jan 25 04:50:08 AM PST 24
Peak memory 145016 kb
Host smart-20a46721-3ee9-4887-a888-85da9a1abc7c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2031113538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2031113538
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.7596121
Short name T60
Test name
Test status
Simulation time 8629707 ps
CPU time 0.39 seconds
Started Jan 25 04:50:03 AM PST 24
Finished Jan 25 04:50:12 AM PST 24
Peak memory 145092 kb
Host smart-598dd551-2158-42d1-b7f3-50767fc26912
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=7596121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.7596121
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2169935199
Short name T33
Test name
Test status
Simulation time 10361447 ps
CPU time 0.43 seconds
Started Jan 25 04:49:59 AM PST 24
Finished Jan 25 04:50:08 AM PST 24
Peak memory 145092 kb
Host smart-21b3d109-7dba-426d-b08c-d3580c48d6a5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2169935199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2169935199
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3019829459
Short name T36
Test name
Test status
Simulation time 8974436 ps
CPU time 0.39 seconds
Started Jan 25 04:49:40 AM PST 24
Finished Jan 25 04:49:55 AM PST 24
Peak memory 145092 kb
Host smart-6771f03e-e242-4eb3-80d5-fecae02bbce1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3019829459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3019829459
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.995297868
Short name T32
Test name
Test status
Simulation time 9423827 ps
CPU time 0.39 seconds
Started Jan 25 05:24:59 AM PST 24
Finished Jan 25 05:25:00 AM PST 24
Peak memory 145104 kb
Host smart-eedc8f63-c37e-4556-95f4-c6df3c5c5803
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=995297868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.995297868
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1480836542
Short name T62
Test name
Test status
Simulation time 8317198 ps
CPU time 0.37 seconds
Started Jan 25 05:08:55 AM PST 24
Finished Jan 25 05:08:57 AM PST 24
Peak memory 145132 kb
Host smart-c367914e-e60a-4d5b-8e82-14a657233d07
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1480836542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1480836542
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.4085009204
Short name T29
Test name
Test status
Simulation time 8873259 ps
CPU time 0.4 seconds
Started Jan 25 04:49:46 AM PST 24
Finished Jan 25 04:49:57 AM PST 24
Peak memory 145108 kb
Host smart-0a3467e6-a291-4a1d-a069-94496aee8593
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4085009204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.4085009204
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2576741607
Short name T56
Test name
Test status
Simulation time 9971955 ps
CPU time 0.39 seconds
Started Jan 25 05:25:23 AM PST 24
Finished Jan 25 05:25:26 AM PST 24
Peak memory 145092 kb
Host smart-5d836b43-35e0-4bcc-95d9-e061b7dcd6cd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2576741607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2576741607
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3994930080
Short name T34
Test name
Test status
Simulation time 9209550 ps
CPU time 0.41 seconds
Started Jan 25 04:49:39 AM PST 24
Finished Jan 25 04:49:54 AM PST 24
Peak memory 145116 kb
Host smart-dff7a5c8-50af-4557-ae80-491ea207f275
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3994930080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3994930080
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.3035608604
Short name T31
Test name
Test status
Simulation time 9528140 ps
CPU time 0.39 seconds
Started Jan 25 05:27:02 AM PST 24
Finished Jan 25 05:27:04 AM PST 24
Peak memory 145108 kb
Host smart-77f71319-cfc7-48ca-bfbb-f6e4baece105
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3035608604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3035608604
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1293636695
Short name T57
Test name
Test status
Simulation time 9838908 ps
CPU time 0.39 seconds
Started Jan 25 04:49:50 AM PST 24
Finished Jan 25 04:49:59 AM PST 24
Peak memory 145060 kb
Host smart-08e3c4f6-4ce4-4b19-8f09-cb602765bfc2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1293636695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1293636695
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1412397910
Short name T70
Test name
Test status
Simulation time 30630969 ps
CPU time 0.44 seconds
Started Jan 24 12:43:06 PM PST 24
Finished Jan 24 12:43:53 PM PST 24
Peak memory 144056 kb
Host smart-14ad0fff-392c-4210-8e0a-a1939c48a2f2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1412397910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1412397910
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3930441842
Short name T69
Test name
Test status
Simulation time 28078040 ps
CPU time 0.4 seconds
Started Jan 24 12:49:32 PM PST 24
Finished Jan 24 12:49:52 PM PST 24
Peak memory 145052 kb
Host smart-05ed1329-92cd-4b62-89f7-cc37d36271e5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3930441842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3930441842
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3032024473
Short name T74
Test name
Test status
Simulation time 28945944 ps
CPU time 0.4 seconds
Started Jan 24 01:25:15 PM PST 24
Finished Jan 24 01:26:00 PM PST 24
Peak memory 145144 kb
Host smart-6e1a2d78-f78e-4727-aeb1-35cb5550aad8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3032024473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3032024473
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1581093580
Short name T68
Test name
Test status
Simulation time 31206207 ps
CPU time 0.41 seconds
Started Jan 24 12:42:52 PM PST 24
Finished Jan 24 12:43:34 PM PST 24
Peak memory 144784 kb
Host smart-3e555416-4f7c-4484-8d0e-2e699e2eb0da
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1581093580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1581093580
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2348685791
Short name T79
Test name
Test status
Simulation time 27250057 ps
CPU time 0.46 seconds
Started Jan 24 12:53:42 PM PST 24
Finished Jan 24 12:54:03 PM PST 24
Peak memory 145136 kb
Host smart-f7aba5ba-5462-431b-9d1e-2f3eadf38714
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2348685791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2348685791
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.996644494
Short name T6
Test name
Test status
Simulation time 28970291 ps
CPU time 0.39 seconds
Started Jan 24 12:56:37 PM PST 24
Finished Jan 24 12:57:07 PM PST 24
Peak memory 145140 kb
Host smart-dbd87adc-fd02-44b7-98f1-f9d35169f78c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=996644494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.996644494
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.346334577
Short name T66
Test name
Test status
Simulation time 26808199 ps
CPU time 0.39 seconds
Started Jan 24 01:03:31 PM PST 24
Finished Jan 24 01:04:06 PM PST 24
Peak memory 145076 kb
Host smart-eaf37fa0-bd33-4442-af54-69ff1aba4885
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=346334577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.346334577
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3504941443
Short name T5
Test name
Test status
Simulation time 26950538 ps
CPU time 0.45 seconds
Started Jan 24 12:42:59 PM PST 24
Finished Jan 24 12:43:43 PM PST 24
Peak memory 144608 kb
Host smart-37135990-4124-4aa2-baf9-39e818777e8e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3504941443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3504941443
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1117087485
Short name T67
Test name
Test status
Simulation time 27978554 ps
CPU time 0.41 seconds
Started Jan 24 12:42:59 PM PST 24
Finished Jan 24 12:43:43 PM PST 24
Peak memory 144376 kb
Host smart-d7fbd2c1-51cb-4a57-b3c5-aa26d481d257
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1117087485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1117087485
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.291492709
Short name T64
Test name
Test status
Simulation time 27050238 ps
CPU time 0.39 seconds
Started Jan 24 12:42:59 PM PST 24
Finished Jan 24 12:43:43 PM PST 24
Peak memory 144612 kb
Host smart-1aaf7bc0-940b-4365-9f90-a16d62fd4a77
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=291492709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.291492709
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.692262046
Short name T75
Test name
Test status
Simulation time 27903822 ps
CPU time 0.39 seconds
Started Jan 24 01:05:42 PM PST 24
Finished Jan 24 01:06:33 PM PST 24
Peak memory 145160 kb
Host smart-40f07d3e-abb1-4926-ac9e-a62802a71d8a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=692262046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.692262046
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4274868737
Short name T71
Test name
Test status
Simulation time 26924394 ps
CPU time 0.4 seconds
Started Jan 24 01:03:28 PM PST 24
Finished Jan 24 01:04:00 PM PST 24
Peak memory 145036 kb
Host smart-05b8969e-627d-4d60-8d76-7bd9015e82f5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4274868737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.4274868737
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.299472479
Short name T65
Test name
Test status
Simulation time 27854327 ps
CPU time 0.4 seconds
Started Jan 24 12:42:53 PM PST 24
Finished Jan 24 12:43:34 PM PST 24
Peak memory 145116 kb
Host smart-d7e55e7e-679b-4ed6-9e04-252129c07971
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=299472479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.299472479
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1986102629
Short name T76
Test name
Test status
Simulation time 27539552 ps
CPU time 0.4 seconds
Started Jan 24 12:42:59 PM PST 24
Finished Jan 24 12:43:43 PM PST 24
Peak memory 144628 kb
Host smart-5627051e-2549-49c1-89d1-c4fcbca00740
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1986102629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1986102629
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1261799140
Short name T77
Test name
Test status
Simulation time 27787261 ps
CPU time 0.46 seconds
Started Jan 24 12:43:06 PM PST 24
Finished Jan 24 12:43:53 PM PST 24
Peak memory 144620 kb
Host smart-b97e8dbc-948d-41d7-a9b5-7c91aa8358a3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1261799140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1261799140
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3351139582
Short name T72
Test name
Test status
Simulation time 26467002 ps
CPU time 0.4 seconds
Started Jan 24 12:42:59 PM PST 24
Finished Jan 24 12:43:43 PM PST 24
Peak memory 145256 kb
Host smart-7cf5fe29-b021-468e-b46f-1d9bbe228dcb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3351139582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3351139582
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1924623626
Short name T73
Test name
Test status
Simulation time 26949234 ps
CPU time 0.47 seconds
Started Jan 24 12:43:06 PM PST 24
Finished Jan 24 12:43:53 PM PST 24
Peak memory 144264 kb
Host smart-47180fce-5ef6-4416-96f5-490da11b3339
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1924623626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1924623626
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.569883407
Short name T78
Test name
Test status
Simulation time 28618386 ps
CPU time 0.4 seconds
Started Jan 24 12:42:59 PM PST 24
Finished Jan 24 12:43:43 PM PST 24
Peak memory 144336 kb
Host smart-c256c087-802c-41c2-a345-154193a98d47
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=569883407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.569883407
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1282783971
Short name T63
Test name
Test status
Simulation time 27004313 ps
CPU time 0.42 seconds
Started Jan 24 12:42:52 PM PST 24
Finished Jan 24 12:43:34 PM PST 24
Peak memory 144408 kb
Host smart-26539076-f98d-465a-ac7b-d153700d7eaf
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1282783971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1282783971
Directory /workspace/9.prim_sync_fatal_alert/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%