Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 76
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.88 88.88 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/3.prim_async_alert.635129437
92.01 3.13 100.00 0.00 93.75 0.00 100.00 0.00 85.71 7.14 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/8.prim_sync_alert.1752257338
93.76 1.76 100.00 0.00 93.75 0.00 100.00 0.00 89.29 3.57 95.83 0.00 83.72 6.98 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1811834692
94.50 0.73 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 2.33 /workspace/coverage/default/16.prim_async_alert.2944275408
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1865622888
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/1.prim_sync_alert.825629245

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.803279587
/workspace/coverage/default/1.prim_async_alert.543917330
/workspace/coverage/default/10.prim_async_alert.3147910759
/workspace/coverage/default/11.prim_async_alert.259698185
/workspace/coverage/default/12.prim_async_alert.2658990314
/workspace/coverage/default/13.prim_async_alert.419647445
/workspace/coverage/default/14.prim_async_alert.662569381
/workspace/coverage/default/15.prim_async_alert.3845727147
/workspace/coverage/default/17.prim_async_alert.735682154
/workspace/coverage/default/18.prim_async_alert.391760271
/workspace/coverage/default/19.prim_async_alert.1533891950
/workspace/coverage/default/2.prim_async_alert.3612785891
/workspace/coverage/default/4.prim_async_alert.1516919551
/workspace/coverage/default/5.prim_async_alert.71978783
/workspace/coverage/default/6.prim_async_alert.1163362047
/workspace/coverage/default/7.prim_async_alert.3581703053
/workspace/coverage/default/8.prim_async_alert.2916352612
/workspace/coverage/default/9.prim_async_alert.1083515546
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3159711909
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.653950404
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.4216092459
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.855117252
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.479003912
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1040737583
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2845036182
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1556709974
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.938705844
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1200200779
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.138439722
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1780425476
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3531024916
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3472088470
/workspace/coverage/sync_alert/0.prim_sync_alert.1039097756
/workspace/coverage/sync_alert/10.prim_sync_alert.951719640
/workspace/coverage/sync_alert/11.prim_sync_alert.215235590
/workspace/coverage/sync_alert/12.prim_sync_alert.3123527893
/workspace/coverage/sync_alert/13.prim_sync_alert.1907737262
/workspace/coverage/sync_alert/14.prim_sync_alert.3869266848
/workspace/coverage/sync_alert/15.prim_sync_alert.3018267008
/workspace/coverage/sync_alert/16.prim_sync_alert.1238038816
/workspace/coverage/sync_alert/17.prim_sync_alert.2695760731
/workspace/coverage/sync_alert/18.prim_sync_alert.960720419
/workspace/coverage/sync_alert/19.prim_sync_alert.1423592116
/workspace/coverage/sync_alert/2.prim_sync_alert.756462242
/workspace/coverage/sync_alert/3.prim_sync_alert.2018677682
/workspace/coverage/sync_alert/4.prim_sync_alert.1333118394
/workspace/coverage/sync_alert/5.prim_sync_alert.1885903926
/workspace/coverage/sync_alert/6.prim_sync_alert.2948285397
/workspace/coverage/sync_alert/7.prim_sync_alert.4273329486
/workspace/coverage/sync_alert/9.prim_sync_alert.2731407926
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3836602090
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.678993729
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.732217716
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3415353271
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1528648542
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.705685509
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2500433430
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3003732419
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.945867356
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4123517476
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4193890677
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4074957798
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4115974680
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.103510729
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1093089749
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.200546559
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.315878021
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.719868586
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4222869180
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3107464517



Total test records in report: 76
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/6.prim_async_alert.1163362047 Feb 04 12:22:29 PM PST 24 Feb 04 12:22:33 PM PST 24 11921283 ps
T2 /workspace/coverage/default/13.prim_async_alert.419647445 Feb 04 12:25:42 PM PST 24 Feb 04 12:25:48 PM PST 24 12913827 ps
T3 /workspace/coverage/default/11.prim_async_alert.259698185 Feb 04 12:22:28 PM PST 24 Feb 04 12:22:33 PM PST 24 11701223 ps
T10 /workspace/coverage/default/5.prim_async_alert.71978783 Feb 04 12:24:01 PM PST 24 Feb 04 12:24:03 PM PST 24 11230571 ps
T11 /workspace/coverage/default/19.prim_async_alert.1533891950 Feb 04 12:21:46 PM PST 24 Feb 04 12:21:50 PM PST 24 11624991 ps
T7 /workspace/coverage/default/3.prim_async_alert.635129437 Feb 04 12:25:42 PM PST 24 Feb 04 12:25:48 PM PST 24 12150710 ps
T16 /workspace/coverage/default/15.prim_async_alert.3845727147 Feb 04 12:21:12 PM PST 24 Feb 04 12:21:18 PM PST 24 10377574 ps
T17 /workspace/coverage/default/7.prim_async_alert.3581703053 Feb 04 12:21:12 PM PST 24 Feb 04 12:21:18 PM PST 24 11022950 ps
T18 /workspace/coverage/default/16.prim_async_alert.2944275408 Feb 04 12:29:13 PM PST 24 Feb 04 12:29:18 PM PST 24 11081616 ps
T8 /workspace/coverage/default/4.prim_async_alert.1516919551 Feb 04 12:29:14 PM PST 24 Feb 04 12:29:20 PM PST 24 10951002 ps
T24 /workspace/coverage/default/8.prim_async_alert.2916352612 Feb 04 12:21:13 PM PST 24 Feb 04 12:21:18 PM PST 24 11064497 ps
T14 /workspace/coverage/default/2.prim_async_alert.3612785891 Feb 04 12:28:03 PM PST 24 Feb 04 12:28:06 PM PST 24 11220005 ps
T15 /workspace/coverage/default/18.prim_async_alert.391760271 Feb 04 12:21:13 PM PST 24 Feb 04 12:21:18 PM PST 24 11027151 ps
T25 /workspace/coverage/default/14.prim_async_alert.662569381 Feb 04 12:28:39 PM PST 24 Feb 04 12:28:45 PM PST 24 10978672 ps
T19 /workspace/coverage/default/12.prim_async_alert.2658990314 Feb 04 12:21:10 PM PST 24 Feb 04 12:21:17 PM PST 24 10585560 ps
T20 /workspace/coverage/default/17.prim_async_alert.735682154 Feb 04 12:23:28 PM PST 24 Feb 04 12:23:35 PM PST 24 10880419 ps
T12 /workspace/coverage/default/1.prim_async_alert.543917330 Feb 04 12:28:12 PM PST 24 Feb 04 12:28:15 PM PST 24 11831617 ps
T21 /workspace/coverage/default/9.prim_async_alert.1083515546 Feb 04 12:21:13 PM PST 24 Feb 04 12:21:18 PM PST 24 11778346 ps
T13 /workspace/coverage/default/10.prim_async_alert.3147910759 Feb 04 12:29:13 PM PST 24 Feb 04 12:29:18 PM PST 24 12017224 ps
T22 /workspace/coverage/default/0.prim_async_alert.803279587 Feb 04 12:21:13 PM PST 24 Feb 04 12:21:18 PM PST 24 10630825 ps
T23 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.479003912 Feb 04 12:48:32 PM PST 24 Feb 04 12:48:38 PM PST 24 29740827 ps
T38 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1200200779 Feb 04 12:21:08 PM PST 24 Feb 04 12:21:10 PM PST 24 29409005 ps
T39 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3159711909 Feb 04 12:20:57 PM PST 24 Feb 04 12:20:59 PM PST 24 29358941 ps
T40 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1556709974 Feb 04 12:21:53 PM PST 24 Feb 04 12:21:58 PM PST 24 30862783 ps
T41 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1780425476 Feb 04 12:20:55 PM PST 24 Feb 04 12:20:57 PM PST 24 27686659 ps
T42 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.138439722 Feb 04 12:21:08 PM PST 24 Feb 04 12:21:10 PM PST 24 30088754 ps
T43 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3531024916 Feb 04 12:21:08 PM PST 24 Feb 04 12:21:10 PM PST 24 30123590 ps
T44 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.938705844 Feb 04 12:22:21 PM PST 24 Feb 04 12:22:32 PM PST 24 31703239 ps
T4 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1040737583 Feb 04 12:26:57 PM PST 24 Feb 04 12:27:00 PM PST 24 30722155 ps
T45 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1811834692 Feb 04 12:20:56 PM PST 24 Feb 04 12:20:57 PM PST 24 30963628 ps
T46 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.4216092459 Feb 04 12:21:08 PM PST 24 Feb 04 12:21:10 PM PST 24 33548212 ps
T47 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3472088470 Feb 04 12:22:23 PM PST 24 Feb 04 12:22:32 PM PST 24 30969187 ps
T5 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1865622888 Feb 04 12:20:51 PM PST 24 Feb 04 12:20:53 PM PST 24 30656888 ps
T48 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2845036182 Feb 04 12:55:02 PM PST 24 Feb 04 12:55:06 PM PST 24 28623093 ps
T49 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.653950404 Feb 04 12:28:10 PM PST 24 Feb 04 12:28:14 PM PST 24 28992375 ps
T50 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.855117252 Feb 04 12:21:08 PM PST 24 Feb 04 12:21:10 PM PST 24 30242877 ps
T34 /workspace/coverage/sync_alert/18.prim_sync_alert.960720419 Feb 04 12:26:48 PM PST 24 Feb 04 12:26:51 PM PST 24 9242579 ps
T26 /workspace/coverage/sync_alert/15.prim_sync_alert.3018267008 Feb 04 12:26:48 PM PST 24 Feb 04 12:26:51 PM PST 24 9634492 ps
T27 /workspace/coverage/sync_alert/5.prim_sync_alert.1885903926 Feb 04 12:26:57 PM PST 24 Feb 04 12:27:00 PM PST 24 8428430 ps
T35 /workspace/coverage/sync_alert/8.prim_sync_alert.1752257338 Feb 04 12:22:02 PM PST 24 Feb 04 12:22:05 PM PST 24 8473633 ps
T36 /workspace/coverage/sync_alert/7.prim_sync_alert.4273329486 Feb 04 12:24:40 PM PST 24 Feb 04 12:24:48 PM PST 24 8547842 ps
T37 /workspace/coverage/sync_alert/10.prim_sync_alert.951719640 Feb 04 12:20:57 PM PST 24 Feb 04 12:20:59 PM PST 24 8451136 ps
T28 /workspace/coverage/sync_alert/14.prim_sync_alert.3869266848 Feb 04 12:30:03 PM PST 24 Feb 04 12:30:11 PM PST 24 9272122 ps
T29 /workspace/coverage/sync_alert/4.prim_sync_alert.1333118394 Feb 04 12:27:20 PM PST 24 Feb 04 12:27:25 PM PST 24 10757365 ps
T30 /workspace/coverage/sync_alert/0.prim_sync_alert.1039097756 Feb 04 12:22:52 PM PST 24 Feb 04 12:22:54 PM PST 24 9431666 ps
T31 /workspace/coverage/sync_alert/17.prim_sync_alert.2695760731 Feb 04 12:24:52 PM PST 24 Feb 04 12:24:56 PM PST 24 8900313 ps
T32 /workspace/coverage/sync_alert/6.prim_sync_alert.2948285397 Feb 04 12:30:02 PM PST 24 Feb 04 12:30:10 PM PST 24 9661508 ps
T33 /workspace/coverage/sync_alert/16.prim_sync_alert.1238038816 Feb 04 12:40:42 PM PST 24 Feb 04 12:40:44 PM PST 24 9591112 ps
T9 /workspace/coverage/sync_alert/1.prim_sync_alert.825629245 Feb 04 12:28:41 PM PST 24 Feb 04 12:28:47 PM PST 24 10157028 ps
T51 /workspace/coverage/sync_alert/2.prim_sync_alert.756462242 Feb 04 12:27:13 PM PST 24 Feb 04 12:27:16 PM PST 24 8257795 ps
T52 /workspace/coverage/sync_alert/3.prim_sync_alert.2018677682 Feb 04 12:30:51 PM PST 24 Feb 04 12:30:53 PM PST 24 10132853 ps
T53 /workspace/coverage/sync_alert/12.prim_sync_alert.3123527893 Feb 04 12:27:13 PM PST 24 Feb 04 12:27:16 PM PST 24 10904152 ps
T54 /workspace/coverage/sync_alert/9.prim_sync_alert.2731407926 Feb 04 12:37:02 PM PST 24 Feb 04 12:37:14 PM PST 24 9686051 ps
T55 /workspace/coverage/sync_alert/19.prim_sync_alert.1423592116 Feb 04 12:24:29 PM PST 24 Feb 04 12:24:30 PM PST 24 8957681 ps
T56 /workspace/coverage/sync_alert/11.prim_sync_alert.215235590 Feb 04 12:36:05 PM PST 24 Feb 04 12:36:12 PM PST 24 8685811 ps
T57 /workspace/coverage/sync_alert/13.prim_sync_alert.1907737262 Feb 04 12:28:40 PM PST 24 Feb 04 12:28:47 PM PST 24 9972565 ps
T58 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3836602090 Feb 04 12:26:33 PM PST 24 Feb 04 12:26:36 PM PST 24 26755182 ps
T59 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1093089749 Feb 04 12:22:24 PM PST 24 Feb 04 12:22:32 PM PST 24 28787788 ps
T60 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3003732419 Feb 04 12:28:42 PM PST 24 Feb 04 12:28:48 PM PST 24 27497530 ps
T61 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4193890677 Feb 04 12:23:43 PM PST 24 Feb 04 12:23:47 PM PST 24 27585695 ps
T62 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.719868586 Feb 04 12:23:07 PM PST 24 Feb 04 12:23:09 PM PST 24 27948466 ps
T63 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4074957798 Feb 04 12:23:40 PM PST 24 Feb 04 12:23:46 PM PST 24 26639692 ps
T64 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.315878021 Feb 04 12:28:52 PM PST 24 Feb 04 12:28:55 PM PST 24 27726299 ps
T65 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4115974680 Feb 04 12:21:11 PM PST 24 Feb 04 12:21:17 PM PST 24 27072603 ps
T66 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4123517476 Feb 04 12:23:40 PM PST 24 Feb 04 12:23:46 PM PST 24 26780696 ps
T67 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2500433430 Feb 04 12:26:33 PM PST 24 Feb 04 12:26:37 PM PST 24 25178220 ps
T68 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.103510729 Feb 04 12:21:25 PM PST 24 Feb 04 12:21:31 PM PST 24 27330085 ps
T69 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4222869180 Feb 04 12:21:32 PM PST 24 Feb 04 12:21:33 PM PST 24 28842947 ps
T70 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.945867356 Feb 04 12:23:43 PM PST 24 Feb 04 12:23:47 PM PST 24 28339317 ps
T6 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.732217716 Feb 04 12:22:53 PM PST 24 Feb 04 12:22:59 PM PST 24 28960623 ps
T71 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3107464517 Feb 04 12:22:20 PM PST 24 Feb 04 12:22:32 PM PST 24 30930007 ps
T72 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.678993729 Feb 04 12:22:28 PM PST 24 Feb 04 12:22:33 PM PST 24 26139269 ps
T73 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3415353271 Feb 04 12:23:14 PM PST 24 Feb 04 12:23:15 PM PST 24 28663328 ps
T74 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.705685509 Feb 04 12:23:14 PM PST 24 Feb 04 12:23:15 PM PST 24 26337978 ps
T75 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.200546559 Feb 04 12:26:50 PM PST 24 Feb 04 12:26:58 PM PST 24 27367910 ps
T76 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1528648542 Feb 04 12:22:28 PM PST 24 Feb 04 12:22:33 PM PST 24 28164122 ps

Test location /workspace/coverage/default/3.prim_async_alert.635129437
Short name T7
Test name
Test status
Simulation time 12150710 ps
CPU time 0.39 seconds
Started Feb 04 12:25:42 PM PST 24
Finished Feb 04 12:25:48 PM PST 24
Peak memory 145684 kb
Host smart-cf6c9fc0-d163-4359-872a-5c30a6a78e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635129437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.635129437
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1752257338
Short name T35
Test name
Test status
Simulation time 8473633 ps
CPU time 0.46 seconds
Started Feb 04 12:22:02 PM PST 24
Finished Feb 04 12:22:05 PM PST 24
Peak memory 144500 kb
Host smart-926cd5f0-13c9-41f7-9235-65fddfad5fb3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1752257338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1752257338
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1811834692
Short name T45
Test name
Test status
Simulation time 30963628 ps
CPU time 0.44 seconds
Started Feb 04 12:20:56 PM PST 24
Finished Feb 04 12:20:57 PM PST 24
Peak memory 145252 kb
Host smart-b4acd26b-71e6-4767-9a8e-2bc5b75c2220
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1811834692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1811834692
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2944275408
Short name T18
Test name
Test status
Simulation time 11081616 ps
CPU time 0.43 seconds
Started Feb 04 12:29:13 PM PST 24
Finished Feb 04 12:29:18 PM PST 24
Peak memory 144628 kb
Host smart-575cef5b-45fe-4e13-8c76-97f7bb830f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944275408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2944275408
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1865622888
Short name T5
Test name
Test status
Simulation time 30656888 ps
CPU time 0.41 seconds
Started Feb 04 12:20:51 PM PST 24
Finished Feb 04 12:20:53 PM PST 24
Peak memory 145856 kb
Host smart-1c3c591a-ce48-40c3-b480-33a7a1e5890a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1865622888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1865622888
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.825629245
Short name T9
Test name
Test status
Simulation time 10157028 ps
CPU time 0.42 seconds
Started Feb 04 12:28:41 PM PST 24
Finished Feb 04 12:28:47 PM PST 24
Peak memory 144896 kb
Host smart-4ea4542e-b198-47a4-99a2-8790c585dbfe
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=825629245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.825629245
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.803279587
Short name T22
Test name
Test status
Simulation time 10630825 ps
CPU time 0.44 seconds
Started Feb 04 12:21:13 PM PST 24
Finished Feb 04 12:21:18 PM PST 24
Peak memory 145380 kb
Host smart-ab9dbfa2-529d-4d29-8396-8bdfa4e8615b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803279587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.803279587
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.543917330
Short name T12
Test name
Test status
Simulation time 11831617 ps
CPU time 0.46 seconds
Started Feb 04 12:28:12 PM PST 24
Finished Feb 04 12:28:15 PM PST 24
Peak memory 146052 kb
Host smart-dc8fc80e-3ec0-4375-97ef-7f5e286af0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543917330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.543917330
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3147910759
Short name T13
Test name
Test status
Simulation time 12017224 ps
CPU time 0.46 seconds
Started Feb 04 12:29:13 PM PST 24
Finished Feb 04 12:29:18 PM PST 24
Peak memory 144612 kb
Host smart-05ddb884-6c08-4619-a797-eeb3a82bbe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147910759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3147910759
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.259698185
Short name T3
Test name
Test status
Simulation time 11701223 ps
CPU time 0.42 seconds
Started Feb 04 12:22:28 PM PST 24
Finished Feb 04 12:22:33 PM PST 24
Peak memory 145388 kb
Host smart-59e1ce8b-e608-4d05-891d-a60945130033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259698185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.259698185
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2658990314
Short name T19
Test name
Test status
Simulation time 10585560 ps
CPU time 0.39 seconds
Started Feb 04 12:21:10 PM PST 24
Finished Feb 04 12:21:17 PM PST 24
Peak memory 145156 kb
Host smart-f593019e-b90b-4e44-ac07-e95b30202a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658990314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2658990314
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.419647445
Short name T2
Test name
Test status
Simulation time 12913827 ps
CPU time 0.42 seconds
Started Feb 04 12:25:42 PM PST 24
Finished Feb 04 12:25:48 PM PST 24
Peak memory 145684 kb
Host smart-5cd6600d-be1b-4fb7-8f54-87c2e115cc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419647445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.419647445
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.662569381
Short name T25
Test name
Test status
Simulation time 10978672 ps
CPU time 0.37 seconds
Started Feb 04 12:28:39 PM PST 24
Finished Feb 04 12:28:45 PM PST 24
Peak memory 145620 kb
Host smart-a3c82f33-e044-4773-bde6-0f8de648f506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662569381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.662569381
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.3845727147
Short name T16
Test name
Test status
Simulation time 10377574 ps
CPU time 0.39 seconds
Started Feb 04 12:21:12 PM PST 24
Finished Feb 04 12:21:18 PM PST 24
Peak memory 145380 kb
Host smart-cec01a7c-d19f-4a95-9dcf-bdf08f3d0659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845727147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3845727147
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.735682154
Short name T20
Test name
Test status
Simulation time 10880419 ps
CPU time 0.4 seconds
Started Feb 04 12:23:28 PM PST 24
Finished Feb 04 12:23:35 PM PST 24
Peak memory 145724 kb
Host smart-4e465433-aa8d-4711-94f8-32de9c39dff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735682154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.735682154
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.391760271
Short name T15
Test name
Test status
Simulation time 11027151 ps
CPU time 0.43 seconds
Started Feb 04 12:21:13 PM PST 24
Finished Feb 04 12:21:18 PM PST 24
Peak memory 144168 kb
Host smart-89b4fa2b-d3ce-4ab5-b4da-1a867f38c4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391760271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.391760271
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1533891950
Short name T11
Test name
Test status
Simulation time 11624991 ps
CPU time 0.45 seconds
Started Feb 04 12:21:46 PM PST 24
Finished Feb 04 12:21:50 PM PST 24
Peak memory 145472 kb
Host smart-e98e2d0a-8292-41e3-b99a-ffcb03d86407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533891950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1533891950
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3612785891
Short name T14
Test name
Test status
Simulation time 11220005 ps
CPU time 0.45 seconds
Started Feb 04 12:28:03 PM PST 24
Finished Feb 04 12:28:06 PM PST 24
Peak memory 144544 kb
Host smart-8e669920-5cbb-4fa3-9029-e2381bfd7fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612785891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3612785891
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1516919551
Short name T8
Test name
Test status
Simulation time 10951002 ps
CPU time 0.39 seconds
Started Feb 04 12:29:14 PM PST 24
Finished Feb 04 12:29:20 PM PST 24
Peak memory 145172 kb
Host smart-f3c26f83-20a6-46a3-a9d5-e965ba9cb563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516919551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1516919551
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.71978783
Short name T10
Test name
Test status
Simulation time 11230571 ps
CPU time 0.43 seconds
Started Feb 04 12:24:01 PM PST 24
Finished Feb 04 12:24:03 PM PST 24
Peak memory 145628 kb
Host smart-6707a597-9b88-4e48-b27c-8a1c55113a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71978783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.71978783
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1163362047
Short name T1
Test name
Test status
Simulation time 11921283 ps
CPU time 0.42 seconds
Started Feb 04 12:22:29 PM PST 24
Finished Feb 04 12:22:33 PM PST 24
Peak memory 145388 kb
Host smart-2b8ed51a-b342-4a5d-9271-768debfae273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163362047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1163362047
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3581703053
Short name T17
Test name
Test status
Simulation time 11022950 ps
CPU time 0.42 seconds
Started Feb 04 12:21:12 PM PST 24
Finished Feb 04 12:21:18 PM PST 24
Peak memory 145384 kb
Host smart-1558bd7b-3556-4ff4-bfcb-58933abff443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581703053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3581703053
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2916352612
Short name T24
Test name
Test status
Simulation time 11064497 ps
CPU time 0.39 seconds
Started Feb 04 12:21:13 PM PST 24
Finished Feb 04 12:21:18 PM PST 24
Peak memory 143852 kb
Host smart-eceb781a-f757-4e73-9fd5-92046b9a5e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916352612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2916352612
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1083515546
Short name T21
Test name
Test status
Simulation time 11778346 ps
CPU time 0.4 seconds
Started Feb 04 12:21:13 PM PST 24
Finished Feb 04 12:21:18 PM PST 24
Peak memory 146528 kb
Host smart-ad9df0ec-fa63-4892-a121-8a238b066dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083515546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1083515546
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3159711909
Short name T39
Test name
Test status
Simulation time 29358941 ps
CPU time 0.42 seconds
Started Feb 04 12:20:57 PM PST 24
Finished Feb 04 12:20:59 PM PST 24
Peak memory 145268 kb
Host smart-710fcb11-a87d-419b-8be5-9a2d5caf5cc7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3159711909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3159711909
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.653950404
Short name T49
Test name
Test status
Simulation time 28992375 ps
CPU time 0.4 seconds
Started Feb 04 12:28:10 PM PST 24
Finished Feb 04 12:28:14 PM PST 24
Peak memory 145532 kb
Host smart-a29fcadf-64ce-421a-9a3c-48941adb3e36
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=653950404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.653950404
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.4216092459
Short name T46
Test name
Test status
Simulation time 33548212 ps
CPU time 0.53 seconds
Started Feb 04 12:21:08 PM PST 24
Finished Feb 04 12:21:10 PM PST 24
Peak memory 143448 kb
Host smart-98c71ee5-baab-48c7-96d1-be99ad4101dd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4216092459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.4216092459
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.855117252
Short name T50
Test name
Test status
Simulation time 30242877 ps
CPU time 0.56 seconds
Started Feb 04 12:21:08 PM PST 24
Finished Feb 04 12:21:10 PM PST 24
Peak memory 143416 kb
Host smart-011aa08c-03c3-4f2c-b00f-b2740e8cb24b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=855117252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.855117252
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.479003912
Short name T23
Test name
Test status
Simulation time 29740827 ps
CPU time 0.41 seconds
Started Feb 04 12:48:32 PM PST 24
Finished Feb 04 12:48:38 PM PST 24
Peak memory 145620 kb
Host smart-4dff693f-8e39-4cb6-93ec-4fe50e158b0c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=479003912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.479003912
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1040737583
Short name T4
Test name
Test status
Simulation time 30722155 ps
CPU time 0.47 seconds
Started Feb 04 12:26:57 PM PST 24
Finished Feb 04 12:27:00 PM PST 24
Peak memory 145896 kb
Host smart-9aa4dba5-89cd-4e96-8309-d9768ffdbf0a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1040737583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1040737583
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2845036182
Short name T48
Test name
Test status
Simulation time 28623093 ps
CPU time 0.44 seconds
Started Feb 04 12:55:02 PM PST 24
Finished Feb 04 12:55:06 PM PST 24
Peak memory 145628 kb
Host smart-4a2cfa6b-942c-486b-91b1-70ecc9e2ac10
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2845036182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2845036182
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1556709974
Short name T40
Test name
Test status
Simulation time 30862783 ps
CPU time 0.4 seconds
Started Feb 04 12:21:53 PM PST 24
Finished Feb 04 12:21:58 PM PST 24
Peak memory 145328 kb
Host smart-65c01de7-dfd3-46f5-8bce-9f9306839c9c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1556709974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1556709974
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.938705844
Short name T44
Test name
Test status
Simulation time 31703239 ps
CPU time 0.4 seconds
Started Feb 04 12:22:21 PM PST 24
Finished Feb 04 12:22:32 PM PST 24
Peak memory 145092 kb
Host smart-d7d7489a-0629-4b6d-8dd0-76cdc96f7aed
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=938705844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.938705844
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1200200779
Short name T38
Test name
Test status
Simulation time 29409005 ps
CPU time 0.5 seconds
Started Feb 04 12:21:08 PM PST 24
Finished Feb 04 12:21:10 PM PST 24
Peak memory 144160 kb
Host smart-7e69e16a-ded5-469d-92e3-5960308bfa3d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1200200779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1200200779
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.138439722
Short name T42
Test name
Test status
Simulation time 30088754 ps
CPU time 0.58 seconds
Started Feb 04 12:21:08 PM PST 24
Finished Feb 04 12:21:10 PM PST 24
Peak memory 143924 kb
Host smart-ea568146-0f5f-4021-b007-0283854066fd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=138439722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.138439722
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1780425476
Short name T41
Test name
Test status
Simulation time 27686659 ps
CPU time 0.44 seconds
Started Feb 04 12:20:55 PM PST 24
Finished Feb 04 12:20:57 PM PST 24
Peak memory 145876 kb
Host smart-5f60f4a2-6ac7-46c4-ae73-774f68c044f4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1780425476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1780425476
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3531024916
Short name T43
Test name
Test status
Simulation time 30123590 ps
CPU time 0.5 seconds
Started Feb 04 12:21:08 PM PST 24
Finished Feb 04 12:21:10 PM PST 24
Peak memory 144336 kb
Host smart-72d34f49-f89b-4b1a-801c-63a275d8f00c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3531024916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3531024916
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3472088470
Short name T47
Test name
Test status
Simulation time 30969187 ps
CPU time 0.39 seconds
Started Feb 04 12:22:23 PM PST 24
Finished Feb 04 12:22:32 PM PST 24
Peak memory 146312 kb
Host smart-5744f56a-2ba7-49c4-8ec7-83b29b497498
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3472088470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3472088470
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1039097756
Short name T30
Test name
Test status
Simulation time 9431666 ps
CPU time 0.43 seconds
Started Feb 04 12:22:52 PM PST 24
Finished Feb 04 12:22:54 PM PST 24
Peak memory 144936 kb
Host smart-756d7ba4-0d20-4214-9473-b1380518aa5d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1039097756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1039097756
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.951719640
Short name T37
Test name
Test status
Simulation time 8451136 ps
CPU time 0.39 seconds
Started Feb 04 12:20:57 PM PST 24
Finished Feb 04 12:20:59 PM PST 24
Peak memory 144636 kb
Host smart-1c228732-638f-40b1-a122-15fe76b9e3a1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=951719640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.951719640
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.215235590
Short name T56
Test name
Test status
Simulation time 8685811 ps
CPU time 0.38 seconds
Started Feb 04 12:36:05 PM PST 24
Finished Feb 04 12:36:12 PM PST 24
Peak memory 144948 kb
Host smart-4fd50e64-63aa-4240-b045-d5e55cf0690b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=215235590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.215235590
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3123527893
Short name T53
Test name
Test status
Simulation time 10904152 ps
CPU time 0.4 seconds
Started Feb 04 12:27:13 PM PST 24
Finished Feb 04 12:27:16 PM PST 24
Peak memory 144896 kb
Host smart-1aca7310-6a31-409d-bc40-4c37195c717b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3123527893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3123527893
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1907737262
Short name T57
Test name
Test status
Simulation time 9972565 ps
CPU time 0.38 seconds
Started Feb 04 12:28:40 PM PST 24
Finished Feb 04 12:28:47 PM PST 24
Peak memory 144876 kb
Host smart-2cf88c51-3d4b-4112-84c3-3e2ca4279194
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1907737262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1907737262
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3869266848
Short name T28
Test name
Test status
Simulation time 9272122 ps
CPU time 0.45 seconds
Started Feb 04 12:30:03 PM PST 24
Finished Feb 04 12:30:11 PM PST 24
Peak memory 144668 kb
Host smart-cfff38b2-7900-4f50-a380-52385a8ff3a4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3869266848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3869266848
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3018267008
Short name T26
Test name
Test status
Simulation time 9634492 ps
CPU time 0.43 seconds
Started Feb 04 12:26:48 PM PST 24
Finished Feb 04 12:26:51 PM PST 24
Peak memory 142976 kb
Host smart-71e1d517-ace5-4aa6-b89a-fc9c0338ae99
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3018267008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3018267008
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1238038816
Short name T33
Test name
Test status
Simulation time 9591112 ps
CPU time 0.4 seconds
Started Feb 04 12:40:42 PM PST 24
Finished Feb 04 12:40:44 PM PST 24
Peak memory 145000 kb
Host smart-3dac96d4-7559-40a4-9bf5-bc5994dcd888
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1238038816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1238038816
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2695760731
Short name T31
Test name
Test status
Simulation time 8900313 ps
CPU time 0.43 seconds
Started Feb 04 12:24:52 PM PST 24
Finished Feb 04 12:24:56 PM PST 24
Peak memory 144956 kb
Host smart-7bc6cd93-e6e4-43af-88b3-a786ce291189
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2695760731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2695760731
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.960720419
Short name T34
Test name
Test status
Simulation time 9242579 ps
CPU time 0.44 seconds
Started Feb 04 12:26:48 PM PST 24
Finished Feb 04 12:26:51 PM PST 24
Peak memory 144336 kb
Host smart-1033df56-2c60-4e37-9cfd-f1786ce28eea
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=960720419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.960720419
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1423592116
Short name T55
Test name
Test status
Simulation time 8957681 ps
CPU time 0.39 seconds
Started Feb 04 12:24:29 PM PST 24
Finished Feb 04 12:24:30 PM PST 24
Peak memory 144956 kb
Host smart-cf2f66d8-fa7c-469f-bc69-b0f1a7f7c386
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1423592116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1423592116
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.756462242
Short name T51
Test name
Test status
Simulation time 8257795 ps
CPU time 0.39 seconds
Started Feb 04 12:27:13 PM PST 24
Finished Feb 04 12:27:16 PM PST 24
Peak memory 144892 kb
Host smart-aaa2a997-ffb2-4153-b2ee-6bc671c3d7a3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=756462242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.756462242
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2018677682
Short name T52
Test name
Test status
Simulation time 10132853 ps
CPU time 0.38 seconds
Started Feb 04 12:30:51 PM PST 24
Finished Feb 04 12:30:53 PM PST 24
Peak memory 144916 kb
Host smart-3efe1997-9608-4ecd-93eb-3ca91aaf2188
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2018677682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2018677682
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1333118394
Short name T29
Test name
Test status
Simulation time 10757365 ps
CPU time 0.38 seconds
Started Feb 04 12:27:20 PM PST 24
Finished Feb 04 12:27:25 PM PST 24
Peak memory 144672 kb
Host smart-b5dce227-4bb1-4e80-9033-650f36190d76
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1333118394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1333118394
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1885903926
Short name T27
Test name
Test status
Simulation time 8428430 ps
CPU time 0.4 seconds
Started Feb 04 12:26:57 PM PST 24
Finished Feb 04 12:27:00 PM PST 24
Peak memory 144092 kb
Host smart-1c1f205b-c7c1-4ce8-98ee-b7c87972c789
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1885903926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1885903926
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2948285397
Short name T32
Test name
Test status
Simulation time 9661508 ps
CPU time 0.38 seconds
Started Feb 04 12:30:02 PM PST 24
Finished Feb 04 12:30:10 PM PST 24
Peak memory 144092 kb
Host smart-c168447c-2db3-4297-8968-4033e956762e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2948285397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2948285397
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.4273329486
Short name T36
Test name
Test status
Simulation time 8547842 ps
CPU time 0.4 seconds
Started Feb 04 12:24:40 PM PST 24
Finished Feb 04 12:24:48 PM PST 24
Peak memory 144872 kb
Host smart-ab17d7dc-aa2f-4910-9b32-ad54fbfe2170
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4273329486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.4273329486
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2731407926
Short name T54
Test name
Test status
Simulation time 9686051 ps
CPU time 0.39 seconds
Started Feb 04 12:37:02 PM PST 24
Finished Feb 04 12:37:14 PM PST 24
Peak memory 145028 kb
Host smart-07ad9ee1-a741-4737-a066-1bdb4c6c9cdd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2731407926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2731407926
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3836602090
Short name T58
Test name
Test status
Simulation time 26755182 ps
CPU time 0.38 seconds
Started Feb 04 12:26:33 PM PST 24
Finished Feb 04 12:26:36 PM PST 24
Peak memory 144940 kb
Host smart-9e13dfd6-0ca1-47fa-968c-789a65f4bffc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3836602090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3836602090
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.678993729
Short name T72
Test name
Test status
Simulation time 26139269 ps
CPU time 0.39 seconds
Started Feb 04 12:22:28 PM PST 24
Finished Feb 04 12:22:33 PM PST 24
Peak memory 144772 kb
Host smart-79b0250b-8eff-46bb-9f51-7cee008457e9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=678993729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.678993729
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.732217716
Short name T6
Test name
Test status
Simulation time 28960623 ps
CPU time 0.4 seconds
Started Feb 04 12:22:53 PM PST 24
Finished Feb 04 12:22:59 PM PST 24
Peak memory 145024 kb
Host smart-89a8aafd-eff0-486d-ab60-af3cd16736f8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=732217716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.732217716
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3415353271
Short name T73
Test name
Test status
Simulation time 28663328 ps
CPU time 0.39 seconds
Started Feb 04 12:23:14 PM PST 24
Finished Feb 04 12:23:15 PM PST 24
Peak memory 145028 kb
Host smart-6c822795-76b1-478d-9a79-7f0906ec17a6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3415353271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3415353271
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1528648542
Short name T76
Test name
Test status
Simulation time 28164122 ps
CPU time 0.4 seconds
Started Feb 04 12:22:28 PM PST 24
Finished Feb 04 12:22:33 PM PST 24
Peak memory 144816 kb
Host smart-3094471e-a327-4311-99c1-f04bfe6e7fca
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1528648542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1528648542
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.705685509
Short name T74
Test name
Test status
Simulation time 26337978 ps
CPU time 0.39 seconds
Started Feb 04 12:23:14 PM PST 24
Finished Feb 04 12:23:15 PM PST 24
Peak memory 145032 kb
Host smart-a5c6f4ff-7366-4f19-882f-92a87b5ebb0d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=705685509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.705685509
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2500433430
Short name T67
Test name
Test status
Simulation time 25178220 ps
CPU time 0.38 seconds
Started Feb 04 12:26:33 PM PST 24
Finished Feb 04 12:26:37 PM PST 24
Peak memory 144924 kb
Host smart-6f3135c2-26e7-4704-b7b0-a1e9de98d17b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2500433430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2500433430
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3003732419
Short name T60
Test name
Test status
Simulation time 27497530 ps
CPU time 0.43 seconds
Started Feb 04 12:28:42 PM PST 24
Finished Feb 04 12:28:48 PM PST 24
Peak memory 145020 kb
Host smart-a01d8fd4-a530-45ff-bc9b-ecabb1e57e56
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3003732419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3003732419
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.945867356
Short name T70
Test name
Test status
Simulation time 28339317 ps
CPU time 0.43 seconds
Started Feb 04 12:23:43 PM PST 24
Finished Feb 04 12:23:47 PM PST 24
Peak memory 144948 kb
Host smart-924b942f-1633-470b-af5b-a1aea06f9e06
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=945867356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.945867356
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4123517476
Short name T66
Test name
Test status
Simulation time 26780696 ps
CPU time 0.41 seconds
Started Feb 04 12:23:40 PM PST 24
Finished Feb 04 12:23:46 PM PST 24
Peak memory 144868 kb
Host smart-9f8dd5a1-76ad-40e1-a312-88c6470158e0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4123517476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.4123517476
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4193890677
Short name T61
Test name
Test status
Simulation time 27585695 ps
CPU time 0.41 seconds
Started Feb 04 12:23:43 PM PST 24
Finished Feb 04 12:23:47 PM PST 24
Peak memory 144816 kb
Host smart-e15c4ad2-54e4-40b7-a01e-7c0a037c2e9a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4193890677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.4193890677
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4074957798
Short name T63
Test name
Test status
Simulation time 26639692 ps
CPU time 0.4 seconds
Started Feb 04 12:23:40 PM PST 24
Finished Feb 04 12:23:46 PM PST 24
Peak memory 144820 kb
Host smart-cb802858-aa3b-4ee9-afd3-40e114fde618
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4074957798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4074957798
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4115974680
Short name T65
Test name
Test status
Simulation time 27072603 ps
CPU time 0.41 seconds
Started Feb 04 12:21:11 PM PST 24
Finished Feb 04 12:21:17 PM PST 24
Peak memory 144884 kb
Host smart-5092acc3-1923-4a6e-9889-694c9f953074
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4115974680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.4115974680
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.103510729
Short name T68
Test name
Test status
Simulation time 27330085 ps
CPU time 0.46 seconds
Started Feb 04 12:21:25 PM PST 24
Finished Feb 04 12:21:31 PM PST 24
Peak memory 144616 kb
Host smart-8eea9769-1fde-47f9-8d90-b8264a0fd73b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=103510729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.103510729
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1093089749
Short name T59
Test name
Test status
Simulation time 28787788 ps
CPU time 0.4 seconds
Started Feb 04 12:22:24 PM PST 24
Finished Feb 04 12:22:32 PM PST 24
Peak memory 145008 kb
Host smart-dad5958a-c2c3-4b6c-b178-12ac48a67166
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1093089749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1093089749
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.200546559
Short name T75
Test name
Test status
Simulation time 27367910 ps
CPU time 0.39 seconds
Started Feb 04 12:26:50 PM PST 24
Finished Feb 04 12:26:58 PM PST 24
Peak memory 144728 kb
Host smart-cfeab5b8-ae94-4b6d-b2b2-c891fb5b6ea8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=200546559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.200546559
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.315878021
Short name T64
Test name
Test status
Simulation time 27726299 ps
CPU time 0.4 seconds
Started Feb 04 12:28:52 PM PST 24
Finished Feb 04 12:28:55 PM PST 24
Peak memory 144980 kb
Host smart-bbabed6c-e42f-47e5-88f1-dda70b09344f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=315878021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.315878021
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.719868586
Short name T62
Test name
Test status
Simulation time 27948466 ps
CPU time 0.43 seconds
Started Feb 04 12:23:07 PM PST 24
Finished Feb 04 12:23:09 PM PST 24
Peak memory 144776 kb
Host smart-0c352e14-1929-4203-98d3-6b652ff4f709
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=719868586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.719868586
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4222869180
Short name T69
Test name
Test status
Simulation time 28842947 ps
CPU time 0.42 seconds
Started Feb 04 12:21:32 PM PST 24
Finished Feb 04 12:21:33 PM PST 24
Peak memory 144756 kb
Host smart-af6617fa-914e-4864-b6b1-afe2a41520d2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4222869180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.4222869180
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3107464517
Short name T71
Test name
Test status
Simulation time 30930007 ps
CPU time 0.39 seconds
Started Feb 04 12:22:20 PM PST 24
Finished Feb 04 12:22:32 PM PST 24
Peak memory 144868 kb
Host smart-a64350a9-5d28-451c-9255-f2cd31cc5bd4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3107464517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3107464517
Directory /workspace/9.prim_sync_fatal_alert/latest
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