| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.28 | 88.28 | 100.00 | 100.00 | 93.75 | 93.75 | 96.43 | 96.43 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/15.prim_async_alert.1630612234 |
| 91.02 | 2.74 | 100.00 | 0.00 | 93.75 | 0.00 | 96.43 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 74.42 | 9.30 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3205917903 |
| 93.56 | 2.53 | 100.00 | 0.00 | 93.75 | 0.00 | 96.43 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 11.63 | /workspace/coverage/sync_alert/2.prim_sync_alert.720894731 |
| 94.50 | 0.94 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 3.57 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/0.prim_async_alert.3157901151 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1319075607 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/15.prim_sync_alert.2694544502 |
| Name |
|---|
| /workspace/coverage/default/11.prim_async_alert.3065737014 |
| /workspace/coverage/default/12.prim_async_alert.4262673734 |
| /workspace/coverage/default/13.prim_async_alert.3472373253 |
| /workspace/coverage/default/14.prim_async_alert.838001901 |
| /workspace/coverage/default/16.prim_async_alert.3360308076 |
| /workspace/coverage/default/17.prim_async_alert.762397187 |
| /workspace/coverage/default/18.prim_async_alert.3215512970 |
| /workspace/coverage/default/19.prim_async_alert.3703361978 |
| /workspace/coverage/default/2.prim_async_alert.1236272553 |
| /workspace/coverage/default/3.prim_async_alert.1181465838 |
| /workspace/coverage/default/4.prim_async_alert.3456418548 |
| /workspace/coverage/default/5.prim_async_alert.1149631169 |
| /workspace/coverage/default/6.prim_async_alert.3971608021 |
| /workspace/coverage/default/7.prim_async_alert.4135747045 |
| /workspace/coverage/default/8.prim_async_alert.1242811918 |
| /workspace/coverage/default/9.prim_async_alert.3197215758 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.488934631 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1526059127 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1963111491 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.426355690 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3800091076 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3713761317 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1225077583 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1955462174 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3964101674 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3890231724 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1006052356 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2266880865 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2990125593 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3111927747 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1721822596 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.610936956 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1395121497 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.3011714238 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.3145590759 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.2707076285 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1585867218 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.2136255347 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.376552535 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.2749133480 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.2334064774 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.3582134532 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.2162172219 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.1022734311 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3861581238 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.3476384875 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.765991721 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.3230472388 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.202677736 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.3359910542 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.2736698571 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3202108835 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.423319388 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.404357727 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1734380863 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3197565419 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.151065998 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3184098301 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3194194583 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.172183564 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3826176361 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.262343276 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.960284034 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3437998852 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2287825083 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.630794629 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.555106038 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3943829998 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1063147286 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2308121633 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.755940475 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/15.prim_async_alert.1630612234 | Feb 21 12:32:37 PM PST 24 | Feb 21 12:32:38 PM PST 24 | 11335831 ps | ||
| T2 | /workspace/coverage/default/2.prim_async_alert.1236272553 | Feb 21 12:32:40 PM PST 24 | Feb 21 12:32:41 PM PST 24 | 11352621 ps | ||
| T3 | /workspace/coverage/default/0.prim_async_alert.3157901151 | Feb 21 12:32:43 PM PST 24 | Feb 21 12:32:44 PM PST 24 | 11982851 ps | ||
| T13 | /workspace/coverage/default/6.prim_async_alert.3971608021 | Feb 21 12:32:46 PM PST 24 | Feb 21 12:32:47 PM PST 24 | 11579042 ps | ||
| T7 | /workspace/coverage/default/12.prim_async_alert.4262673734 | Feb 21 12:32:37 PM PST 24 | Feb 21 12:32:38 PM PST 24 | 11675215 ps | ||
| T14 | /workspace/coverage/default/18.prim_async_alert.3215512970 | Feb 21 12:32:26 PM PST 24 | Feb 21 12:32:27 PM PST 24 | 11358920 ps | ||
| T9 | /workspace/coverage/default/16.prim_async_alert.3360308076 | Feb 21 12:32:18 PM PST 24 | Feb 21 12:32:21 PM PST 24 | 11572429 ps | ||
| T19 | /workspace/coverage/default/8.prim_async_alert.1242811918 | Feb 21 12:32:38 PM PST 24 | Feb 21 12:32:39 PM PST 24 | 10945463 ps | ||
| T21 | /workspace/coverage/default/3.prim_async_alert.1181465838 | Feb 21 12:32:40 PM PST 24 | Feb 21 12:32:41 PM PST 24 | 10885274 ps | ||
| T8 | /workspace/coverage/default/7.prim_async_alert.4135747045 | Feb 21 12:32:41 PM PST 24 | Feb 21 12:32:42 PM PST 24 | 11230321 ps | ||
| T26 | /workspace/coverage/default/11.prim_async_alert.3065737014 | Feb 21 12:32:44 PM PST 24 | Feb 21 12:32:45 PM PST 24 | 10577473 ps | ||
| T17 | /workspace/coverage/default/9.prim_async_alert.3197215758 | Feb 21 12:32:41 PM PST 24 | Feb 21 12:32:42 PM PST 24 | 10846587 ps | ||
| T47 | /workspace/coverage/default/19.prim_async_alert.3703361978 | Feb 21 12:32:26 PM PST 24 | Feb 21 12:32:27 PM PST 24 | 10654787 ps | ||
| T15 | /workspace/coverage/default/5.prim_async_alert.1149631169 | Feb 21 12:32:51 PM PST 24 | Feb 21 12:32:53 PM PST 24 | 12556538 ps | ||
| T48 | /workspace/coverage/default/13.prim_async_alert.3472373253 | Feb 21 12:32:41 PM PST 24 | Feb 21 12:32:42 PM PST 24 | 10654727 ps | ||
| T16 | /workspace/coverage/default/17.prim_async_alert.762397187 | Feb 21 12:32:21 PM PST 24 | Feb 21 12:32:22 PM PST 24 | 11866940 ps | ||
| T49 | /workspace/coverage/default/14.prim_async_alert.838001901 | Feb 21 12:32:41 PM PST 24 | Feb 21 12:32:42 PM PST 24 | 11285003 ps | ||
| T18 | /workspace/coverage/default/4.prim_async_alert.3456418548 | Feb 21 12:32:31 PM PST 24 | Feb 21 12:32:31 PM PST 24 | 11038518 ps | ||
| T20 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1006052356 | Feb 21 12:36:07 PM PST 24 | Feb 21 12:36:08 PM PST 24 | 29764432 ps | ||
| T22 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1395121497 | Feb 21 12:35:50 PM PST 24 | Feb 21 12:35:52 PM PST 24 | 30043235 ps | ||
| T23 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3111927747 | Feb 21 12:36:02 PM PST 24 | Feb 21 12:36:04 PM PST 24 | 29375184 ps | ||
| T43 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2990125593 | Feb 21 12:35:42 PM PST 24 | Feb 21 12:35:43 PM PST 24 | 30262022 ps | ||
| T44 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.610936956 | Feb 21 12:36:07 PM PST 24 | Feb 21 12:36:08 PM PST 24 | 31576124 ps | ||
| T24 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3205917903 | Feb 21 12:36:00 PM PST 24 | Feb 21 12:36:01 PM PST 24 | 31258447 ps | ||
| T4 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1319075607 | Feb 21 12:36:21 PM PST 24 | Feb 21 12:36:22 PM PST 24 | 30615822 ps | ||
| T45 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1526059127 | Feb 21 12:36:00 PM PST 24 | Feb 21 12:36:01 PM PST 24 | 31695800 ps | ||
| T25 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.488934631 | Feb 21 12:36:28 PM PST 24 | Feb 21 12:36:29 PM PST 24 | 28995658 ps | ||
| T46 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1955462174 | Feb 21 12:36:03 PM PST 24 | Feb 21 12:36:05 PM PST 24 | 31263632 ps | ||
| T50 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3964101674 | Feb 21 12:36:09 PM PST 24 | Feb 21 12:36:10 PM PST 24 | 31214679 ps | ||
| T51 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3890231724 | Feb 21 12:36:15 PM PST 24 | Feb 21 12:36:17 PM PST 24 | 31077234 ps | ||
| T52 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2266880865 | Feb 21 12:36:02 PM PST 24 | Feb 21 12:36:05 PM PST 24 | 30664296 ps | ||
| T53 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1225077583 | Feb 21 12:35:50 PM PST 24 | Feb 21 12:35:52 PM PST 24 | 31322133 ps | ||
| T54 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1721822596 | Feb 21 12:36:11 PM PST 24 | Feb 21 12:36:12 PM PST 24 | 30421726 ps | ||
| T55 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3800091076 | Feb 21 12:36:07 PM PST 24 | Feb 21 12:36:08 PM PST 24 | 29748687 ps | ||
| T56 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.426355690 | Feb 21 12:35:53 PM PST 24 | Feb 21 12:35:53 PM PST 24 | 32763469 ps | ||
| T57 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1963111491 | Feb 21 12:35:49 PM PST 24 | Feb 21 12:35:52 PM PST 24 | 30839974 ps | ||
| T58 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3713761317 | Feb 21 12:36:18 PM PST 24 | Feb 21 12:36:20 PM PST 24 | 30868828 ps | ||
| T35 | /workspace/coverage/sync_alert/1.prim_sync_alert.3145590759 | Feb 21 02:52:02 PM PST 24 | Feb 21 02:52:03 PM PST 24 | 8583381 ps | ||
| T36 | /workspace/coverage/sync_alert/8.prim_sync_alert.3359910542 | Feb 21 02:51:58 PM PST 24 | Feb 21 02:51:59 PM PST 24 | 9561491 ps | ||
| T37 | /workspace/coverage/sync_alert/19.prim_sync_alert.1022734311 | Feb 21 02:51:56 PM PST 24 | Feb 21 02:51:58 PM PST 24 | 8670670 ps | ||
| T27 | /workspace/coverage/sync_alert/2.prim_sync_alert.720894731 | Feb 21 02:51:57 PM PST 24 | Feb 21 02:51:58 PM PST 24 | 9499036 ps | ||
| T38 | /workspace/coverage/sync_alert/16.prim_sync_alert.2334064774 | Feb 21 02:51:59 PM PST 24 | Feb 21 02:52:01 PM PST 24 | 9085704 ps | ||
| T39 | /workspace/coverage/sync_alert/17.prim_sync_alert.3582134532 | Feb 21 02:51:58 PM PST 24 | Feb 21 02:52:00 PM PST 24 | 8748656 ps | ||
| T40 | /workspace/coverage/sync_alert/5.prim_sync_alert.765991721 | Feb 21 02:51:37 PM PST 24 | Feb 21 02:51:37 PM PST 24 | 9305616 ps | ||
| T28 | /workspace/coverage/sync_alert/13.prim_sync_alert.376552535 | Feb 21 02:52:14 PM PST 24 | Feb 21 02:52:15 PM PST 24 | 8832241 ps | ||
| T41 | /workspace/coverage/sync_alert/14.prim_sync_alert.2749133480 | Feb 21 02:51:51 PM PST 24 | Feb 21 02:51:52 PM PST 24 | 8930739 ps | ||
| T42 | /workspace/coverage/sync_alert/11.prim_sync_alert.1585867218 | Feb 21 02:51:55 PM PST 24 | Feb 21 02:51:57 PM PST 24 | 8883158 ps | ||
| T29 | /workspace/coverage/sync_alert/12.prim_sync_alert.2136255347 | Feb 21 02:51:42 PM PST 24 | Feb 21 02:51:42 PM PST 24 | 9007404 ps | ||
| T30 | /workspace/coverage/sync_alert/0.prim_sync_alert.3011714238 | Feb 21 02:52:03 PM PST 24 | Feb 21 02:52:04 PM PST 24 | 8558955 ps | ||
| T59 | /workspace/coverage/sync_alert/4.prim_sync_alert.3476384875 | Feb 21 02:52:02 PM PST 24 | Feb 21 02:52:03 PM PST 24 | 8623734 ps | ||
| T31 | /workspace/coverage/sync_alert/18.prim_sync_alert.2162172219 | Feb 21 02:51:50 PM PST 24 | Feb 21 02:51:51 PM PST 24 | 9779233 ps | ||
| T10 | /workspace/coverage/sync_alert/15.prim_sync_alert.2694544502 | Feb 21 02:51:58 PM PST 24 | Feb 21 02:51:59 PM PST 24 | 8865032 ps | ||
| T60 | /workspace/coverage/sync_alert/7.prim_sync_alert.202677736 | Feb 21 02:51:58 PM PST 24 | Feb 21 02:51:59 PM PST 24 | 8997460 ps | ||
| T61 | /workspace/coverage/sync_alert/6.prim_sync_alert.3230472388 | Feb 21 02:51:37 PM PST 24 | Feb 21 02:51:38 PM PST 24 | 9707282 ps | ||
| T62 | /workspace/coverage/sync_alert/10.prim_sync_alert.2707076285 | Feb 21 02:52:04 PM PST 24 | Feb 21 02:52:05 PM PST 24 | 8976171 ps | ||
| T11 | /workspace/coverage/sync_alert/9.prim_sync_alert.2736698571 | Feb 21 02:51:58 PM PST 24 | Feb 21 02:51:59 PM PST 24 | 9124701 ps | ||
| T63 | /workspace/coverage/sync_alert/3.prim_sync_alert.3861581238 | Feb 21 02:52:02 PM PST 24 | Feb 21 02:52:03 PM PST 24 | 8997282 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3194194583 | Feb 21 02:51:15 PM PST 24 | Feb 21 02:51:15 PM PST 24 | 27523489 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3202108835 | Feb 21 02:51:09 PM PST 24 | Feb 21 02:51:11 PM PST 24 | 27407910 ps | ||
| T32 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.151065998 | Feb 21 02:50:59 PM PST 24 | Feb 21 02:51:00 PM PST 24 | 27600943 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.555106038 | Feb 21 02:51:04 PM PST 24 | Feb 21 02:51:05 PM PST 24 | 26594700 ps | ||
| T12 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.630794629 | Feb 21 02:50:56 PM PST 24 | Feb 21 02:50:56 PM PST 24 | 27780362 ps | ||
| T33 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.172183564 | Feb 21 02:51:10 PM PST 24 | Feb 21 02:51:11 PM PST 24 | 26949950 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.423319388 | Feb 21 02:50:56 PM PST 24 | Feb 21 02:50:57 PM PST 24 | 28021947 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3184098301 | Feb 21 02:50:59 PM PST 24 | Feb 21 02:51:00 PM PST 24 | 30140450 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.262343276 | Feb 21 02:51:09 PM PST 24 | Feb 21 02:51:10 PM PST 24 | 29602815 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.755940475 | Feb 21 02:51:02 PM PST 24 | Feb 21 02:51:03 PM PST 24 | 29457064 ps | ||
| T34 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3943829998 | Feb 21 02:51:02 PM PST 24 | Feb 21 02:51:03 PM PST 24 | 28121866 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3197565419 | Feb 21 02:51:04 PM PST 24 | Feb 21 02:51:04 PM PST 24 | 27232362 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.960284034 | Feb 21 02:51:16 PM PST 24 | Feb 21 02:51:16 PM PST 24 | 27991245 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2308121633 | Feb 21 02:50:58 PM PST 24 | Feb 21 02:50:59 PM PST 24 | 27179215 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1063147286 | Feb 21 02:50:59 PM PST 24 | Feb 21 02:51:00 PM PST 24 | 26870325 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3826176361 | Feb 21 02:50:57 PM PST 24 | Feb 21 02:50:58 PM PST 24 | 27045242 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1734380863 | Feb 21 02:50:59 PM PST 24 | Feb 21 02:51:00 PM PST 24 | 24627478 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3437998852 | Feb 21 02:51:00 PM PST 24 | Feb 21 02:51:00 PM PST 24 | 28246585 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2287825083 | Feb 21 02:51:02 PM PST 24 | Feb 21 02:51:03 PM PST 24 | 27722429 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.404357727 | Feb 21 02:51:01 PM PST 24 | Feb 21 02:51:02 PM PST 24 | 30353156 ps |
| Test location | /workspace/coverage/default/15.prim_async_alert.1630612234 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11335831 ps |
| CPU time | 0.41 seconds |
| Started | Feb 21 12:32:37 PM PST 24 |
| Finished | Feb 21 12:32:38 PM PST 24 |
| Peak memory | 145536 kb |
| Host | smart-b0b56362-518d-44a4-aac3-cddad8cdd297 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1630612234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1630612234 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3205917903 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 31258447 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 12:36:00 PM PST 24 |
| Finished | Feb 21 12:36:01 PM PST 24 |
| Peak memory | 145652 kb |
| Host | smart-48ab24b2-b82f-4563-b803-e09323b0b17d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3205917903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3205917903 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.720894731 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9499036 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 02:51:57 PM PST 24 |
| Finished | Feb 21 02:51:58 PM PST 24 |
| Peak memory | 145040 kb |
| Host | smart-042a8a89-457c-4e40-8940-64ed1a5efaa9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=720894731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.720894731 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.3157901151 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11982851 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 12:32:43 PM PST 24 |
| Finished | Feb 21 12:32:44 PM PST 24 |
| Peak memory | 145452 kb |
| Host | smart-9cde2b86-b387-4805-a0f3-b229f83f555b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3157901151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3157901151 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1319075607 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30615822 ps |
| CPU time | 0.42 seconds |
| Started | Feb 21 12:36:21 PM PST 24 |
| Finished | Feb 21 12:36:22 PM PST 24 |
| Peak memory | 145620 kb |
| Host | smart-1a9966bb-3e47-46ae-9019-38ac71346817 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1319075607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1319075607 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.2694544502 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8865032 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 02:51:58 PM PST 24 |
| Finished | Feb 21 02:51:59 PM PST 24 |
| Peak memory | 145020 kb |
| Host | smart-56643235-8a35-42f5-9097-c949b7ca6866 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2694544502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2694544502 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3065737014 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10577473 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 12:32:44 PM PST 24 |
| Finished | Feb 21 12:32:45 PM PST 24 |
| Peak memory | 145468 kb |
| Host | smart-d3fe6d38-dd8d-438a-8344-e2ef6215a19b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3065737014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3065737014 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.4262673734 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11675215 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 12:32:37 PM PST 24 |
| Finished | Feb 21 12:32:38 PM PST 24 |
| Peak memory | 145536 kb |
| Host | smart-134fb401-f2af-401d-9a6d-130aef6d0ed5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4262673734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.4262673734 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3472373253 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10654727 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 12:32:41 PM PST 24 |
| Finished | Feb 21 12:32:42 PM PST 24 |
| Peak memory | 145536 kb |
| Host | smart-07a3c649-9522-4d53-9a95-17ac5955659c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472373253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3472373253 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.838001901 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11285003 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 12:32:41 PM PST 24 |
| Finished | Feb 21 12:32:42 PM PST 24 |
| Peak memory | 145476 kb |
| Host | smart-c3143717-c390-4655-8685-9124f8a9ce4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=838001901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.838001901 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.3360308076 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11572429 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 12:32:18 PM PST 24 |
| Finished | Feb 21 12:32:21 PM PST 24 |
| Peak memory | 145612 kb |
| Host | smart-c812e8f2-dd88-4018-bea2-5533fbd80014 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3360308076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3360308076 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.762397187 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11866940 ps |
| CPU time | 0.45 seconds |
| Started | Feb 21 12:32:21 PM PST 24 |
| Finished | Feb 21 12:32:22 PM PST 24 |
| Peak memory | 145684 kb |
| Host | smart-12cb9d99-ec7c-4f9d-9fd0-696b14ddd045 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762397187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.762397187 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.3215512970 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11358920 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 12:32:26 PM PST 24 |
| Finished | Feb 21 12:32:27 PM PST 24 |
| Peak memory | 145520 kb |
| Host | smart-b611fdcf-3a8e-453d-a9d4-d30f4aac2021 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215512970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3215512970 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3703361978 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10654787 ps |
| CPU time | 0.41 seconds |
| Started | Feb 21 12:32:26 PM PST 24 |
| Finished | Feb 21 12:32:27 PM PST 24 |
| Peak memory | 145520 kb |
| Host | smart-7b0d21f5-407d-45aa-a859-9b9b1783860e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703361978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3703361978 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.1236272553 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11352621 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 12:32:40 PM PST 24 |
| Finished | Feb 21 12:32:41 PM PST 24 |
| Peak memory | 145452 kb |
| Host | smart-742e6862-e58f-4257-81a6-8c1713c47efb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236272553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1236272553 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.1181465838 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10885274 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 12:32:40 PM PST 24 |
| Finished | Feb 21 12:32:41 PM PST 24 |
| Peak memory | 145448 kb |
| Host | smart-d1577a4c-b7f0-47a9-8006-9f893615f6a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1181465838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1181465838 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.3456418548 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11038518 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 12:32:31 PM PST 24 |
| Finished | Feb 21 12:32:31 PM PST 24 |
| Peak memory | 145476 kb |
| Host | smart-d834544d-e18f-428c-9cac-cd2500709581 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456418548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3456418548 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1149631169 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12556538 ps |
| CPU time | 0.42 seconds |
| Started | Feb 21 12:32:51 PM PST 24 |
| Finished | Feb 21 12:32:53 PM PST 24 |
| Peak memory | 145464 kb |
| Host | smart-98a41c88-5718-45b9-974a-aeb3986e321f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1149631169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1149631169 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.3971608021 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11579042 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 12:32:46 PM PST 24 |
| Finished | Feb 21 12:32:47 PM PST 24 |
| Peak memory | 145464 kb |
| Host | smart-676d573d-2286-4680-8ce3-0b1e2a189bf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3971608021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3971608021 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.4135747045 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11230321 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 12:32:41 PM PST 24 |
| Finished | Feb 21 12:32:42 PM PST 24 |
| Peak memory | 145464 kb |
| Host | smart-3cc2e7e5-e9ec-46c7-95f9-ef23aa1a715c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4135747045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.4135747045 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.1242811918 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10945463 ps |
| CPU time | 0.36 seconds |
| Started | Feb 21 12:32:38 PM PST 24 |
| Finished | Feb 21 12:32:39 PM PST 24 |
| Peak memory | 145508 kb |
| Host | smart-dc5b6260-6021-4a17-ac7c-a7b1ba1855d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1242811918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1242811918 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.3197215758 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10846587 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 12:32:41 PM PST 24 |
| Finished | Feb 21 12:32:42 PM PST 24 |
| Peak memory | 145464 kb |
| Host | smart-ffd9a772-be98-42be-a73a-c380bac4a6a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3197215758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3197215758 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.488934631 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 28995658 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 12:36:28 PM PST 24 |
| Finished | Feb 21 12:36:29 PM PST 24 |
| Peak memory | 145620 kb |
| Host | smart-52968ecb-70fa-4d7e-bb1c-24b0b52087ac |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=488934631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.488934631 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1526059127 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 31695800 ps |
| CPU time | 0.41 seconds |
| Started | Feb 21 12:36:00 PM PST 24 |
| Finished | Feb 21 12:36:01 PM PST 24 |
| Peak memory | 145736 kb |
| Host | smart-848b706a-2730-4501-95c7-86720a78bacf |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1526059127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1526059127 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1963111491 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 30839974 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 12:35:49 PM PST 24 |
| Finished | Feb 21 12:35:52 PM PST 24 |
| Peak memory | 145684 kb |
| Host | smart-05101452-0c9d-4a3d-82eb-b5c4fff5ac1c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1963111491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1963111491 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.426355690 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 32763469 ps |
| CPU time | 0.42 seconds |
| Started | Feb 21 12:35:53 PM PST 24 |
| Finished | Feb 21 12:35:53 PM PST 24 |
| Peak memory | 145652 kb |
| Host | smart-4a3a227e-e18e-4f82-b87a-026432e473d9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=426355690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.426355690 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3800091076 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29748687 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 12:36:07 PM PST 24 |
| Finished | Feb 21 12:36:08 PM PST 24 |
| Peak memory | 145544 kb |
| Host | smart-2d24977e-473c-4777-816a-949d15702242 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3800091076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3800091076 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3713761317 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 30868828 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 12:36:18 PM PST 24 |
| Finished | Feb 21 12:36:20 PM PST 24 |
| Peak memory | 145748 kb |
| Host | smart-29e9aff1-fbfa-4ec6-8b7c-70535147c577 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3713761317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3713761317 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1225077583 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 31322133 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 12:35:50 PM PST 24 |
| Finished | Feb 21 12:35:52 PM PST 24 |
| Peak memory | 145720 kb |
| Host | smart-e0ccc339-c248-4ad3-b299-5e3c85f529d0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1225077583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1225077583 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1955462174 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 31263632 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 12:36:03 PM PST 24 |
| Finished | Feb 21 12:36:05 PM PST 24 |
| Peak memory | 145684 kb |
| Host | smart-86de4ccf-49c3-46aa-96aa-fde4ffd3971f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1955462174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1955462174 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3964101674 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 31214679 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 12:36:09 PM PST 24 |
| Finished | Feb 21 12:36:10 PM PST 24 |
| Peak memory | 145644 kb |
| Host | smart-2785dd57-0588-49f8-8b93-0057c855dfe8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3964101674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3964101674 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3890231724 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 31077234 ps |
| CPU time | 0.41 seconds |
| Started | Feb 21 12:36:15 PM PST 24 |
| Finished | Feb 21 12:36:17 PM PST 24 |
| Peak memory | 145720 kb |
| Host | smart-e1166948-3b24-4e61-9bcd-4028953bf584 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3890231724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3890231724 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1006052356 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 29764432 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 12:36:07 PM PST 24 |
| Finished | Feb 21 12:36:08 PM PST 24 |
| Peak memory | 145648 kb |
| Host | smart-cc8a3aa6-7405-4b09-bfc9-eb41b8951ab2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1006052356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1006052356 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2266880865 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30664296 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 12:36:02 PM PST 24 |
| Finished | Feb 21 12:36:05 PM PST 24 |
| Peak memory | 145580 kb |
| Host | smart-fc966f0c-efa8-4ca5-9bb8-8627bd2fae7a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2266880865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2266880865 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2990125593 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30262022 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 12:35:42 PM PST 24 |
| Finished | Feb 21 12:35:43 PM PST 24 |
| Peak memory | 145640 kb |
| Host | smart-88bfcd87-15a3-4c3a-8bfc-4e4b21fc18ae |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2990125593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2990125593 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3111927747 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 29375184 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 12:36:02 PM PST 24 |
| Finished | Feb 21 12:36:04 PM PST 24 |
| Peak memory | 145660 kb |
| Host | smart-16d81b87-d845-4951-89c1-4cb5d4ccb237 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3111927747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3111927747 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1721822596 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30421726 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 12:36:11 PM PST 24 |
| Finished | Feb 21 12:36:12 PM PST 24 |
| Peak memory | 145652 kb |
| Host | smart-eefb494c-ca42-49e5-8b04-031af7904c83 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1721822596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1721822596 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.610936956 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 31576124 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 12:36:07 PM PST 24 |
| Finished | Feb 21 12:36:08 PM PST 24 |
| Peak memory | 145500 kb |
| Host | smart-7764bd7f-d666-4e3b-8922-a1cec70dbe78 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=610936956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.610936956 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1395121497 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 30043235 ps |
| CPU time | 0.41 seconds |
| Started | Feb 21 12:35:50 PM PST 24 |
| Finished | Feb 21 12:35:52 PM PST 24 |
| Peak memory | 145840 kb |
| Host | smart-0a160fa4-bb01-453d-8e54-b66b88d44378 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1395121497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1395121497 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.3011714238 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8558955 ps |
| CPU time | 0.41 seconds |
| Started | Feb 21 02:52:03 PM PST 24 |
| Finished | Feb 21 02:52:04 PM PST 24 |
| Peak memory | 145036 kb |
| Host | smart-cbbd20ec-1e35-4e22-9fa5-60e990683abb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3011714238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3011714238 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.3145590759 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8583381 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 02:52:02 PM PST 24 |
| Finished | Feb 21 02:52:03 PM PST 24 |
| Peak memory | 144828 kb |
| Host | smart-6794e01a-a635-4093-ae13-ccd49af30d06 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3145590759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3145590759 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.2707076285 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 8976171 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 02:52:04 PM PST 24 |
| Finished | Feb 21 02:52:05 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-393a2a73-85b8-42c6-9512-e8275871ec8a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2707076285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2707076285 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1585867218 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8883158 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 02:51:55 PM PST 24 |
| Finished | Feb 21 02:51:57 PM PST 24 |
| Peak memory | 145036 kb |
| Host | smart-db878297-72dc-4e54-9ee7-787c0af5cce0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1585867218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1585867218 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.2136255347 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9007404 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 02:51:42 PM PST 24 |
| Finished | Feb 21 02:51:42 PM PST 24 |
| Peak memory | 145036 kb |
| Host | smart-4a6522ec-4f59-40ad-8a55-8358b511432b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2136255347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2136255347 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.376552535 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8832241 ps |
| CPU time | 0.37 seconds |
| Started | Feb 21 02:52:14 PM PST 24 |
| Finished | Feb 21 02:52:15 PM PST 24 |
| Peak memory | 145036 kb |
| Host | smart-a4b6f983-9253-4846-8a8a-0853000f265d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=376552535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.376552535 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.2749133480 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8930739 ps |
| CPU time | 0.37 seconds |
| Started | Feb 21 02:51:51 PM PST 24 |
| Finished | Feb 21 02:51:52 PM PST 24 |
| Peak memory | 145036 kb |
| Host | smart-7a397ccf-a71d-491e-8d4c-06346e8e43f5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2749133480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2749133480 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.2334064774 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9085704 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 02:51:59 PM PST 24 |
| Finished | Feb 21 02:52:01 PM PST 24 |
| Peak memory | 145036 kb |
| Host | smart-ed3a30e3-92b2-46dc-b6b1-7e5c003aa842 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2334064774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2334064774 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.3582134532 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8748656 ps |
| CPU time | 0.44 seconds |
| Started | Feb 21 02:51:58 PM PST 24 |
| Finished | Feb 21 02:52:00 PM PST 24 |
| Peak memory | 145020 kb |
| Host | smart-917e8c73-e326-4f36-a7bb-73e5d9731a84 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3582134532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3582134532 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.2162172219 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9779233 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 02:51:50 PM PST 24 |
| Finished | Feb 21 02:51:51 PM PST 24 |
| Peak memory | 144956 kb |
| Host | smart-4be9fb4d-400e-491e-86e6-741c6eef134d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2162172219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2162172219 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.1022734311 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8670670 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 02:51:56 PM PST 24 |
| Finished | Feb 21 02:51:58 PM PST 24 |
| Peak memory | 145028 kb |
| Host | smart-7c7f7ee8-f251-4b1b-8707-90e1450fc8b5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1022734311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1022734311 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3861581238 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 8997282 ps |
| CPU time | 0.37 seconds |
| Started | Feb 21 02:52:02 PM PST 24 |
| Finished | Feb 21 02:52:03 PM PST 24 |
| Peak memory | 145040 kb |
| Host | smart-90c741dd-f2a2-4286-9286-d9ea2b6b9bcc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3861581238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3861581238 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.3476384875 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8623734 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 02:52:02 PM PST 24 |
| Finished | Feb 21 02:52:03 PM PST 24 |
| Peak memory | 144836 kb |
| Host | smart-75cdae2c-198e-4fd9-b988-fd21eabf937f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3476384875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3476384875 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.765991721 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9305616 ps |
| CPU time | 0.37 seconds |
| Started | Feb 21 02:51:37 PM PST 24 |
| Finished | Feb 21 02:51:37 PM PST 24 |
| Peak memory | 145028 kb |
| Host | smart-aac7d941-eecd-4473-adcf-cd21490b9b93 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=765991721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.765991721 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.3230472388 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9707282 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 02:51:37 PM PST 24 |
| Finished | Feb 21 02:51:38 PM PST 24 |
| Peak memory | 145028 kb |
| Host | smart-faee9574-685e-455c-9ba7-78ef3bf65b71 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3230472388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3230472388 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.202677736 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8997460 ps |
| CPU time | 0.44 seconds |
| Started | Feb 21 02:51:58 PM PST 24 |
| Finished | Feb 21 02:51:59 PM PST 24 |
| Peak memory | 145028 kb |
| Host | smart-86c9e148-1d95-485a-b3b2-a8528b424975 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=202677736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.202677736 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.3359910542 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9561491 ps |
| CPU time | 0.37 seconds |
| Started | Feb 21 02:51:58 PM PST 24 |
| Finished | Feb 21 02:51:59 PM PST 24 |
| Peak memory | 145028 kb |
| Host | smart-694f204a-e4ed-4b6d-aa6e-09cc743556b8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3359910542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3359910542 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.2736698571 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9124701 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 02:51:58 PM PST 24 |
| Finished | Feb 21 02:51:59 PM PST 24 |
| Peak memory | 145028 kb |
| Host | smart-3010f75a-2679-4d2d-90a9-e3172659260c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2736698571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2736698571 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3202108835 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27407910 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 02:51:09 PM PST 24 |
| Finished | Feb 21 02:51:11 PM PST 24 |
| Peak memory | 145176 kb |
| Host | smart-0eb5e75f-2b8a-458a-86cc-cd8ab548a34c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3202108835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3202108835 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.423319388 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 28021947 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 02:50:56 PM PST 24 |
| Finished | Feb 21 02:50:57 PM PST 24 |
| Peak memory | 145172 kb |
| Host | smart-37147b30-0c82-4053-9030-f17de2fc194c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=423319388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.423319388 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.404357727 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 30353156 ps |
| CPU time | 0.44 seconds |
| Started | Feb 21 02:51:01 PM PST 24 |
| Finished | Feb 21 02:51:02 PM PST 24 |
| Peak memory | 145172 kb |
| Host | smart-43658b8d-f94b-42fb-8a81-a869077b0d3b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=404357727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.404357727 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1734380863 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 24627478 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 02:50:59 PM PST 24 |
| Finished | Feb 21 02:51:00 PM PST 24 |
| Peak memory | 145072 kb |
| Host | smart-e2ed1f46-b2b6-4113-9199-1b4d67718a0a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1734380863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1734380863 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3197565419 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27232362 ps |
| CPU time | 0.45 seconds |
| Started | Feb 21 02:51:04 PM PST 24 |
| Finished | Feb 21 02:51:04 PM PST 24 |
| Peak memory | 145220 kb |
| Host | smart-d22dae38-dfae-4976-9d4b-06fcab0bf7c9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3197565419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3197565419 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.151065998 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 27600943 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 02:50:59 PM PST 24 |
| Finished | Feb 21 02:51:00 PM PST 24 |
| Peak memory | 145176 kb |
| Host | smart-ed6a5f08-0663-4ff3-bc6b-6b4a90b48dc1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=151065998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.151065998 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3184098301 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 30140450 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 02:50:59 PM PST 24 |
| Finished | Feb 21 02:51:00 PM PST 24 |
| Peak memory | 145132 kb |
| Host | smart-cd131766-e5b5-41b3-ba67-c6892fbd27d2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3184098301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3184098301 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3194194583 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27523489 ps |
| CPU time | 0.41 seconds |
| Started | Feb 21 02:51:15 PM PST 24 |
| Finished | Feb 21 02:51:15 PM PST 24 |
| Peak memory | 145164 kb |
| Host | smart-4c2eb1ee-0c3c-4864-8745-7d7f9be76539 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3194194583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3194194583 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.172183564 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 26949950 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 02:51:10 PM PST 24 |
| Finished | Feb 21 02:51:11 PM PST 24 |
| Peak memory | 145188 kb |
| Host | smart-76907b9a-6f27-4d07-bad1-0f5d2f40cc88 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=172183564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.172183564 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3826176361 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27045242 ps |
| CPU time | 0.43 seconds |
| Started | Feb 21 02:50:57 PM PST 24 |
| Finished | Feb 21 02:50:58 PM PST 24 |
| Peak memory | 145176 kb |
| Host | smart-25f15073-f571-4026-9b8e-25f266820d52 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3826176361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3826176361 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.262343276 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 29602815 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 02:51:09 PM PST 24 |
| Finished | Feb 21 02:51:10 PM PST 24 |
| Peak memory | 145176 kb |
| Host | smart-9b420fd8-9cb5-420c-8a8a-36b1a006167c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=262343276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.262343276 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.960284034 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27991245 ps |
| CPU time | 0.41 seconds |
| Started | Feb 21 02:51:16 PM PST 24 |
| Finished | Feb 21 02:51:16 PM PST 24 |
| Peak memory | 145128 kb |
| Host | smart-5b7b2d1c-c253-4da4-a60a-0c00e36c44a6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=960284034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.960284034 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3437998852 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 28246585 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 02:51:00 PM PST 24 |
| Finished | Feb 21 02:51:00 PM PST 24 |
| Peak memory | 145176 kb |
| Host | smart-3258a716-0c07-4607-8f72-40e3f0d10468 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3437998852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3437998852 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2287825083 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27722429 ps |
| CPU time | 0.42 seconds |
| Started | Feb 21 02:51:02 PM PST 24 |
| Finished | Feb 21 02:51:03 PM PST 24 |
| Peak memory | 145164 kb |
| Host | smart-4a29abe8-25fb-48f2-8537-e1d99490708b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2287825083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2287825083 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.630794629 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 27780362 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 02:50:56 PM PST 24 |
| Finished | Feb 21 02:50:56 PM PST 24 |
| Peak memory | 145180 kb |
| Host | smart-9850b46f-9c23-483c-b5a4-ff28c1c1f786 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=630794629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.630794629 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.555106038 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 26594700 ps |
| CPU time | 0.48 seconds |
| Started | Feb 21 02:51:04 PM PST 24 |
| Finished | Feb 21 02:51:05 PM PST 24 |
| Peak memory | 145176 kb |
| Host | smart-7d534ec8-ee7c-46e3-9883-417b9c9a8de4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=555106038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.555106038 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3943829998 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 28121866 ps |
| CPU time | 0.41 seconds |
| Started | Feb 21 02:51:02 PM PST 24 |
| Finished | Feb 21 02:51:03 PM PST 24 |
| Peak memory | 145176 kb |
| Host | smart-59f6f26e-50af-4824-8154-a252471aae82 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3943829998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3943829998 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1063147286 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26870325 ps |
| CPU time | 0.4 seconds |
| Started | Feb 21 02:50:59 PM PST 24 |
| Finished | Feb 21 02:51:00 PM PST 24 |
| Peak memory | 145180 kb |
| Host | smart-2984fef0-c6d4-4570-9755-b6a53cfeed4b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1063147286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1063147286 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2308121633 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27179215 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 02:50:58 PM PST 24 |
| Finished | Feb 21 02:50:59 PM PST 24 |
| Peak memory | 145168 kb |
| Host | smart-9ed2e6f1-1232-44f5-90e6-3f642e8397e8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2308121633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2308121633 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.755940475 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 29457064 ps |
| CPU time | 0.41 seconds |
| Started | Feb 21 02:51:02 PM PST 24 |
| Finished | Feb 21 02:51:03 PM PST 24 |
| Peak memory | 145176 kb |
| Host | smart-856524b2-ed0f-4a13-9209-72c33e365d33 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=755940475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.755940475 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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