Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.92 88.92 100.00 100.00 91.67 91.67 100.00 100.00 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/6.prim_async_alert.636213133
92.39 3.48 100.00 0.00 93.75 2.08 100.00 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/16.prim_sync_alert.1566600619
94.50 2.11 100.00 0.00 95.83 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3271798753
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/11.prim_async_alert.1051497870
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3834182173

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.904574228
/workspace/coverage/default/1.prim_async_alert.2788869296
/workspace/coverage/default/10.prim_async_alert.760901208
/workspace/coverage/default/12.prim_async_alert.1303333289
/workspace/coverage/default/13.prim_async_alert.1191214167
/workspace/coverage/default/14.prim_async_alert.1883906627
/workspace/coverage/default/15.prim_async_alert.1226068148
/workspace/coverage/default/16.prim_async_alert.3785335299
/workspace/coverage/default/17.prim_async_alert.1281459930
/workspace/coverage/default/18.prim_async_alert.3874392522
/workspace/coverage/default/19.prim_async_alert.2259176611
/workspace/coverage/default/2.prim_async_alert.1745061222
/workspace/coverage/default/3.prim_async_alert.3068166815
/workspace/coverage/default/4.prim_async_alert.1391789064
/workspace/coverage/default/5.prim_async_alert.2191910084
/workspace/coverage/default/7.prim_async_alert.1710109221
/workspace/coverage/default/8.prim_async_alert.319055533
/workspace/coverage/default/9.prim_async_alert.3823190242
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3985836889
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.825345186
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1887357618
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.369141923
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1692538713
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3884932270
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.656100849
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3382324341
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3742622696
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2867385459
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1786578806
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3567531763
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3020221462
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1900833196
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2139556891
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2144177701
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.173322334
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.949746965
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1942786290
/workspace/coverage/sync_alert/0.prim_sync_alert.3875672681
/workspace/coverage/sync_alert/1.prim_sync_alert.2350607233
/workspace/coverage/sync_alert/10.prim_sync_alert.931976492
/workspace/coverage/sync_alert/11.prim_sync_alert.3355009449
/workspace/coverage/sync_alert/12.prim_sync_alert.324603037
/workspace/coverage/sync_alert/13.prim_sync_alert.1244586442
/workspace/coverage/sync_alert/14.prim_sync_alert.2991491410
/workspace/coverage/sync_alert/15.prim_sync_alert.566008539
/workspace/coverage/sync_alert/17.prim_sync_alert.3580483871
/workspace/coverage/sync_alert/18.prim_sync_alert.911718469
/workspace/coverage/sync_alert/19.prim_sync_alert.390915993
/workspace/coverage/sync_alert/2.prim_sync_alert.116476270
/workspace/coverage/sync_alert/3.prim_sync_alert.3847769583
/workspace/coverage/sync_alert/4.prim_sync_alert.1145757830
/workspace/coverage/sync_alert/5.prim_sync_alert.91842032
/workspace/coverage/sync_alert/6.prim_sync_alert.1169772643
/workspace/coverage/sync_alert/7.prim_sync_alert.2933144335
/workspace/coverage/sync_alert/8.prim_sync_alert.3008975975
/workspace/coverage/sync_alert/9.prim_sync_alert.1288254549
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3457931260
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.735044578
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.914293978
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3698977567
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4084315915
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3731949658
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4079116643
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1352108068
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3012256500
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3853442595
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2072447463
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1282882624
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3128271661
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3783439797
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3007718743
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3494781995
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.94694824
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2960311525
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1229414920



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.prim_async_alert.904574228 Feb 25 12:42:07 PM PST 24 Feb 25 12:42:08 PM PST 24 10789911 ps
T2 /workspace/coverage/default/8.prim_async_alert.319055533 Feb 25 12:42:08 PM PST 24 Feb 25 12:42:08 PM PST 24 11110512 ps
T3 /workspace/coverage/default/6.prim_async_alert.636213133 Feb 25 12:42:05 PM PST 24 Feb 25 12:42:06 PM PST 24 11929346 ps
T6 /workspace/coverage/default/15.prim_async_alert.1226068148 Feb 25 12:42:11 PM PST 24 Feb 25 12:42:11 PM PST 24 10820106 ps
T21 /workspace/coverage/default/2.prim_async_alert.1745061222 Feb 25 12:41:47 PM PST 24 Feb 25 12:41:48 PM PST 24 10620781 ps
T22 /workspace/coverage/default/3.prim_async_alert.3068166815 Feb 25 12:42:03 PM PST 24 Feb 25 12:42:04 PM PST 24 10336399 ps
T20 /workspace/coverage/default/4.prim_async_alert.1391789064 Feb 25 12:42:03 PM PST 24 Feb 25 12:42:03 PM PST 24 11374114 ps
T9 /workspace/coverage/default/11.prim_async_alert.1051497870 Feb 25 12:41:46 PM PST 24 Feb 25 12:41:51 PM PST 24 11261650 ps
T17 /workspace/coverage/default/1.prim_async_alert.2788869296 Feb 25 12:41:51 PM PST 24 Feb 25 12:41:51 PM PST 24 11279837 ps
T7 /workspace/coverage/default/10.prim_async_alert.760901208 Feb 25 12:41:50 PM PST 24 Feb 25 12:41:51 PM PST 24 11682184 ps
T10 /workspace/coverage/default/5.prim_async_alert.2191910084 Feb 25 12:41:49 PM PST 24 Feb 25 12:41:50 PM PST 24 10601868 ps
T23 /workspace/coverage/default/7.prim_async_alert.1710109221 Feb 25 12:41:49 PM PST 24 Feb 25 12:41:50 PM PST 24 11132969 ps
T13 /workspace/coverage/default/17.prim_async_alert.1281459930 Feb 25 12:42:15 PM PST 24 Feb 25 12:42:16 PM PST 24 11659794 ps
T43 /workspace/coverage/default/14.prim_async_alert.1883906627 Feb 25 12:42:13 PM PST 24 Feb 25 12:42:13 PM PST 24 10900555 ps
T18 /workspace/coverage/default/9.prim_async_alert.3823190242 Feb 25 12:42:03 PM PST 24 Feb 25 12:42:04 PM PST 24 10734296 ps
T14 /workspace/coverage/default/18.prim_async_alert.3874392522 Feb 25 12:42:02 PM PST 24 Feb 25 12:42:03 PM PST 24 12492758 ps
T44 /workspace/coverage/default/16.prim_async_alert.3785335299 Feb 25 12:41:51 PM PST 24 Feb 25 12:41:51 PM PST 24 10409006 ps
T8 /workspace/coverage/default/12.prim_async_alert.1303333289 Feb 25 12:42:07 PM PST 24 Feb 25 12:42:07 PM PST 24 11106753 ps
T45 /workspace/coverage/default/19.prim_async_alert.2259176611 Feb 25 12:42:08 PM PST 24 Feb 25 12:42:08 PM PST 24 10480436 ps
T24 /workspace/coverage/default/13.prim_async_alert.1191214167 Feb 25 12:42:04 PM PST 24 Feb 25 12:42:10 PM PST 24 11543529 ps
T36 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1887357618 Feb 25 12:42:03 PM PST 24 Feb 25 12:42:05 PM PST 24 29929709 ps
T37 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1942786290 Feb 25 12:42:07 PM PST 24 Feb 25 12:42:08 PM PST 24 30142968 ps
T38 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3567531763 Feb 25 12:41:47 PM PST 24 Feb 25 12:41:48 PM PST 24 30649774 ps
T39 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1692538713 Feb 25 12:41:53 PM PST 24 Feb 25 12:41:53 PM PST 24 30393424 ps
T40 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.173322334 Feb 25 12:41:42 PM PST 24 Feb 25 12:41:42 PM PST 24 29923488 ps
T19 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2867385459 Feb 25 12:41:58 PM PST 24 Feb 25 12:41:59 PM PST 24 30203030 ps
T41 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1900833196 Feb 25 12:42:07 PM PST 24 Feb 25 12:42:08 PM PST 24 29957742 ps
T15 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3271798753 Feb 25 12:42:04 PM PST 24 Feb 25 12:42:05 PM PST 24 30940753 ps
T16 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3020221462 Feb 25 12:41:55 PM PST 24 Feb 25 12:41:56 PM PST 24 32504539 ps
T42 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.825345186 Feb 25 12:42:06 PM PST 24 Feb 25 12:42:07 PM PST 24 30069390 ps
T46 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2144177701 Feb 25 12:41:52 PM PST 24 Feb 25 12:41:53 PM PST 24 31190954 ps
T47 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2139556891 Feb 25 12:41:57 PM PST 24 Feb 25 12:41:58 PM PST 24 30335283 ps
T48 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.949746965 Feb 25 12:41:48 PM PST 24 Feb 25 12:41:59 PM PST 24 29766082 ps
T49 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3985836889 Feb 25 12:42:07 PM PST 24 Feb 25 12:42:07 PM PST 24 30140020 ps
T50 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3884932270 Feb 25 12:42:03 PM PST 24 Feb 25 12:42:04 PM PST 24 29190280 ps
T51 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.656100849 Feb 25 12:42:09 PM PST 24 Feb 25 12:42:09 PM PST 24 30940013 ps
T52 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1786578806 Feb 25 12:42:19 PM PST 24 Feb 25 12:42:19 PM PST 24 31407321 ps
T53 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3382324341 Feb 25 12:42:20 PM PST 24 Feb 25 12:42:20 PM PST 24 30768145 ps
T54 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.369141923 Feb 25 12:42:02 PM PST 24 Feb 25 12:42:02 PM PST 24 29669217 ps
T55 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3742622696 Feb 25 12:41:55 PM PST 24 Feb 25 12:41:56 PM PST 24 31724827 ps
T25 /workspace/coverage/sync_alert/1.prim_sync_alert.2350607233 Feb 25 12:35:14 PM PST 24 Feb 25 12:35:16 PM PST 24 9641085 ps
T26 /workspace/coverage/sync_alert/0.prim_sync_alert.3875672681 Feb 25 12:35:23 PM PST 24 Feb 25 12:35:25 PM PST 24 9358240 ps
T11 /workspace/coverage/sync_alert/16.prim_sync_alert.1566600619 Feb 25 12:35:21 PM PST 24 Feb 25 12:35:22 PM PST 24 9372721 ps
T27 /workspace/coverage/sync_alert/15.prim_sync_alert.566008539 Feb 25 12:35:20 PM PST 24 Feb 25 12:35:21 PM PST 24 9016693 ps
T33 /workspace/coverage/sync_alert/17.prim_sync_alert.3580483871 Feb 25 12:35:28 PM PST 24 Feb 25 12:35:29 PM PST 24 10109491 ps
T28 /workspace/coverage/sync_alert/10.prim_sync_alert.931976492 Feb 25 12:35:21 PM PST 24 Feb 25 12:35:22 PM PST 24 9599224 ps
T34 /workspace/coverage/sync_alert/5.prim_sync_alert.91842032 Feb 25 12:35:12 PM PST 24 Feb 25 12:35:13 PM PST 24 9011009 ps
T29 /workspace/coverage/sync_alert/19.prim_sync_alert.390915993 Feb 25 12:35:26 PM PST 24 Feb 25 12:35:28 PM PST 24 9934126 ps
T30 /workspace/coverage/sync_alert/8.prim_sync_alert.3008975975 Feb 25 12:35:23 PM PST 24 Feb 25 12:35:24 PM PST 24 8105511 ps
T35 /workspace/coverage/sync_alert/3.prim_sync_alert.3847769583 Feb 25 12:35:14 PM PST 24 Feb 25 12:35:16 PM PST 24 9327315 ps
T56 /workspace/coverage/sync_alert/4.prim_sync_alert.1145757830 Feb 25 12:35:21 PM PST 24 Feb 25 12:35:22 PM PST 24 10838383 ps
T57 /workspace/coverage/sync_alert/14.prim_sync_alert.2991491410 Feb 25 12:35:16 PM PST 24 Feb 25 12:35:16 PM PST 24 9871277 ps
T31 /workspace/coverage/sync_alert/18.prim_sync_alert.911718469 Feb 25 12:36:13 PM PST 24 Feb 25 12:36:14 PM PST 24 9630072 ps
T58 /workspace/coverage/sync_alert/7.prim_sync_alert.2933144335 Feb 25 12:35:10 PM PST 24 Feb 25 12:35:11 PM PST 24 9232457 ps
T59 /workspace/coverage/sync_alert/11.prim_sync_alert.3355009449 Feb 25 12:35:09 PM PST 24 Feb 25 12:35:10 PM PST 24 10348770 ps
T60 /workspace/coverage/sync_alert/12.prim_sync_alert.324603037 Feb 25 12:35:17 PM PST 24 Feb 25 12:35:17 PM PST 24 7789989 ps
T32 /workspace/coverage/sync_alert/9.prim_sync_alert.1288254549 Feb 25 12:35:10 PM PST 24 Feb 25 12:35:11 PM PST 24 9540487 ps
T61 /workspace/coverage/sync_alert/6.prim_sync_alert.1169772643 Feb 25 12:35:24 PM PST 24 Feb 25 12:35:25 PM PST 24 9652921 ps
T62 /workspace/coverage/sync_alert/13.prim_sync_alert.1244586442 Feb 25 12:35:13 PM PST 24 Feb 25 12:35:15 PM PST 24 9205433 ps
T63 /workspace/coverage/sync_alert/2.prim_sync_alert.116476270 Feb 25 12:35:29 PM PST 24 Feb 25 12:35:29 PM PST 24 9716714 ps
T12 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2960311525 Feb 25 12:34:26 PM PST 24 Feb 25 12:34:27 PM PST 24 26439598 ps
T64 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3494781995 Feb 25 12:34:06 PM PST 24 Feb 25 12:34:06 PM PST 24 27618025 ps
T4 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3834182173 Feb 25 12:34:43 PM PST 24 Feb 25 12:34:47 PM PST 24 28548235 ps
T65 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2072447463 Feb 25 12:34:26 PM PST 24 Feb 25 12:34:27 PM PST 24 28123002 ps
T66 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.94694824 Feb 25 12:34:51 PM PST 24 Feb 25 12:34:52 PM PST 24 28892796 ps
T67 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.735044578 Feb 25 12:34:29 PM PST 24 Feb 25 12:34:31 PM PST 24 27461621 ps
T5 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4079116643 Feb 25 12:34:22 PM PST 24 Feb 25 12:34:23 PM PST 24 26747691 ps
T68 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3007718743 Feb 25 12:34:20 PM PST 24 Feb 25 12:34:20 PM PST 24 27043105 ps
T69 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3128271661 Feb 25 12:34:35 PM PST 24 Feb 25 12:34:36 PM PST 24 27878734 ps
T70 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3853442595 Feb 25 12:34:29 PM PST 24 Feb 25 12:34:31 PM PST 24 27072335 ps
T71 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1229414920 Feb 25 12:34:18 PM PST 24 Feb 25 12:34:18 PM PST 24 27729458 ps
T72 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3012256500 Feb 25 12:34:17 PM PST 24 Feb 25 12:34:18 PM PST 24 27216122 ps
T73 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4084315915 Feb 25 12:34:18 PM PST 24 Feb 25 12:34:19 PM PST 24 26269852 ps
T74 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1352108068 Feb 25 12:34:20 PM PST 24 Feb 25 12:34:22 PM PST 24 27066110 ps
T75 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1282882624 Feb 25 12:33:57 PM PST 24 Feb 25 12:33:58 PM PST 24 26843797 ps
T76 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3783439797 Feb 25 12:34:29 PM PST 24 Feb 25 12:34:31 PM PST 24 28374057 ps
T77 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.914293978 Feb 25 12:34:01 PM PST 24 Feb 25 12:34:02 PM PST 24 28008414 ps
T78 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3457931260 Feb 25 12:34:23 PM PST 24 Feb 25 12:34:23 PM PST 24 27423798 ps
T79 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3731949658 Feb 25 12:34:23 PM PST 24 Feb 25 12:34:24 PM PST 24 28514109 ps
T80 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3698977567 Feb 25 12:34:01 PM PST 24 Feb 25 12:34:02 PM PST 24 27593764 ps

Test location /workspace/coverage/default/6.prim_async_alert.636213133
Short name T3
Test name
Test status
Simulation time 11929346 ps
CPU time 0.39 seconds
Started Feb 25 12:42:05 PM PST 24
Finished Feb 25 12:42:06 PM PST 24
Peak memory 145516 kb
Host smart-ff972323-4c29-4cb0-b3e1-39d7b64d053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636213133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.636213133
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1566600619
Short name T11
Test name
Test status
Simulation time 9372721 ps
CPU time 0.37 seconds
Started Feb 25 12:35:21 PM PST 24
Finished Feb 25 12:35:22 PM PST 24
Peak memory 144944 kb
Host smart-46110e40-a9ed-4a23-b4c2-01a8819f83ff
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1566600619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1566600619
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3271798753
Short name T15
Test name
Test status
Simulation time 30940753 ps
CPU time 0.39 seconds
Started Feb 25 12:42:04 PM PST 24
Finished Feb 25 12:42:05 PM PST 24
Peak memory 145636 kb
Host smart-fc051cfd-6a61-4427-b30b-83277c5c4db8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3271798753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3271798753
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1051497870
Short name T9
Test name
Test status
Simulation time 11261650 ps
CPU time 0.39 seconds
Started Feb 25 12:41:46 PM PST 24
Finished Feb 25 12:41:51 PM PST 24
Peak memory 145532 kb
Host smart-3ed47c36-ce2e-4b22-b10b-603d080ea444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051497870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1051497870
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3834182173
Short name T4
Test name
Test status
Simulation time 28548235 ps
CPU time 0.4 seconds
Started Feb 25 12:34:43 PM PST 24
Finished Feb 25 12:34:47 PM PST 24
Peak memory 145128 kb
Host smart-8feee939-fd7a-4051-8154-9a573c467e94
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3834182173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3834182173
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.904574228
Short name T1
Test name
Test status
Simulation time 10789911 ps
CPU time 0.39 seconds
Started Feb 25 12:42:07 PM PST 24
Finished Feb 25 12:42:08 PM PST 24
Peak memory 145516 kb
Host smart-7a4880ce-97af-4e20-967e-ad10c085f66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904574228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.904574228
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2788869296
Short name T17
Test name
Test status
Simulation time 11279837 ps
CPU time 0.41 seconds
Started Feb 25 12:41:51 PM PST 24
Finished Feb 25 12:41:51 PM PST 24
Peak memory 145528 kb
Host smart-f6aa3472-ddcb-4ca1-9870-4a9604be38d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788869296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2788869296
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.760901208
Short name T7
Test name
Test status
Simulation time 11682184 ps
CPU time 0.39 seconds
Started Feb 25 12:41:50 PM PST 24
Finished Feb 25 12:41:51 PM PST 24
Peak memory 145528 kb
Host smart-3198ecc3-f711-49a0-80c9-3a7689f002fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760901208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.760901208
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1303333289
Short name T8
Test name
Test status
Simulation time 11106753 ps
CPU time 0.4 seconds
Started Feb 25 12:42:07 PM PST 24
Finished Feb 25 12:42:07 PM PST 24
Peak memory 145524 kb
Host smart-9dc2d301-d3ba-40c9-b994-000a8c99edf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303333289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1303333289
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1191214167
Short name T24
Test name
Test status
Simulation time 11543529 ps
CPU time 0.39 seconds
Started Feb 25 12:42:04 PM PST 24
Finished Feb 25 12:42:10 PM PST 24
Peak memory 145532 kb
Host smart-a3ce0765-d424-481e-98cb-3bd302f52c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191214167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1191214167
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1883906627
Short name T43
Test name
Test status
Simulation time 10900555 ps
CPU time 0.4 seconds
Started Feb 25 12:42:13 PM PST 24
Finished Feb 25 12:42:13 PM PST 24
Peak memory 145600 kb
Host smart-f249a423-52c2-40ae-8ca4-3f4ff408954c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883906627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1883906627
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1226068148
Short name T6
Test name
Test status
Simulation time 10820106 ps
CPU time 0.37 seconds
Started Feb 25 12:42:11 PM PST 24
Finished Feb 25 12:42:11 PM PST 24
Peak memory 145524 kb
Host smart-c2fa16da-3a50-423d-828a-61175a9c80c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226068148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1226068148
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3785335299
Short name T44
Test name
Test status
Simulation time 10409006 ps
CPU time 0.38 seconds
Started Feb 25 12:41:51 PM PST 24
Finished Feb 25 12:41:51 PM PST 24
Peak memory 145524 kb
Host smart-229e78cc-d2c9-4709-be04-5a5dbe9b6da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785335299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3785335299
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1281459930
Short name T13
Test name
Test status
Simulation time 11659794 ps
CPU time 0.39 seconds
Started Feb 25 12:42:15 PM PST 24
Finished Feb 25 12:42:16 PM PST 24
Peak memory 145524 kb
Host smart-f0b430a0-b819-4afa-a54b-4a6718bf9847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281459930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1281459930
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3874392522
Short name T14
Test name
Test status
Simulation time 12492758 ps
CPU time 0.38 seconds
Started Feb 25 12:42:02 PM PST 24
Finished Feb 25 12:42:03 PM PST 24
Peak memory 145476 kb
Host smart-9b06c005-6b3a-48fd-8254-61d17dc83297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874392522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3874392522
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2259176611
Short name T45
Test name
Test status
Simulation time 10480436 ps
CPU time 0.41 seconds
Started Feb 25 12:42:08 PM PST 24
Finished Feb 25 12:42:08 PM PST 24
Peak memory 145524 kb
Host smart-c54d604c-2030-4fee-aa24-d53af2f825da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259176611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2259176611
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.1745061222
Short name T21
Test name
Test status
Simulation time 10620781 ps
CPU time 0.38 seconds
Started Feb 25 12:41:47 PM PST 24
Finished Feb 25 12:41:48 PM PST 24
Peak memory 145472 kb
Host smart-bd20b223-9931-4432-a1b8-6075ee92e226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745061222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1745061222
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3068166815
Short name T22
Test name
Test status
Simulation time 10336399 ps
CPU time 0.38 seconds
Started Feb 25 12:42:03 PM PST 24
Finished Feb 25 12:42:04 PM PST 24
Peak memory 145472 kb
Host smart-dfc4a18b-7b2c-4dd5-817f-f98a317671e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068166815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3068166815
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1391789064
Short name T20
Test name
Test status
Simulation time 11374114 ps
CPU time 0.4 seconds
Started Feb 25 12:42:03 PM PST 24
Finished Feb 25 12:42:03 PM PST 24
Peak memory 145472 kb
Host smart-8058e26c-2cd7-4900-8720-d457004ac766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391789064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1391789064
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2191910084
Short name T10
Test name
Test status
Simulation time 10601868 ps
CPU time 0.4 seconds
Started Feb 25 12:41:49 PM PST 24
Finished Feb 25 12:41:50 PM PST 24
Peak memory 145528 kb
Host smart-f3923380-b31d-49bc-8ae7-465ab587491a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191910084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2191910084
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1710109221
Short name T23
Test name
Test status
Simulation time 11132969 ps
CPU time 0.41 seconds
Started Feb 25 12:41:49 PM PST 24
Finished Feb 25 12:41:50 PM PST 24
Peak memory 145488 kb
Host smart-0aa70aee-8732-4533-9880-774bff98d1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710109221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1710109221
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.319055533
Short name T2
Test name
Test status
Simulation time 11110512 ps
CPU time 0.41 seconds
Started Feb 25 12:42:08 PM PST 24
Finished Feb 25 12:42:08 PM PST 24
Peak memory 145516 kb
Host smart-84b37b5a-519b-41e3-896d-db8b6fcf65fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319055533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.319055533
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3823190242
Short name T18
Test name
Test status
Simulation time 10734296 ps
CPU time 0.41 seconds
Started Feb 25 12:42:03 PM PST 24
Finished Feb 25 12:42:04 PM PST 24
Peak memory 145528 kb
Host smart-79e38852-efc8-4b32-a4dd-f12c560f8b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823190242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3823190242
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3985836889
Short name T49
Test name
Test status
Simulation time 30140020 ps
CPU time 0.4 seconds
Started Feb 25 12:42:07 PM PST 24
Finished Feb 25 12:42:07 PM PST 24
Peak memory 145628 kb
Host smart-88e72368-b3d1-461d-afcf-30f6afb78a41
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3985836889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3985836889
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.825345186
Short name T42
Test name
Test status
Simulation time 30069390 ps
CPU time 0.4 seconds
Started Feb 25 12:42:06 PM PST 24
Finished Feb 25 12:42:07 PM PST 24
Peak memory 145628 kb
Host smart-0d151828-a5d6-416d-b775-260c63dd8e7a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=825345186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.825345186
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1887357618
Short name T36
Test name
Test status
Simulation time 29929709 ps
CPU time 0.42 seconds
Started Feb 25 12:42:03 PM PST 24
Finished Feb 25 12:42:05 PM PST 24
Peak memory 145636 kb
Host smart-a48b1c33-503e-476e-a651-d51c86bcea9a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1887357618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1887357618
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.369141923
Short name T54
Test name
Test status
Simulation time 29669217 ps
CPU time 0.39 seconds
Started Feb 25 12:42:02 PM PST 24
Finished Feb 25 12:42:02 PM PST 24
Peak memory 145648 kb
Host smart-1c05a4df-77d5-4b45-b578-2cb3cb746835
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=369141923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.369141923
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1692538713
Short name T39
Test name
Test status
Simulation time 30393424 ps
CPU time 0.4 seconds
Started Feb 25 12:41:53 PM PST 24
Finished Feb 25 12:41:53 PM PST 24
Peak memory 145716 kb
Host smart-b70ee841-aa87-477a-a947-ed5582eb5349
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1692538713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1692538713
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3884932270
Short name T50
Test name
Test status
Simulation time 29190280 ps
CPU time 0.39 seconds
Started Feb 25 12:42:03 PM PST 24
Finished Feb 25 12:42:04 PM PST 24
Peak memory 145688 kb
Host smart-e62a436c-ea92-44b8-a498-f0c92369870d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3884932270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3884932270
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.656100849
Short name T51
Test name
Test status
Simulation time 30940013 ps
CPU time 0.41 seconds
Started Feb 25 12:42:09 PM PST 24
Finished Feb 25 12:42:09 PM PST 24
Peak memory 145628 kb
Host smart-33567971-d17f-4cbe-a882-5a0fa3fd51fb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=656100849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.656100849
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3382324341
Short name T53
Test name
Test status
Simulation time 30768145 ps
CPU time 0.38 seconds
Started Feb 25 12:42:20 PM PST 24
Finished Feb 25 12:42:20 PM PST 24
Peak memory 145636 kb
Host smart-628eaf4e-a167-456d-a698-a32a1548905b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3382324341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3382324341
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3742622696
Short name T55
Test name
Test status
Simulation time 31724827 ps
CPU time 0.41 seconds
Started Feb 25 12:41:55 PM PST 24
Finished Feb 25 12:41:56 PM PST 24
Peak memory 145616 kb
Host smart-85a600b9-5555-4bc9-91a4-5a26744d317d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3742622696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3742622696
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2867385459
Short name T19
Test name
Test status
Simulation time 30203030 ps
CPU time 0.41 seconds
Started Feb 25 12:41:58 PM PST 24
Finished Feb 25 12:41:59 PM PST 24
Peak memory 145688 kb
Host smart-15fd8fa9-9c3a-482d-9ac9-087276abde93
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2867385459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2867385459
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1786578806
Short name T52
Test name
Test status
Simulation time 31407321 ps
CPU time 0.39 seconds
Started Feb 25 12:42:19 PM PST 24
Finished Feb 25 12:42:19 PM PST 24
Peak memory 145688 kb
Host smart-528f51df-1c52-41bf-9ef6-eecef1d2a062
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1786578806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1786578806
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3567531763
Short name T38
Test name
Test status
Simulation time 30649774 ps
CPU time 0.44 seconds
Started Feb 25 12:41:47 PM PST 24
Finished Feb 25 12:41:48 PM PST 24
Peak memory 145716 kb
Host smart-ddcca558-449d-4b79-89b4-21be22cf1226
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3567531763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3567531763
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3020221462
Short name T16
Test name
Test status
Simulation time 32504539 ps
CPU time 0.43 seconds
Started Feb 25 12:41:55 PM PST 24
Finished Feb 25 12:41:56 PM PST 24
Peak memory 145864 kb
Host smart-4cb63b13-d815-43c1-b1d1-a08a42c9c17d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3020221462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3020221462
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1900833196
Short name T41
Test name
Test status
Simulation time 29957742 ps
CPU time 0.4 seconds
Started Feb 25 12:42:07 PM PST 24
Finished Feb 25 12:42:08 PM PST 24
Peak memory 145644 kb
Host smart-3bcdb4e7-74ab-4843-8176-8f243984d01a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1900833196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1900833196
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2139556891
Short name T47
Test name
Test status
Simulation time 30335283 ps
CPU time 0.4 seconds
Started Feb 25 12:41:57 PM PST 24
Finished Feb 25 12:41:58 PM PST 24
Peak memory 145644 kb
Host smart-3fda7be1-9f4a-4ad5-9fe4-7480e170bfcc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2139556891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2139556891
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2144177701
Short name T46
Test name
Test status
Simulation time 31190954 ps
CPU time 0.39 seconds
Started Feb 25 12:41:52 PM PST 24
Finished Feb 25 12:41:53 PM PST 24
Peak memory 145640 kb
Host smart-73e2a52a-ebc9-496e-8b9a-dc672f1604c5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2144177701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2144177701
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.173322334
Short name T40
Test name
Test status
Simulation time 29923488 ps
CPU time 0.4 seconds
Started Feb 25 12:41:42 PM PST 24
Finished Feb 25 12:41:42 PM PST 24
Peak memory 145728 kb
Host smart-246b3da8-e53c-4f23-a462-b0d190efa48b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=173322334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.173322334
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.949746965
Short name T48
Test name
Test status
Simulation time 29766082 ps
CPU time 0.4 seconds
Started Feb 25 12:41:48 PM PST 24
Finished Feb 25 12:41:59 PM PST 24
Peak memory 145732 kb
Host smart-9a17edd0-e527-4bc0-983f-d3dc90cdc71e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=949746965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.949746965
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1942786290
Short name T37
Test name
Test status
Simulation time 30142968 ps
CPU time 0.4 seconds
Started Feb 25 12:42:07 PM PST 24
Finished Feb 25 12:42:08 PM PST 24
Peak memory 145644 kb
Host smart-539e8896-d418-4d36-8e0d-3834758cfd0b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1942786290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1942786290
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3875672681
Short name T26
Test name
Test status
Simulation time 9358240 ps
CPU time 0.38 seconds
Started Feb 25 12:35:23 PM PST 24
Finished Feb 25 12:35:25 PM PST 24
Peak memory 144900 kb
Host smart-40409c0b-e490-47c9-8940-4db9051122c9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3875672681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3875672681
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2350607233
Short name T25
Test name
Test status
Simulation time 9641085 ps
CPU time 0.38 seconds
Started Feb 25 12:35:14 PM PST 24
Finished Feb 25 12:35:16 PM PST 24
Peak memory 144928 kb
Host smart-43bc531a-f43a-48ea-af61-6ae9ba33f7e8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2350607233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2350607233
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.931976492
Short name T28
Test name
Test status
Simulation time 9599224 ps
CPU time 0.37 seconds
Started Feb 25 12:35:21 PM PST 24
Finished Feb 25 12:35:22 PM PST 24
Peak memory 144940 kb
Host smart-40e96c96-c94a-46a8-9875-023343cbb635
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=931976492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.931976492
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3355009449
Short name T59
Test name
Test status
Simulation time 10348770 ps
CPU time 0.38 seconds
Started Feb 25 12:35:09 PM PST 24
Finished Feb 25 12:35:10 PM PST 24
Peak memory 145012 kb
Host smart-2adf0bac-779a-431c-877b-633641e894ed
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3355009449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3355009449
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.324603037
Short name T60
Test name
Test status
Simulation time 7789989 ps
CPU time 0.39 seconds
Started Feb 25 12:35:17 PM PST 24
Finished Feb 25 12:35:17 PM PST 24
Peak memory 144944 kb
Host smart-7fc7cdd8-b275-4c6f-b930-b0162fbc86b6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=324603037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.324603037
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1244586442
Short name T62
Test name
Test status
Simulation time 9205433 ps
CPU time 0.42 seconds
Started Feb 25 12:35:13 PM PST 24
Finished Feb 25 12:35:15 PM PST 24
Peak memory 144944 kb
Host smart-b5c03e7c-d018-443f-b576-80acc8ed4680
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1244586442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1244586442
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2991491410
Short name T57
Test name
Test status
Simulation time 9871277 ps
CPU time 0.39 seconds
Started Feb 25 12:35:16 PM PST 24
Finished Feb 25 12:35:16 PM PST 24
Peak memory 144944 kb
Host smart-0462855a-90f8-4501-b2de-0bdb41a1cd4c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2991491410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2991491410
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.566008539
Short name T27
Test name
Test status
Simulation time 9016693 ps
CPU time 0.38 seconds
Started Feb 25 12:35:20 PM PST 24
Finished Feb 25 12:35:21 PM PST 24
Peak memory 144940 kb
Host smart-288aee04-fad9-433a-b5d6-5d1c2192825a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=566008539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.566008539
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3580483871
Short name T33
Test name
Test status
Simulation time 10109491 ps
CPU time 0.4 seconds
Started Feb 25 12:35:28 PM PST 24
Finished Feb 25 12:35:29 PM PST 24
Peak memory 144944 kb
Host smart-597d7662-44c0-49e4-8ff2-3e8d1fd9f2a1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3580483871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3580483871
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.911718469
Short name T31
Test name
Test status
Simulation time 9630072 ps
CPU time 0.37 seconds
Started Feb 25 12:36:13 PM PST 24
Finished Feb 25 12:36:14 PM PST 24
Peak memory 145156 kb
Host smart-527b99a8-6814-4e8e-a2ec-a7013e9bb5d3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=911718469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.911718469
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.390915993
Short name T29
Test name
Test status
Simulation time 9934126 ps
CPU time 0.37 seconds
Started Feb 25 12:35:26 PM PST 24
Finished Feb 25 12:35:28 PM PST 24
Peak memory 144940 kb
Host smart-6b928a97-2922-45b5-a8b9-4f4a0b54cc39
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=390915993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.390915993
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.116476270
Short name T63
Test name
Test status
Simulation time 9716714 ps
CPU time 0.39 seconds
Started Feb 25 12:35:29 PM PST 24
Finished Feb 25 12:35:29 PM PST 24
Peak memory 144932 kb
Host smart-55aa7b77-b72f-4145-b2f9-ab091e8a4c8b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=116476270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.116476270
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3847769583
Short name T35
Test name
Test status
Simulation time 9327315 ps
CPU time 0.39 seconds
Started Feb 25 12:35:14 PM PST 24
Finished Feb 25 12:35:16 PM PST 24
Peak memory 144932 kb
Host smart-c12e63e6-d183-4067-8496-dccce72b33c2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3847769583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3847769583
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1145757830
Short name T56
Test name
Test status
Simulation time 10838383 ps
CPU time 0.4 seconds
Started Feb 25 12:35:21 PM PST 24
Finished Feb 25 12:35:22 PM PST 24
Peak memory 144916 kb
Host smart-a88f64ae-3e60-40d6-896f-54294db592cd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1145757830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1145757830
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.91842032
Short name T34
Test name
Test status
Simulation time 9011009 ps
CPU time 0.37 seconds
Started Feb 25 12:35:12 PM PST 24
Finished Feb 25 12:35:13 PM PST 24
Peak memory 144936 kb
Host smart-4798703c-f0d4-4ff4-8d58-e4218cd6928a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=91842032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.91842032
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1169772643
Short name T61
Test name
Test status
Simulation time 9652921 ps
CPU time 0.39 seconds
Started Feb 25 12:35:24 PM PST 24
Finished Feb 25 12:35:25 PM PST 24
Peak memory 144932 kb
Host smart-25e75a3b-4510-4c88-91d7-9049c2b6d1fb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1169772643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1169772643
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2933144335
Short name T58
Test name
Test status
Simulation time 9232457 ps
CPU time 0.39 seconds
Started Feb 25 12:35:10 PM PST 24
Finished Feb 25 12:35:11 PM PST 24
Peak memory 144932 kb
Host smart-0e55a95d-20e3-475b-a5c7-7b9c5c3750eb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2933144335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2933144335
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.3008975975
Short name T30
Test name
Test status
Simulation time 8105511 ps
CPU time 0.39 seconds
Started Feb 25 12:35:23 PM PST 24
Finished Feb 25 12:35:24 PM PST 24
Peak memory 145012 kb
Host smart-b3b7ffbc-0333-4def-bdae-100475fdfe4b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3008975975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3008975975
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1288254549
Short name T32
Test name
Test status
Simulation time 9540487 ps
CPU time 0.37 seconds
Started Feb 25 12:35:10 PM PST 24
Finished Feb 25 12:35:11 PM PST 24
Peak memory 144900 kb
Host smart-c47feaea-b902-4d3b-a5fa-df6c63432c36
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1288254549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1288254549
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3457931260
Short name T78
Test name
Test status
Simulation time 27423798 ps
CPU time 0.4 seconds
Started Feb 25 12:34:23 PM PST 24
Finished Feb 25 12:34:23 PM PST 24
Peak memory 145072 kb
Host smart-7f778d4b-dc69-42e0-bd51-e8623fe366b1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3457931260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3457931260
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.735044578
Short name T67
Test name
Test status
Simulation time 27461621 ps
CPU time 0.39 seconds
Started Feb 25 12:34:29 PM PST 24
Finished Feb 25 12:34:31 PM PST 24
Peak memory 145088 kb
Host smart-a68f7acb-9938-4232-80c4-7dad89344c77
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=735044578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.735044578
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.914293978
Short name T77
Test name
Test status
Simulation time 28008414 ps
CPU time 0.4 seconds
Started Feb 25 12:34:01 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 145016 kb
Host smart-6e3ead24-46db-4cc3-93a8-f0f8e15904ee
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=914293978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.914293978
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3698977567
Short name T80
Test name
Test status
Simulation time 27593764 ps
CPU time 0.39 seconds
Started Feb 25 12:34:01 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 145036 kb
Host smart-ed6f2287-cba0-4040-80ec-76b66d1ca718
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3698977567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3698977567
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4084315915
Short name T73
Test name
Test status
Simulation time 26269852 ps
CPU time 0.39 seconds
Started Feb 25 12:34:18 PM PST 24
Finished Feb 25 12:34:19 PM PST 24
Peak memory 145156 kb
Host smart-62188330-67e5-4d76-ab37-b2dd9e120e4d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4084315915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4084315915
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3731949658
Short name T79
Test name
Test status
Simulation time 28514109 ps
CPU time 0.39 seconds
Started Feb 25 12:34:23 PM PST 24
Finished Feb 25 12:34:24 PM PST 24
Peak memory 145156 kb
Host smart-c2fd03a8-51cd-4b0f-aaac-96ccb1710c3b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3731949658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3731949658
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4079116643
Short name T5
Test name
Test status
Simulation time 26747691 ps
CPU time 0.38 seconds
Started Feb 25 12:34:22 PM PST 24
Finished Feb 25 12:34:23 PM PST 24
Peak memory 145128 kb
Host smart-40c8508f-9efc-4825-a5ef-89769a2c021f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4079116643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.4079116643
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1352108068
Short name T74
Test name
Test status
Simulation time 27066110 ps
CPU time 0.4 seconds
Started Feb 25 12:34:20 PM PST 24
Finished Feb 25 12:34:22 PM PST 24
Peak memory 145068 kb
Host smart-210ab33b-1271-4d40-bbd0-cc6af78b81c8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1352108068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1352108068
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3012256500
Short name T72
Test name
Test status
Simulation time 27216122 ps
CPU time 0.4 seconds
Started Feb 25 12:34:17 PM PST 24
Finished Feb 25 12:34:18 PM PST 24
Peak memory 145076 kb
Host smart-177f6d17-4eec-4eb1-aa60-11d1cdb4b2f3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3012256500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3012256500
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3853442595
Short name T70
Test name
Test status
Simulation time 27072335 ps
CPU time 0.4 seconds
Started Feb 25 12:34:29 PM PST 24
Finished Feb 25 12:34:31 PM PST 24
Peak memory 145076 kb
Host smart-0a5dc7ed-cb79-4caa-b3b7-15942d4272fc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3853442595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3853442595
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2072447463
Short name T65
Test name
Test status
Simulation time 28123002 ps
CPU time 0.4 seconds
Started Feb 25 12:34:26 PM PST 24
Finished Feb 25 12:34:27 PM PST 24
Peak memory 145080 kb
Host smart-67cdaee6-e0b9-4adf-a3fa-406f1f966d5d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2072447463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2072447463
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1282882624
Short name T75
Test name
Test status
Simulation time 26843797 ps
CPU time 0.39 seconds
Started Feb 25 12:33:57 PM PST 24
Finished Feb 25 12:33:58 PM PST 24
Peak memory 145132 kb
Host smart-9203796c-3c8d-440e-a119-09d582edbb09
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1282882624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1282882624
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3128271661
Short name T69
Test name
Test status
Simulation time 27878734 ps
CPU time 0.41 seconds
Started Feb 25 12:34:35 PM PST 24
Finished Feb 25 12:34:36 PM PST 24
Peak memory 145140 kb
Host smart-f9daebc1-b6ef-49e3-a290-73510f5376c3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3128271661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3128271661
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3783439797
Short name T76
Test name
Test status
Simulation time 28374057 ps
CPU time 0.4 seconds
Started Feb 25 12:34:29 PM PST 24
Finished Feb 25 12:34:31 PM PST 24
Peak memory 145072 kb
Host smart-05aaa922-ee28-421f-9a23-14053b621dda
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3783439797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3783439797
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3007718743
Short name T68
Test name
Test status
Simulation time 27043105 ps
CPU time 0.41 seconds
Started Feb 25 12:34:20 PM PST 24
Finished Feb 25 12:34:20 PM PST 24
Peak memory 145072 kb
Host smart-899126bb-93e0-40de-8588-4adab5676e9d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3007718743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3007718743
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3494781995
Short name T64
Test name
Test status
Simulation time 27618025 ps
CPU time 0.4 seconds
Started Feb 25 12:34:06 PM PST 24
Finished Feb 25 12:34:06 PM PST 24
Peak memory 145028 kb
Host smart-006355a5-68da-4f9e-919c-4484c4ade1b0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3494781995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3494781995
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.94694824
Short name T66
Test name
Test status
Simulation time 28892796 ps
CPU time 0.38 seconds
Started Feb 25 12:34:51 PM PST 24
Finished Feb 25 12:34:52 PM PST 24
Peak memory 145136 kb
Host smart-350647e6-fb1f-406e-9da8-d3e1b4faa241
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=94694824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.94694824
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2960311525
Short name T12
Test name
Test status
Simulation time 26439598 ps
CPU time 0.4 seconds
Started Feb 25 12:34:26 PM PST 24
Finished Feb 25 12:34:27 PM PST 24
Peak memory 145084 kb
Host smart-bb8c69be-f594-4a35-8173-4cc0148c4574
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2960311525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2960311525
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1229414920
Short name T71
Test name
Test status
Simulation time 27729458 ps
CPU time 0.4 seconds
Started Feb 25 12:34:18 PM PST 24
Finished Feb 25 12:34:18 PM PST 24
Peak memory 145072 kb
Host smart-c24f59e4-9616-4f32-9d83-40dc2026b44f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1229414920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1229414920
Directory /workspace/9.prim_sync_fatal_alert/latest
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