Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 96.43 96.43 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/6.prim_async_alert.3398229439
91.80 3.13 100.00 0.00 93.75 0.00 96.43 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/13.prim_sync_alert.3352982662
93.56 1.76 100.00 0.00 93.75 0.00 100.00 3.57 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.514794433
94.50 0.94 100.00 0.00 95.83 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2384571012
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/0.prim_async_alert.3747755757
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3821722079

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.3003947322
/workspace/coverage/default/10.prim_async_alert.1139524230
/workspace/coverage/default/11.prim_async_alert.2291108478
/workspace/coverage/default/12.prim_async_alert.568460454
/workspace/coverage/default/13.prim_async_alert.66696487
/workspace/coverage/default/14.prim_async_alert.2725258837
/workspace/coverage/default/15.prim_async_alert.3273719726
/workspace/coverage/default/16.prim_async_alert.3632896964
/workspace/coverage/default/17.prim_async_alert.2601971243
/workspace/coverage/default/18.prim_async_alert.2725415468
/workspace/coverage/default/19.prim_async_alert.2843956182
/workspace/coverage/default/2.prim_async_alert.3679138725
/workspace/coverage/default/3.prim_async_alert.3547637698
/workspace/coverage/default/5.prim_async_alert.2903958104
/workspace/coverage/default/7.prim_async_alert.2088062259
/workspace/coverage/default/8.prim_async_alert.2293280707
/workspace/coverage/default/9.prim_async_alert.19397008
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.930449410
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1579660146
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2837252591
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2509342694
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3713680411
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1594093801
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1269004171
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3251065856
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.16625205
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4169619814
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.513642790
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.405607457
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3229697777
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3162724102
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3285277217
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2213277303
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4177699076
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3712803637
/workspace/coverage/sync_alert/0.prim_sync_alert.1107051219
/workspace/coverage/sync_alert/1.prim_sync_alert.1993991218
/workspace/coverage/sync_alert/10.prim_sync_alert.3739353194
/workspace/coverage/sync_alert/11.prim_sync_alert.2896726455
/workspace/coverage/sync_alert/12.prim_sync_alert.1743999816
/workspace/coverage/sync_alert/14.prim_sync_alert.2715477239
/workspace/coverage/sync_alert/15.prim_sync_alert.2513446190
/workspace/coverage/sync_alert/16.prim_sync_alert.3316500815
/workspace/coverage/sync_alert/17.prim_sync_alert.3018906770
/workspace/coverage/sync_alert/18.prim_sync_alert.4262124476
/workspace/coverage/sync_alert/19.prim_sync_alert.3804192582
/workspace/coverage/sync_alert/2.prim_sync_alert.516359563
/workspace/coverage/sync_alert/3.prim_sync_alert.3548739648
/workspace/coverage/sync_alert/4.prim_sync_alert.2686939956
/workspace/coverage/sync_alert/5.prim_sync_alert.3656213137
/workspace/coverage/sync_alert/6.prim_sync_alert.2024682051
/workspace/coverage/sync_alert/7.prim_sync_alert.1657820704
/workspace/coverage/sync_alert/8.prim_sync_alert.927599193
/workspace/coverage/sync_alert/9.prim_sync_alert.128429264
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.434489596
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1266339197
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3170927467
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4121089848
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3610157258
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3690267981
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1268476162
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2452045229
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4239011377
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.705585360
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2071633169
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2185746171
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1778590053
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3323381364
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.396834047
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.5946019
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2422483925
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.762876227
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3830639699



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/5.prim_async_alert.2903958104 Feb 29 12:16:56 PM PST 24 Feb 29 12:16:58 PM PST 24 10938089 ps
T2 /workspace/coverage/default/11.prim_async_alert.2291108478 Feb 29 12:16:52 PM PST 24 Feb 29 12:16:53 PM PST 24 11138144 ps
T3 /workspace/coverage/default/2.prim_async_alert.3679138725 Feb 29 12:16:51 PM PST 24 Feb 29 12:16:51 PM PST 24 11802195 ps
T7 /workspace/coverage/default/7.prim_async_alert.2088062259 Feb 29 12:16:50 PM PST 24 Feb 29 12:16:51 PM PST 24 10844293 ps
T19 /workspace/coverage/default/10.prim_async_alert.1139524230 Feb 29 12:16:51 PM PST 24 Feb 29 12:16:51 PM PST 24 11579764 ps
T20 /workspace/coverage/default/0.prim_async_alert.3747755757 Feb 29 12:16:51 PM PST 24 Feb 29 12:16:52 PM PST 24 10695935 ps
T21 /workspace/coverage/default/17.prim_async_alert.2601971243 Feb 29 12:16:52 PM PST 24 Feb 29 12:16:53 PM PST 24 11496432 ps
T22 /workspace/coverage/default/8.prim_async_alert.2293280707 Feb 29 12:16:50 PM PST 24 Feb 29 12:16:51 PM PST 24 10958065 ps
T6 /workspace/coverage/default/6.prim_async_alert.3398229439 Feb 29 12:16:52 PM PST 24 Feb 29 12:16:53 PM PST 24 11364571 ps
T23 /workspace/coverage/default/14.prim_async_alert.2725258837 Feb 29 12:16:51 PM PST 24 Feb 29 12:16:51 PM PST 24 11077819 ps
T24 /workspace/coverage/default/3.prim_async_alert.3547637698 Feb 29 12:16:54 PM PST 24 Feb 29 12:16:55 PM PST 24 11028823 ps
T11 /workspace/coverage/default/9.prim_async_alert.19397008 Feb 29 12:16:52 PM PST 24 Feb 29 12:16:53 PM PST 24 11625901 ps
T47 /workspace/coverage/default/13.prim_async_alert.66696487 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 11212414 ps
T48 /workspace/coverage/default/16.prim_async_alert.3632896964 Feb 29 12:16:51 PM PST 24 Feb 29 12:16:51 PM PST 24 10515040 ps
T25 /workspace/coverage/default/18.prim_async_alert.2725415468 Feb 29 12:16:50 PM PST 24 Feb 29 12:16:50 PM PST 24 10477177 ps
T49 /workspace/coverage/default/12.prim_async_alert.568460454 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 11460202 ps
T50 /workspace/coverage/default/1.prim_async_alert.3003947322 Feb 29 12:16:54 PM PST 24 Feb 29 12:16:54 PM PST 24 11035615 ps
T17 /workspace/coverage/default/15.prim_async_alert.3273719726 Feb 29 12:16:51 PM PST 24 Feb 29 12:16:51 PM PST 24 11391664 ps
T51 /workspace/coverage/default/19.prim_async_alert.2843956182 Feb 29 12:16:53 PM PST 24 Feb 29 12:16:54 PM PST 24 10889722 ps
T12 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.514794433 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:02 PM PST 24 31823717 ps
T13 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.513642790 Feb 29 12:16:55 PM PST 24 Feb 29 12:16:55 PM PST 24 31032841 ps
T15 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1594093801 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 32516072 ps
T41 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3251065856 Feb 29 12:17:01 PM PST 24 Feb 29 12:17:03 PM PST 24 31481665 ps
T42 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1579660146 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 27268415 ps
T43 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3162724102 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 31857030 ps
T44 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1269004171 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 29747214 ps
T45 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4177699076 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 30578041 ps
T16 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4169619814 Feb 29 12:16:55 PM PST 24 Feb 29 12:16:56 PM PST 24 31022316 ps
T46 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.930449410 Feb 29 12:16:57 PM PST 24 Feb 29 12:17:01 PM PST 24 31487044 ps
T52 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3713680411 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 30173070 ps
T53 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.16625205 Feb 29 12:16:53 PM PST 24 Feb 29 12:16:54 PM PST 24 30466372 ps
T54 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3712803637 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:01 PM PST 24 31062707 ps
T55 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2837252591 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:01 PM PST 24 31588846 ps
T56 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2509342694 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:00 PM PST 24 29861324 ps
T57 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3229697777 Feb 29 12:16:57 PM PST 24 Feb 29 12:17:02 PM PST 24 28878415 ps
T58 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3285277217 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 31521496 ps
T59 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.405607457 Feb 29 12:16:57 PM PST 24 Feb 29 12:17:01 PM PST 24 30996457 ps
T60 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2213277303 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 30967358 ps
T4 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3821722079 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 29731061 ps
T26 /workspace/coverage/sync_alert/15.prim_sync_alert.2513446190 Feb 29 12:16:56 PM PST 24 Feb 29 12:16:57 PM PST 24 8481258 ps
T34 /workspace/coverage/sync_alert/9.prim_sync_alert.128429264 Feb 29 12:16:57 PM PST 24 Feb 29 12:17:00 PM PST 24 9414584 ps
T18 /workspace/coverage/sync_alert/17.prim_sync_alert.3018906770 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 9431459 ps
T35 /workspace/coverage/sync_alert/5.prim_sync_alert.3656213137 Feb 29 12:16:56 PM PST 24 Feb 29 12:16:56 PM PST 24 9520496 ps
T36 /workspace/coverage/sync_alert/14.prim_sync_alert.2715477239 Feb 29 12:16:57 PM PST 24 Feb 29 12:17:01 PM PST 24 9003731 ps
T37 /workspace/coverage/sync_alert/3.prim_sync_alert.3548739648 Feb 29 12:16:56 PM PST 24 Feb 29 12:16:56 PM PST 24 8595765 ps
T38 /workspace/coverage/sync_alert/13.prim_sync_alert.3352982662 Feb 29 12:16:55 PM PST 24 Feb 29 12:16:56 PM PST 24 9371818 ps
T39 /workspace/coverage/sync_alert/8.prim_sync_alert.927599193 Feb 29 12:17:05 PM PST 24 Feb 29 12:17:06 PM PST 24 9287846 ps
T27 /workspace/coverage/sync_alert/19.prim_sync_alert.3804192582 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 9823250 ps
T40 /workspace/coverage/sync_alert/16.prim_sync_alert.3316500815 Feb 29 12:16:56 PM PST 24 Feb 29 12:16:58 PM PST 24 10274090 ps
T61 /workspace/coverage/sync_alert/0.prim_sync_alert.1107051219 Feb 29 12:17:02 PM PST 24 Feb 29 12:17:03 PM PST 24 10461283 ps
T62 /workspace/coverage/sync_alert/12.prim_sync_alert.1743999816 Feb 29 12:16:56 PM PST 24 Feb 29 12:16:57 PM PST 24 9826814 ps
T63 /workspace/coverage/sync_alert/10.prim_sync_alert.3739353194 Feb 29 12:16:53 PM PST 24 Feb 29 12:16:53 PM PST 24 8708997 ps
T64 /workspace/coverage/sync_alert/7.prim_sync_alert.1657820704 Feb 29 12:16:53 PM PST 24 Feb 29 12:16:54 PM PST 24 10537504 ps
T28 /workspace/coverage/sync_alert/11.prim_sync_alert.2896726455 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:01 PM PST 24 10512864 ps
T8 /workspace/coverage/sync_alert/6.prim_sync_alert.2024682051 Feb 29 12:16:57 PM PST 24 Feb 29 12:17:00 PM PST 24 8566301 ps
T29 /workspace/coverage/sync_alert/4.prim_sync_alert.2686939956 Feb 29 12:16:54 PM PST 24 Feb 29 12:16:55 PM PST 24 8787563 ps
T30 /workspace/coverage/sync_alert/18.prim_sync_alert.4262124476 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 9174386 ps
T31 /workspace/coverage/sync_alert/1.prim_sync_alert.1993991218 Feb 29 12:16:56 PM PST 24 Feb 29 12:16:57 PM PST 24 9328338 ps
T65 /workspace/coverage/sync_alert/2.prim_sync_alert.516359563 Feb 29 12:16:55 PM PST 24 Feb 29 12:16:56 PM PST 24 9544852 ps
T32 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1268476162 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 29969714 ps
T66 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1266339197 Feb 29 12:16:57 PM PST 24 Feb 29 12:17:01 PM PST 24 26637982 ps
T33 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2071633169 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 26221891 ps
T5 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3610157258 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 26975831 ps
T67 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4239011377 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 29341421 ps
T68 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4121089848 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 28703426 ps
T69 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.5946019 Feb 29 12:16:57 PM PST 24 Feb 29 12:17:02 PM PST 24 29391740 ps
T9 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.434489596 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 26111734 ps
T10 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2384571012 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 28377991 ps
T14 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3323381364 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 29742260 ps
T70 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2452045229 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 28271221 ps
T71 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.705585360 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 26464041 ps
T72 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.396834047 Feb 29 12:16:57 PM PST 24 Feb 29 12:17:00 PM PST 24 28211671 ps
T73 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.762876227 Feb 29 12:16:57 PM PST 24 Feb 29 12:17:02 PM PST 24 27112174 ps
T74 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1778590053 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 28125406 ps
T75 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2185746171 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:02 PM PST 24 29047117 ps
T76 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3170927467 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 28476661 ps
T77 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3830639699 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 28946012 ps
T78 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2422483925 Feb 29 12:16:59 PM PST 24 Feb 29 12:17:03 PM PST 24 27416715 ps
T79 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3690267981 Feb 29 12:16:58 PM PST 24 Feb 29 12:17:02 PM PST 24 25768015 ps

Test location /workspace/coverage/default/6.prim_async_alert.3398229439
Short name T6
Test name
Test status
Simulation time 11364571 ps
CPU time 0.44 seconds
Started Feb 29 12:16:52 PM PST 24
Finished Feb 29 12:16:53 PM PST 24
Peak memory 145584 kb
Host smart-5e1835ec-a9c8-4da2-8f93-0cfd5739ba43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398229439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3398229439
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3352982662
Short name T38
Test name
Test status
Simulation time 9371818 ps
CPU time 0.37 seconds
Started Feb 29 12:16:55 PM PST 24
Finished Feb 29 12:16:56 PM PST 24
Peak memory 144968 kb
Host smart-74546111-602e-4b3d-aa4b-0ad4ce0419e6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3352982662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3352982662
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.514794433
Short name T12
Test name
Test status
Simulation time 31823717 ps
CPU time 0.4 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145768 kb
Host smart-f378922f-c1f5-4e7b-b4fb-51ee1bde1057
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=514794433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.514794433
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2384571012
Short name T10
Test name
Test status
Simulation time 28377991 ps
CPU time 0.39 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145084 kb
Host smart-b56a91a0-c0c7-4f59-9428-74ec1461bb97
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2384571012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2384571012
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3747755757
Short name T20
Test name
Test status
Simulation time 10695935 ps
CPU time 0.39 seconds
Started Feb 29 12:16:51 PM PST 24
Finished Feb 29 12:16:52 PM PST 24
Peak memory 145716 kb
Host smart-335aa628-5b84-439c-a51c-9656d5199b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747755757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3747755757
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3821722079
Short name T4
Test name
Test status
Simulation time 29731061 ps
CPU time 0.39 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145656 kb
Host smart-75cce467-52f8-42b1-ba83-bea637b81b17
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3821722079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3821722079
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3003947322
Short name T50
Test name
Test status
Simulation time 11035615 ps
CPU time 0.37 seconds
Started Feb 29 12:16:54 PM PST 24
Finished Feb 29 12:16:54 PM PST 24
Peak memory 145584 kb
Host smart-2418f8bb-7c47-4b83-b2d7-54d5b6c9edee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003947322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3003947322
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1139524230
Short name T19
Test name
Test status
Simulation time 11579764 ps
CPU time 0.39 seconds
Started Feb 29 12:16:51 PM PST 24
Finished Feb 29 12:16:51 PM PST 24
Peak memory 145684 kb
Host smart-a783918e-ab31-4728-bd9c-6ae7a0a248aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139524230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1139524230
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2291108478
Short name T2
Test name
Test status
Simulation time 11138144 ps
CPU time 0.38 seconds
Started Feb 29 12:16:52 PM PST 24
Finished Feb 29 12:16:53 PM PST 24
Peak memory 145552 kb
Host smart-7009bb82-5c4c-4191-a14c-7a724f533e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291108478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2291108478
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.568460454
Short name T49
Test name
Test status
Simulation time 11460202 ps
CPU time 0.4 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145576 kb
Host smart-90ae9a74-bda6-48d9-a67a-26a06d8f253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568460454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.568460454
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.66696487
Short name T47
Test name
Test status
Simulation time 11212414 ps
CPU time 0.39 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145488 kb
Host smart-d6c7e49b-48d6-4039-94a9-ec0fe65cd615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66696487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.66696487
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2725258837
Short name T23
Test name
Test status
Simulation time 11077819 ps
CPU time 0.39 seconds
Started Feb 29 12:16:51 PM PST 24
Finished Feb 29 12:16:51 PM PST 24
Peak memory 145716 kb
Host smart-bd9b65eb-6d2d-43f5-8ae3-4882cec3aa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725258837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2725258837
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.3273719726
Short name T17
Test name
Test status
Simulation time 11391664 ps
CPU time 0.38 seconds
Started Feb 29 12:16:51 PM PST 24
Finished Feb 29 12:16:51 PM PST 24
Peak memory 145492 kb
Host smart-bf3eb49e-7ea7-43ca-9e6b-a7113635358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273719726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3273719726
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3632896964
Short name T48
Test name
Test status
Simulation time 10515040 ps
CPU time 0.39 seconds
Started Feb 29 12:16:51 PM PST 24
Finished Feb 29 12:16:51 PM PST 24
Peak memory 145684 kb
Host smart-6f1fd176-5889-4421-9951-39dc946f374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632896964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3632896964
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2601971243
Short name T21
Test name
Test status
Simulation time 11496432 ps
CPU time 0.4 seconds
Started Feb 29 12:16:52 PM PST 24
Finished Feb 29 12:16:53 PM PST 24
Peak memory 145176 kb
Host smart-209b40ef-af50-449e-957a-9920cd98c398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601971243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2601971243
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2725415468
Short name T25
Test name
Test status
Simulation time 10477177 ps
CPU time 0.39 seconds
Started Feb 29 12:16:50 PM PST 24
Finished Feb 29 12:16:50 PM PST 24
Peak memory 145576 kb
Host smart-826d6957-d084-401d-ae59-50ffb410fda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725415468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2725415468
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2843956182
Short name T51
Test name
Test status
Simulation time 10889722 ps
CPU time 0.38 seconds
Started Feb 29 12:16:53 PM PST 24
Finished Feb 29 12:16:54 PM PST 24
Peak memory 145544 kb
Host smart-1bc4d138-0862-4a0e-9918-a0b298705459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843956182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2843956182
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3679138725
Short name T3
Test name
Test status
Simulation time 11802195 ps
CPU time 0.38 seconds
Started Feb 29 12:16:51 PM PST 24
Finished Feb 29 12:16:51 PM PST 24
Peak memory 145716 kb
Host smart-695edb5b-dc60-48ba-8a65-6ea2ea1005ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679138725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3679138725
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3547637698
Short name T24
Test name
Test status
Simulation time 11028823 ps
CPU time 0.4 seconds
Started Feb 29 12:16:54 PM PST 24
Finished Feb 29 12:16:55 PM PST 24
Peak memory 145552 kb
Host smart-f11ee33b-0d99-417e-9ee7-d7d648acfbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547637698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3547637698
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2903958104
Short name T1
Test name
Test status
Simulation time 10938089 ps
CPU time 0.38 seconds
Started Feb 29 12:16:56 PM PST 24
Finished Feb 29 12:16:58 PM PST 24
Peak memory 145468 kb
Host smart-55ece015-fd0d-4f88-b8e0-0a6deb58f16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903958104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2903958104
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2088062259
Short name T7
Test name
Test status
Simulation time 10844293 ps
CPU time 0.39 seconds
Started Feb 29 12:16:50 PM PST 24
Finished Feb 29 12:16:51 PM PST 24
Peak memory 145700 kb
Host smart-f537eeb6-79dc-439a-809f-601aef0b5bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088062259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2088062259
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2293280707
Short name T22
Test name
Test status
Simulation time 10958065 ps
CPU time 0.41 seconds
Started Feb 29 12:16:50 PM PST 24
Finished Feb 29 12:16:51 PM PST 24
Peak memory 145576 kb
Host smart-76de1a60-aff9-4804-abe0-95bc2f577dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293280707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2293280707
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.19397008
Short name T11
Test name
Test status
Simulation time 11625901 ps
CPU time 0.41 seconds
Started Feb 29 12:16:52 PM PST 24
Finished Feb 29 12:16:53 PM PST 24
Peak memory 145032 kb
Host smart-e4a68758-8372-4493-98cf-1a2ce45f5e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19397008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.19397008
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.930449410
Short name T46
Test name
Test status
Simulation time 31487044 ps
CPU time 0.4 seconds
Started Feb 29 12:16:57 PM PST 24
Finished Feb 29 12:17:01 PM PST 24
Peak memory 145712 kb
Host smart-77d5f4dc-2604-4c91-9f08-bad469150c55
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=930449410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.930449410
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1579660146
Short name T42
Test name
Test status
Simulation time 27268415 ps
CPU time 0.39 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145656 kb
Host smart-2bfa542b-a715-4f5d-8bc4-eff850cc81b1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1579660146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1579660146
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2837252591
Short name T55
Test name
Test status
Simulation time 31588846 ps
CPU time 0.43 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:01 PM PST 24
Peak memory 145656 kb
Host smart-b05a848d-e9a8-4143-be59-b40b5fd03ac6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2837252591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2837252591
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2509342694
Short name T56
Test name
Test status
Simulation time 29861324 ps
CPU time 0.39 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:00 PM PST 24
Peak memory 145656 kb
Host smart-7fb60d60-1f1f-4b55-9987-d62dbb30a792
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2509342694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2509342694
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3713680411
Short name T52
Test name
Test status
Simulation time 30173070 ps
CPU time 0.4 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145644 kb
Host smart-ff806d30-6687-467e-9013-7ac7b9c00abc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3713680411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3713680411
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1594093801
Short name T15
Test name
Test status
Simulation time 32516072 ps
CPU time 0.4 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145656 kb
Host smart-62a0b284-73b5-4421-9085-8499cf8c0bfc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1594093801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1594093801
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1269004171
Short name T44
Test name
Test status
Simulation time 29747214 ps
CPU time 0.4 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145644 kb
Host smart-8b3d2cc1-50e8-4b33-85b4-a67a10ad5b6f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1269004171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1269004171
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3251065856
Short name T41
Test name
Test status
Simulation time 31481665 ps
CPU time 0.4 seconds
Started Feb 29 12:17:01 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145796 kb
Host smart-1f4a8e06-378e-48f2-8eec-17051ed52361
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3251065856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3251065856
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.16625205
Short name T53
Test name
Test status
Simulation time 30466372 ps
CPU time 0.4 seconds
Started Feb 29 12:16:53 PM PST 24
Finished Feb 29 12:16:54 PM PST 24
Peak memory 145768 kb
Host smart-9a531247-8243-4eed-8a9b-5285ab982eb4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=16625205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.16625205
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4169619814
Short name T16
Test name
Test status
Simulation time 31022316 ps
CPU time 0.39 seconds
Started Feb 29 12:16:55 PM PST 24
Finished Feb 29 12:16:56 PM PST 24
Peak memory 145788 kb
Host smart-b7d74475-0547-4b7c-a892-67c4a556c04b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4169619814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.4169619814
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.513642790
Short name T13
Test name
Test status
Simulation time 31032841 ps
CPU time 0.4 seconds
Started Feb 29 12:16:55 PM PST 24
Finished Feb 29 12:16:55 PM PST 24
Peak memory 145700 kb
Host smart-5f4fbb4e-a34e-40d0-b5d7-d8558f3dfcfc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=513642790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.513642790
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.405607457
Short name T59
Test name
Test status
Simulation time 30996457 ps
CPU time 0.4 seconds
Started Feb 29 12:16:57 PM PST 24
Finished Feb 29 12:17:01 PM PST 24
Peak memory 145684 kb
Host smart-01308a73-ac1c-4a22-b3bb-d1526463318d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=405607457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.405607457
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3229697777
Short name T57
Test name
Test status
Simulation time 28878415 ps
CPU time 0.4 seconds
Started Feb 29 12:16:57 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145772 kb
Host smart-095d5949-73a5-47a8-84ad-e77c0726cfd0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3229697777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3229697777
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3162724102
Short name T43
Test name
Test status
Simulation time 31857030 ps
CPU time 0.42 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145656 kb
Host smart-6a1c4493-f5a7-4157-940a-115bb49b1ffd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3162724102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3162724102
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3285277217
Short name T58
Test name
Test status
Simulation time 31521496 ps
CPU time 0.43 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145568 kb
Host smart-500430d9-e5fa-4a84-b52d-43538282a5e8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3285277217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3285277217
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2213277303
Short name T60
Test name
Test status
Simulation time 30967358 ps
CPU time 0.42 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145596 kb
Host smart-c4ec860b-c254-4fbb-9286-02121b20c8ca
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2213277303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2213277303
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4177699076
Short name T45
Test name
Test status
Simulation time 30578041 ps
CPU time 0.4 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145656 kb
Host smart-0655d1ab-a796-4394-bbaf-de0858154119
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4177699076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.4177699076
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3712803637
Short name T54
Test name
Test status
Simulation time 31062707 ps
CPU time 0.44 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:01 PM PST 24
Peak memory 145628 kb
Host smart-17deb38b-4200-4173-aee2-8c71ea979a76
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3712803637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3712803637
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1107051219
Short name T61
Test name
Test status
Simulation time 10461283 ps
CPU time 0.38 seconds
Started Feb 29 12:17:02 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145000 kb
Host smart-d95646da-75d5-451c-a341-338d47dae1b5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1107051219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1107051219
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1993991218
Short name T31
Test name
Test status
Simulation time 9328338 ps
CPU time 0.37 seconds
Started Feb 29 12:16:56 PM PST 24
Finished Feb 29 12:16:57 PM PST 24
Peak memory 144920 kb
Host smart-bf39132a-fb45-4115-980c-7585b6d0ff1c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1993991218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1993991218
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3739353194
Short name T63
Test name
Test status
Simulation time 8708997 ps
CPU time 0.37 seconds
Started Feb 29 12:16:53 PM PST 24
Finished Feb 29 12:16:53 PM PST 24
Peak memory 145032 kb
Host smart-9d712bb0-bd07-427a-aa12-430ebe6a4e2b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3739353194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3739353194
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2896726455
Short name T28
Test name
Test status
Simulation time 10512864 ps
CPU time 0.39 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:01 PM PST 24
Peak memory 145120 kb
Host smart-c36bf248-f89e-4eae-8405-28c240004022
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2896726455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2896726455
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1743999816
Short name T62
Test name
Test status
Simulation time 9826814 ps
CPU time 0.37 seconds
Started Feb 29 12:16:56 PM PST 24
Finished Feb 29 12:16:57 PM PST 24
Peak memory 144980 kb
Host smart-9bb56909-f4ba-43af-9178-76ea781b70d4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1743999816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1743999816
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2715477239
Short name T36
Test name
Test status
Simulation time 9003731 ps
CPU time 0.38 seconds
Started Feb 29 12:16:57 PM PST 24
Finished Feb 29 12:17:01 PM PST 24
Peak memory 144936 kb
Host smart-be768751-e8cf-487a-bd1c-9e585e9997bf
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2715477239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2715477239
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2513446190
Short name T26
Test name
Test status
Simulation time 8481258 ps
CPU time 0.38 seconds
Started Feb 29 12:16:56 PM PST 24
Finished Feb 29 12:16:57 PM PST 24
Peak memory 144932 kb
Host smart-6f39a3cc-a34b-483b-8eb5-be002e8bcc88
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2513446190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2513446190
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3316500815
Short name T40
Test name
Test status
Simulation time 10274090 ps
CPU time 0.37 seconds
Started Feb 29 12:16:56 PM PST 24
Finished Feb 29 12:16:58 PM PST 24
Peak memory 144932 kb
Host smart-1185b0aa-c03c-471b-a014-a387297ca37f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3316500815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3316500815
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3018906770
Short name T18
Test name
Test status
Simulation time 9431459 ps
CPU time 0.37 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145008 kb
Host smart-faeeb3b7-e6d0-4ec9-8992-d2d386e76662
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3018906770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3018906770
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.4262124476
Short name T30
Test name
Test status
Simulation time 9174386 ps
CPU time 0.42 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 144948 kb
Host smart-dfaafb43-f23d-42e2-8f55-67620cd5caa5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4262124476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.4262124476
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3804192582
Short name T27
Test name
Test status
Simulation time 9823250 ps
CPU time 0.37 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145000 kb
Host smart-5e955b5d-a791-4cf2-96fa-69c1ffa0d74d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3804192582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3804192582
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.516359563
Short name T65
Test name
Test status
Simulation time 9544852 ps
CPU time 0.43 seconds
Started Feb 29 12:16:55 PM PST 24
Finished Feb 29 12:16:56 PM PST 24
Peak memory 145000 kb
Host smart-f2edebef-ab2c-45ab-9b80-95889a0cf6f2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=516359563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.516359563
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3548739648
Short name T37
Test name
Test status
Simulation time 8595765 ps
CPU time 0.37 seconds
Started Feb 29 12:16:56 PM PST 24
Finished Feb 29 12:16:56 PM PST 24
Peak memory 145000 kb
Host smart-b7533654-4027-4c18-9783-14983379b885
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3548739648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3548739648
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2686939956
Short name T29
Test name
Test status
Simulation time 8787563 ps
CPU time 0.41 seconds
Started Feb 29 12:16:54 PM PST 24
Finished Feb 29 12:16:55 PM PST 24
Peak memory 145016 kb
Host smart-89f7439c-907e-4c8f-a48e-b6d7043d70e8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2686939956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2686939956
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3656213137
Short name T35
Test name
Test status
Simulation time 9520496 ps
CPU time 0.38 seconds
Started Feb 29 12:16:56 PM PST 24
Finished Feb 29 12:16:56 PM PST 24
Peak memory 144924 kb
Host smart-8872bac6-cb0e-4928-8f5e-5c9106b34adb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3656213137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3656213137
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2024682051
Short name T8
Test name
Test status
Simulation time 8566301 ps
CPU time 0.39 seconds
Started Feb 29 12:16:57 PM PST 24
Finished Feb 29 12:17:00 PM PST 24
Peak memory 144920 kb
Host smart-1331eda7-c5eb-479d-a1f9-4b0b3c8d3b9e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2024682051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2024682051
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1657820704
Short name T64
Test name
Test status
Simulation time 10537504 ps
CPU time 0.37 seconds
Started Feb 29 12:16:53 PM PST 24
Finished Feb 29 12:16:54 PM PST 24
Peak memory 145036 kb
Host smart-48c0a49b-21e0-4f91-862d-7650fb60b2a4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1657820704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1657820704
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.927599193
Short name T39
Test name
Test status
Simulation time 9287846 ps
CPU time 0.4 seconds
Started Feb 29 12:17:05 PM PST 24
Finished Feb 29 12:17:06 PM PST 24
Peak memory 145116 kb
Host smart-997bc31a-2027-4fb9-b6d3-b7b329efabb3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=927599193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.927599193
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.128429264
Short name T34
Test name
Test status
Simulation time 9414584 ps
CPU time 0.38 seconds
Started Feb 29 12:16:57 PM PST 24
Finished Feb 29 12:17:00 PM PST 24
Peak memory 145116 kb
Host smart-20ee2b58-0146-41dd-8b7b-210e4c413960
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=128429264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.128429264
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.434489596
Short name T9
Test name
Test status
Simulation time 26111734 ps
CPU time 0.4 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145036 kb
Host smart-9867e991-2c5f-4a0b-8f39-aaefbcf8ee3e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=434489596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.434489596
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1266339197
Short name T66
Test name
Test status
Simulation time 26637982 ps
CPU time 0.43 seconds
Started Feb 29 12:16:57 PM PST 24
Finished Feb 29 12:17:01 PM PST 24
Peak memory 145032 kb
Host smart-0a7089ad-8ab0-4c80-b413-c7820f25f5b4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1266339197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1266339197
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3170927467
Short name T76
Test name
Test status
Simulation time 28476661 ps
CPU time 0.39 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145084 kb
Host smart-4497273c-ab7f-4a64-85cf-eb267c84106a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3170927467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3170927467
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4121089848
Short name T68
Test name
Test status
Simulation time 28703426 ps
CPU time 0.39 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145084 kb
Host smart-c6666482-028f-4ea2-8ea2-a2d62e161171
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4121089848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4121089848
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3610157258
Short name T5
Test name
Test status
Simulation time 26975831 ps
CPU time 0.4 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145084 kb
Host smart-f3d608d4-3251-41f2-9b89-ec3f421d8682
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3610157258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3610157258
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3690267981
Short name T79
Test name
Test status
Simulation time 25768015 ps
CPU time 0.42 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145084 kb
Host smart-fdf891c4-9f90-4c5b-9617-3bae30d6f827
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3690267981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3690267981
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1268476162
Short name T32
Test name
Test status
Simulation time 29969714 ps
CPU time 0.43 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145084 kb
Host smart-b8a4360c-2b9d-43fa-aa98-290950283e79
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1268476162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1268476162
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2452045229
Short name T70
Test name
Test status
Simulation time 28271221 ps
CPU time 0.39 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145084 kb
Host smart-1b13ac79-11dd-4c35-8f42-300a50560680
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2452045229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2452045229
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4239011377
Short name T67
Test name
Test status
Simulation time 29341421 ps
CPU time 0.4 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145084 kb
Host smart-02e9813c-68fd-4e20-90c6-2503c0ba53ee
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4239011377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.4239011377
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.705585360
Short name T71
Test name
Test status
Simulation time 26464041 ps
CPU time 0.39 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145092 kb
Host smart-6a11c6d3-a55d-41b8-8faa-fd01a6c5d81e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=705585360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.705585360
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2071633169
Short name T33
Test name
Test status
Simulation time 26221891 ps
CPU time 0.4 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145084 kb
Host smart-e81e2a3c-5c53-41b5-9fcf-4fafb3782cba
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2071633169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2071633169
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2185746171
Short name T75
Test name
Test status
Simulation time 29047117 ps
CPU time 0.4 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145032 kb
Host smart-13eb364b-f65f-469f-8515-f62cd7d12909
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2185746171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2185746171
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1778590053
Short name T74
Test name
Test status
Simulation time 28125406 ps
CPU time 0.4 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145088 kb
Host smart-b69516fc-a670-4111-8e86-588bc7e066d1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1778590053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1778590053
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3323381364
Short name T14
Test name
Test status
Simulation time 29742260 ps
CPU time 0.4 seconds
Started Feb 29 12:16:58 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145096 kb
Host smart-feacdba1-78b1-4fa5-a53a-ee5e4092076a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3323381364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3323381364
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.396834047
Short name T72
Test name
Test status
Simulation time 28211671 ps
CPU time 0.38 seconds
Started Feb 29 12:16:57 PM PST 24
Finished Feb 29 12:17:00 PM PST 24
Peak memory 145092 kb
Host smart-8b6036d5-8a72-49aa-a546-3a52f02269e5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=396834047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.396834047
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.5946019
Short name T69
Test name
Test status
Simulation time 29391740 ps
CPU time 0.44 seconds
Started Feb 29 12:16:57 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145028 kb
Host smart-e556bf6e-0a23-4cae-947e-b83accadf460
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=5946019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.5946019
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2422483925
Short name T78
Test name
Test status
Simulation time 27416715 ps
CPU time 0.39 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145140 kb
Host smart-0aa1630c-b560-49cf-86dd-4f0ef0d2efd6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2422483925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2422483925
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.762876227
Short name T73
Test name
Test status
Simulation time 27112174 ps
CPU time 0.4 seconds
Started Feb 29 12:16:57 PM PST 24
Finished Feb 29 12:17:02 PM PST 24
Peak memory 145136 kb
Host smart-c134c23c-b56b-4ea7-b797-b7ce3b967a2c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=762876227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.762876227
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3830639699
Short name T77
Test name
Test status
Simulation time 28946012 ps
CPU time 0.4 seconds
Started Feb 29 12:16:59 PM PST 24
Finished Feb 29 12:17:03 PM PST 24
Peak memory 145012 kb
Host smart-bf68c144-db41-4587-9fe6-71d6045f139f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3830639699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3830639699
Directory /workspace/9.prim_sync_fatal_alert/latest
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