| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.28 | 88.28 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 75.00 | 75.00 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/1.prim_async_alert.2262309127 |
| 91.41 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/14.prim_sync_alert.302757373 |
| 94.11 | 2.70 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 7.14 | 95.83 | 0.00 | 83.72 | 6.98 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3488298841 |
| 94.50 | 0.39 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 2.33 | /workspace/coverage/default/10.prim_async_alert.2279057309 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3200490408 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/11.prim_sync_alert.2481283708 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.2614518004 |
| /workspace/coverage/default/11.prim_async_alert.864663261 |
| /workspace/coverage/default/12.prim_async_alert.501839864 |
| /workspace/coverage/default/13.prim_async_alert.1752058734 |
| /workspace/coverage/default/14.prim_async_alert.1773254906 |
| /workspace/coverage/default/15.prim_async_alert.1276401009 |
| /workspace/coverage/default/16.prim_async_alert.375428638 |
| /workspace/coverage/default/17.prim_async_alert.438057567 |
| /workspace/coverage/default/18.prim_async_alert.792189723 |
| /workspace/coverage/default/19.prim_async_alert.3604088134 |
| /workspace/coverage/default/2.prim_async_alert.273996407 |
| /workspace/coverage/default/3.prim_async_alert.3420126345 |
| /workspace/coverage/default/4.prim_async_alert.1357295370 |
| /workspace/coverage/default/5.prim_async_alert.3362206202 |
| /workspace/coverage/default/6.prim_async_alert.6948051 |
| /workspace/coverage/default/7.prim_async_alert.1608776678 |
| /workspace/coverage/default/8.prim_async_alert.1900514793 |
| /workspace/coverage/default/9.prim_async_alert.878217879 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1323032724 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4013469732 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3364546778 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1384567831 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.343437461 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.951000907 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2953952453 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1506819285 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.132440543 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2195678588 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3834263308 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.938534572 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3471966018 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2458707191 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4077248831 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.122047030 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3618244293 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.2576716048 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.2817152349 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.2448475311 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3157079621 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1275482144 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.3544176315 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.554898950 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.1400442675 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.660321987 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.1987629142 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.1290245996 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3284925203 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.3943455630 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.378896436 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1874791885 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.3728235374 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.1023109290 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.3675457459 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.301238793 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2059297307 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1349523702 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3732290879 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.843260477 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.835141102 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3472348729 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.271965162 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2694423097 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.757711227 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.953182913 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2266915125 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4230767838 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3563717722 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3757753029 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3542279804 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2172262625 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1085531360 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3608434387 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.698559155 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/16.prim_async_alert.375428638 | Mar 03 12:47:13 PM PST 24 | Mar 03 12:47:13 PM PST 24 | 12030683 ps | ||
| T2 | /workspace/coverage/default/14.prim_async_alert.1773254906 | Mar 03 12:47:04 PM PST 24 | Mar 03 12:47:05 PM PST 24 | 11110150 ps | ||
| T3 | /workspace/coverage/default/1.prim_async_alert.2262309127 | Mar 03 12:46:59 PM PST 24 | Mar 03 12:47:00 PM PST 24 | 11804231 ps | ||
| T21 | /workspace/coverage/default/7.prim_async_alert.1608776678 | Mar 03 12:47:14 PM PST 24 | Mar 03 12:47:14 PM PST 24 | 10853767 ps | ||
| T9 | /workspace/coverage/default/19.prim_async_alert.3604088134 | Mar 03 12:47:03 PM PST 24 | Mar 03 12:47:04 PM PST 24 | 10406801 ps | ||
| T22 | /workspace/coverage/default/0.prim_async_alert.2614518004 | Mar 03 12:47:18 PM PST 24 | Mar 03 12:47:18 PM PST 24 | 10862289 ps | ||
| T7 | /workspace/coverage/default/9.prim_async_alert.878217879 | Mar 03 12:46:59 PM PST 24 | Mar 03 12:47:00 PM PST 24 | 11682793 ps | ||
| T23 | /workspace/coverage/default/3.prim_async_alert.3420126345 | Mar 03 12:47:10 PM PST 24 | Mar 03 12:47:11 PM PST 24 | 11512278 ps | ||
| T16 | /workspace/coverage/default/4.prim_async_alert.1357295370 | Mar 03 12:47:01 PM PST 24 | Mar 03 12:47:02 PM PST 24 | 11383467 ps | ||
| T8 | /workspace/coverage/default/18.prim_async_alert.792189723 | Mar 03 12:47:07 PM PST 24 | Mar 03 12:47:08 PM PST 24 | 11147929 ps | ||
| T17 | /workspace/coverage/default/10.prim_async_alert.2279057309 | Mar 03 12:47:01 PM PST 24 | Mar 03 12:47:02 PM PST 24 | 11486988 ps | ||
| T24 | /workspace/coverage/default/5.prim_async_alert.3362206202 | Mar 03 12:47:12 PM PST 24 | Mar 03 12:47:13 PM PST 24 | 11326925 ps | ||
| T12 | /workspace/coverage/default/12.prim_async_alert.501839864 | Mar 03 12:47:11 PM PST 24 | Mar 03 12:47:12 PM PST 24 | 12472282 ps | ||
| T25 | /workspace/coverage/default/11.prim_async_alert.864663261 | Mar 03 12:47:14 PM PST 24 | Mar 03 12:47:14 PM PST 24 | 10740328 ps | ||
| T26 | /workspace/coverage/default/17.prim_async_alert.438057567 | Mar 03 12:46:59 PM PST 24 | Mar 03 12:47:00 PM PST 24 | 10640943 ps | ||
| T45 | /workspace/coverage/default/6.prim_async_alert.6948051 | Mar 03 12:47:01 PM PST 24 | Mar 03 12:47:02 PM PST 24 | 10921457 ps | ||
| T46 | /workspace/coverage/default/8.prim_async_alert.1900514793 | Mar 03 12:47:18 PM PST 24 | Mar 03 12:47:19 PM PST 24 | 10914840 ps | ||
| T47 | /workspace/coverage/default/2.prim_async_alert.273996407 | Mar 03 12:46:59 PM PST 24 | Mar 03 12:47:00 PM PST 24 | 11475639 ps | ||
| T48 | /workspace/coverage/default/13.prim_async_alert.1752058734 | Mar 03 12:47:11 PM PST 24 | Mar 03 12:47:11 PM PST 24 | 11402526 ps | ||
| T13 | /workspace/coverage/default/15.prim_async_alert.1276401009 | Mar 03 12:46:59 PM PST 24 | Mar 03 12:47:00 PM PST 24 | 11703672 ps | ||
| T14 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3618244293 | Mar 03 12:18:47 PM PST 24 | Mar 03 12:18:47 PM PST 24 | 30477257 ps | ||
| T38 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2195678588 | Mar 03 12:24:42 PM PST 24 | Mar 03 12:24:43 PM PST 24 | 29491145 ps | ||
| T39 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3471966018 | Mar 03 12:18:14 PM PST 24 | Mar 03 12:18:15 PM PST 24 | 30755613 ps | ||
| T4 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3200490408 | Mar 03 12:20:52 PM PST 24 | Mar 03 12:20:53 PM PST 24 | 28883715 ps | ||
| T40 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2953952453 | Mar 03 12:18:14 PM PST 24 | Mar 03 12:18:15 PM PST 24 | 30224285 ps | ||
| T41 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4013469732 | Mar 03 12:24:58 PM PST 24 | Mar 03 12:25:00 PM PST 24 | 29172989 ps | ||
| T15 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3488298841 | Mar 03 12:24:58 PM PST 24 | Mar 03 12:25:00 PM PST 24 | 31435528 ps | ||
| T42 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.938534572 | Mar 03 12:18:12 PM PST 24 | Mar 03 12:18:13 PM PST 24 | 29957938 ps | ||
| T43 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.951000907 | Mar 03 12:24:42 PM PST 24 | Mar 03 12:24:43 PM PST 24 | 30592670 ps | ||
| T44 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1506819285 | Mar 03 12:18:13 PM PST 24 | Mar 03 12:18:13 PM PST 24 | 28714066 ps | ||
| T49 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3364546778 | Mar 03 12:18:11 PM PST 24 | Mar 03 12:18:12 PM PST 24 | 30158445 ps | ||
| T18 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3834263308 | Mar 03 12:18:13 PM PST 24 | Mar 03 12:18:14 PM PST 24 | 27954361 ps | ||
| T50 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2458707191 | Mar 03 12:18:13 PM PST 24 | Mar 03 12:18:15 PM PST 24 | 30784595 ps | ||
| T19 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1323032724 | Mar 03 12:24:58 PM PST 24 | Mar 03 12:24:58 PM PST 24 | 31342874 ps | ||
| T51 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1384567831 | Mar 03 12:18:13 PM PST 24 | Mar 03 12:18:15 PM PST 24 | 29110028 ps | ||
| T20 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.343437461 | Mar 03 12:18:14 PM PST 24 | Mar 03 12:18:15 PM PST 24 | 29535922 ps | ||
| T52 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.122047030 | Mar 03 12:18:13 PM PST 24 | Mar 03 12:18:14 PM PST 24 | 30036323 ps | ||
| T53 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.132440543 | Mar 03 12:18:12 PM PST 24 | Mar 03 12:18:13 PM PST 24 | 31120670 ps | ||
| T54 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4077248831 | Mar 03 12:18:14 PM PST 24 | Mar 03 12:18:15 PM PST 24 | 29107360 ps | ||
| T35 | /workspace/coverage/sync_alert/5.prim_sync_alert.378896436 | Mar 03 12:33:50 PM PST 24 | Mar 03 12:33:51 PM PST 24 | 9826444 ps | ||
| T36 | /workspace/coverage/sync_alert/9.prim_sync_alert.3675457459 | Mar 03 12:34:02 PM PST 24 | Mar 03 12:34:03 PM PST 24 | 9967129 ps | ||
| T27 | /workspace/coverage/sync_alert/4.prim_sync_alert.3943455630 | Mar 03 12:33:54 PM PST 24 | Mar 03 12:33:55 PM PST 24 | 10136693 ps | ||
| T28 | /workspace/coverage/sync_alert/8.prim_sync_alert.1023109290 | Mar 03 12:33:51 PM PST 24 | Mar 03 12:33:53 PM PST 24 | 9437069 ps | ||
| T29 | /workspace/coverage/sync_alert/10.prim_sync_alert.2448475311 | Mar 03 12:33:56 PM PST 24 | Mar 03 12:33:58 PM PST 24 | 10415320 ps | ||
| T37 | /workspace/coverage/sync_alert/2.prim_sync_alert.1290245996 | Mar 03 12:33:50 PM PST 24 | Mar 03 12:33:51 PM PST 24 | 9102501 ps | ||
| T10 | /workspace/coverage/sync_alert/11.prim_sync_alert.2481283708 | Mar 03 12:33:56 PM PST 24 | Mar 03 12:33:58 PM PST 24 | 9277739 ps | ||
| T30 | /workspace/coverage/sync_alert/15.prim_sync_alert.3544176315 | Mar 03 12:34:13 PM PST 24 | Mar 03 12:34:13 PM PST 24 | 11342857 ps | ||
| T31 | /workspace/coverage/sync_alert/14.prim_sync_alert.302757373 | Mar 03 12:33:54 PM PST 24 | Mar 03 12:33:54 PM PST 24 | 9329158 ps | ||
| T32 | /workspace/coverage/sync_alert/7.prim_sync_alert.3728235374 | Mar 03 12:34:02 PM PST 24 | Mar 03 12:34:03 PM PST 24 | 9175839 ps | ||
| T33 | /workspace/coverage/sync_alert/0.prim_sync_alert.2576716048 | Mar 03 12:34:01 PM PST 24 | Mar 03 12:34:02 PM PST 24 | 8750987 ps | ||
| T34 | /workspace/coverage/sync_alert/6.prim_sync_alert.1874791885 | Mar 03 12:34:01 PM PST 24 | Mar 03 12:34:02 PM PST 24 | 10103644 ps | ||
| T55 | /workspace/coverage/sync_alert/17.prim_sync_alert.1400442675 | Mar 03 12:33:50 PM PST 24 | Mar 03 12:33:51 PM PST 24 | 9364973 ps | ||
| T56 | /workspace/coverage/sync_alert/12.prim_sync_alert.3157079621 | Mar 03 12:34:05 PM PST 24 | Mar 03 12:34:07 PM PST 24 | 9733184 ps | ||
| T57 | /workspace/coverage/sync_alert/1.prim_sync_alert.2817152349 | Mar 03 12:33:56 PM PST 24 | Mar 03 12:33:56 PM PST 24 | 9179380 ps | ||
| T11 | /workspace/coverage/sync_alert/13.prim_sync_alert.1275482144 | Mar 03 12:34:12 PM PST 24 | Mar 03 12:34:13 PM PST 24 | 8978596 ps | ||
| T58 | /workspace/coverage/sync_alert/3.prim_sync_alert.3284925203 | Mar 03 12:34:00 PM PST 24 | Mar 03 12:34:01 PM PST 24 | 8850526 ps | ||
| T59 | /workspace/coverage/sync_alert/18.prim_sync_alert.660321987 | Mar 03 12:34:08 PM PST 24 | Mar 03 12:34:08 PM PST 24 | 8919534 ps | ||
| T60 | /workspace/coverage/sync_alert/19.prim_sync_alert.1987629142 | Mar 03 12:33:49 PM PST 24 | Mar 03 12:33:50 PM PST 24 | 9606504 ps | ||
| T61 | /workspace/coverage/sync_alert/16.prim_sync_alert.554898950 | Mar 03 12:34:05 PM PST 24 | Mar 03 12:34:07 PM PST 24 | 9297093 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.843260477 | Mar 03 02:05:03 PM PST 24 | Mar 03 02:05:04 PM PST 24 | 26534217 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1349523702 | Mar 03 02:05:04 PM PST 24 | Mar 03 02:05:05 PM PST 24 | 27598970 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1085531360 | Mar 03 02:04:59 PM PST 24 | Mar 03 02:05:02 PM PST 24 | 27540043 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4230767838 | Mar 03 02:05:03 PM PST 24 | Mar 03 02:05:04 PM PST 24 | 27261762 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3542279804 | Mar 03 02:05:00 PM PST 24 | Mar 03 02:05:01 PM PST 24 | 27847046 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.271965162 | Mar 03 02:05:06 PM PST 24 | Mar 03 02:05:07 PM PST 24 | 27303198 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.953182913 | Mar 03 02:05:04 PM PST 24 | Mar 03 02:05:05 PM PST 24 | 27342854 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2266915125 | Mar 03 02:05:03 PM PST 24 | Mar 03 02:05:04 PM PST 24 | 27404975 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2694423097 | Mar 03 02:05:06 PM PST 24 | Mar 03 02:05:06 PM PST 24 | 27836683 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3472348729 | Mar 03 02:05:04 PM PST 24 | Mar 03 02:05:05 PM PST 24 | 27918741 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3757753029 | Mar 03 02:05:00 PM PST 24 | Mar 03 02:05:01 PM PST 24 | 27836611 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2059297307 | Mar 03 02:04:58 PM PST 24 | Mar 03 02:05:01 PM PST 24 | 29625390 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2172262625 | Mar 03 02:05:00 PM PST 24 | Mar 03 02:05:01 PM PST 24 | 26486712 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.835141102 | Mar 03 02:05:06 PM PST 24 | Mar 03 02:05:07 PM PST 24 | 26882221 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.301238793 | Mar 03 02:04:59 PM PST 24 | Mar 03 02:05:01 PM PST 24 | 27378742 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3608434387 | Mar 03 02:05:04 PM PST 24 | Mar 03 02:05:04 PM PST 24 | 28179126 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.698559155 | Mar 03 02:05:04 PM PST 24 | Mar 03 02:05:04 PM PST 24 | 25368043 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3563717722 | Mar 03 02:04:55 PM PST 24 | Mar 03 02:04:56 PM PST 24 | 29361316 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3732290879 | Mar 03 02:05:05 PM PST 24 | Mar 03 02:05:06 PM PST 24 | 26982506 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.757711227 | Mar 03 02:05:04 PM PST 24 | Mar 03 02:05:04 PM PST 24 | 28408683 ps |
| Test location | /workspace/coverage/default/1.prim_async_alert.2262309127 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11804231 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:46:59 PM PST 24 |
| Finished | Mar 03 12:47:00 PM PST 24 |
| Peak memory | 145532 kb |
| Host | smart-102be20e-631d-469b-a0d2-31f7583b660c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2262309127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2262309127 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.302757373 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9329158 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 12:33:54 PM PST 24 |
| Finished | Mar 03 12:33:54 PM PST 24 |
| Peak memory | 144920 kb |
| Host | smart-7bbdce09-6bb4-4730-bf7e-5388635cbd85 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=302757373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.302757373 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3488298841 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 31435528 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 12:24:58 PM PST 24 |
| Finished | Mar 03 12:25:00 PM PST 24 |
| Peak memory | 145360 kb |
| Host | smart-0e30a8ff-812a-47e2-a3da-500477482f5d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3488298841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3488298841 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.2279057309 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11486988 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:47:01 PM PST 24 |
| Finished | Mar 03 12:47:02 PM PST 24 |
| Peak memory | 145660 kb |
| Host | smart-fb074ee4-546f-4733-b9da-3eca7ceb6a3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279057309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2279057309 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3200490408 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28883715 ps |
| CPU time | 0.42 seconds |
| Started | Mar 03 12:20:52 PM PST 24 |
| Finished | Mar 03 12:20:53 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-04b3eff9-6daf-45de-91dd-f5c11b468e95 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3200490408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3200490408 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.2481283708 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9277739 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:33:56 PM PST 24 |
| Finished | Mar 03 12:33:58 PM PST 24 |
| Peak memory | 145004 kb |
| Host | smart-3ae93acc-8d01-4110-a25b-f999fffb6fb6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2481283708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2481283708 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.2614518004 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10862289 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:47:18 PM PST 24 |
| Finished | Mar 03 12:47:18 PM PST 24 |
| Peak memory | 145544 kb |
| Host | smart-924068b4-7e32-46bb-ade7-aead8675507e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2614518004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2614518004 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.864663261 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10740328 ps |
| CPU time | 0.42 seconds |
| Started | Mar 03 12:47:14 PM PST 24 |
| Finished | Mar 03 12:47:14 PM PST 24 |
| Peak memory | 145592 kb |
| Host | smart-15d54104-a323-454f-acd2-409931a91004 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864663261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.864663261 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.501839864 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12472282 ps |
| CPU time | 0.43 seconds |
| Started | Mar 03 12:47:11 PM PST 24 |
| Finished | Mar 03 12:47:12 PM PST 24 |
| Peak memory | 145544 kb |
| Host | smart-7da2ede6-27f6-4385-9378-73a4c7ac883d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501839864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.501839864 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1752058734 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11402526 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:47:11 PM PST 24 |
| Finished | Mar 03 12:47:11 PM PST 24 |
| Peak memory | 145604 kb |
| Host | smart-316b7b6f-737a-411e-9cdd-f414c8305e6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1752058734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1752058734 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1773254906 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11110150 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:47:04 PM PST 24 |
| Finished | Mar 03 12:47:05 PM PST 24 |
| Peak memory | 145536 kb |
| Host | smart-ce00a7a1-7422-45ef-8c19-53e6a0f8e541 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1773254906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1773254906 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1276401009 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11703672 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:46:59 PM PST 24 |
| Finished | Mar 03 12:47:00 PM PST 24 |
| Peak memory | 145544 kb |
| Host | smart-9af41371-a0a5-4b19-8819-db7ad4c6fbe2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1276401009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1276401009 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.375428638 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12030683 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:47:13 PM PST 24 |
| Finished | Mar 03 12:47:13 PM PST 24 |
| Peak memory | 145572 kb |
| Host | smart-92dcd1fc-ed2a-44b5-a078-3dc0d694e607 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375428638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.375428638 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.438057567 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10640943 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:46:59 PM PST 24 |
| Finished | Mar 03 12:47:00 PM PST 24 |
| Peak memory | 145484 kb |
| Host | smart-8c205d1b-f1c4-40e1-9160-61bbdafb1be0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438057567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.438057567 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.792189723 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11147929 ps |
| CPU time | 0.42 seconds |
| Started | Mar 03 12:47:07 PM PST 24 |
| Finished | Mar 03 12:47:08 PM PST 24 |
| Peak memory | 145564 kb |
| Host | smart-74e19aab-de73-436c-aab1-079b10630652 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792189723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.792189723 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3604088134 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10406801 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 12:47:03 PM PST 24 |
| Finished | Mar 03 12:47:04 PM PST 24 |
| Peak memory | 145488 kb |
| Host | smart-801dea08-d5d3-4ea8-bcdd-2454db3f1c5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604088134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3604088134 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.273996407 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11475639 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:46:59 PM PST 24 |
| Finished | Mar 03 12:47:00 PM PST 24 |
| Peak memory | 145688 kb |
| Host | smart-2b2dbbc8-4547-430b-8b68-17b86040a214 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273996407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.273996407 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.3420126345 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11512278 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:47:10 PM PST 24 |
| Finished | Mar 03 12:47:11 PM PST 24 |
| Peak memory | 145556 kb |
| Host | smart-1667537e-6472-47f1-b095-bfae071bf769 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3420126345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3420126345 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.1357295370 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11383467 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 12:47:01 PM PST 24 |
| Finished | Mar 03 12:47:02 PM PST 24 |
| Peak memory | 145544 kb |
| Host | smart-df70ef8c-baa8-431e-b577-585d10557c32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1357295370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1357295370 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3362206202 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11326925 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 12:47:12 PM PST 24 |
| Finished | Mar 03 12:47:13 PM PST 24 |
| Peak memory | 145588 kb |
| Host | smart-baf9ef44-8b00-4cc0-98bc-071e97162a9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3362206202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3362206202 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.6948051 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10921457 ps |
| CPU time | 0.42 seconds |
| Started | Mar 03 12:47:01 PM PST 24 |
| Finished | Mar 03 12:47:02 PM PST 24 |
| Peak memory | 145564 kb |
| Host | smart-9a7bfae9-9304-4a96-81fe-2c8fba1d4553 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6948051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.6948051 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.1608776678 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10853767 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 12:47:14 PM PST 24 |
| Finished | Mar 03 12:47:14 PM PST 24 |
| Peak memory | 145592 kb |
| Host | smart-c05b71e9-1564-4179-95ba-6dd7ba9b4df5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608776678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1608776678 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.1900514793 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10914840 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:47:18 PM PST 24 |
| Finished | Mar 03 12:47:19 PM PST 24 |
| Peak memory | 145464 kb |
| Host | smart-2445d1bc-7bec-4d37-9e2e-b3f5298780dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1900514793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1900514793 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.878217879 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11682793 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:46:59 PM PST 24 |
| Finished | Mar 03 12:47:00 PM PST 24 |
| Peak memory | 145528 kb |
| Host | smart-dab8dc67-66f6-4e62-965d-2b3d882f027e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=878217879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.878217879 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1323032724 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 31342874 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:24:58 PM PST 24 |
| Finished | Mar 03 12:24:58 PM PST 24 |
| Peak memory | 145360 kb |
| Host | smart-5e133771-563c-4c5e-9a2f-957656b83a4c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1323032724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1323032724 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4013469732 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29172989 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 12:24:58 PM PST 24 |
| Finished | Mar 03 12:25:00 PM PST 24 |
| Peak memory | 145360 kb |
| Host | smart-491876d3-74fe-4df0-a273-029e359cd312 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4013469732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.4013469732 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3364546778 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 30158445 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 12:18:11 PM PST 24 |
| Finished | Mar 03 12:18:12 PM PST 24 |
| Peak memory | 145868 kb |
| Host | smart-2a232493-481a-4c87-bd31-a264ba5d22c7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3364546778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3364546778 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1384567831 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29110028 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:18:13 PM PST 24 |
| Finished | Mar 03 12:18:15 PM PST 24 |
| Peak memory | 145940 kb |
| Host | smart-68122dae-44b9-4288-8c1a-2570b91af97b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1384567831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1384567831 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.343437461 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 29535922 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 12:18:14 PM PST 24 |
| Finished | Mar 03 12:18:15 PM PST 24 |
| Peak memory | 144456 kb |
| Host | smart-40300cf2-76a8-4562-900f-ae75ebc432b9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=343437461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.343437461 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.951000907 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30592670 ps |
| CPU time | 0.43 seconds |
| Started | Mar 03 12:24:42 PM PST 24 |
| Finished | Mar 03 12:24:43 PM PST 24 |
| Peak memory | 144508 kb |
| Host | smart-de0f9591-5534-4d6d-9d50-fb5aef6cb2db |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=951000907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.951000907 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2953952453 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 30224285 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:18:14 PM PST 24 |
| Finished | Mar 03 12:18:15 PM PST 24 |
| Peak memory | 145196 kb |
| Host | smart-d2b7c98e-9dad-4f41-ab7e-49e6428b639d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2953952453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2953952453 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1506819285 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 28714066 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 12:18:13 PM PST 24 |
| Finished | Mar 03 12:18:13 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-861a07e0-2575-4633-be33-d25e6f051a2e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1506819285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1506819285 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.132440543 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 31120670 ps |
| CPU time | 0.45 seconds |
| Started | Mar 03 12:18:12 PM PST 24 |
| Finished | Mar 03 12:18:13 PM PST 24 |
| Peak memory | 145832 kb |
| Host | smart-beeccfba-91c9-47ca-9442-eda42a87c0ca |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=132440543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.132440543 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2195678588 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 29491145 ps |
| CPU time | 0.42 seconds |
| Started | Mar 03 12:24:42 PM PST 24 |
| Finished | Mar 03 12:24:43 PM PST 24 |
| Peak memory | 145264 kb |
| Host | smart-a84ab8fc-deae-473a-9711-8eaa677f08b4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2195678588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2195678588 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3834263308 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 27954361 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 12:18:13 PM PST 24 |
| Finished | Mar 03 12:18:14 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-d9ee39dc-f1e7-4ade-9cfa-5eac304746b0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3834263308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3834263308 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.938534572 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29957938 ps |
| CPU time | 0.43 seconds |
| Started | Mar 03 12:18:12 PM PST 24 |
| Finished | Mar 03 12:18:13 PM PST 24 |
| Peak memory | 145360 kb |
| Host | smart-c9849147-93ed-45c4-9922-5d6bd8cd6d88 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=938534572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.938534572 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3471966018 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 30755613 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:18:14 PM PST 24 |
| Finished | Mar 03 12:18:15 PM PST 24 |
| Peak memory | 144976 kb |
| Host | smart-9bc0afab-8fdc-4faa-b47e-866b634f06da |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3471966018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3471966018 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2458707191 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30784595 ps |
| CPU time | 0.43 seconds |
| Started | Mar 03 12:18:13 PM PST 24 |
| Finished | Mar 03 12:18:15 PM PST 24 |
| Peak memory | 145536 kb |
| Host | smart-f424c447-88a0-47f5-8ba3-0cf15c29baa8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2458707191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2458707191 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4077248831 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 29107360 ps |
| CPU time | 0.43 seconds |
| Started | Mar 03 12:18:14 PM PST 24 |
| Finished | Mar 03 12:18:15 PM PST 24 |
| Peak memory | 144760 kb |
| Host | smart-152af731-7f8f-4e5d-9d28-77f198bb6324 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4077248831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.4077248831 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.122047030 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30036323 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:18:13 PM PST 24 |
| Finished | Mar 03 12:18:14 PM PST 24 |
| Peak memory | 145472 kb |
| Host | smart-a109e8fd-bfcd-40e4-a7fb-305386820569 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=122047030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.122047030 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3618244293 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 30477257 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:18:47 PM PST 24 |
| Finished | Mar 03 12:18:47 PM PST 24 |
| Peak memory | 145416 kb |
| Host | smart-a9b5dec5-c8d1-46bb-8dbb-ddaaffb587b7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3618244293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3618244293 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.2576716048 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8750987 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:34:01 PM PST 24 |
| Finished | Mar 03 12:34:02 PM PST 24 |
| Peak memory | 144916 kb |
| Host | smart-dba41909-f086-4710-81e5-02c13e5130b9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2576716048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2576716048 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.2817152349 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9179380 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:33:56 PM PST 24 |
| Finished | Mar 03 12:33:56 PM PST 24 |
| Peak memory | 144912 kb |
| Host | smart-084291ea-6fac-45e5-930c-9751cdcc4732 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2817152349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2817152349 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.2448475311 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10415320 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:33:56 PM PST 24 |
| Finished | Mar 03 12:33:58 PM PST 24 |
| Peak memory | 144924 kb |
| Host | smart-665b5149-eba9-4b34-9212-36a0748fc47b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2448475311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2448475311 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3157079621 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9733184 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 12:34:05 PM PST 24 |
| Finished | Mar 03 12:34:07 PM PST 24 |
| Peak memory | 144900 kb |
| Host | smart-29f01989-64f6-4ae8-bf02-c748417011c8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3157079621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3157079621 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1275482144 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8978596 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 12:34:12 PM PST 24 |
| Finished | Mar 03 12:34:13 PM PST 24 |
| Peak memory | 144876 kb |
| Host | smart-29e0322f-d330-4654-b4a9-aeecdfc87b43 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1275482144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1275482144 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3544176315 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 11342857 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 12:34:13 PM PST 24 |
| Finished | Mar 03 12:34:13 PM PST 24 |
| Peak memory | 144856 kb |
| Host | smart-79ba87c0-0ba8-4aa8-9e24-bfb81ca672f8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3544176315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3544176315 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.554898950 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9297093 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 12:34:05 PM PST 24 |
| Finished | Mar 03 12:34:07 PM PST 24 |
| Peak memory | 144948 kb |
| Host | smart-4bc669c7-627b-44d4-8fb3-c1cc14ac38b8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=554898950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.554898950 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.1400442675 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9364973 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 12:33:50 PM PST 24 |
| Finished | Mar 03 12:33:51 PM PST 24 |
| Peak memory | 144904 kb |
| Host | smart-f43aa7b9-6a2e-497f-a727-f46a22341220 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1400442675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1400442675 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.660321987 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8919534 ps |
| CPU time | 0.44 seconds |
| Started | Mar 03 12:34:08 PM PST 24 |
| Finished | Mar 03 12:34:08 PM PST 24 |
| Peak memory | 144900 kb |
| Host | smart-eb96ce9a-f1ec-4abf-a94e-5055cc412a55 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=660321987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.660321987 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.1987629142 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9606504 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:33:49 PM PST 24 |
| Finished | Mar 03 12:33:50 PM PST 24 |
| Peak memory | 144924 kb |
| Host | smart-65aa5936-83f7-4b34-9ae7-ee53807c7004 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1987629142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1987629142 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.1290245996 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9102501 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:33:50 PM PST 24 |
| Finished | Mar 03 12:33:51 PM PST 24 |
| Peak memory | 144916 kb |
| Host | smart-80a02c2b-bce2-4b66-b8c0-2386418d28f9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1290245996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1290245996 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3284925203 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8850526 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 12:34:00 PM PST 24 |
| Finished | Mar 03 12:34:01 PM PST 24 |
| Peak memory | 144888 kb |
| Host | smart-0783dcdb-31c6-4970-84f5-8b6040a7d02d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3284925203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3284925203 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.3943455630 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10136693 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:33:54 PM PST 24 |
| Finished | Mar 03 12:33:55 PM PST 24 |
| Peak memory | 144916 kb |
| Host | smart-29cc612b-2532-4082-8e47-1613addf0ad0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3943455630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3943455630 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.378896436 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9826444 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:33:50 PM PST 24 |
| Finished | Mar 03 12:33:51 PM PST 24 |
| Peak memory | 144880 kb |
| Host | smart-adcab788-0204-4cc2-8a8c-e2e9e1a9e0fd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=378896436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.378896436 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1874791885 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10103644 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:34:01 PM PST 24 |
| Finished | Mar 03 12:34:02 PM PST 24 |
| Peak memory | 144916 kb |
| Host | smart-d7383028-a992-4ed3-83ab-115b1bbe9bda |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1874791885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1874791885 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.3728235374 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9175839 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:34:02 PM PST 24 |
| Finished | Mar 03 12:34:03 PM PST 24 |
| Peak memory | 144892 kb |
| Host | smart-b02d8484-b989-47e2-a319-14acb8186b33 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3728235374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3728235374 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1023109290 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9437069 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:33:51 PM PST 24 |
| Finished | Mar 03 12:33:53 PM PST 24 |
| Peak memory | 144936 kb |
| Host | smart-d1343585-dfd4-42e1-b873-7ccba164b4a8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1023109290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1023109290 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.3675457459 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9967129 ps |
| CPU time | 0.43 seconds |
| Started | Mar 03 12:34:02 PM PST 24 |
| Finished | Mar 03 12:34:03 PM PST 24 |
| Peak memory | 144916 kb |
| Host | smart-196c31d9-513f-4b08-b4f3-84d24359da21 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3675457459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3675457459 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.301238793 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27378742 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 02:04:59 PM PST 24 |
| Finished | Mar 03 02:05:01 PM PST 24 |
| Peak memory | 145192 kb |
| Host | smart-5829b82a-1660-4b0e-b92d-27945e8c144f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=301238793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.301238793 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2059297307 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 29625390 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 02:04:58 PM PST 24 |
| Finished | Mar 03 02:05:01 PM PST 24 |
| Peak memory | 145180 kb |
| Host | smart-fa56d29d-e40f-4fd8-ad57-159a3e3223b3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2059297307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2059297307 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1349523702 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27598970 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 02:05:04 PM PST 24 |
| Finished | Mar 03 02:05:05 PM PST 24 |
| Peak memory | 145156 kb |
| Host | smart-1c08f99b-d165-4649-869d-b2ac4149162c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1349523702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1349523702 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3732290879 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26982506 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 02:05:05 PM PST 24 |
| Finished | Mar 03 02:05:06 PM PST 24 |
| Peak memory | 145180 kb |
| Host | smart-0c2b06c9-1311-4291-ada9-f80e990c37fe |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3732290879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3732290879 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.843260477 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 26534217 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 02:05:03 PM PST 24 |
| Finished | Mar 03 02:05:04 PM PST 24 |
| Peak memory | 145180 kb |
| Host | smart-ec131d94-5f59-488d-b755-0c627291ecff |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=843260477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.843260477 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.835141102 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26882221 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 02:05:06 PM PST 24 |
| Finished | Mar 03 02:05:07 PM PST 24 |
| Peak memory | 145192 kb |
| Host | smart-a05fdf8d-e277-452d-b54d-b0e04333db45 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=835141102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.835141102 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3472348729 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27918741 ps |
| CPU time | 0.42 seconds |
| Started | Mar 03 02:05:04 PM PST 24 |
| Finished | Mar 03 02:05:05 PM PST 24 |
| Peak memory | 145172 kb |
| Host | smart-e19d22de-4711-481d-ad25-33bb591222d6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3472348729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3472348729 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.271965162 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27303198 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 02:05:06 PM PST 24 |
| Finished | Mar 03 02:05:07 PM PST 24 |
| Peak memory | 145168 kb |
| Host | smart-65658db3-906c-4670-a800-1355e6e28ff5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=271965162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.271965162 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2694423097 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27836683 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 02:05:06 PM PST 24 |
| Finished | Mar 03 02:05:06 PM PST 24 |
| Peak memory | 145168 kb |
| Host | smart-0864615d-7069-4c64-8231-389af847c7b5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2694423097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2694423097 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.757711227 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 28408683 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 02:05:04 PM PST 24 |
| Finished | Mar 03 02:05:04 PM PST 24 |
| Peak memory | 145164 kb |
| Host | smart-bb4a1d46-8f11-474d-b074-2cdc1b51387d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=757711227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.757711227 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.953182913 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27342854 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 02:05:04 PM PST 24 |
| Finished | Mar 03 02:05:05 PM PST 24 |
| Peak memory | 145192 kb |
| Host | smart-8f6660d2-69d8-4418-9fdb-dba940671f1f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=953182913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.953182913 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2266915125 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27404975 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 02:05:03 PM PST 24 |
| Finished | Mar 03 02:05:04 PM PST 24 |
| Peak memory | 145068 kb |
| Host | smart-593f2d04-c214-4bbe-b0b1-08696d23dfba |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2266915125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2266915125 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4230767838 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 27261762 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 02:05:03 PM PST 24 |
| Finished | Mar 03 02:05:04 PM PST 24 |
| Peak memory | 145172 kb |
| Host | smart-bbabe34a-3cd4-450e-992b-a60cbf852636 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4230767838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.4230767838 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3563717722 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 29361316 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 02:04:55 PM PST 24 |
| Finished | Mar 03 02:04:56 PM PST 24 |
| Peak memory | 145084 kb |
| Host | smart-799f6151-5d18-492a-9f17-37866b77c4fa |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3563717722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3563717722 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3757753029 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27836611 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 02:05:00 PM PST 24 |
| Finished | Mar 03 02:05:01 PM PST 24 |
| Peak memory | 145120 kb |
| Host | smart-8b04ae94-4ca0-4daa-954b-4d68749e37bb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3757753029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3757753029 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3542279804 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27847046 ps |
| CPU time | 0.4 seconds |
| Started | Mar 03 02:05:00 PM PST 24 |
| Finished | Mar 03 02:05:01 PM PST 24 |
| Peak memory | 145188 kb |
| Host | smart-7a951b99-2265-4080-984a-bc49fe2140d8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3542279804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3542279804 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2172262625 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26486712 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 02:05:00 PM PST 24 |
| Finished | Mar 03 02:05:01 PM PST 24 |
| Peak memory | 145088 kb |
| Host | smart-639c196f-a872-4992-be12-f21843021745 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2172262625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2172262625 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1085531360 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27540043 ps |
| CPU time | 0.45 seconds |
| Started | Mar 03 02:04:59 PM PST 24 |
| Finished | Mar 03 02:05:02 PM PST 24 |
| Peak memory | 145176 kb |
| Host | smart-e6d96395-6b10-4c20-9852-df0778bcecbf |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1085531360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1085531360 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3608434387 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 28179126 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 02:05:04 PM PST 24 |
| Finished | Mar 03 02:05:04 PM PST 24 |
| Peak memory | 145160 kb |
| Host | smart-a7441a86-f7e2-44fa-b735-b6cf3c93e7ba |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3608434387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3608434387 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.698559155 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 25368043 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 02:05:04 PM PST 24 |
| Finished | Mar 03 02:05:04 PM PST 24 |
| Peak memory | 145196 kb |
| Host | smart-dd802c3e-4612-4406-846d-efe634781c48 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=698559155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.698559155 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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