| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.63 | 88.63 | 100.00 | 100.00 | 95.83 | 95.83 | 100.00 | 100.00 | 75.00 | 75.00 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/9.prim_async_alert.2924296054 |
| 91.76 | 3.13 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/1.prim_sync_alert.735354146 |
| 93.27 | 1.51 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 82.14 | 0.00 | 95.83 | 0.00 | 83.72 | 6.98 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.991016847 |
| 94.25 | 0.98 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 85.71 | 3.57 | 95.83 | 0.00 | 86.05 | 2.33 | /workspace/coverage/default/1.prim_async_alert.1897533962 |
| 94.85 | 0.60 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/12.prim_async_alert.4201242795 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.948478997 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.992297748 |
| /workspace/coverage/default/10.prim_async_alert.650800808 |
| /workspace/coverage/default/11.prim_async_alert.417162138 |
| /workspace/coverage/default/13.prim_async_alert.1731593699 |
| /workspace/coverage/default/14.prim_async_alert.205091284 |
| /workspace/coverage/default/15.prim_async_alert.2021620291 |
| /workspace/coverage/default/16.prim_async_alert.835469149 |
| /workspace/coverage/default/17.prim_async_alert.4175984564 |
| /workspace/coverage/default/18.prim_async_alert.3261631952 |
| /workspace/coverage/default/19.prim_async_alert.4266441934 |
| /workspace/coverage/default/2.prim_async_alert.1997378847 |
| /workspace/coverage/default/3.prim_async_alert.202345964 |
| /workspace/coverage/default/4.prim_async_alert.1460881714 |
| /workspace/coverage/default/5.prim_async_alert.634025309 |
| /workspace/coverage/default/6.prim_async_alert.2998361951 |
| /workspace/coverage/default/7.prim_async_alert.3227823187 |
| /workspace/coverage/default/8.prim_async_alert.3885514508 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3782190135 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4159854697 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1304447125 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2849636895 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.950206874 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2158957533 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2347337049 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1367439826 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3661563341 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2454655358 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3702012840 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1196034593 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2159483456 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1785286136 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.465845863 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2161038416 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.287625446 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3202571116 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.2498612665 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3155453311 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.3853973256 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1927091991 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.1120773854 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.3967626929 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.2490255711 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.8105313 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.3783344333 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.3778368266 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.817331581 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.3268135269 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.2366265300 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.2576334630 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.2197705643 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.3840048768 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.2985750626 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1288830605 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1148758695 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4232202838 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3081381109 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1052079048 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1397762657 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.17037492 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.126019621 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.269207638 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.542467913 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.965330785 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.200220929 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1111917441 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4066349968 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3077216037 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1120052574 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3957235413 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3204398105 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3402341489 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/5.prim_async_alert.634025309 | Mar 07 12:28:13 PM PST 24 | Mar 07 12:28:14 PM PST 24 | 10642001 ps | ||
| T2 | /workspace/coverage/default/10.prim_async_alert.650800808 | Mar 07 12:20:50 PM PST 24 | Mar 07 12:20:50 PM PST 24 | 10635999 ps | ||
| T3 | /workspace/coverage/default/1.prim_async_alert.1897533962 | Mar 07 12:27:23 PM PST 24 | Mar 07 12:27:24 PM PST 24 | 10904627 ps | ||
| T7 | /workspace/coverage/default/15.prim_async_alert.2021620291 | Mar 07 12:20:32 PM PST 24 | Mar 07 12:20:33 PM PST 24 | 11484292 ps | ||
| T10 | /workspace/coverage/default/16.prim_async_alert.835469149 | Mar 07 12:20:28 PM PST 24 | Mar 07 12:20:29 PM PST 24 | 12041773 ps | ||
| T17 | /workspace/coverage/default/17.prim_async_alert.4175984564 | Mar 07 12:20:46 PM PST 24 | Mar 07 12:20:47 PM PST 24 | 10005836 ps | ||
| T18 | /workspace/coverage/default/4.prim_async_alert.1460881714 | Mar 07 12:20:07 PM PST 24 | Mar 07 12:20:07 PM PST 24 | 10842558 ps | ||
| T8 | /workspace/coverage/default/6.prim_async_alert.2998361951 | Mar 07 12:21:00 PM PST 24 | Mar 07 12:21:01 PM PST 24 | 11954206 ps | ||
| T9 | /workspace/coverage/default/9.prim_async_alert.2924296054 | Mar 07 12:20:15 PM PST 24 | Mar 07 12:20:16 PM PST 24 | 12269169 ps | ||
| T19 | /workspace/coverage/default/19.prim_async_alert.4266441934 | Mar 07 12:21:37 PM PST 24 | Mar 07 12:21:38 PM PST 24 | 11440879 ps | ||
| T13 | /workspace/coverage/default/12.prim_async_alert.4201242795 | Mar 07 12:20:28 PM PST 24 | Mar 07 12:20:28 PM PST 24 | 11628308 ps | ||
| T20 | /workspace/coverage/default/8.prim_async_alert.3885514508 | Mar 07 12:20:02 PM PST 24 | Mar 07 12:20:02 PM PST 24 | 12065546 ps | ||
| T14 | /workspace/coverage/default/11.prim_async_alert.417162138 | Mar 07 12:20:01 PM PST 24 | Mar 07 12:20:01 PM PST 24 | 10825184 ps | ||
| T15 | /workspace/coverage/default/14.prim_async_alert.205091284 | Mar 07 12:20:59 PM PST 24 | Mar 07 12:21:00 PM PST 24 | 10817653 ps | ||
| T21 | /workspace/coverage/default/3.prim_async_alert.202345964 | Mar 07 12:20:09 PM PST 24 | Mar 07 12:20:10 PM PST 24 | 11487230 ps | ||
| T48 | /workspace/coverage/default/13.prim_async_alert.1731593699 | Mar 07 12:21:51 PM PST 24 | Mar 07 12:21:52 PM PST 24 | 11215378 ps | ||
| T22 | /workspace/coverage/default/0.prim_async_alert.992297748 | Mar 07 12:20:02 PM PST 24 | Mar 07 12:20:03 PM PST 24 | 10437367 ps | ||
| T49 | /workspace/coverage/default/18.prim_async_alert.3261631952 | Mar 07 12:19:35 PM PST 24 | Mar 07 12:19:36 PM PST 24 | 11119807 ps | ||
| T23 | /workspace/coverage/default/7.prim_async_alert.3227823187 | Mar 07 12:32:30 PM PST 24 | Mar 07 12:32:30 PM PST 24 | 11990276 ps | ||
| T50 | /workspace/coverage/default/2.prim_async_alert.1997378847 | Mar 07 12:22:57 PM PST 24 | Mar 07 12:22:57 PM PST 24 | 12438797 ps | ||
| T41 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1304447125 | Mar 07 12:18:33 PM PST 24 | Mar 07 12:18:34 PM PST 24 | 28552415 ps | ||
| T4 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.991016847 | Mar 07 12:18:42 PM PST 24 | Mar 07 12:18:43 PM PST 24 | 29275836 ps | ||
| T40 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3782190135 | Mar 07 12:18:48 PM PST 24 | Mar 07 12:18:49 PM PST 24 | 31670537 ps | ||
| T42 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.465845863 | Mar 07 12:18:42 PM PST 24 | Mar 07 12:18:43 PM PST 24 | 29142637 ps | ||
| T43 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2159483456 | Mar 07 12:18:51 PM PST 24 | Mar 07 12:18:52 PM PST 24 | 31034678 ps | ||
| T44 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1785286136 | Mar 07 12:18:43 PM PST 24 | Mar 07 12:18:44 PM PST 24 | 31059554 ps | ||
| T45 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3702012840 | Mar 07 12:18:52 PM PST 24 | Mar 07 12:18:52 PM PST 24 | 29361853 ps | ||
| T46 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2849636895 | Mar 07 12:18:43 PM PST 24 | Mar 07 12:18:43 PM PST 24 | 30595635 ps | ||
| T16 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.950206874 | Mar 07 12:18:43 PM PST 24 | Mar 07 12:18:44 PM PST 24 | 29913277 ps | ||
| T47 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4159854697 | Mar 07 12:18:52 PM PST 24 | Mar 07 12:18:52 PM PST 24 | 32776963 ps | ||
| T51 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2158957533 | Mar 07 12:18:33 PM PST 24 | Mar 07 12:18:34 PM PST 24 | 29781718 ps | ||
| T5 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1367439826 | Mar 07 12:18:52 PM PST 24 | Mar 07 12:18:52 PM PST 24 | 30885547 ps | ||
| T52 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1196034593 | Mar 07 12:18:52 PM PST 24 | Mar 07 12:18:53 PM PST 24 | 30877790 ps | ||
| T6 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2454655358 | Mar 07 12:18:42 PM PST 24 | Mar 07 12:18:43 PM PST 24 | 30715853 ps | ||
| T53 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3661563341 | Mar 07 12:18:52 PM PST 24 | Mar 07 12:18:52 PM PST 24 | 32229702 ps | ||
| T54 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2347337049 | Mar 07 12:18:48 PM PST 24 | Mar 07 12:18:49 PM PST 24 | 27994118 ps | ||
| T55 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2161038416 | Mar 07 12:18:43 PM PST 24 | Mar 07 12:18:44 PM PST 24 | 30918610 ps | ||
| T24 | /workspace/coverage/sync_alert/7.prim_sync_alert.2197705643 | Mar 07 12:20:01 PM PST 24 | Mar 07 12:20:01 PM PST 24 | 8372388 ps | ||
| T34 | /workspace/coverage/sync_alert/5.prim_sync_alert.2366265300 | Mar 07 12:24:35 PM PST 24 | Mar 07 12:24:35 PM PST 24 | 8419067 ps | ||
| T35 | /workspace/coverage/sync_alert/18.prim_sync_alert.8105313 | Mar 07 12:19:38 PM PST 24 | Mar 07 12:19:38 PM PST 24 | 9929183 ps | ||
| T36 | /workspace/coverage/sync_alert/10.prim_sync_alert.3202571116 | Mar 07 12:22:09 PM PST 24 | Mar 07 12:22:09 PM PST 24 | 9032308 ps | ||
| T25 | /workspace/coverage/sync_alert/11.prim_sync_alert.2498612665 | Mar 07 12:20:01 PM PST 24 | Mar 07 12:20:01 PM PST 24 | 8545984 ps | ||
| T26 | /workspace/coverage/sync_alert/0.prim_sync_alert.287625446 | Mar 07 12:21:42 PM PST 24 | Mar 07 12:21:43 PM PST 24 | 8436076 ps | ||
| T37 | /workspace/coverage/sync_alert/1.prim_sync_alert.735354146 | Mar 07 12:20:01 PM PST 24 | Mar 07 12:20:01 PM PST 24 | 8930364 ps | ||
| T38 | /workspace/coverage/sync_alert/4.prim_sync_alert.3268135269 | Mar 07 12:21:52 PM PST 24 | Mar 07 12:21:53 PM PST 24 | 10827532 ps | ||
| T27 | /workspace/coverage/sync_alert/6.prim_sync_alert.2576334630 | Mar 07 12:21:44 PM PST 24 | Mar 07 12:21:45 PM PST 24 | 9113171 ps | ||
| T39 | /workspace/coverage/sync_alert/3.prim_sync_alert.817331581 | Mar 07 12:21:27 PM PST 24 | Mar 07 12:21:27 PM PST 24 | 9132870 ps | ||
| T56 | /workspace/coverage/sync_alert/9.prim_sync_alert.2985750626 | Mar 07 12:19:52 PM PST 24 | Mar 07 12:19:52 PM PST 24 | 8552887 ps | ||
| T28 | /workspace/coverage/sync_alert/15.prim_sync_alert.1120773854 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:19:13 PM PST 24 | 9787048 ps | ||
| T29 | /workspace/coverage/sync_alert/14.prim_sync_alert.1927091991 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:19:13 PM PST 24 | 9667622 ps | ||
| T57 | /workspace/coverage/sync_alert/13.prim_sync_alert.3853973256 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:19:13 PM PST 24 | 9227639 ps | ||
| T30 | /workspace/coverage/sync_alert/2.prim_sync_alert.3778368266 | Mar 07 12:21:51 PM PST 24 | Mar 07 12:21:52 PM PST 24 | 9004162 ps | ||
| T58 | /workspace/coverage/sync_alert/8.prim_sync_alert.3840048768 | Mar 07 12:32:20 PM PST 24 | Mar 07 12:32:22 PM PST 24 | 9769201 ps | ||
| T31 | /workspace/coverage/sync_alert/19.prim_sync_alert.3783344333 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:19:13 PM PST 24 | 9053342 ps | ||
| T59 | /workspace/coverage/sync_alert/17.prim_sync_alert.2490255711 | Mar 07 12:26:24 PM PST 24 | Mar 07 12:26:26 PM PST 24 | 10203138 ps | ||
| T60 | /workspace/coverage/sync_alert/12.prim_sync_alert.3155453311 | Mar 07 12:22:05 PM PST 24 | Mar 07 12:22:06 PM PST 24 | 9387985 ps | ||
| T61 | /workspace/coverage/sync_alert/16.prim_sync_alert.3967626929 | Mar 07 12:19:13 PM PST 24 | Mar 07 12:19:14 PM PST 24 | 9089276 ps | ||
| T11 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.948478997 | Mar 07 12:20:10 PM PST 24 | Mar 07 12:20:10 PM PST 24 | 28138299 ps | ||
| T12 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1052079048 | Mar 07 12:20:50 PM PST 24 | Mar 07 12:20:50 PM PST 24 | 29055517 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1148758695 | Mar 07 12:19:13 PM PST 24 | Mar 07 12:19:14 PM PST 24 | 27630659 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1120052574 | Mar 07 12:20:27 PM PST 24 | Mar 07 12:20:27 PM PST 24 | 29102454 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3957235413 | Mar 07 12:20:13 PM PST 24 | Mar 07 12:20:14 PM PST 24 | 25896795 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.200220929 | Mar 07 12:21:11 PM PST 24 | Mar 07 12:21:12 PM PST 24 | 27918513 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.17037492 | Mar 07 12:27:22 PM PST 24 | Mar 07 12:27:23 PM PST 24 | 26560639 ps | ||
| T32 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.965330785 | Mar 07 12:20:01 PM PST 24 | Mar 07 12:20:02 PM PST 24 | 28264978 ps | ||
| T33 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4066349968 | Mar 07 12:20:07 PM PST 24 | Mar 07 12:20:07 PM PST 24 | 26966223 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1111917441 | Mar 07 12:21:12 PM PST 24 | Mar 07 12:21:12 PM PST 24 | 27616841 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3204398105 | Mar 07 12:20:06 PM PST 24 | Mar 07 12:20:07 PM PST 24 | 27274342 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4232202838 | Mar 07 12:20:17 PM PST 24 | Mar 07 12:20:18 PM PST 24 | 27982124 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3081381109 | Mar 07 12:32:28 PM PST 24 | Mar 07 12:32:29 PM PST 24 | 27051184 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.542467913 | Mar 07 12:20:02 PM PST 24 | Mar 07 12:20:03 PM PST 24 | 28533763 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3077216037 | Mar 07 12:19:58 PM PST 24 | Mar 07 12:19:59 PM PST 24 | 26830319 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.269207638 | Mar 07 12:20:02 PM PST 24 | Mar 07 12:20:02 PM PST 24 | 29143218 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3402341489 | Mar 07 12:20:59 PM PST 24 | Mar 07 12:20:59 PM PST 24 | 25426692 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1397762657 | Mar 07 12:20:59 PM PST 24 | Mar 07 12:20:59 PM PST 24 | 26854508 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1288830605 | Mar 07 12:21:08 PM PST 24 | Mar 07 12:21:09 PM PST 24 | 25883481 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.126019621 | Mar 07 12:20:49 PM PST 24 | Mar 07 12:20:50 PM PST 24 | 28581289 ps |
| Test location | /workspace/coverage/default/9.prim_async_alert.2924296054 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12269169 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:15 PM PST 24 |
| Finished | Mar 07 12:20:16 PM PST 24 |
| Peak memory | 145652 kb |
| Host | smart-23e1bb52-50fc-449c-a2c0-0542cb4fc7b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924296054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2924296054 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.735354146 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8930364 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:01 PM PST 24 |
| Finished | Mar 07 12:20:01 PM PST 24 |
| Peak memory | 144904 kb |
| Host | smart-1cc813fe-f205-40c0-b474-139ba963b64f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=735354146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.735354146 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.991016847 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 29275836 ps |
| CPU time | 0.41 seconds |
| Started | Mar 07 12:18:42 PM PST 24 |
| Finished | Mar 07 12:18:43 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-5b11e42e-28c5-4786-952b-98aab2d34f9a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=991016847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.991016847 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1897533962 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10904627 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:27:23 PM PST 24 |
| Finished | Mar 07 12:27:24 PM PST 24 |
| Peak memory | 145768 kb |
| Host | smart-71665646-e5d0-4f3a-8333-b00dea6dd3d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1897533962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1897533962 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.4201242795 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11628308 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:20:28 PM PST 24 |
| Finished | Mar 07 12:20:28 PM PST 24 |
| Peak memory | 145648 kb |
| Host | smart-cafa0fe2-f95a-4977-b97a-a75afa47d785 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4201242795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.4201242795 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.948478997 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 28138299 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:10 PM PST 24 |
| Finished | Mar 07 12:20:10 PM PST 24 |
| Peak memory | 145168 kb |
| Host | smart-8ee462e0-c6c4-4607-a691-ffd730f4491c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=948478997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.948478997 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.992297748 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10437367 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:02 PM PST 24 |
| Finished | Mar 07 12:20:03 PM PST 24 |
| Peak memory | 145668 kb |
| Host | smart-a5752c78-8376-4517-814d-87b554b31bc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=992297748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.992297748 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.650800808 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10635999 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:20:50 PM PST 24 |
| Finished | Mar 07 12:20:50 PM PST 24 |
| Peak memory | 145632 kb |
| Host | smart-a851ea0c-cb4f-4757-87fd-e346ba703812 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650800808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.650800808 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.417162138 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10825184 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:01 PM PST 24 |
| Finished | Mar 07 12:20:01 PM PST 24 |
| Peak memory | 145460 kb |
| Host | smart-2eeed90e-9719-4083-b276-03e0382317c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=417162138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.417162138 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1731593699 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11215378 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:21:51 PM PST 24 |
| Finished | Mar 07 12:21:52 PM PST 24 |
| Peak memory | 145636 kb |
| Host | smart-65ce326e-2e44-41b9-aa09-7f42ad4d3144 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1731593699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1731593699 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.205091284 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10817653 ps |
| CPU time | 0.41 seconds |
| Started | Mar 07 12:20:59 PM PST 24 |
| Finished | Mar 07 12:21:00 PM PST 24 |
| Peak memory | 145632 kb |
| Host | smart-a886ac3a-a8d0-4dd3-b86d-469ba0765136 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205091284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.205091284 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.2021620291 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11484292 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:32 PM PST 24 |
| Finished | Mar 07 12:20:33 PM PST 24 |
| Peak memory | 145668 kb |
| Host | smart-e609ed5b-3899-4883-914c-93c26002fd99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2021620291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2021620291 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.835469149 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12041773 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:20:28 PM PST 24 |
| Finished | Mar 07 12:20:29 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-e31d40a7-d068-4fb6-a68d-6b62641e6f31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835469149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.835469149 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.4175984564 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10005836 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:46 PM PST 24 |
| Finished | Mar 07 12:20:47 PM PST 24 |
| Peak memory | 145556 kb |
| Host | smart-f9d67309-7985-4442-b89c-f7940de3e6df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175984564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4175984564 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.3261631952 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11119807 ps |
| CPU time | 0.43 seconds |
| Started | Mar 07 12:19:35 PM PST 24 |
| Finished | Mar 07 12:19:36 PM PST 24 |
| Peak memory | 145592 kb |
| Host | smart-ffa8c859-36d6-4f28-b6ef-9c7ee314f489 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3261631952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3261631952 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.4266441934 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11440879 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:21:37 PM PST 24 |
| Finished | Mar 07 12:21:38 PM PST 24 |
| Peak memory | 145628 kb |
| Host | smart-1c6e2018-ff50-4c49-a68c-b8f99d4f8cc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4266441934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.4266441934 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.1997378847 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 12438797 ps |
| CPU time | 0.41 seconds |
| Started | Mar 07 12:22:57 PM PST 24 |
| Finished | Mar 07 12:22:57 PM PST 24 |
| Peak memory | 145444 kb |
| Host | smart-182ae61a-d522-4216-967d-59ef59683109 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997378847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1997378847 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.202345964 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11487230 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:20:09 PM PST 24 |
| Finished | Mar 07 12:20:10 PM PST 24 |
| Peak memory | 145644 kb |
| Host | smart-889d232f-8de9-4a1a-a725-3499b647efc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=202345964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.202345964 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.1460881714 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10842558 ps |
| CPU time | 0.41 seconds |
| Started | Mar 07 12:20:07 PM PST 24 |
| Finished | Mar 07 12:20:07 PM PST 24 |
| Peak memory | 145632 kb |
| Host | smart-15fa5a19-e1be-4943-b433-8404802fbb5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1460881714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1460881714 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.634025309 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10642001 ps |
| CPU time | 0.38 seconds |
| Started | Mar 07 12:28:13 PM PST 24 |
| Finished | Mar 07 12:28:14 PM PST 24 |
| Peak memory | 145356 kb |
| Host | smart-77941cd4-645b-48cc-ba96-8b04213a63bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=634025309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.634025309 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2998361951 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11954206 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:21:00 PM PST 24 |
| Finished | Mar 07 12:21:01 PM PST 24 |
| Peak memory | 145628 kb |
| Host | smart-7d0f53b6-7418-4baa-8b72-3f367c1614f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2998361951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2998361951 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.3227823187 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11990276 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:32:30 PM PST 24 |
| Finished | Mar 07 12:32:30 PM PST 24 |
| Peak memory | 145660 kb |
| Host | smart-fcd62540-ab68-4b44-9a4a-34b8bdf5d3ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227823187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3227823187 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.3885514508 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12065546 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:20:02 PM PST 24 |
| Finished | Mar 07 12:20:02 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-3ff9bf0b-0d95-4293-af03-3e7087cc7401 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885514508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3885514508 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3782190135 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 31670537 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:18:48 PM PST 24 |
| Finished | Mar 07 12:18:49 PM PST 24 |
| Peak memory | 145800 kb |
| Host | smart-df8f619a-a826-45bb-8c25-db3acbb7df30 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3782190135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3782190135 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4159854697 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 32776963 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:18:52 PM PST 24 |
| Finished | Mar 07 12:18:52 PM PST 24 |
| Peak memory | 145772 kb |
| Host | smart-1a0d07ed-6aad-41cd-a17a-aa5225b141f0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4159854697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.4159854697 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1304447125 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 28552415 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:18:33 PM PST 24 |
| Finished | Mar 07 12:18:34 PM PST 24 |
| Peak memory | 145748 kb |
| Host | smart-225e4cb7-2937-4443-8731-869145bac7ed |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1304447125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1304447125 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2849636895 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 30595635 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:18:43 PM PST 24 |
| Finished | Mar 07 12:18:43 PM PST 24 |
| Peak memory | 145772 kb |
| Host | smart-8f44b91e-4ed0-4a33-b1c3-d7955eb1f228 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2849636895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2849636895 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.950206874 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 29913277 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:18:43 PM PST 24 |
| Finished | Mar 07 12:18:44 PM PST 24 |
| Peak memory | 145772 kb |
| Host | smart-90005b47-270d-4b72-9c04-1ca66c843d28 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=950206874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.950206874 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2158957533 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29781718 ps |
| CPU time | 0.42 seconds |
| Started | Mar 07 12:18:33 PM PST 24 |
| Finished | Mar 07 12:18:34 PM PST 24 |
| Peak memory | 145748 kb |
| Host | smart-591a6a9e-fd74-46e4-99f4-3797b70e8c51 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2158957533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2158957533 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2347337049 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 27994118 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:18:48 PM PST 24 |
| Finished | Mar 07 12:18:49 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-0c9b812c-8d45-4fc8-b1cd-f53382c492af |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2347337049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2347337049 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1367439826 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30885547 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:18:52 PM PST 24 |
| Finished | Mar 07 12:18:52 PM PST 24 |
| Peak memory | 145772 kb |
| Host | smart-7ee04c98-6eaf-4798-9fcd-ad2202a22a69 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1367439826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1367439826 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3661563341 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 32229702 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:18:52 PM PST 24 |
| Finished | Mar 07 12:18:52 PM PST 24 |
| Peak memory | 145772 kb |
| Host | smart-fffe2071-d6d7-4392-97a9-c61b7b7b04fb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3661563341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3661563341 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2454655358 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 30715853 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:18:42 PM PST 24 |
| Finished | Mar 07 12:18:43 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-b3879ee3-5e7f-4494-878c-88136b3914ac |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2454655358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2454655358 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3702012840 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29361853 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:18:52 PM PST 24 |
| Finished | Mar 07 12:18:52 PM PST 24 |
| Peak memory | 145736 kb |
| Host | smart-c9fd47ae-787a-4cd6-a262-d4636aef61b9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3702012840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3702012840 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1196034593 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30877790 ps |
| CPU time | 0.38 seconds |
| Started | Mar 07 12:18:52 PM PST 24 |
| Finished | Mar 07 12:18:53 PM PST 24 |
| Peak memory | 145760 kb |
| Host | smart-511019d1-01cb-41b0-809a-9a7ce84b9f0a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1196034593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1196034593 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2159483456 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31034678 ps |
| CPU time | 0.42 seconds |
| Started | Mar 07 12:18:51 PM PST 24 |
| Finished | Mar 07 12:18:52 PM PST 24 |
| Peak memory | 145800 kb |
| Host | smart-5f0baa1d-9dfc-44c5-be65-cb90af5cc2c8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2159483456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2159483456 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1785286136 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 31059554 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:18:43 PM PST 24 |
| Finished | Mar 07 12:18:44 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-75cb660d-a2ba-4cc4-ac41-ac0b8a8ea54f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1785286136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1785286136 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.465845863 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29142637 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:18:42 PM PST 24 |
| Finished | Mar 07 12:18:43 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-5a7496fd-3528-483e-aa17-268ae044f68b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=465845863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.465845863 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2161038416 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 30918610 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:18:43 PM PST 24 |
| Finished | Mar 07 12:18:44 PM PST 24 |
| Peak memory | 145760 kb |
| Host | smart-fd748080-a4f1-4786-b6ee-f98449e351b4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2161038416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2161038416 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.287625446 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8436076 ps |
| CPU time | 0.41 seconds |
| Started | Mar 07 12:21:42 PM PST 24 |
| Finished | Mar 07 12:21:43 PM PST 24 |
| Peak memory | 145036 kb |
| Host | smart-a52c67cb-7f4c-42fd-9d82-38895d0c3b44 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=287625446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.287625446 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3202571116 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9032308 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:22:09 PM PST 24 |
| Finished | Mar 07 12:22:09 PM PST 24 |
| Peak memory | 145008 kb |
| Host | smart-b1a0ba32-b0f7-41e6-9e3b-3bc09c4ff5a4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3202571116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3202571116 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.2498612665 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8545984 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:20:01 PM PST 24 |
| Finished | Mar 07 12:20:01 PM PST 24 |
| Peak memory | 145028 kb |
| Host | smart-3af5d546-7182-46b0-a063-81efe3e31d17 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2498612665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2498612665 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3155453311 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9387985 ps |
| CPU time | 0.38 seconds |
| Started | Mar 07 12:22:05 PM PST 24 |
| Finished | Mar 07 12:22:06 PM PST 24 |
| Peak memory | 144848 kb |
| Host | smart-0047554c-ebf3-440a-912d-93f045c4d00a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3155453311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3155453311 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.3853973256 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9227639 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:19:13 PM PST 24 |
| Peak memory | 144996 kb |
| Host | smart-02c5d3b0-cf5f-45b6-8142-7edfacdc6443 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3853973256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3853973256 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1927091991 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9667622 ps |
| CPU time | 0.38 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:19:13 PM PST 24 |
| Peak memory | 145072 kb |
| Host | smart-517845b8-99f8-4af3-82cd-a0956bfe34e1 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1927091991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1927091991 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.1120773854 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9787048 ps |
| CPU time | 0.38 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:19:13 PM PST 24 |
| Peak memory | 144996 kb |
| Host | smart-a8d12ca6-549a-4695-a950-c5d0031a89f1 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1120773854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1120773854 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.3967626929 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9089276 ps |
| CPU time | 0.38 seconds |
| Started | Mar 07 12:19:13 PM PST 24 |
| Finished | Mar 07 12:19:14 PM PST 24 |
| Peak memory | 144996 kb |
| Host | smart-f8e60842-c93b-465b-aa22-f0a439a2637f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3967626929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3967626929 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.2490255711 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 10203138 ps |
| CPU time | 0.41 seconds |
| Started | Mar 07 12:26:24 PM PST 24 |
| Finished | Mar 07 12:26:26 PM PST 24 |
| Peak memory | 144184 kb |
| Host | smart-ada8a687-4542-4f33-bc9a-51216aea08b1 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2490255711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2490255711 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.8105313 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9929183 ps |
| CPU time | 0.38 seconds |
| Started | Mar 07 12:19:38 PM PST 24 |
| Finished | Mar 07 12:19:38 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-76b89012-677f-4157-b1d2-6bc0e3f265e7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=8105313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.8105313 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.3783344333 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9053342 ps |
| CPU time | 0.41 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:19:13 PM PST 24 |
| Peak memory | 144980 kb |
| Host | smart-d95c1231-4343-49b7-a0e5-fb7fa665b59b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3783344333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3783344333 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3778368266 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9004162 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:21:51 PM PST 24 |
| Finished | Mar 07 12:21:52 PM PST 24 |
| Peak memory | 145044 kb |
| Host | smart-aa303ce7-841b-47e6-a6e5-2e865a59dab6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3778368266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3778368266 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.817331581 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9132870 ps |
| CPU time | 0.41 seconds |
| Started | Mar 07 12:21:27 PM PST 24 |
| Finished | Mar 07 12:21:27 PM PST 24 |
| Peak memory | 144996 kb |
| Host | smart-809505f5-230d-4f5d-9f53-d9ca53492f04 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=817331581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.817331581 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.3268135269 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10827532 ps |
| CPU time | 0.44 seconds |
| Started | Mar 07 12:21:52 PM PST 24 |
| Finished | Mar 07 12:21:53 PM PST 24 |
| Peak memory | 144912 kb |
| Host | smart-293ce3b4-298d-4a6a-a783-afb9bb72ed34 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3268135269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3268135269 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.2366265300 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8419067 ps |
| CPU time | 0.44 seconds |
| Started | Mar 07 12:24:35 PM PST 24 |
| Finished | Mar 07 12:24:35 PM PST 24 |
| Peak memory | 144996 kb |
| Host | smart-f89734b9-a845-413b-90bc-0e5098b14b38 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2366265300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2366265300 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.2576334630 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9113171 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:21:44 PM PST 24 |
| Finished | Mar 07 12:21:45 PM PST 24 |
| Peak memory | 145008 kb |
| Host | smart-16ee5c8c-497e-4825-8add-eb1dae7b9936 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2576334630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2576334630 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.2197705643 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8372388 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:20:01 PM PST 24 |
| Finished | Mar 07 12:20:01 PM PST 24 |
| Peak memory | 144828 kb |
| Host | smart-3f56c496-2a4b-41d6-8daa-7cf711fc45b7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2197705643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2197705643 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.3840048768 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9769201 ps |
| CPU time | 0.43 seconds |
| Started | Mar 07 12:32:20 PM PST 24 |
| Finished | Mar 07 12:32:22 PM PST 24 |
| Peak memory | 144636 kb |
| Host | smart-d83852b0-8a04-4ef3-a006-86830c3f2da3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3840048768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3840048768 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.2985750626 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8552887 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:19:52 PM PST 24 |
| Finished | Mar 07 12:19:52 PM PST 24 |
| Peak memory | 145104 kb |
| Host | smart-848ed3ac-fcdb-47da-8fa7-ce4f9ae79ca2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2985750626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2985750626 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1288830605 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 25883481 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:21:08 PM PST 24 |
| Finished | Mar 07 12:21:09 PM PST 24 |
| Peak memory | 144936 kb |
| Host | smart-f9d98502-9534-4ffb-b3be-23f9e07b1563 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1288830605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1288830605 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1148758695 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27630659 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:19:13 PM PST 24 |
| Finished | Mar 07 12:19:14 PM PST 24 |
| Peak memory | 145160 kb |
| Host | smart-3fa401d5-619c-4675-baad-42b68632582e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1148758695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1148758695 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4232202838 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27982124 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:20:17 PM PST 24 |
| Finished | Mar 07 12:20:18 PM PST 24 |
| Peak memory | 145140 kb |
| Host | smart-b13dd6bf-b2ac-43a5-8420-e91c4868d5fe |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4232202838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.4232202838 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3081381109 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27051184 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:32:28 PM PST 24 |
| Finished | Mar 07 12:32:29 PM PST 24 |
| Peak memory | 145220 kb |
| Host | smart-b07d5812-e053-4e83-9565-c2298942a7b5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3081381109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3081381109 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1052079048 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 29055517 ps |
| CPU time | 0.46 seconds |
| Started | Mar 07 12:20:50 PM PST 24 |
| Finished | Mar 07 12:20:50 PM PST 24 |
| Peak memory | 145184 kb |
| Host | smart-2251a8d7-9cc4-498f-9dbf-85a9bde1bf68 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1052079048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1052079048 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1397762657 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26854508 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:59 PM PST 24 |
| Finished | Mar 07 12:20:59 PM PST 24 |
| Peak memory | 145168 kb |
| Host | smart-790dc7ea-6f24-4286-a426-8d11a78cd0a2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1397762657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1397762657 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.17037492 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26560639 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:27:22 PM PST 24 |
| Finished | Mar 07 12:27:23 PM PST 24 |
| Peak memory | 144840 kb |
| Host | smart-6d815fdd-d908-465e-ac2f-9ce30c69b0ad |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=17037492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.17037492 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.126019621 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 28581289 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:20:49 PM PST 24 |
| Finished | Mar 07 12:20:50 PM PST 24 |
| Peak memory | 145168 kb |
| Host | smart-b04bcb30-7baa-4251-83db-6083a6f6cb73 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=126019621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.126019621 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.269207638 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 29143218 ps |
| CPU time | 0.44 seconds |
| Started | Mar 07 12:20:02 PM PST 24 |
| Finished | Mar 07 12:20:02 PM PST 24 |
| Peak memory | 145188 kb |
| Host | smart-7ecbee4f-aa40-4725-a7d7-da91dab94c9e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=269207638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.269207638 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.542467913 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28533763 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:02 PM PST 24 |
| Finished | Mar 07 12:20:03 PM PST 24 |
| Peak memory | 145188 kb |
| Host | smart-245aaee3-75d2-4999-b693-b4124e2f7d63 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=542467913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.542467913 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.965330785 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 28264978 ps |
| CPU time | 0.49 seconds |
| Started | Mar 07 12:20:01 PM PST 24 |
| Finished | Mar 07 12:20:02 PM PST 24 |
| Peak memory | 145052 kb |
| Host | smart-008d94d8-c9c8-474f-a372-f5210a12f292 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=965330785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.965330785 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.200220929 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27918513 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:21:11 PM PST 24 |
| Finished | Mar 07 12:21:12 PM PST 24 |
| Peak memory | 144948 kb |
| Host | smart-06af541c-1719-4862-9e1e-54b593f7762d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=200220929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.200220929 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1111917441 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27616841 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:21:12 PM PST 24 |
| Finished | Mar 07 12:21:12 PM PST 24 |
| Peak memory | 144952 kb |
| Host | smart-0f65264f-559a-4aa7-9e0b-1d6be7c84abe |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1111917441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1111917441 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4066349968 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 26966223 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:07 PM PST 24 |
| Finished | Mar 07 12:20:07 PM PST 24 |
| Peak memory | 145148 kb |
| Host | smart-697c916a-b542-440f-bee5-5dcb060436c1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4066349968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.4066349968 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3077216037 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26830319 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:19:58 PM PST 24 |
| Finished | Mar 07 12:19:59 PM PST 24 |
| Peak memory | 145148 kb |
| Host | smart-47c0decb-fdd9-4ff3-a76d-68075582a939 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3077216037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3077216037 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1120052574 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 29102454 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:27 PM PST 24 |
| Finished | Mar 07 12:20:27 PM PST 24 |
| Peak memory | 145144 kb |
| Host | smart-7949a46e-87a0-4e0d-8c90-6a2005594214 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1120052574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1120052574 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3957235413 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 25896795 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:13 PM PST 24 |
| Finished | Mar 07 12:20:14 PM PST 24 |
| Peak memory | 145164 kb |
| Host | smart-682938e4-4a12-47bf-af58-8b48dfc707f4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3957235413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3957235413 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3204398105 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27274342 ps |
| CPU time | 0.43 seconds |
| Started | Mar 07 12:20:06 PM PST 24 |
| Finished | Mar 07 12:20:07 PM PST 24 |
| Peak memory | 145140 kb |
| Host | smart-3c4673a8-7f0c-4aa7-8001-2fe68bb1891c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3204398105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3204398105 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3402341489 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 25426692 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:20:59 PM PST 24 |
| Finished | Mar 07 12:20:59 PM PST 24 |
| Peak memory | 145116 kb |
| Host | smart-ddb33d3e-0875-4c55-9be0-64ec28767116 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3402341489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3402341489 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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