Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.53 88.53 100.00 100.00 91.67 91.67 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/2.prim_async_alert.2275966222
91.37 2.84 100.00 0.00 95.83 4.17 100.00 0.00 82.14 3.57 95.83 0.00 74.42 9.30 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3931260258
93.31 1.94 100.00 0.00 95.83 0.00 100.00 0.00 82.14 0.00 95.83 0.00 86.05 11.63 /workspace/coverage/sync_alert/10.prim_sync_alert.3740540
94.50 1.19 100.00 0.00 95.83 0.00 100.00 0.00 89.29 7.14 95.83 0.00 86.05 0.00 /workspace/coverage/default/7.prim_async_alert.713363809
95.19 0.69 100.00 0.00 100.00 4.17 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3486249014

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.4215863734
/workspace/coverage/default/1.prim_async_alert.1988740780
/workspace/coverage/default/10.prim_async_alert.2123933552
/workspace/coverage/default/11.prim_async_alert.1590432755
/workspace/coverage/default/12.prim_async_alert.4251811724
/workspace/coverage/default/13.prim_async_alert.2765693099
/workspace/coverage/default/14.prim_async_alert.3828600509
/workspace/coverage/default/15.prim_async_alert.1865640072
/workspace/coverage/default/16.prim_async_alert.1072248122
/workspace/coverage/default/17.prim_async_alert.462264769
/workspace/coverage/default/18.prim_async_alert.4158907695
/workspace/coverage/default/19.prim_async_alert.1430526129
/workspace/coverage/default/3.prim_async_alert.3916078203
/workspace/coverage/default/4.prim_async_alert.93534316
/workspace/coverage/default/5.prim_async_alert.3578533290
/workspace/coverage/default/6.prim_async_alert.310610348
/workspace/coverage/default/8.prim_async_alert.305283726
/workspace/coverage/default/9.prim_async_alert.2419100878
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3625323608
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2835990895
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3443876146
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3234312128
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1576028057
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.618295763
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1220512683
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1926179282
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1624627821
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3612202801
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1681794649
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.973274155
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1496871312
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2245695434
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3340660957
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2954827469
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2894660810
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3753752236
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.303045131
/workspace/coverage/sync_alert/0.prim_sync_alert.1085284984
/workspace/coverage/sync_alert/1.prim_sync_alert.2434901976
/workspace/coverage/sync_alert/11.prim_sync_alert.2821571131
/workspace/coverage/sync_alert/12.prim_sync_alert.4137805012
/workspace/coverage/sync_alert/13.prim_sync_alert.1875220209
/workspace/coverage/sync_alert/14.prim_sync_alert.3010395118
/workspace/coverage/sync_alert/15.prim_sync_alert.3910444856
/workspace/coverage/sync_alert/16.prim_sync_alert.3665172255
/workspace/coverage/sync_alert/17.prim_sync_alert.1139478870
/workspace/coverage/sync_alert/18.prim_sync_alert.292285296
/workspace/coverage/sync_alert/19.prim_sync_alert.3114764449
/workspace/coverage/sync_alert/2.prim_sync_alert.1738060310
/workspace/coverage/sync_alert/3.prim_sync_alert.869899669
/workspace/coverage/sync_alert/4.prim_sync_alert.3713015755
/workspace/coverage/sync_alert/5.prim_sync_alert.1503046159
/workspace/coverage/sync_alert/6.prim_sync_alert.1336434048
/workspace/coverage/sync_alert/7.prim_sync_alert.753186439
/workspace/coverage/sync_alert/8.prim_sync_alert.383826725
/workspace/coverage/sync_alert/9.prim_sync_alert.997331875
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.383246622
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3021437124
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3115569498
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.335881543
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1655951044
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3747486362
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2084343908
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2112556565
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2905776352
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1610896258
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1623931560
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3099945671
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2290470391
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1824152678
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.638116597
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3044731020
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4277076748
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3678377456
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.620360292



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.prim_async_alert.2123933552 Mar 10 12:19:55 PM PDT 24 Mar 10 12:19:55 PM PDT 24 10753448 ps
T2 /workspace/coverage/default/8.prim_async_alert.305283726 Mar 10 12:23:57 PM PDT 24 Mar 10 12:23:58 PM PDT 24 10779480 ps
T3 /workspace/coverage/default/9.prim_async_alert.2419100878 Mar 10 12:19:43 PM PDT 24 Mar 10 12:19:43 PM PDT 24 11362284 ps
T7 /workspace/coverage/default/12.prim_async_alert.4251811724 Mar 10 12:19:18 PM PDT 24 Mar 10 12:19:19 PM PDT 24 11148272 ps
T11 /workspace/coverage/default/2.prim_async_alert.2275966222 Mar 10 12:18:54 PM PDT 24 Mar 10 12:18:56 PM PDT 24 12232474 ps
T19 /workspace/coverage/default/1.prim_async_alert.1988740780 Mar 10 12:19:07 PM PDT 24 Mar 10 12:19:08 PM PDT 24 10554105 ps
T12 /workspace/coverage/default/16.prim_async_alert.1072248122 Mar 10 12:18:54 PM PDT 24 Mar 10 12:18:55 PM PDT 24 12187330 ps
T8 /workspace/coverage/default/18.prim_async_alert.4158907695 Mar 10 12:17:57 PM PDT 24 Mar 10 12:17:58 PM PDT 24 10657397 ps
T20 /workspace/coverage/default/6.prim_async_alert.310610348 Mar 10 12:18:22 PM PDT 24 Mar 10 12:18:23 PM PDT 24 11359123 ps
T14 /workspace/coverage/default/5.prim_async_alert.3578533290 Mar 10 12:23:57 PM PDT 24 Mar 10 12:23:58 PM PDT 24 10374897 ps
T5 /workspace/coverage/default/14.prim_async_alert.3828600509 Mar 10 12:23:57 PM PDT 24 Mar 10 12:23:58 PM PDT 24 10745703 ps
T6 /workspace/coverage/default/7.prim_async_alert.713363809 Mar 10 12:33:10 PM PDT 24 Mar 10 12:33:11 PM PDT 24 12778079 ps
T21 /workspace/coverage/default/13.prim_async_alert.2765693099 Mar 10 12:19:23 PM PDT 24 Mar 10 12:19:25 PM PDT 24 10827723 ps
T15 /workspace/coverage/default/3.prim_async_alert.3916078203 Mar 10 12:19:55 PM PDT 24 Mar 10 12:19:55 PM PDT 24 11940135 ps
T17 /workspace/coverage/default/11.prim_async_alert.1590432755 Mar 10 12:18:22 PM PDT 24 Mar 10 12:18:23 PM PDT 24 11376888 ps
T18 /workspace/coverage/default/19.prim_async_alert.1430526129 Mar 10 12:18:57 PM PDT 24 Mar 10 12:18:58 PM PDT 24 11343303 ps
T49 /workspace/coverage/default/0.prim_async_alert.4215863734 Mar 10 12:22:53 PM PDT 24 Mar 10 12:22:53 PM PDT 24 11056417 ps
T16 /workspace/coverage/default/15.prim_async_alert.1865640072 Mar 10 12:18:22 PM PDT 24 Mar 10 12:18:23 PM PDT 24 11293160 ps
T50 /workspace/coverage/default/17.prim_async_alert.462264769 Mar 10 12:19:37 PM PDT 24 Mar 10 12:19:38 PM PDT 24 10963579 ps
T22 /workspace/coverage/default/4.prim_async_alert.93534316 Mar 10 12:23:01 PM PDT 24 Mar 10 12:23:02 PM PDT 24 11025299 ps
T23 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3931260258 Mar 10 12:59:48 PM PDT 24 Mar 10 12:59:49 PM PDT 24 30096853 ps
T40 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3340660957 Mar 10 12:59:48 PM PDT 24 Mar 10 12:59:48 PM PDT 24 30510725 ps
T42 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3443876146 Mar 10 12:59:51 PM PDT 24 Mar 10 12:59:51 PM PDT 24 27318901 ps
T43 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1576028057 Mar 10 12:59:53 PM PDT 24 Mar 10 12:59:53 PM PDT 24 29804084 ps
T24 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.973274155 Mar 10 12:59:58 PM PDT 24 Mar 10 12:59:59 PM PDT 24 26719758 ps
T44 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2835990895 Mar 10 12:59:47 PM PDT 24 Mar 10 12:59:48 PM PDT 24 29480534 ps
T45 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2954827469 Mar 10 12:59:48 PM PDT 24 Mar 10 12:59:48 PM PDT 24 30249365 ps
T46 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3625323608 Mar 10 12:59:48 PM PDT 24 Mar 10 12:59:49 PM PDT 24 30780724 ps
T47 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3612202801 Mar 10 12:59:52 PM PDT 24 Mar 10 12:59:52 PM PDT 24 29124787 ps
T48 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1681794649 Mar 10 12:59:57 PM PDT 24 Mar 10 12:59:58 PM PDT 24 30199572 ps
T51 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1926179282 Mar 10 12:59:52 PM PDT 24 Mar 10 12:59:52 PM PDT 24 31283106 ps
T52 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.303045131 Mar 10 12:59:52 PM PDT 24 Mar 10 12:59:52 PM PDT 24 30674429 ps
T53 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.618295763 Mar 10 12:59:52 PM PDT 24 Mar 10 12:59:52 PM PDT 24 29501247 ps
T54 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3753752236 Mar 10 12:59:53 PM PDT 24 Mar 10 12:59:53 PM PDT 24 31359237 ps
T55 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1624627821 Mar 10 12:59:54 PM PDT 24 Mar 10 12:59:55 PM PDT 24 29612962 ps
T41 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2894660810 Mar 10 12:59:47 PM PDT 24 Mar 10 12:59:47 PM PDT 24 30309691 ps
T56 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3234312128 Mar 10 12:59:52 PM PDT 24 Mar 10 12:59:52 PM PDT 24 29049641 ps
T57 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1220512683 Mar 10 12:59:51 PM PDT 24 Mar 10 12:59:52 PM PDT 24 29656649 ps
T58 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2245695434 Mar 10 12:59:46 PM PDT 24 Mar 10 12:59:47 PM PDT 24 30766086 ps
T59 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1496871312 Mar 10 12:59:47 PM PDT 24 Mar 10 12:59:47 PM PDT 24 30515346 ps
T33 /workspace/coverage/sync_alert/16.prim_sync_alert.3665172255 Mar 10 12:20:02 PM PDT 24 Mar 10 12:20:03 PM PDT 24 9964517 ps
T25 /workspace/coverage/sync_alert/11.prim_sync_alert.2821571131 Mar 10 12:19:54 PM PDT 24 Mar 10 12:19:55 PM PDT 24 10175526 ps
T34 /workspace/coverage/sync_alert/15.prim_sync_alert.3910444856 Mar 10 12:24:28 PM PDT 24 Mar 10 12:24:29 PM PDT 24 9542877 ps
T26 /workspace/coverage/sync_alert/10.prim_sync_alert.3740540 Mar 10 12:21:12 PM PDT 24 Mar 10 12:21:12 PM PDT 24 9592069 ps
T35 /workspace/coverage/sync_alert/2.prim_sync_alert.1738060310 Mar 10 12:19:07 PM PDT 24 Mar 10 12:19:08 PM PDT 24 10984771 ps
T36 /workspace/coverage/sync_alert/13.prim_sync_alert.1875220209 Mar 10 12:33:10 PM PDT 24 Mar 10 12:33:11 PM PDT 24 9154995 ps
T37 /workspace/coverage/sync_alert/18.prim_sync_alert.292285296 Mar 10 12:30:17 PM PDT 24 Mar 10 12:30:18 PM PDT 24 8432724 ps
T27 /workspace/coverage/sync_alert/17.prim_sync_alert.1139478870 Mar 10 12:30:22 PM PDT 24 Mar 10 12:30:23 PM PDT 24 7665665 ps
T38 /workspace/coverage/sync_alert/14.prim_sync_alert.3010395118 Mar 10 12:24:45 PM PDT 24 Mar 10 12:24:46 PM PDT 24 9157503 ps
T39 /workspace/coverage/sync_alert/12.prim_sync_alert.4137805012 Mar 10 12:30:23 PM PDT 24 Mar 10 12:30:24 PM PDT 24 9951648 ps
T60 /workspace/coverage/sync_alert/0.prim_sync_alert.1085284984 Mar 10 12:19:40 PM PDT 24 Mar 10 12:19:40 PM PDT 24 9459306 ps
T9 /workspace/coverage/sync_alert/5.prim_sync_alert.1503046159 Mar 10 12:23:57 PM PDT 24 Mar 10 12:23:58 PM PDT 24 8844510 ps
T61 /workspace/coverage/sync_alert/1.prim_sync_alert.2434901976 Mar 10 12:18:52 PM PDT 24 Mar 10 12:18:52 PM PDT 24 9281160 ps
T62 /workspace/coverage/sync_alert/19.prim_sync_alert.3114764449 Mar 10 12:20:41 PM PDT 24 Mar 10 12:20:41 PM PDT 24 8216802 ps
T28 /workspace/coverage/sync_alert/7.prim_sync_alert.753186439 Mar 10 12:18:23 PM PDT 24 Mar 10 12:18:23 PM PDT 24 8517505 ps
T63 /workspace/coverage/sync_alert/3.prim_sync_alert.869899669 Mar 10 12:18:38 PM PDT 24 Mar 10 12:18:39 PM PDT 24 9067504 ps
T64 /workspace/coverage/sync_alert/9.prim_sync_alert.997331875 Mar 10 12:19:04 PM PDT 24 Mar 10 12:19:05 PM PDT 24 8610352 ps
T29 /workspace/coverage/sync_alert/4.prim_sync_alert.3713015755 Mar 10 12:19:55 PM PDT 24 Mar 10 12:19:55 PM PDT 24 9163269 ps
T65 /workspace/coverage/sync_alert/8.prim_sync_alert.383826725 Mar 10 12:18:33 PM PDT 24 Mar 10 12:18:33 PM PDT 24 8933371 ps
T13 /workspace/coverage/sync_alert/6.prim_sync_alert.1336434048 Mar 10 12:19:35 PM PDT 24 Mar 10 12:19:35 PM PDT 24 8938689 ps
T30 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3044731020 Mar 10 12:19:05 PM PDT 24 Mar 10 12:19:06 PM PDT 24 26441718 ps
T31 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.638116597 Mar 10 12:19:39 PM PDT 24 Mar 10 12:19:40 PM PDT 24 25427831 ps
T66 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.620360292 Mar 10 12:33:12 PM PDT 24 Mar 10 12:33:14 PM PDT 24 27633893 ps
T67 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2112556565 Mar 10 12:18:18 PM PDT 24 Mar 10 12:18:19 PM PDT 24 25310266 ps
T68 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1655951044 Mar 10 12:20:02 PM PDT 24 Mar 10 12:20:03 PM PDT 24 28874142 ps
T69 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1623931560 Mar 10 12:20:18 PM PDT 24 Mar 10 12:20:18 PM PDT 24 28608043 ps
T70 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2084343908 Mar 10 12:20:41 PM PDT 24 Mar 10 12:20:41 PM PDT 24 26897927 ps
T71 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3021437124 Mar 10 12:19:55 PM PDT 24 Mar 10 12:19:55 PM PDT 24 25891915 ps
T32 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2905776352 Mar 10 12:20:02 PM PDT 24 Mar 10 12:20:03 PM PDT 24 26070215 ps
T72 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3099945671 Mar 10 12:33:12 PM PDT 24 Mar 10 12:33:14 PM PDT 24 26023285 ps
T73 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1824152678 Mar 10 12:19:48 PM PDT 24 Mar 10 12:19:48 PM PDT 24 25148940 ps
T74 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.335881543 Mar 10 12:18:43 PM PDT 24 Mar 10 12:18:43 PM PDT 24 27516149 ps
T75 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1610896258 Mar 10 12:20:18 PM PDT 24 Mar 10 12:20:18 PM PDT 24 27737296 ps
T76 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3747486362 Mar 10 12:24:12 PM PDT 24 Mar 10 12:24:12 PM PDT 24 27012040 ps
T77 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3115569498 Mar 10 12:20:18 PM PDT 24 Mar 10 12:20:18 PM PDT 24 28666060 ps
T4 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3486249014 Mar 10 12:20:02 PM PDT 24 Mar 10 12:20:03 PM PDT 24 26206702 ps
T78 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.383246622 Mar 10 12:18:56 PM PDT 24 Mar 10 12:18:58 PM PDT 24 27266956 ps
T79 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2290470391 Mar 10 12:19:48 PM PDT 24 Mar 10 12:19:49 PM PDT 24 28918590 ps
T80 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4277076748 Mar 10 12:32:50 PM PDT 24 Mar 10 12:32:50 PM PDT 24 29729491 ps
T10 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3678377456 Mar 10 12:19:39 PM PDT 24 Mar 10 12:19:40 PM PDT 24 27137605 ps

Test location /workspace/coverage/default/2.prim_async_alert.2275966222
Short name T11
Test name
Test status
Simulation time 12232474 ps
CPU time 0.38 seconds
Started Mar 10 12:18:54 PM PDT 24
Finished Mar 10 12:18:56 PM PDT 24
Peak memory 145716 kb
Host smart-552cdc71-965a-463a-8a1e-484a32163311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275966222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2275966222
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3931260258
Short name T23
Test name
Test status
Simulation time 30096853 ps
CPU time 0.38 seconds
Started Mar 10 12:59:48 PM PDT 24
Finished Mar 10 12:59:49 PM PDT 24
Peak memory 145684 kb
Host smart-14740580-7c99-41b1-bed1-1d53f4ea6139
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3931260258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3931260258
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3740540
Short name T26
Test name
Test status
Simulation time 9592069 ps
CPU time 0.39 seconds
Started Mar 10 12:21:12 PM PDT 24
Finished Mar 10 12:21:12 PM PDT 24
Peak memory 145088 kb
Host smart-1003cbef-da35-447f-82f8-33d8755f62b6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3740540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3740540
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.713363809
Short name T6
Test name
Test status
Simulation time 12778079 ps
CPU time 0.38 seconds
Started Mar 10 12:33:10 PM PDT 24
Finished Mar 10 12:33:11 PM PDT 24
Peak memory 145480 kb
Host smart-91471113-972b-4eaa-868c-f4f8266035dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713363809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.713363809
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3486249014
Short name T4
Test name
Test status
Simulation time 26206702 ps
CPU time 0.4 seconds
Started Mar 10 12:20:02 PM PDT 24
Finished Mar 10 12:20:03 PM PDT 24
Peak memory 145328 kb
Host smart-95014acf-814b-4db2-877d-a5ebb3aeadd8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3486249014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3486249014
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.4215863734
Short name T49
Test name
Test status
Simulation time 11056417 ps
CPU time 0.37 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:53 PM PDT 24
Peak memory 145372 kb
Host smart-f5c4b4cd-6015-4da8-b7dc-d6610ac72f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215863734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.4215863734
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1988740780
Short name T19
Test name
Test status
Simulation time 10554105 ps
CPU time 0.43 seconds
Started Mar 10 12:19:07 PM PDT 24
Finished Mar 10 12:19:08 PM PDT 24
Peak memory 145412 kb
Host smart-6ff86638-ae3d-4462-a1ee-159e4f4ac830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988740780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1988740780
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2123933552
Short name T1
Test name
Test status
Simulation time 10753448 ps
CPU time 0.4 seconds
Started Mar 10 12:19:55 PM PDT 24
Finished Mar 10 12:19:55 PM PDT 24
Peak memory 145240 kb
Host smart-e0a5c301-bac3-49f8-901b-56234a5ee55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123933552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2123933552
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1590432755
Short name T17
Test name
Test status
Simulation time 11376888 ps
CPU time 0.41 seconds
Started Mar 10 12:18:22 PM PDT 24
Finished Mar 10 12:18:23 PM PDT 24
Peak memory 144984 kb
Host smart-72a81ea8-8a19-457e-bbc6-7fe3e2ca69ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590432755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1590432755
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.4251811724
Short name T7
Test name
Test status
Simulation time 11148272 ps
CPU time 0.38 seconds
Started Mar 10 12:19:18 PM PDT 24
Finished Mar 10 12:19:19 PM PDT 24
Peak memory 145460 kb
Host smart-2fdf4ed0-5f63-4f71-9dc2-2f4ea2375d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251811724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.4251811724
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2765693099
Short name T21
Test name
Test status
Simulation time 10827723 ps
CPU time 0.43 seconds
Started Mar 10 12:19:23 PM PDT 24
Finished Mar 10 12:19:25 PM PDT 24
Peak memory 145640 kb
Host smart-a213b246-adf4-43c7-8074-862b9f98e63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765693099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2765693099
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3828600509
Short name T5
Test name
Test status
Simulation time 10745703 ps
CPU time 0.39 seconds
Started Mar 10 12:23:57 PM PDT 24
Finished Mar 10 12:23:58 PM PDT 24
Peak memory 143648 kb
Host smart-cb1718e6-47c2-49bf-8b7a-4bd0e28050ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828600509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3828600509
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1865640072
Short name T16
Test name
Test status
Simulation time 11293160 ps
CPU time 0.42 seconds
Started Mar 10 12:18:22 PM PDT 24
Finished Mar 10 12:18:23 PM PDT 24
Peak memory 146404 kb
Host smart-1c7a20a8-32fa-4906-8c5d-dbe0ba8a0b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865640072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1865640072
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1072248122
Short name T12
Test name
Test status
Simulation time 12187330 ps
CPU time 0.41 seconds
Started Mar 10 12:18:54 PM PDT 24
Finished Mar 10 12:18:55 PM PDT 24
Peak memory 145640 kb
Host smart-a583132b-9994-433a-b2a2-47282b649091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072248122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1072248122
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.462264769
Short name T50
Test name
Test status
Simulation time 10963579 ps
CPU time 0.42 seconds
Started Mar 10 12:19:37 PM PDT 24
Finished Mar 10 12:19:38 PM PDT 24
Peak memory 145336 kb
Host smart-872a20a3-5b31-4268-ab90-0f3743f6ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462264769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.462264769
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.4158907695
Short name T8
Test name
Test status
Simulation time 10657397 ps
CPU time 0.42 seconds
Started Mar 10 12:17:57 PM PDT 24
Finished Mar 10 12:17:58 PM PDT 24
Peak memory 145780 kb
Host smart-be15bb45-94c4-488f-9c4f-d7dcf58510a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158907695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.4158907695
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1430526129
Short name T18
Test name
Test status
Simulation time 11343303 ps
CPU time 0.41 seconds
Started Mar 10 12:18:57 PM PDT 24
Finished Mar 10 12:18:58 PM PDT 24
Peak memory 145508 kb
Host smart-78ec583e-81c1-4fef-af2e-88bb83d92aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430526129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1430526129
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3916078203
Short name T15
Test name
Test status
Simulation time 11940135 ps
CPU time 0.42 seconds
Started Mar 10 12:19:55 PM PDT 24
Finished Mar 10 12:19:55 PM PDT 24
Peak memory 145160 kb
Host smart-eac428e1-98c9-4f6b-a0cf-f14dafcb4ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916078203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3916078203
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.93534316
Short name T22
Test name
Test status
Simulation time 11025299 ps
CPU time 0.38 seconds
Started Mar 10 12:23:01 PM PDT 24
Finished Mar 10 12:23:02 PM PDT 24
Peak memory 145400 kb
Host smart-6af7ffa5-9283-488e-b1e1-ea90daccc1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93534316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.93534316
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3578533290
Short name T14
Test name
Test status
Simulation time 10374897 ps
CPU time 0.44 seconds
Started Mar 10 12:23:57 PM PDT 24
Finished Mar 10 12:23:58 PM PDT 24
Peak memory 143600 kb
Host smart-5391f77e-7c52-4a1a-8bf2-54b90aa69d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578533290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3578533290
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.310610348
Short name T20
Test name
Test status
Simulation time 11359123 ps
CPU time 0.38 seconds
Started Mar 10 12:18:22 PM PDT 24
Finished Mar 10 12:18:23 PM PDT 24
Peak memory 145456 kb
Host smart-f8793680-f710-4283-8734-14624a87e353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310610348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.310610348
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.305283726
Short name T2
Test name
Test status
Simulation time 10779480 ps
CPU time 0.41 seconds
Started Mar 10 12:23:57 PM PDT 24
Finished Mar 10 12:23:58 PM PDT 24
Peak memory 144172 kb
Host smart-22e365ed-588b-4fcb-b935-d661178b7e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305283726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.305283726
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2419100878
Short name T3
Test name
Test status
Simulation time 11362284 ps
CPU time 0.39 seconds
Started Mar 10 12:19:43 PM PDT 24
Finished Mar 10 12:19:43 PM PDT 24
Peak memory 145640 kb
Host smart-19dca66d-452b-40b1-8c5c-a167c98b503a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419100878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2419100878
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3625323608
Short name T46
Test name
Test status
Simulation time 30780724 ps
CPU time 0.41 seconds
Started Mar 10 12:59:48 PM PDT 24
Finished Mar 10 12:59:49 PM PDT 24
Peak memory 145732 kb
Host smart-0ebd4476-8e23-48bd-bde1-b0e93fae0400
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3625323608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3625323608
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2835990895
Short name T44
Test name
Test status
Simulation time 29480534 ps
CPU time 0.39 seconds
Started Mar 10 12:59:47 PM PDT 24
Finished Mar 10 12:59:48 PM PDT 24
Peak memory 145672 kb
Host smart-5a8d575a-c5d9-496f-b34b-b99b6acff2e7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2835990895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2835990895
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3443876146
Short name T42
Test name
Test status
Simulation time 27318901 ps
CPU time 0.39 seconds
Started Mar 10 12:59:51 PM PDT 24
Finished Mar 10 12:59:51 PM PDT 24
Peak memory 145668 kb
Host smart-01e7a58a-a0a4-4c81-ace9-6c9b1394017d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3443876146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3443876146
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3234312128
Short name T56
Test name
Test status
Simulation time 29049641 ps
CPU time 0.41 seconds
Started Mar 10 12:59:52 PM PDT 24
Finished Mar 10 12:59:52 PM PDT 24
Peak memory 145736 kb
Host smart-768864ea-7ac3-451f-bf7a-3fcefc8368a8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3234312128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3234312128
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1576028057
Short name T43
Test name
Test status
Simulation time 29804084 ps
CPU time 0.41 seconds
Started Mar 10 12:59:53 PM PDT 24
Finished Mar 10 12:59:53 PM PDT 24
Peak memory 145752 kb
Host smart-2455a7cb-e26c-4709-ab1b-561a31b8c87b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1576028057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1576028057
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.618295763
Short name T53
Test name
Test status
Simulation time 29501247 ps
CPU time 0.44 seconds
Started Mar 10 12:59:52 PM PDT 24
Finished Mar 10 12:59:52 PM PDT 24
Peak memory 145744 kb
Host smart-c6f5ce85-f793-425d-bd5d-2c1e984f5fe6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=618295763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.618295763
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1220512683
Short name T57
Test name
Test status
Simulation time 29656649 ps
CPU time 0.4 seconds
Started Mar 10 12:59:51 PM PDT 24
Finished Mar 10 12:59:52 PM PDT 24
Peak memory 145692 kb
Host smart-dd77bdf8-ee78-4384-9220-e8f8af928dcb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1220512683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1220512683
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1926179282
Short name T51
Test name
Test status
Simulation time 31283106 ps
CPU time 0.39 seconds
Started Mar 10 12:59:52 PM PDT 24
Finished Mar 10 12:59:52 PM PDT 24
Peak memory 145688 kb
Host smart-9349f468-772e-487a-bb8d-c7ad882573fb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1926179282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1926179282
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1624627821
Short name T55
Test name
Test status
Simulation time 29612962 ps
CPU time 0.39 seconds
Started Mar 10 12:59:54 PM PDT 24
Finished Mar 10 12:59:55 PM PDT 24
Peak memory 145796 kb
Host smart-e23823d6-5d88-4408-88e7-1e7568141ecb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1624627821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1624627821
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3612202801
Short name T47
Test name
Test status
Simulation time 29124787 ps
CPU time 0.4 seconds
Started Mar 10 12:59:52 PM PDT 24
Finished Mar 10 12:59:52 PM PDT 24
Peak memory 145708 kb
Host smart-53879df2-3258-4b89-8e4c-b1e01dc7f5c8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3612202801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3612202801
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1681794649
Short name T48
Test name
Test status
Simulation time 30199572 ps
CPU time 0.4 seconds
Started Mar 10 12:59:57 PM PDT 24
Finished Mar 10 12:59:58 PM PDT 24
Peak memory 145672 kb
Host smart-50f5676c-227d-4483-b021-9783d7f6bce9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1681794649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1681794649
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.973274155
Short name T24
Test name
Test status
Simulation time 26719758 ps
CPU time 0.4 seconds
Started Mar 10 12:59:58 PM PDT 24
Finished Mar 10 12:59:59 PM PDT 24
Peak memory 145644 kb
Host smart-5264d695-f0d7-42de-9d15-04a630e3aa6b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=973274155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.973274155
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1496871312
Short name T59
Test name
Test status
Simulation time 30515346 ps
CPU time 0.38 seconds
Started Mar 10 12:59:47 PM PDT 24
Finished Mar 10 12:59:47 PM PDT 24
Peak memory 145680 kb
Host smart-035a6508-0f8a-4f6a-9b20-d9e9d3e97fcd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1496871312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1496871312
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2245695434
Short name T58
Test name
Test status
Simulation time 30766086 ps
CPU time 0.39 seconds
Started Mar 10 12:59:46 PM PDT 24
Finished Mar 10 12:59:47 PM PDT 24
Peak memory 145680 kb
Host smart-643aa466-fb1e-4a71-8bd0-0f6845c185e2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2245695434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2245695434
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3340660957
Short name T40
Test name
Test status
Simulation time 30510725 ps
CPU time 0.4 seconds
Started Mar 10 12:59:48 PM PDT 24
Finished Mar 10 12:59:48 PM PDT 24
Peak memory 145584 kb
Host smart-d462b198-1d65-4c64-b2eb-6d1a98138815
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3340660957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3340660957
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2954827469
Short name T45
Test name
Test status
Simulation time 30249365 ps
CPU time 0.39 seconds
Started Mar 10 12:59:48 PM PDT 24
Finished Mar 10 12:59:48 PM PDT 24
Peak memory 145684 kb
Host smart-06046810-d364-4beb-9aef-3a6e0112ec1e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2954827469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2954827469
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2894660810
Short name T41
Test name
Test status
Simulation time 30309691 ps
CPU time 0.4 seconds
Started Mar 10 12:59:47 PM PDT 24
Finished Mar 10 12:59:47 PM PDT 24
Peak memory 145712 kb
Host smart-894e3ed7-112b-454b-abb5-81aae17a1ecb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2894660810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2894660810
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3753752236
Short name T54
Test name
Test status
Simulation time 31359237 ps
CPU time 0.41 seconds
Started Mar 10 12:59:53 PM PDT 24
Finished Mar 10 12:59:53 PM PDT 24
Peak memory 145728 kb
Host smart-356b898c-9159-4a42-83df-b2fb792e392e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3753752236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3753752236
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.303045131
Short name T52
Test name
Test status
Simulation time 30674429 ps
CPU time 0.39 seconds
Started Mar 10 12:59:52 PM PDT 24
Finished Mar 10 12:59:52 PM PDT 24
Peak memory 145776 kb
Host smart-d87e7261-f9e8-4c43-84e7-0ab0d27083bc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=303045131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.303045131
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1085284984
Short name T60
Test name
Test status
Simulation time 9459306 ps
CPU time 0.39 seconds
Started Mar 10 12:19:40 PM PDT 24
Finished Mar 10 12:19:40 PM PDT 24
Peak memory 145076 kb
Host smart-d535f2c6-108a-4e70-bdd3-092f4d4680c3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1085284984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1085284984
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2434901976
Short name T61
Test name
Test status
Simulation time 9281160 ps
CPU time 0.38 seconds
Started Mar 10 12:18:52 PM PDT 24
Finished Mar 10 12:18:52 PM PDT 24
Peak memory 145184 kb
Host smart-3a8a050d-2674-4a5e-b207-e4ba617b685f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2434901976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2434901976
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2821571131
Short name T25
Test name
Test status
Simulation time 10175526 ps
CPU time 0.39 seconds
Started Mar 10 12:19:54 PM PDT 24
Finished Mar 10 12:19:55 PM PDT 24
Peak memory 144908 kb
Host smart-640b5973-725e-478a-82e6-f3af76b0d420
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2821571131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2821571131
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.4137805012
Short name T39
Test name
Test status
Simulation time 9951648 ps
CPU time 0.37 seconds
Started Mar 10 12:30:23 PM PDT 24
Finished Mar 10 12:30:24 PM PDT 24
Peak memory 144916 kb
Host smart-f2d0748b-8bf7-4bfe-8572-45716eba0c7e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4137805012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.4137805012
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1875220209
Short name T36
Test name
Test status
Simulation time 9154995 ps
CPU time 0.37 seconds
Started Mar 10 12:33:10 PM PDT 24
Finished Mar 10 12:33:11 PM PDT 24
Peak memory 144900 kb
Host smart-0e4bb674-75d6-4582-9b35-f0a1b86001cf
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1875220209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1875220209
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3010395118
Short name T38
Test name
Test status
Simulation time 9157503 ps
CPU time 0.42 seconds
Started Mar 10 12:24:45 PM PDT 24
Finished Mar 10 12:24:46 PM PDT 24
Peak memory 144884 kb
Host smart-5d788dbb-d832-4361-b7f5-7d3a58570fa8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3010395118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3010395118
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3910444856
Short name T34
Test name
Test status
Simulation time 9542877 ps
CPU time 0.43 seconds
Started Mar 10 12:24:28 PM PDT 24
Finished Mar 10 12:24:29 PM PDT 24
Peak memory 143796 kb
Host smart-59152b50-6222-4a5b-8515-9acab70cebce
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3910444856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3910444856
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3665172255
Short name T33
Test name
Test status
Simulation time 9964517 ps
CPU time 0.48 seconds
Started Mar 10 12:20:02 PM PDT 24
Finished Mar 10 12:20:03 PM PDT 24
Peak memory 143668 kb
Host smart-dd6608e3-3730-4bfd-9772-ba37a5e16b81
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3665172255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3665172255
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1139478870
Short name T27
Test name
Test status
Simulation time 7665665 ps
CPU time 0.36 seconds
Started Mar 10 12:30:22 PM PDT 24
Finished Mar 10 12:30:23 PM PDT 24
Peak memory 145004 kb
Host smart-1ef7a3eb-c2d0-4a7f-b1c5-8b21485b5075
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1139478870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1139478870
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.292285296
Short name T37
Test name
Test status
Simulation time 8432724 ps
CPU time 0.37 seconds
Started Mar 10 12:30:17 PM PDT 24
Finished Mar 10 12:30:18 PM PDT 24
Peak memory 144936 kb
Host smart-fefacf45-2257-4606-9e4d-1de25f753ba0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=292285296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.292285296
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3114764449
Short name T62
Test name
Test status
Simulation time 8216802 ps
CPU time 0.39 seconds
Started Mar 10 12:20:41 PM PDT 24
Finished Mar 10 12:20:41 PM PDT 24
Peak memory 144924 kb
Host smart-e0e2a62c-dd15-4503-a02d-d96290d831b8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3114764449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3114764449
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1738060310
Short name T35
Test name
Test status
Simulation time 10984771 ps
CPU time 0.39 seconds
Started Mar 10 12:19:07 PM PDT 24
Finished Mar 10 12:19:08 PM PDT 24
Peak memory 144880 kb
Host smart-ff258fff-6ad4-45d6-a965-92077f4b7c08
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1738060310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1738060310
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.869899669
Short name T63
Test name
Test status
Simulation time 9067504 ps
CPU time 0.38 seconds
Started Mar 10 12:18:38 PM PDT 24
Finished Mar 10 12:18:39 PM PDT 24
Peak memory 144868 kb
Host smart-1fc7a249-cf3a-4d4d-83d2-1361342d1295
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=869899669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.869899669
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3713015755
Short name T29
Test name
Test status
Simulation time 9163269 ps
CPU time 0.4 seconds
Started Mar 10 12:19:55 PM PDT 24
Finished Mar 10 12:19:55 PM PDT 24
Peak memory 146136 kb
Host smart-52020afc-8e9f-4223-8b8f-62a33c5cf49a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3713015755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3713015755
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1503046159
Short name T9
Test name
Test status
Simulation time 8844510 ps
CPU time 0.43 seconds
Started Mar 10 12:23:57 PM PDT 24
Finished Mar 10 12:23:58 PM PDT 24
Peak memory 144624 kb
Host smart-fcbb614c-211c-4cd1-9524-23f41829d6f9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1503046159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1503046159
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1336434048
Short name T13
Test name
Test status
Simulation time 8938689 ps
CPU time 0.46 seconds
Started Mar 10 12:19:35 PM PDT 24
Finished Mar 10 12:19:35 PM PDT 24
Peak memory 144892 kb
Host smart-026ba459-b5b3-4f46-aa24-6b6401fc42d3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1336434048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1336434048
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.753186439
Short name T28
Test name
Test status
Simulation time 8517505 ps
CPU time 0.4 seconds
Started Mar 10 12:18:23 PM PDT 24
Finished Mar 10 12:18:23 PM PDT 24
Peak memory 144880 kb
Host smart-1d58b5a8-46c0-4a38-ab62-e5b1487123b1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=753186439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.753186439
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.383826725
Short name T65
Test name
Test status
Simulation time 8933371 ps
CPU time 0.39 seconds
Started Mar 10 12:18:33 PM PDT 24
Finished Mar 10 12:18:33 PM PDT 24
Peak memory 144880 kb
Host smart-1a50a8a2-bf89-462e-94dd-30c20e6db81e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=383826725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.383826725
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.997331875
Short name T64
Test name
Test status
Simulation time 8610352 ps
CPU time 0.4 seconds
Started Mar 10 12:19:04 PM PDT 24
Finished Mar 10 12:19:05 PM PDT 24
Peak memory 144912 kb
Host smart-3cac58f9-e13d-4b8d-83b7-78d6bc6f1d07
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=997331875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.997331875
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.383246622
Short name T78
Test name
Test status
Simulation time 27266956 ps
CPU time 0.4 seconds
Started Mar 10 12:18:56 PM PDT 24
Finished Mar 10 12:18:58 PM PDT 24
Peak memory 145056 kb
Host smart-818d0f27-ebcd-4342-a06f-5bbc723565ac
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=383246622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.383246622
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3021437124
Short name T71
Test name
Test status
Simulation time 25891915 ps
CPU time 0.4 seconds
Started Mar 10 12:19:55 PM PDT 24
Finished Mar 10 12:19:55 PM PDT 24
Peak memory 144912 kb
Host smart-0e2ca265-8fd6-44ea-ad09-98273d625b50
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3021437124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3021437124
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3115569498
Short name T77
Test name
Test status
Simulation time 28666060 ps
CPU time 0.4 seconds
Started Mar 10 12:20:18 PM PDT 24
Finished Mar 10 12:20:18 PM PDT 24
Peak memory 145056 kb
Host smart-6df2802d-7879-4309-90ce-559a02f81244
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3115569498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3115569498
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.335881543
Short name T74
Test name
Test status
Simulation time 27516149 ps
CPU time 0.4 seconds
Started Mar 10 12:18:43 PM PDT 24
Finished Mar 10 12:18:43 PM PDT 24
Peak memory 145048 kb
Host smart-016b6d58-2c8b-4b12-acfa-ef6f7ddb35fb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=335881543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.335881543
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1655951044
Short name T68
Test name
Test status
Simulation time 28874142 ps
CPU time 0.51 seconds
Started Mar 10 12:20:02 PM PDT 24
Finished Mar 10 12:20:03 PM PDT 24
Peak memory 143976 kb
Host smart-1af27315-a459-4487-b222-cfd49e2cc432
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1655951044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1655951044
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3747486362
Short name T76
Test name
Test status
Simulation time 27012040 ps
CPU time 0.42 seconds
Started Mar 10 12:24:12 PM PDT 24
Finished Mar 10 12:24:12 PM PDT 24
Peak memory 143800 kb
Host smart-37d925a0-493e-4d58-985e-76cde0fa9a9a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3747486362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3747486362
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2084343908
Short name T70
Test name
Test status
Simulation time 26897927 ps
CPU time 0.45 seconds
Started Mar 10 12:20:41 PM PDT 24
Finished Mar 10 12:20:41 PM PDT 24
Peak memory 145056 kb
Host smart-315ab46f-3dde-4f99-a122-da1c998a25ca
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2084343908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2084343908
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2112556565
Short name T67
Test name
Test status
Simulation time 25310266 ps
CPU time 0.42 seconds
Started Mar 10 12:18:18 PM PDT 24
Finished Mar 10 12:18:19 PM PDT 24
Peak memory 145012 kb
Host smart-2af3746c-3864-4a04-8737-0915761e1e23
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2112556565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2112556565
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2905776352
Short name T32
Test name
Test status
Simulation time 26070215 ps
CPU time 0.44 seconds
Started Mar 10 12:20:02 PM PDT 24
Finished Mar 10 12:20:03 PM PDT 24
Peak memory 143944 kb
Host smart-e220ce29-6421-4b4d-ad33-d7b91a10f856
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2905776352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2905776352
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1610896258
Short name T75
Test name
Test status
Simulation time 27737296 ps
CPU time 0.39 seconds
Started Mar 10 12:20:18 PM PDT 24
Finished Mar 10 12:20:18 PM PDT 24
Peak memory 145056 kb
Host smart-37023b34-d8de-4dbe-90b3-bb0851d7f8b3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1610896258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1610896258
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1623931560
Short name T69
Test name
Test status
Simulation time 28608043 ps
CPU time 0.39 seconds
Started Mar 10 12:20:18 PM PDT 24
Finished Mar 10 12:20:18 PM PDT 24
Peak memory 145056 kb
Host smart-97986543-7119-4370-aa03-4b50742cbf01
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1623931560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1623931560
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3099945671
Short name T72
Test name
Test status
Simulation time 26023285 ps
CPU time 0.38 seconds
Started Mar 10 12:33:12 PM PDT 24
Finished Mar 10 12:33:14 PM PDT 24
Peak memory 145044 kb
Host smart-48e547ae-94a8-4f08-a2d6-358e7519d9c2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3099945671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3099945671
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2290470391
Short name T79
Test name
Test status
Simulation time 28918590 ps
CPU time 0.42 seconds
Started Mar 10 12:19:48 PM PDT 24
Finished Mar 10 12:19:49 PM PDT 24
Peak memory 145056 kb
Host smart-f69cb6ef-f979-4317-9c53-cab47433a2da
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2290470391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2290470391
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1824152678
Short name T73
Test name
Test status
Simulation time 25148940 ps
CPU time 0.4 seconds
Started Mar 10 12:19:48 PM PDT 24
Finished Mar 10 12:19:48 PM PDT 24
Peak memory 145064 kb
Host smart-11fe1b49-1b61-484a-8761-ad47dd239592
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1824152678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1824152678
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.638116597
Short name T31
Test name
Test status
Simulation time 25427831 ps
CPU time 0.41 seconds
Started Mar 10 12:19:39 PM PDT 24
Finished Mar 10 12:19:40 PM PDT 24
Peak memory 145056 kb
Host smart-64b712ab-df92-4b21-914b-64865ca1fb27
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=638116597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.638116597
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3044731020
Short name T30
Test name
Test status
Simulation time 26441718 ps
CPU time 0.39 seconds
Started Mar 10 12:19:05 PM PDT 24
Finished Mar 10 12:19:06 PM PDT 24
Peak memory 145336 kb
Host smart-57c4ac54-f86b-4280-b792-90750bd48d63
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3044731020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3044731020
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4277076748
Short name T80
Test name
Test status
Simulation time 29729491 ps
CPU time 0.38 seconds
Started Mar 10 12:32:50 PM PDT 24
Finished Mar 10 12:32:50 PM PDT 24
Peak memory 145084 kb
Host smart-fc39d1ff-a362-4a03-a26c-32f31e0d2952
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4277076748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.4277076748
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3678377456
Short name T10
Test name
Test status
Simulation time 27137605 ps
CPU time 0.44 seconds
Started Mar 10 12:19:39 PM PDT 24
Finished Mar 10 12:19:40 PM PDT 24
Peak memory 145056 kb
Host smart-f50bef8e-1e44-47cb-8129-5f0cfa85c7c3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3678377456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3678377456
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.620360292
Short name T66
Test name
Test status
Simulation time 27633893 ps
CPU time 0.39 seconds
Started Mar 10 12:33:12 PM PDT 24
Finished Mar 10 12:33:14 PM PDT 24
Peak memory 145048 kb
Host smart-c348974e-a1b6-4c1f-a9a5-e10dde499d4b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=620360292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.620360292
Directory /workspace/9.prim_sync_fatal_alert/latest
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