Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 96.43 96.43 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/15.prim_async_alert.3132088389
91.80 3.13 100.00 0.00 93.75 0.00 96.43 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/13.prim_sync_alert.2053035440
94.15 2.35 100.00 0.00 93.75 0.00 100.00 3.57 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.269355298
94.50 0.35 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/1.prim_async_alert.4014287375
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2865683517
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.484694127

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3362609450
/workspace/coverage/default/10.prim_async_alert.2902846411
/workspace/coverage/default/11.prim_async_alert.3051761174
/workspace/coverage/default/12.prim_async_alert.324181301
/workspace/coverage/default/13.prim_async_alert.2533546919
/workspace/coverage/default/14.prim_async_alert.175384552
/workspace/coverage/default/16.prim_async_alert.272128084
/workspace/coverage/default/17.prim_async_alert.2793963697
/workspace/coverage/default/18.prim_async_alert.2914302913
/workspace/coverage/default/19.prim_async_alert.2360203827
/workspace/coverage/default/2.prim_async_alert.1182710566
/workspace/coverage/default/3.prim_async_alert.1475442116
/workspace/coverage/default/4.prim_async_alert.2251100860
/workspace/coverage/default/5.prim_async_alert.4062930716
/workspace/coverage/default/6.prim_async_alert.3283521228
/workspace/coverage/default/7.prim_async_alert.2981140132
/workspace/coverage/default/8.prim_async_alert.4256999345
/workspace/coverage/default/9.prim_async_alert.3442335271
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1643206560
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3765692173
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.913172788
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.78255928
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2504953666
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.110932182
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1348470157
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3262931417
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2608198497
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2857736097
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.554094459
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4293268223
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3650135451
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1627130910
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.119754368
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3968145280
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1020236128
/workspace/coverage/sync_alert/0.prim_sync_alert.290913308
/workspace/coverage/sync_alert/1.prim_sync_alert.1218320976
/workspace/coverage/sync_alert/10.prim_sync_alert.3639095235
/workspace/coverage/sync_alert/11.prim_sync_alert.3529757426
/workspace/coverage/sync_alert/12.prim_sync_alert.2133628180
/workspace/coverage/sync_alert/14.prim_sync_alert.2546347304
/workspace/coverage/sync_alert/15.prim_sync_alert.3722493134
/workspace/coverage/sync_alert/16.prim_sync_alert.2123342645
/workspace/coverage/sync_alert/17.prim_sync_alert.1444748801
/workspace/coverage/sync_alert/18.prim_sync_alert.967809164
/workspace/coverage/sync_alert/19.prim_sync_alert.4041331210
/workspace/coverage/sync_alert/2.prim_sync_alert.3814450255
/workspace/coverage/sync_alert/3.prim_sync_alert.3072425986
/workspace/coverage/sync_alert/4.prim_sync_alert.3013345025
/workspace/coverage/sync_alert/5.prim_sync_alert.482882136
/workspace/coverage/sync_alert/6.prim_sync_alert.2694550505
/workspace/coverage/sync_alert/7.prim_sync_alert.2890603452
/workspace/coverage/sync_alert/8.prim_sync_alert.473126075
/workspace/coverage/sync_alert/9.prim_sync_alert.2177327897
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1442365707
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1990207405
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2382249458
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2129883939
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1750885719
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4024588238
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2793835433
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1190250133
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.576877053
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3798422590
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2965194574
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.302762758
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2794855308
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.476207678
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.485174883
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1335515132
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3040572806
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3013745807
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3509759709



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/7.prim_async_alert.2981140132 Mar 12 12:32:04 PM PDT 24 Mar 12 12:32:04 PM PDT 24 11087635 ps
T2 /workspace/coverage/default/12.prim_async_alert.324181301 Mar 12 12:31:59 PM PDT 24 Mar 12 12:31:59 PM PDT 24 11819565 ps
T3 /workspace/coverage/default/9.prim_async_alert.3442335271 Mar 12 12:32:03 PM PDT 24 Mar 12 12:32:03 PM PDT 24 10912709 ps
T13 /workspace/coverage/default/4.prim_async_alert.2251100860 Mar 12 12:32:04 PM PDT 24 Mar 12 12:32:04 PM PDT 24 11475019 ps
T19 /workspace/coverage/default/10.prim_async_alert.2902846411 Mar 12 12:32:04 PM PDT 24 Mar 12 12:32:04 PM PDT 24 11172245 ps
T7 /workspace/coverage/default/6.prim_async_alert.3283521228 Mar 12 12:32:08 PM PDT 24 Mar 12 12:32:08 PM PDT 24 10831606 ps
T9 /workspace/coverage/default/15.prim_async_alert.3132088389 Mar 12 12:32:07 PM PDT 24 Mar 12 12:32:07 PM PDT 24 10957410 ps
T23 /workspace/coverage/default/18.prim_async_alert.2914302913 Mar 12 12:32:03 PM PDT 24 Mar 12 12:32:03 PM PDT 24 11134752 ps
T8 /workspace/coverage/default/14.prim_async_alert.175384552 Mar 12 12:32:01 PM PDT 24 Mar 12 12:32:01 PM PDT 24 11627426 ps
T24 /workspace/coverage/default/8.prim_async_alert.4256999345 Mar 12 12:32:04 PM PDT 24 Mar 12 12:32:04 PM PDT 24 10821112 ps
T25 /workspace/coverage/default/13.prim_async_alert.2533546919 Mar 12 12:32:04 PM PDT 24 Mar 12 12:32:05 PM PDT 24 10499516 ps
T14 /workspace/coverage/default/0.prim_async_alert.3362609450 Mar 12 12:32:05 PM PDT 24 Mar 12 12:32:05 PM PDT 24 11630671 ps
T26 /workspace/coverage/default/3.prim_async_alert.1475442116 Mar 12 12:32:02 PM PDT 24 Mar 12 12:32:03 PM PDT 24 10488406 ps
T27 /workspace/coverage/default/11.prim_async_alert.3051761174 Mar 12 12:32:02 PM PDT 24 Mar 12 12:32:02 PM PDT 24 11413531 ps
T10 /workspace/coverage/default/19.prim_async_alert.2360203827 Mar 12 12:32:05 PM PDT 24 Mar 12 12:32:05 PM PDT 24 11585227 ps
T50 /workspace/coverage/default/1.prim_async_alert.4014287375 Mar 12 12:32:05 PM PDT 24 Mar 12 12:32:06 PM PDT 24 10619008 ps
T15 /workspace/coverage/default/16.prim_async_alert.272128084 Mar 12 12:32:03 PM PDT 24 Mar 12 12:32:03 PM PDT 24 11837461 ps
T51 /workspace/coverage/default/2.prim_async_alert.1182710566 Mar 12 12:32:07 PM PDT 24 Mar 12 12:32:07 PM PDT 24 11355116 ps
T52 /workspace/coverage/default/17.prim_async_alert.2793963697 Mar 12 12:32:04 PM PDT 24 Mar 12 12:32:04 PM PDT 24 10835134 ps
T20 /workspace/coverage/default/5.prim_async_alert.4062930716 Mar 12 12:32:08 PM PDT 24 Mar 12 12:32:09 PM PDT 24 11599336 ps
T43 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2608198497 Mar 12 12:32:18 PM PDT 24 Mar 12 12:32:19 PM PDT 24 29877544 ps
T44 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3765692173 Mar 12 12:32:11 PM PDT 24 Mar 12 12:32:12 PM PDT 24 30549398 ps
T16 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.269355298 Mar 12 12:32:19 PM PDT 24 Mar 12 12:32:20 PM PDT 24 29849610 ps
T45 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.110932182 Mar 12 12:32:17 PM PDT 24 Mar 12 12:32:17 PM PDT 24 31413930 ps
T21 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.78255928 Mar 12 12:32:15 PM PDT 24 Mar 12 12:32:15 PM PDT 24 32645514 ps
T46 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2504953666 Mar 12 12:32:07 PM PDT 24 Mar 12 12:32:07 PM PDT 24 29866876 ps
T47 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3968145280 Mar 12 12:32:18 PM PDT 24 Mar 12 12:32:18 PM PDT 24 32036876 ps
T48 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1020236128 Mar 12 12:32:11 PM PDT 24 Mar 12 12:32:12 PM PDT 24 29473387 ps
T22 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2857736097 Mar 12 12:32:17 PM PDT 24 Mar 12 12:32:17 PM PDT 24 30121966 ps
T49 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1627130910 Mar 12 12:32:14 PM PDT 24 Mar 12 12:32:15 PM PDT 24 29489925 ps
T17 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3262931417 Mar 12 12:32:18 PM PDT 24 Mar 12 12:32:19 PM PDT 24 29974605 ps
T53 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.913172788 Mar 12 12:32:13 PM PDT 24 Mar 12 12:32:14 PM PDT 24 31427233 ps
T54 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.119754368 Mar 12 12:32:17 PM PDT 24 Mar 12 12:32:17 PM PDT 24 30044150 ps
T4 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2865683517 Mar 12 12:32:11 PM PDT 24 Mar 12 12:32:12 PM PDT 24 29906830 ps
T55 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.554094459 Mar 12 12:32:15 PM PDT 24 Mar 12 12:32:15 PM PDT 24 30221728 ps
T18 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1643206560 Mar 12 12:32:04 PM PDT 24 Mar 12 12:32:04 PM PDT 24 29885737 ps
T56 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4293268223 Mar 12 12:32:12 PM PDT 24 Mar 12 12:32:13 PM PDT 24 29428979 ps
T57 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3650135451 Mar 12 12:32:12 PM PDT 24 Mar 12 12:32:12 PM PDT 24 29389855 ps
T58 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1348470157 Mar 12 12:32:15 PM PDT 24 Mar 12 12:32:16 PM PDT 24 29321726 ps
T28 /workspace/coverage/sync_alert/3.prim_sync_alert.3072425986 Mar 12 12:32:51 PM PDT 24 Mar 12 12:32:51 PM PDT 24 7956491 ps
T38 /workspace/coverage/sync_alert/0.prim_sync_alert.290913308 Mar 12 12:32:47 PM PDT 24 Mar 12 12:32:48 PM PDT 24 8700190 ps
T29 /workspace/coverage/sync_alert/13.prim_sync_alert.2053035440 Mar 12 12:32:45 PM PDT 24 Mar 12 12:32:45 PM PDT 24 10712666 ps
T39 /workspace/coverage/sync_alert/6.prim_sync_alert.2694550505 Mar 12 12:32:47 PM PDT 24 Mar 12 12:32:48 PM PDT 24 8812720 ps
T40 /workspace/coverage/sync_alert/18.prim_sync_alert.967809164 Mar 12 12:32:45 PM PDT 24 Mar 12 12:32:46 PM PDT 24 10068723 ps
T41 /workspace/coverage/sync_alert/2.prim_sync_alert.3814450255 Mar 12 12:32:48 PM PDT 24 Mar 12 12:32:49 PM PDT 24 8831651 ps
T42 /workspace/coverage/sync_alert/9.prim_sync_alert.2177327897 Mar 12 12:32:52 PM PDT 24 Mar 12 12:32:52 PM PDT 24 9043907 ps
T30 /workspace/coverage/sync_alert/19.prim_sync_alert.4041331210 Mar 12 12:32:45 PM PDT 24 Mar 12 12:32:46 PM PDT 24 8880558 ps
T31 /workspace/coverage/sync_alert/10.prim_sync_alert.3639095235 Mar 12 12:32:48 PM PDT 24 Mar 12 12:32:49 PM PDT 24 9202232 ps
T32 /workspace/coverage/sync_alert/15.prim_sync_alert.3722493134 Mar 12 12:32:49 PM PDT 24 Mar 12 12:32:50 PM PDT 24 10278428 ps
T59 /workspace/coverage/sync_alert/4.prim_sync_alert.3013345025 Mar 12 12:32:49 PM PDT 24 Mar 12 12:32:50 PM PDT 24 9459652 ps
T33 /workspace/coverage/sync_alert/7.prim_sync_alert.2890603452 Mar 12 12:32:48 PM PDT 24 Mar 12 12:32:49 PM PDT 24 8312251 ps
T60 /workspace/coverage/sync_alert/1.prim_sync_alert.1218320976 Mar 12 12:32:48 PM PDT 24 Mar 12 12:32:48 PM PDT 24 9945137 ps
T61 /workspace/coverage/sync_alert/17.prim_sync_alert.1444748801 Mar 12 12:32:46 PM PDT 24 Mar 12 12:32:47 PM PDT 24 9584553 ps
T34 /workspace/coverage/sync_alert/5.prim_sync_alert.482882136 Mar 12 12:32:49 PM PDT 24 Mar 12 12:32:49 PM PDT 24 10416543 ps
T35 /workspace/coverage/sync_alert/8.prim_sync_alert.473126075 Mar 12 12:32:48 PM PDT 24 Mar 12 12:32:49 PM PDT 24 8935511 ps
T62 /workspace/coverage/sync_alert/11.prim_sync_alert.3529757426 Mar 12 12:32:49 PM PDT 24 Mar 12 12:32:50 PM PDT 24 9487995 ps
T63 /workspace/coverage/sync_alert/14.prim_sync_alert.2546347304 Mar 12 12:32:49 PM PDT 24 Mar 12 12:32:49 PM PDT 24 8953528 ps
T36 /workspace/coverage/sync_alert/16.prim_sync_alert.2123342645 Mar 12 12:32:47 PM PDT 24 Mar 12 12:32:48 PM PDT 24 8532048 ps
T64 /workspace/coverage/sync_alert/12.prim_sync_alert.2133628180 Mar 12 12:32:46 PM PDT 24 Mar 12 12:32:47 PM PDT 24 9267356 ps
T37 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2129883939 Mar 12 12:28:23 PM PDT 24 Mar 12 12:28:24 PM PDT 24 28841698 ps
T65 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.485174883 Mar 12 12:28:26 PM PDT 24 Mar 12 12:28:27 PM PDT 24 28912065 ps
T5 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1190250133 Mar 12 12:28:28 PM PDT 24 Mar 12 12:28:28 PM PDT 24 25611150 ps
T66 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2382249458 Mar 12 12:28:24 PM PDT 24 Mar 12 12:28:25 PM PDT 24 25741221 ps
T67 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1442365707 Mar 12 12:28:25 PM PDT 24 Mar 12 12:28:26 PM PDT 24 26886339 ps
T68 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.476207678 Mar 12 12:28:29 PM PDT 24 Mar 12 12:28:30 PM PDT 24 28339452 ps
T69 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.576877053 Mar 12 12:28:24 PM PDT 24 Mar 12 12:28:24 PM PDT 24 25951423 ps
T70 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2794855308 Mar 12 12:28:24 PM PDT 24 Mar 12 12:28:24 PM PDT 24 27266374 ps
T11 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3013745807 Mar 12 12:28:26 PM PDT 24 Mar 12 12:28:26 PM PDT 24 27065347 ps
T12 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.484694127 Mar 12 12:28:31 PM PDT 24 Mar 12 12:28:31 PM PDT 24 28082431 ps
T71 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1335515132 Mar 12 12:28:23 PM PDT 24 Mar 12 12:28:24 PM PDT 24 27509226 ps
T6 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.302762758 Mar 12 12:28:28 PM PDT 24 Mar 12 12:28:28 PM PDT 24 27156674 ps
T72 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2793835433 Mar 12 12:28:25 PM PDT 24 Mar 12 12:28:25 PM PDT 24 27818563 ps
T73 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3798422590 Mar 12 12:28:24 PM PDT 24 Mar 12 12:28:24 PM PDT 24 30054913 ps
T74 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4024588238 Mar 12 12:28:27 PM PDT 24 Mar 12 12:28:27 PM PDT 24 27824430 ps
T75 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2965194574 Mar 12 12:28:26 PM PDT 24 Mar 12 12:28:26 PM PDT 24 29645664 ps
T76 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3040572806 Mar 12 12:28:26 PM PDT 24 Mar 12 12:28:27 PM PDT 24 28096339 ps
T77 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1750885719 Mar 12 12:28:27 PM PDT 24 Mar 12 12:28:28 PM PDT 24 29430529 ps
T78 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1990207405 Mar 12 12:28:26 PM PDT 24 Mar 12 12:28:27 PM PDT 24 26704476 ps
T79 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3509759709 Mar 12 12:28:24 PM PDT 24 Mar 12 12:28:24 PM PDT 24 26461932 ps

Test location /workspace/coverage/default/15.prim_async_alert.3132088389
Short name T9
Test name
Test status
Simulation time 10957410 ps
CPU time 0.37 seconds
Started Mar 12 12:32:07 PM PDT 24
Finished Mar 12 12:32:07 PM PDT 24
Peak memory 145628 kb
Host smart-0d640ed4-58d4-41c5-8851-e715ca0a119f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132088389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3132088389
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2053035440
Short name T29
Test name
Test status
Simulation time 10712666 ps
CPU time 0.36 seconds
Started Mar 12 12:32:45 PM PDT 24
Finished Mar 12 12:32:45 PM PDT 24
Peak memory 145064 kb
Host smart-5c3fb8a0-6453-4294-9a25-579ed6861b92
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2053035440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2053035440
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.269355298
Short name T16
Test name
Test status
Simulation time 29849610 ps
CPU time 0.38 seconds
Started Mar 12 12:32:19 PM PDT 24
Finished Mar 12 12:32:20 PM PDT 24
Peak memory 145612 kb
Host smart-d8817132-40fb-43bd-967f-93d81a28e121
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=269355298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.269355298
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.4014287375
Short name T50
Test name
Test status
Simulation time 10619008 ps
CPU time 0.36 seconds
Started Mar 12 12:32:05 PM PDT 24
Finished Mar 12 12:32:06 PM PDT 24
Peak memory 145516 kb
Host smart-b82a38c8-34cf-46aa-9a91-5a4bb0451d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014287375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.4014287375
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2865683517
Short name T4
Test name
Test status
Simulation time 29906830 ps
CPU time 0.42 seconds
Started Mar 12 12:32:11 PM PDT 24
Finished Mar 12 12:32:12 PM PDT 24
Peak memory 145640 kb
Host smart-35f404af-96ea-4111-8cfc-ded2f6f2c859
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2865683517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2865683517
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.484694127
Short name T12
Test name
Test status
Simulation time 28082431 ps
CPU time 0.4 seconds
Started Mar 12 12:28:31 PM PDT 24
Finished Mar 12 12:28:31 PM PDT 24
Peak memory 145284 kb
Host smart-ea35c41b-5a36-4f3b-96d3-4163d71934be
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=484694127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.484694127
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3362609450
Short name T14
Test name
Test status
Simulation time 11630671 ps
CPU time 0.37 seconds
Started Mar 12 12:32:05 PM PDT 24
Finished Mar 12 12:32:05 PM PDT 24
Peak memory 145436 kb
Host smart-fe940579-8230-44ac-a6de-5282dd6d125d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362609450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3362609450
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2902846411
Short name T19
Test name
Test status
Simulation time 11172245 ps
CPU time 0.38 seconds
Started Mar 12 12:32:04 PM PDT 24
Finished Mar 12 12:32:04 PM PDT 24
Peak memory 145712 kb
Host smart-94dd4754-cd84-41fe-ab56-b8dae27741b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902846411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2902846411
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3051761174
Short name T27
Test name
Test status
Simulation time 11413531 ps
CPU time 0.39 seconds
Started Mar 12 12:32:02 PM PDT 24
Finished Mar 12 12:32:02 PM PDT 24
Peak memory 145596 kb
Host smart-66ad1a4b-563d-4191-8bca-88cc822d5b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051761174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3051761174
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.324181301
Short name T2
Test name
Test status
Simulation time 11819565 ps
CPU time 0.38 seconds
Started Mar 12 12:31:59 PM PDT 24
Finished Mar 12 12:31:59 PM PDT 24
Peak memory 145584 kb
Host smart-35990f36-324c-493c-8423-5566a974774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324181301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.324181301
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2533546919
Short name T25
Test name
Test status
Simulation time 10499516 ps
CPU time 0.42 seconds
Started Mar 12 12:32:04 PM PDT 24
Finished Mar 12 12:32:05 PM PDT 24
Peak memory 145728 kb
Host smart-6fb6cf92-7b60-48d1-855f-9518fef6aed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533546919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2533546919
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.175384552
Short name T8
Test name
Test status
Simulation time 11627426 ps
CPU time 0.37 seconds
Started Mar 12 12:32:01 PM PDT 24
Finished Mar 12 12:32:01 PM PDT 24
Peak memory 145608 kb
Host smart-bd604170-3353-406f-b0f5-546358899a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175384552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.175384552
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.272128084
Short name T15
Test name
Test status
Simulation time 11837461 ps
CPU time 0.39 seconds
Started Mar 12 12:32:03 PM PDT 24
Finished Mar 12 12:32:03 PM PDT 24
Peak memory 145608 kb
Host smart-8eb61a38-1a80-4d3b-b2c1-b89cc6f626e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272128084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.272128084
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2793963697
Short name T52
Test name
Test status
Simulation time 10835134 ps
CPU time 0.38 seconds
Started Mar 12 12:32:04 PM PDT 24
Finished Mar 12 12:32:04 PM PDT 24
Peak memory 145576 kb
Host smart-2d33c2fa-45de-4b2b-b05d-227268e86417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793963697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2793963697
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2914302913
Short name T23
Test name
Test status
Simulation time 11134752 ps
CPU time 0.38 seconds
Started Mar 12 12:32:03 PM PDT 24
Finished Mar 12 12:32:03 PM PDT 24
Peak memory 145812 kb
Host smart-4ac33820-a6af-4dea-a6d1-4109420bbd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914302913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2914302913
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2360203827
Short name T10
Test name
Test status
Simulation time 11585227 ps
CPU time 0.38 seconds
Started Mar 12 12:32:05 PM PDT 24
Finished Mar 12 12:32:05 PM PDT 24
Peak memory 145592 kb
Host smart-dcd8db0f-12a8-4549-9d45-2a6f964079f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360203827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2360203827
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.1182710566
Short name T51
Test name
Test status
Simulation time 11355116 ps
CPU time 0.37 seconds
Started Mar 12 12:32:07 PM PDT 24
Finished Mar 12 12:32:07 PM PDT 24
Peak memory 145456 kb
Host smart-37deb628-2585-4a17-b8ee-6ee0621ab621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182710566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1182710566
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1475442116
Short name T26
Test name
Test status
Simulation time 10488406 ps
CPU time 0.42 seconds
Started Mar 12 12:32:02 PM PDT 24
Finished Mar 12 12:32:03 PM PDT 24
Peak memory 145628 kb
Host smart-8f3c883c-4e27-4caf-8015-24fe9d897f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475442116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1475442116
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2251100860
Short name T13
Test name
Test status
Simulation time 11475019 ps
CPU time 0.38 seconds
Started Mar 12 12:32:04 PM PDT 24
Finished Mar 12 12:32:04 PM PDT 24
Peak memory 145712 kb
Host smart-ecea6340-5a2d-4e87-82c5-3971fea97a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251100860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2251100860
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.4062930716
Short name T20
Test name
Test status
Simulation time 11599336 ps
CPU time 0.37 seconds
Started Mar 12 12:32:08 PM PDT 24
Finished Mar 12 12:32:09 PM PDT 24
Peak memory 145516 kb
Host smart-08c9c4b4-866d-4233-8e9a-6d3f7d964070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062930716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.4062930716
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3283521228
Short name T7
Test name
Test status
Simulation time 10831606 ps
CPU time 0.38 seconds
Started Mar 12 12:32:08 PM PDT 24
Finished Mar 12 12:32:08 PM PDT 24
Peak memory 145596 kb
Host smart-0ecd3510-111c-47b2-a9aa-584ed4afc7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283521228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3283521228
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2981140132
Short name T1
Test name
Test status
Simulation time 11087635 ps
CPU time 0.38 seconds
Started Mar 12 12:32:04 PM PDT 24
Finished Mar 12 12:32:04 PM PDT 24
Peak memory 145488 kb
Host smart-52485cfa-9ae0-4996-a0b5-beba50c56c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981140132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2981140132
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.4256999345
Short name T24
Test name
Test status
Simulation time 10821112 ps
CPU time 0.38 seconds
Started Mar 12 12:32:04 PM PDT 24
Finished Mar 12 12:32:04 PM PDT 24
Peak memory 145724 kb
Host smart-849f8047-bc90-483a-aafc-4dbf3c464b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256999345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.4256999345
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3442335271
Short name T3
Test name
Test status
Simulation time 10912709 ps
CPU time 0.39 seconds
Started Mar 12 12:32:03 PM PDT 24
Finished Mar 12 12:32:03 PM PDT 24
Peak memory 145608 kb
Host smart-b059399e-e918-4cae-b372-3101c7fb0398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442335271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3442335271
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1643206560
Short name T18
Test name
Test status
Simulation time 29885737 ps
CPU time 0.39 seconds
Started Mar 12 12:32:04 PM PDT 24
Finished Mar 12 12:32:04 PM PDT 24
Peak memory 145528 kb
Host smart-d004e1d2-adc8-4dba-9cae-bc60f35e104f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1643206560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1643206560
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3765692173
Short name T44
Test name
Test status
Simulation time 30549398 ps
CPU time 0.45 seconds
Started Mar 12 12:32:11 PM PDT 24
Finished Mar 12 12:32:12 PM PDT 24
Peak memory 145636 kb
Host smart-f5b42748-fb3f-4f5f-8239-a40b86253724
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3765692173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3765692173
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.913172788
Short name T53
Test name
Test status
Simulation time 31427233 ps
CPU time 0.4 seconds
Started Mar 12 12:32:13 PM PDT 24
Finished Mar 12 12:32:14 PM PDT 24
Peak memory 145568 kb
Host smart-0bad0ed7-66ba-42c1-93ec-ad00259e0c8a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=913172788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.913172788
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.78255928
Short name T21
Test name
Test status
Simulation time 32645514 ps
CPU time 0.4 seconds
Started Mar 12 12:32:15 PM PDT 24
Finished Mar 12 12:32:15 PM PDT 24
Peak memory 145620 kb
Host smart-85a644a7-83e6-492f-b608-0731476b3caa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=78255928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.78255928
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2504953666
Short name T46
Test name
Test status
Simulation time 29866876 ps
CPU time 0.4 seconds
Started Mar 12 12:32:07 PM PDT 24
Finished Mar 12 12:32:07 PM PDT 24
Peak memory 145648 kb
Host smart-a3e97d2c-53ea-436b-bfc6-be50a8bc5f51
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2504953666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2504953666
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.110932182
Short name T45
Test name
Test status
Simulation time 31413930 ps
CPU time 0.4 seconds
Started Mar 12 12:32:17 PM PDT 24
Finished Mar 12 12:32:17 PM PDT 24
Peak memory 145588 kb
Host smart-fa37e019-0b28-4463-9896-e349d75a903f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=110932182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.110932182
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1348470157
Short name T58
Test name
Test status
Simulation time 29321726 ps
CPU time 0.38 seconds
Started Mar 12 12:32:15 PM PDT 24
Finished Mar 12 12:32:16 PM PDT 24
Peak memory 145476 kb
Host smart-955ad003-6b94-42ab-8e10-2640f3bf140a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1348470157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1348470157
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3262931417
Short name T17
Test name
Test status
Simulation time 29974605 ps
CPU time 0.41 seconds
Started Mar 12 12:32:18 PM PDT 24
Finished Mar 12 12:32:19 PM PDT 24
Peak memory 145684 kb
Host smart-d8733bbf-8102-46cd-b7ee-7c3bbacd1eb1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3262931417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3262931417
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2608198497
Short name T43
Test name
Test status
Simulation time 29877544 ps
CPU time 0.41 seconds
Started Mar 12 12:32:18 PM PDT 24
Finished Mar 12 12:32:19 PM PDT 24
Peak memory 145600 kb
Host smart-3b177712-0d1a-4989-9266-b8ced7908b80
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2608198497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2608198497
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2857736097
Short name T22
Test name
Test status
Simulation time 30121966 ps
CPU time 0.39 seconds
Started Mar 12 12:32:17 PM PDT 24
Finished Mar 12 12:32:17 PM PDT 24
Peak memory 145636 kb
Host smart-5089f189-41e0-458d-99b2-d6e774d949d6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2857736097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2857736097
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.554094459
Short name T55
Test name
Test status
Simulation time 30221728 ps
CPU time 0.39 seconds
Started Mar 12 12:32:15 PM PDT 24
Finished Mar 12 12:32:15 PM PDT 24
Peak memory 145576 kb
Host smart-6a4dc4fd-4bb2-4ec6-a519-787deb0f8989
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=554094459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.554094459
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4293268223
Short name T56
Test name
Test status
Simulation time 29428979 ps
CPU time 0.43 seconds
Started Mar 12 12:32:12 PM PDT 24
Finished Mar 12 12:32:13 PM PDT 24
Peak memory 145628 kb
Host smart-7fd05ead-244a-4a3c-9ddc-5d61699fe3c8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4293268223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4293268223
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3650135451
Short name T57
Test name
Test status
Simulation time 29389855 ps
CPU time 0.38 seconds
Started Mar 12 12:32:12 PM PDT 24
Finished Mar 12 12:32:12 PM PDT 24
Peak memory 145616 kb
Host smart-3d7d1f66-7091-4dae-9fc7-de61dd244980
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3650135451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3650135451
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1627130910
Short name T49
Test name
Test status
Simulation time 29489925 ps
CPU time 0.38 seconds
Started Mar 12 12:32:14 PM PDT 24
Finished Mar 12 12:32:15 PM PDT 24
Peak memory 145620 kb
Host smart-f5e8ba06-b613-4ec8-aa30-37b3c8379d42
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1627130910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1627130910
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.119754368
Short name T54
Test name
Test status
Simulation time 30044150 ps
CPU time 0.4 seconds
Started Mar 12 12:32:17 PM PDT 24
Finished Mar 12 12:32:17 PM PDT 24
Peak memory 145688 kb
Host smart-ac56c7a7-4c16-4297-9f25-3fe1b9953aad
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=119754368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.119754368
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3968145280
Short name T47
Test name
Test status
Simulation time 32036876 ps
CPU time 0.38 seconds
Started Mar 12 12:32:18 PM PDT 24
Finished Mar 12 12:32:18 PM PDT 24
Peak memory 145620 kb
Host smart-78ad41d8-fc56-43c1-aa00-fac5923c04ce
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3968145280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3968145280
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1020236128
Short name T48
Test name
Test status
Simulation time 29473387 ps
CPU time 0.44 seconds
Started Mar 12 12:32:11 PM PDT 24
Finished Mar 12 12:32:12 PM PDT 24
Peak memory 145616 kb
Host smart-b905a355-471a-4905-ae5d-03cbae5fa620
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1020236128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1020236128
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.290913308
Short name T38
Test name
Test status
Simulation time 8700190 ps
CPU time 0.38 seconds
Started Mar 12 12:32:47 PM PDT 24
Finished Mar 12 12:32:48 PM PDT 24
Peak memory 145036 kb
Host smart-564c0eb9-97ab-4fc0-bdd3-3c7cd86b8bf4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=290913308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.290913308
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1218320976
Short name T60
Test name
Test status
Simulation time 9945137 ps
CPU time 0.38 seconds
Started Mar 12 12:32:48 PM PDT 24
Finished Mar 12 12:32:48 PM PDT 24
Peak memory 145056 kb
Host smart-e0e2080c-eb35-4446-bb67-e5827e0ef0f6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1218320976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1218320976
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3639095235
Short name T31
Test name
Test status
Simulation time 9202232 ps
CPU time 0.37 seconds
Started Mar 12 12:32:48 PM PDT 24
Finished Mar 12 12:32:49 PM PDT 24
Peak memory 145048 kb
Host smart-3dbeadb7-88a3-4cee-b6ce-2f48bd420fd9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3639095235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3639095235
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3529757426
Short name T62
Test name
Test status
Simulation time 9487995 ps
CPU time 0.38 seconds
Started Mar 12 12:32:49 PM PDT 24
Finished Mar 12 12:32:50 PM PDT 24
Peak memory 145004 kb
Host smart-8ee562d8-1037-4239-8085-4a29e4399665
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3529757426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3529757426
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2133628180
Short name T64
Test name
Test status
Simulation time 9267356 ps
CPU time 0.38 seconds
Started Mar 12 12:32:46 PM PDT 24
Finished Mar 12 12:32:47 PM PDT 24
Peak memory 145000 kb
Host smart-5e61c5dd-4b6b-4393-a6a2-db81abdb2d23
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2133628180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2133628180
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2546347304
Short name T63
Test name
Test status
Simulation time 8953528 ps
CPU time 0.37 seconds
Started Mar 12 12:32:49 PM PDT 24
Finished Mar 12 12:32:49 PM PDT 24
Peak memory 145064 kb
Host smart-d3ab7ce8-61b6-4183-9af2-031766dad40c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2546347304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2546347304
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3722493134
Short name T32
Test name
Test status
Simulation time 10278428 ps
CPU time 0.36 seconds
Started Mar 12 12:32:49 PM PDT 24
Finished Mar 12 12:32:50 PM PDT 24
Peak memory 145004 kb
Host smart-46e62b42-8684-4606-946f-d72b626bfdf8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3722493134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3722493134
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2123342645
Short name T36
Test name
Test status
Simulation time 8532048 ps
CPU time 0.38 seconds
Started Mar 12 12:32:47 PM PDT 24
Finished Mar 12 12:32:48 PM PDT 24
Peak memory 145040 kb
Host smart-875ed0ec-2f60-4aa4-a160-20353221bdde
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2123342645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2123342645
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1444748801
Short name T61
Test name
Test status
Simulation time 9584553 ps
CPU time 0.37 seconds
Started Mar 12 12:32:46 PM PDT 24
Finished Mar 12 12:32:47 PM PDT 24
Peak memory 145036 kb
Host smart-d3db85d9-603b-419f-a026-60a06f9fa44a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1444748801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1444748801
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.967809164
Short name T40
Test name
Test status
Simulation time 10068723 ps
CPU time 0.37 seconds
Started Mar 12 12:32:45 PM PDT 24
Finished Mar 12 12:32:46 PM PDT 24
Peak memory 145100 kb
Host smart-f828efa4-f338-4747-bdff-644dc387cb19
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=967809164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.967809164
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.4041331210
Short name T30
Test name
Test status
Simulation time 8880558 ps
CPU time 0.37 seconds
Started Mar 12 12:32:45 PM PDT 24
Finished Mar 12 12:32:46 PM PDT 24
Peak memory 145008 kb
Host smart-b70684b2-0dcb-4510-ab28-c758831edd37
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4041331210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.4041331210
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3814450255
Short name T41
Test name
Test status
Simulation time 8831651 ps
CPU time 0.37 seconds
Started Mar 12 12:32:48 PM PDT 24
Finished Mar 12 12:32:49 PM PDT 24
Peak memory 145064 kb
Host smart-052e9ebf-e373-4d3a-9438-507f2a5bd030
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3814450255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3814450255
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3072425986
Short name T28
Test name
Test status
Simulation time 7956491 ps
CPU time 0.38 seconds
Started Mar 12 12:32:51 PM PDT 24
Finished Mar 12 12:32:51 PM PDT 24
Peak memory 145148 kb
Host smart-f3e3073f-0e87-4da6-bf06-d01b074538b3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3072425986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3072425986
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3013345025
Short name T59
Test name
Test status
Simulation time 9459652 ps
CPU time 0.38 seconds
Started Mar 12 12:32:49 PM PDT 24
Finished Mar 12 12:32:50 PM PDT 24
Peak memory 145032 kb
Host smart-0ff4a9d9-fdd1-43a5-bf4d-a809860a417c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3013345025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3013345025
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.482882136
Short name T34
Test name
Test status
Simulation time 10416543 ps
CPU time 0.38 seconds
Started Mar 12 12:32:49 PM PDT 24
Finished Mar 12 12:32:49 PM PDT 24
Peak memory 145036 kb
Host smart-6ca33bb2-e0a9-482f-b5f9-57b3221e976b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=482882136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.482882136
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2694550505
Short name T39
Test name
Test status
Simulation time 8812720 ps
CPU time 0.38 seconds
Started Mar 12 12:32:47 PM PDT 24
Finished Mar 12 12:32:48 PM PDT 24
Peak memory 144992 kb
Host smart-aec8bfc3-2b58-41ef-9c97-db727d4e5bbd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2694550505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2694550505
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2890603452
Short name T33
Test name
Test status
Simulation time 8312251 ps
CPU time 0.37 seconds
Started Mar 12 12:32:48 PM PDT 24
Finished Mar 12 12:32:49 PM PDT 24
Peak memory 145064 kb
Host smart-ff64f2e0-5bed-4194-b0a7-80a31499435a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2890603452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2890603452
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.473126075
Short name T35
Test name
Test status
Simulation time 8935511 ps
CPU time 0.37 seconds
Started Mar 12 12:32:48 PM PDT 24
Finished Mar 12 12:32:49 PM PDT 24
Peak memory 145188 kb
Host smart-8db734f3-8b45-402f-9cdd-f6314864f5fc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=473126075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.473126075
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2177327897
Short name T42
Test name
Test status
Simulation time 9043907 ps
CPU time 0.38 seconds
Started Mar 12 12:32:52 PM PDT 24
Finished Mar 12 12:32:52 PM PDT 24
Peak memory 145028 kb
Host smart-de355296-7a40-4305-9173-bf902928e83c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2177327897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2177327897
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1442365707
Short name T67
Test name
Test status
Simulation time 26886339 ps
CPU time 0.39 seconds
Started Mar 12 12:28:25 PM PDT 24
Finished Mar 12 12:28:26 PM PDT 24
Peak memory 145296 kb
Host smart-fc826e6c-bc6b-4d0d-8f12-832ca38405e2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1442365707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1442365707
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1990207405
Short name T78
Test name
Test status
Simulation time 26704476 ps
CPU time 0.39 seconds
Started Mar 12 12:28:26 PM PDT 24
Finished Mar 12 12:28:27 PM PDT 24
Peak memory 145292 kb
Host smart-9eeacc03-f3d7-4dcd-a256-526610d2dcfa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1990207405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1990207405
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2382249458
Short name T66
Test name
Test status
Simulation time 25741221 ps
CPU time 0.4 seconds
Started Mar 12 12:28:24 PM PDT 24
Finished Mar 12 12:28:25 PM PDT 24
Peak memory 145328 kb
Host smart-fcbe3395-4b13-419a-8633-0e255d2e013b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2382249458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2382249458
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2129883939
Short name T37
Test name
Test status
Simulation time 28841698 ps
CPU time 0.43 seconds
Started Mar 12 12:28:23 PM PDT 24
Finished Mar 12 12:28:24 PM PDT 24
Peak memory 145240 kb
Host smart-bbb82ff2-365f-48c4-9507-0bc6023687de
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2129883939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2129883939
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1750885719
Short name T77
Test name
Test status
Simulation time 29430529 ps
CPU time 0.38 seconds
Started Mar 12 12:28:27 PM PDT 24
Finished Mar 12 12:28:28 PM PDT 24
Peak memory 145220 kb
Host smart-ee8c59af-fd77-493c-96da-38be2caeacc7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1750885719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1750885719
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4024588238
Short name T74
Test name
Test status
Simulation time 27824430 ps
CPU time 0.39 seconds
Started Mar 12 12:28:27 PM PDT 24
Finished Mar 12 12:28:27 PM PDT 24
Peak memory 145280 kb
Host smart-31ff8ab9-78fb-404a-81ac-134e09d393eb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4024588238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.4024588238
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2793835433
Short name T72
Test name
Test status
Simulation time 27818563 ps
CPU time 0.41 seconds
Started Mar 12 12:28:25 PM PDT 24
Finished Mar 12 12:28:25 PM PDT 24
Peak memory 145328 kb
Host smart-ac89446e-7c76-48d6-ad39-71857837cb9d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2793835433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2793835433
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1190250133
Short name T5
Test name
Test status
Simulation time 25611150 ps
CPU time 0.39 seconds
Started Mar 12 12:28:28 PM PDT 24
Finished Mar 12 12:28:28 PM PDT 24
Peak memory 145300 kb
Host smart-7b693013-b183-4b39-93ed-2f43a0de5e66
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1190250133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1190250133
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.576877053
Short name T69
Test name
Test status
Simulation time 25951423 ps
CPU time 0.4 seconds
Started Mar 12 12:28:24 PM PDT 24
Finished Mar 12 12:28:24 PM PDT 24
Peak memory 145232 kb
Host smart-379cc3eb-0bc9-4f49-b410-c5beed692cf6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=576877053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.576877053
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3798422590
Short name T73
Test name
Test status
Simulation time 30054913 ps
CPU time 0.43 seconds
Started Mar 12 12:28:24 PM PDT 24
Finished Mar 12 12:28:24 PM PDT 24
Peak memory 145300 kb
Host smart-9de6105b-a179-4466-8ea8-aac58daa00cb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3798422590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3798422590
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2965194574
Short name T75
Test name
Test status
Simulation time 29645664 ps
CPU time 0.39 seconds
Started Mar 12 12:28:26 PM PDT 24
Finished Mar 12 12:28:26 PM PDT 24
Peak memory 145276 kb
Host smart-609f69b6-bcde-4fc4-9b27-4beaaf656c02
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2965194574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2965194574
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.302762758
Short name T6
Test name
Test status
Simulation time 27156674 ps
CPU time 0.38 seconds
Started Mar 12 12:28:28 PM PDT 24
Finished Mar 12 12:28:28 PM PDT 24
Peak memory 145172 kb
Host smart-817fecda-c721-4f38-a926-c002d0461ec2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=302762758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.302762758
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2794855308
Short name T70
Test name
Test status
Simulation time 27266374 ps
CPU time 0.4 seconds
Started Mar 12 12:28:24 PM PDT 24
Finished Mar 12 12:28:24 PM PDT 24
Peak memory 145220 kb
Host smart-226313cf-d4ae-4819-915c-0c1d94b86301
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2794855308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2794855308
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.476207678
Short name T68
Test name
Test status
Simulation time 28339452 ps
CPU time 0.39 seconds
Started Mar 12 12:28:29 PM PDT 24
Finished Mar 12 12:28:30 PM PDT 24
Peak memory 145248 kb
Host smart-567ca020-bf74-44fe-9e1e-520b2a8dfd17
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=476207678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.476207678
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.485174883
Short name T65
Test name
Test status
Simulation time 28912065 ps
CPU time 0.41 seconds
Started Mar 12 12:28:26 PM PDT 24
Finished Mar 12 12:28:27 PM PDT 24
Peak memory 145160 kb
Host smart-731fa702-354c-4657-8201-1ed1499c1850
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=485174883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.485174883
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1335515132
Short name T71
Test name
Test status
Simulation time 27509226 ps
CPU time 0.39 seconds
Started Mar 12 12:28:23 PM PDT 24
Finished Mar 12 12:28:24 PM PDT 24
Peak memory 145212 kb
Host smart-6df94deb-5952-4431-a770-6fee0fdb4a06
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1335515132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1335515132
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3040572806
Short name T76
Test name
Test status
Simulation time 28096339 ps
CPU time 0.4 seconds
Started Mar 12 12:28:26 PM PDT 24
Finished Mar 12 12:28:27 PM PDT 24
Peak memory 145108 kb
Host smart-114f8ebe-3d49-440c-89cc-b206d4555d59
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3040572806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3040572806
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3013745807
Short name T11
Test name
Test status
Simulation time 27065347 ps
CPU time 0.39 seconds
Started Mar 12 12:28:26 PM PDT 24
Finished Mar 12 12:28:26 PM PDT 24
Peak memory 145272 kb
Host smart-23fcba70-6a52-4f8b-9446-3d7e8a937870
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3013745807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3013745807
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3509759709
Short name T79
Test name
Test status
Simulation time 26461932 ps
CPU time 0.39 seconds
Started Mar 12 12:28:24 PM PDT 24
Finished Mar 12 12:28:24 PM PDT 24
Peak memory 145108 kb
Host smart-9cca2557-a0d3-4161-9095-b495a16c30e6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3509759709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3509759709
Directory /workspace/9.prim_sync_fatal_alert/latest
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