Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.04 88.04 100.00 100.00 95.83 95.83 96.43 96.43 75.00 75.00 95.83 95.83 65.12 65.12 /workspace/coverage/default/17.prim_async_alert.4260094020
91.16 3.13 100.00 0.00 95.83 0.00 96.43 0.00 82.14 7.14 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/10.prim_sync_alert.1301795555
93.52 2.35 100.00 0.00 95.83 0.00 100.00 3.57 85.71 3.57 95.83 0.00 83.72 6.98 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.413367315
94.21 0.69 100.00 0.00 100.00 4.17 100.00 0.00 85.71 0.00 95.83 0.00 83.72 0.00 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1050178048
94.81 0.60 100.00 0.00 100.00 0.00 100.00 0.00 89.29 3.57 95.83 0.00 83.72 0.00 /workspace/coverage/default/12.prim_async_alert.808189904
95.19 0.39 100.00 0.00 100.00 0.00 100.00 0.00 89.29 0.00 95.83 0.00 86.05 2.33 /workspace/coverage/default/0.prim_async_alert.3039764319

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.2415184668
/workspace/coverage/default/10.prim_async_alert.2516135077
/workspace/coverage/default/11.prim_async_alert.1591789727
/workspace/coverage/default/13.prim_async_alert.2309745161
/workspace/coverage/default/14.prim_async_alert.1385243003
/workspace/coverage/default/15.prim_async_alert.1543243952
/workspace/coverage/default/16.prim_async_alert.606118516
/workspace/coverage/default/18.prim_async_alert.2863358363
/workspace/coverage/default/19.prim_async_alert.781956935
/workspace/coverage/default/2.prim_async_alert.3583036125
/workspace/coverage/default/3.prim_async_alert.23903259
/workspace/coverage/default/4.prim_async_alert.499493051
/workspace/coverage/default/5.prim_async_alert.44121324
/workspace/coverage/default/6.prim_async_alert.770706695
/workspace/coverage/default/7.prim_async_alert.1248377212
/workspace/coverage/default/8.prim_async_alert.2897657789
/workspace/coverage/default/9.prim_async_alert.3946062500
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1879338155
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3230902910
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3894176070
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.936636340
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.155202187
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.707146265
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3100479204
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1177152537
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3335263591
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3100332385
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1381134146
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1005950457
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1958819701
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1502765848
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.295054553
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3872926973
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2170712036
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3866507890
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3700396550
/workspace/coverage/sync_alert/0.prim_sync_alert.3395682256
/workspace/coverage/sync_alert/1.prim_sync_alert.3747874619
/workspace/coverage/sync_alert/11.prim_sync_alert.3721897889
/workspace/coverage/sync_alert/12.prim_sync_alert.920017189
/workspace/coverage/sync_alert/13.prim_sync_alert.3080569754
/workspace/coverage/sync_alert/14.prim_sync_alert.4051087396
/workspace/coverage/sync_alert/15.prim_sync_alert.1732376310
/workspace/coverage/sync_alert/16.prim_sync_alert.3133020890
/workspace/coverage/sync_alert/17.prim_sync_alert.2869748835
/workspace/coverage/sync_alert/18.prim_sync_alert.2924328424
/workspace/coverage/sync_alert/19.prim_sync_alert.591910944
/workspace/coverage/sync_alert/2.prim_sync_alert.3630252382
/workspace/coverage/sync_alert/3.prim_sync_alert.800118958
/workspace/coverage/sync_alert/4.prim_sync_alert.3791239022
/workspace/coverage/sync_alert/5.prim_sync_alert.1434271342
/workspace/coverage/sync_alert/6.prim_sync_alert.2246903178
/workspace/coverage/sync_alert/7.prim_sync_alert.1207797888
/workspace/coverage/sync_alert/8.prim_sync_alert.2959889397
/workspace/coverage/sync_alert/9.prim_sync_alert.1080693076
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.199857845
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2013617904
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.118934797
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2723092453
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1471473589
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1325161522
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3787638857
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2369890156
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3559485300
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3894675925
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2425672578
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2277620944
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3599720954
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.215707697
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.137842525
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.457585128
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2959244142
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.22835813
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1709780029



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/3.prim_async_alert.23903259 Mar 14 12:19:22 PM PDT 24 Mar 14 12:19:23 PM PDT 24 10614851 ps
T2 /workspace/coverage/default/9.prim_async_alert.3946062500 Mar 14 12:18:33 PM PDT 24 Mar 14 12:18:34 PM PDT 24 11391793 ps
T3 /workspace/coverage/default/13.prim_async_alert.2309745161 Mar 14 12:18:35 PM PDT 24 Mar 14 12:18:36 PM PDT 24 11410758 ps
T7 /workspace/coverage/default/10.prim_async_alert.2516135077 Mar 14 12:18:38 PM PDT 24 Mar 14 12:18:39 PM PDT 24 11125281 ps
T8 /workspace/coverage/default/17.prim_async_alert.4260094020 Mar 14 12:21:13 PM PDT 24 Mar 14 12:21:14 PM PDT 24 11265081 ps
T18 /workspace/coverage/default/14.prim_async_alert.1385243003 Mar 14 12:21:02 PM PDT 24 Mar 14 12:21:03 PM PDT 24 10959037 ps
T12 /workspace/coverage/default/12.prim_async_alert.808189904 Mar 14 12:19:22 PM PDT 24 Mar 14 12:19:22 PM PDT 24 11548584 ps
T9 /workspace/coverage/default/8.prim_async_alert.2897657789 Mar 14 12:18:36 PM PDT 24 Mar 14 12:18:36 PM PDT 24 11243969 ps
T19 /workspace/coverage/default/5.prim_async_alert.44121324 Mar 14 12:18:36 PM PDT 24 Mar 14 12:18:36 PM PDT 24 10855592 ps
T20 /workspace/coverage/default/7.prim_async_alert.1248377212 Mar 14 12:18:24 PM PDT 24 Mar 14 12:18:25 PM PDT 24 10530974 ps
T21 /workspace/coverage/default/4.prim_async_alert.499493051 Mar 14 12:18:23 PM PDT 24 Mar 14 12:18:24 PM PDT 24 10209656 ps
T28 /workspace/coverage/default/18.prim_async_alert.2863358363 Mar 14 12:18:42 PM PDT 24 Mar 14 12:18:43 PM PDT 24 11691426 ps
T22 /workspace/coverage/default/0.prim_async_alert.3039764319 Mar 14 12:18:37 PM PDT 24 Mar 14 12:18:37 PM PDT 24 11269893 ps
T13 /workspace/coverage/default/16.prim_async_alert.606118516 Mar 14 12:18:38 PM PDT 24 Mar 14 12:18:38 PM PDT 24 13110709 ps
T14 /workspace/coverage/default/2.prim_async_alert.3583036125 Mar 14 12:18:23 PM PDT 24 Mar 14 12:18:24 PM PDT 24 12337071 ps
T15 /workspace/coverage/default/6.prim_async_alert.770706695 Mar 14 12:18:33 PM PDT 24 Mar 14 12:18:34 PM PDT 24 10649454 ps
T23 /workspace/coverage/default/15.prim_async_alert.1543243952 Mar 14 12:18:35 PM PDT 24 Mar 14 12:18:36 PM PDT 24 10964083 ps
T16 /workspace/coverage/default/19.prim_async_alert.781956935 Mar 14 12:18:37 PM PDT 24 Mar 14 12:18:37 PM PDT 24 11162365 ps
T24 /workspace/coverage/default/11.prim_async_alert.1591789727 Mar 14 12:21:14 PM PDT 24 Mar 14 12:21:14 PM PDT 24 10646309 ps
T50 /workspace/coverage/default/1.prim_async_alert.2415184668 Mar 14 12:18:32 PM PDT 24 Mar 14 12:18:32 PM PDT 24 10633589 ps
T44 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.155202187 Mar 14 01:05:56 PM PDT 24 Mar 14 01:05:57 PM PDT 24 29656034 ps
T45 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.413367315 Mar 14 01:05:57 PM PDT 24 Mar 14 01:05:59 PM PDT 24 30433875 ps
T25 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3230902910 Mar 14 01:05:58 PM PDT 24 Mar 14 01:05:59 PM PDT 24 29395574 ps
T43 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1879338155 Mar 14 01:06:02 PM PDT 24 Mar 14 01:06:03 PM PDT 24 30945758 ps
T26 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.936636340 Mar 14 01:06:01 PM PDT 24 Mar 14 01:06:02 PM PDT 24 30781955 ps
T46 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3100332385 Mar 14 01:05:58 PM PDT 24 Mar 14 01:05:59 PM PDT 24 30032837 ps
T27 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1502765848 Mar 14 01:05:59 PM PDT 24 Mar 14 01:06:00 PM PDT 24 31270824 ps
T47 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3894176070 Mar 14 01:05:58 PM PDT 24 Mar 14 01:05:59 PM PDT 24 28790549 ps
T48 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3872926973 Mar 14 01:05:56 PM PDT 24 Mar 14 01:05:57 PM PDT 24 31571473 ps
T49 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2170712036 Mar 14 01:05:56 PM PDT 24 Mar 14 01:05:57 PM PDT 24 30434005 ps
T4 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3700396550 Mar 14 01:05:57 PM PDT 24 Mar 14 01:05:57 PM PDT 24 29389341 ps
T51 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.707146265 Mar 14 01:06:01 PM PDT 24 Mar 14 01:06:02 PM PDT 24 31431350 ps
T52 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3335263591 Mar 14 01:05:59 PM PDT 24 Mar 14 01:06:00 PM PDT 24 32921829 ps
T53 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1381134146 Mar 14 01:05:59 PM PDT 24 Mar 14 01:06:00 PM PDT 24 28362956 ps
T17 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3100479204 Mar 14 01:05:59 PM PDT 24 Mar 14 01:06:00 PM PDT 24 28399108 ps
T54 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3866507890 Mar 14 01:06:01 PM PDT 24 Mar 14 01:06:02 PM PDT 24 28920508 ps
T55 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1177152537 Mar 14 01:05:57 PM PDT 24 Mar 14 01:05:59 PM PDT 24 31470965 ps
T56 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1958819701 Mar 14 01:05:58 PM PDT 24 Mar 14 01:05:59 PM PDT 24 30419193 ps
T57 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1005950457 Mar 14 01:05:58 PM PDT 24 Mar 14 01:05:59 PM PDT 24 29811607 ps
T58 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.295054553 Mar 14 01:06:01 PM PDT 24 Mar 14 01:06:02 PM PDT 24 31302730 ps
T29 /workspace/coverage/sync_alert/6.prim_sync_alert.2246903178 Mar 14 12:18:51 PM PDT 24 Mar 14 12:18:53 PM PDT 24 10797502 ps
T30 /workspace/coverage/sync_alert/18.prim_sync_alert.2924328424 Mar 14 12:23:26 PM PDT 24 Mar 14 12:23:26 PM PDT 24 9495092 ps
T31 /workspace/coverage/sync_alert/8.prim_sync_alert.2959889397 Mar 14 12:19:59 PM PDT 24 Mar 14 12:19:59 PM PDT 24 10339531 ps
T32 /workspace/coverage/sync_alert/17.prim_sync_alert.2869748835 Mar 14 12:20:04 PM PDT 24 Mar 14 12:20:05 PM PDT 24 9267214 ps
T33 /workspace/coverage/sync_alert/19.prim_sync_alert.591910944 Mar 14 12:19:09 PM PDT 24 Mar 14 12:19:10 PM PDT 24 9322927 ps
T38 /workspace/coverage/sync_alert/13.prim_sync_alert.3080569754 Mar 14 12:21:02 PM PDT 24 Mar 14 12:21:03 PM PDT 24 8812109 ps
T39 /workspace/coverage/sync_alert/10.prim_sync_alert.1301795555 Mar 14 12:18:37 PM PDT 24 Mar 14 12:18:37 PM PDT 24 9012959 ps
T40 /workspace/coverage/sync_alert/0.prim_sync_alert.3395682256 Mar 14 12:18:37 PM PDT 24 Mar 14 12:18:38 PM PDT 24 9408609 ps
T41 /workspace/coverage/sync_alert/15.prim_sync_alert.1732376310 Mar 14 12:18:47 PM PDT 24 Mar 14 12:18:47 PM PDT 24 9202828 ps
T42 /workspace/coverage/sync_alert/7.prim_sync_alert.1207797888 Mar 14 12:20:12 PM PDT 24 Mar 14 12:20:13 PM PDT 24 10323253 ps
T59 /workspace/coverage/sync_alert/9.prim_sync_alert.1080693076 Mar 14 12:19:22 PM PDT 24 Mar 14 12:19:23 PM PDT 24 9238767 ps
T34 /workspace/coverage/sync_alert/16.prim_sync_alert.3133020890 Mar 14 12:18:38 PM PDT 24 Mar 14 12:18:39 PM PDT 24 9803533 ps
T60 /workspace/coverage/sync_alert/4.prim_sync_alert.3791239022 Mar 14 12:20:01 PM PDT 24 Mar 14 12:20:01 PM PDT 24 9299094 ps
T10 /workspace/coverage/sync_alert/1.prim_sync_alert.3747874619 Mar 14 12:18:51 PM PDT 24 Mar 14 12:18:53 PM PDT 24 8888785 ps
T35 /workspace/coverage/sync_alert/2.prim_sync_alert.3630252382 Mar 14 12:19:10 PM PDT 24 Mar 14 12:19:11 PM PDT 24 8901173 ps
T61 /workspace/coverage/sync_alert/11.prim_sync_alert.3721897889 Mar 14 12:22:34 PM PDT 24 Mar 14 12:22:34 PM PDT 24 10000506 ps
T62 /workspace/coverage/sync_alert/3.prim_sync_alert.800118958 Mar 14 12:21:13 PM PDT 24 Mar 14 12:21:14 PM PDT 24 8965516 ps
T63 /workspace/coverage/sync_alert/12.prim_sync_alert.920017189 Mar 14 12:24:18 PM PDT 24 Mar 14 12:24:19 PM PDT 24 9266361 ps
T36 /workspace/coverage/sync_alert/14.prim_sync_alert.4051087396 Mar 14 12:18:42 PM PDT 24 Mar 14 12:18:43 PM PDT 24 8655737 ps
T64 /workspace/coverage/sync_alert/5.prim_sync_alert.1434271342 Mar 14 12:21:13 PM PDT 24 Mar 14 12:21:14 PM PDT 24 10455443 ps
T11 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.118934797 Mar 14 12:19:35 PM PDT 24 Mar 14 12:19:36 PM PDT 24 26510098 ps
T37 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2369890156 Mar 14 12:19:32 PM PDT 24 Mar 14 12:19:32 PM PDT 24 28615311 ps
T5 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1050178048 Mar 14 12:21:13 PM PDT 24 Mar 14 12:21:13 PM PDT 24 26172739 ps
T65 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.137842525 Mar 14 12:20:01 PM PDT 24 Mar 14 12:20:01 PM PDT 24 27109692 ps
T66 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3599720954 Mar 14 12:18:52 PM PDT 24 Mar 14 12:18:53 PM PDT 24 24265619 ps
T67 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2425672578 Mar 14 12:18:43 PM PDT 24 Mar 14 12:18:44 PM PDT 24 27215299 ps
T6 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1471473589 Mar 14 12:18:37 PM PDT 24 Mar 14 12:18:37 PM PDT 24 26014068 ps
T68 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2277620944 Mar 14 12:18:40 PM PDT 24 Mar 14 12:18:41 PM PDT 24 29031470 ps
T69 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.215707697 Mar 14 12:18:49 PM PDT 24 Mar 14 12:18:49 PM PDT 24 26745029 ps
T70 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2959244142 Mar 14 12:18:42 PM PDT 24 Mar 14 12:18:43 PM PDT 24 27062617 ps
T71 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1709780029 Mar 14 12:19:18 PM PDT 24 Mar 14 12:19:19 PM PDT 24 27215049 ps
T72 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.22835813 Mar 14 12:18:43 PM PDT 24 Mar 14 12:18:43 PM PDT 24 27499458 ps
T73 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3894675925 Mar 14 12:18:56 PM PDT 24 Mar 14 12:18:56 PM PDT 24 27631754 ps
T74 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.457585128 Mar 14 12:20:20 PM PDT 24 Mar 14 12:20:20 PM PDT 24 26869943 ps
T75 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.199857845 Mar 14 12:18:50 PM PDT 24 Mar 14 12:18:52 PM PDT 24 27639442 ps
T76 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2013617904 Mar 14 12:24:06 PM PDT 24 Mar 14 12:24:07 PM PDT 24 27529839 ps
T77 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3559485300 Mar 14 12:21:12 PM PDT 24 Mar 14 12:21:13 PM PDT 24 25925922 ps
T78 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2723092453 Mar 14 12:19:09 PM PDT 24 Mar 14 12:19:10 PM PDT 24 29123419 ps
T79 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1325161522 Mar 14 12:20:20 PM PDT 24 Mar 14 12:20:21 PM PDT 24 26529472 ps
T80 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3787638857 Mar 14 12:19:52 PM PDT 24 Mar 14 12:19:53 PM PDT 24 26149135 ps

Test location /workspace/coverage/default/17.prim_async_alert.4260094020
Short name T8
Test name
Test status
Simulation time 11265081 ps
CPU time 0.4 seconds
Started Mar 14 12:21:13 PM PDT 24
Finished Mar 14 12:21:14 PM PDT 24
Peak memory 145648 kb
Host smart-ed10bf8a-f3a1-4ecd-abbb-33cb0556f36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260094020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4260094020
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1301795555
Short name T39
Test name
Test status
Simulation time 9012959 ps
CPU time 0.41 seconds
Started Mar 14 12:18:37 PM PDT 24
Finished Mar 14 12:18:37 PM PDT 24
Peak memory 144864 kb
Host smart-f849c051-bf14-4937-9a87-6e54f834f580
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1301795555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1301795555
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.413367315
Short name T45
Test name
Test status
Simulation time 30433875 ps
CPU time 0.41 seconds
Started Mar 14 01:05:57 PM PDT 24
Finished Mar 14 01:05:59 PM PDT 24
Peak memory 145808 kb
Host smart-8c6873d3-437f-4c24-ba85-cac9a9252247
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=413367315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.413367315
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1050178048
Short name T5
Test name
Test status
Simulation time 26172739 ps
CPU time 0.42 seconds
Started Mar 14 12:21:13 PM PDT 24
Finished Mar 14 12:21:13 PM PDT 24
Peak memory 144900 kb
Host smart-3735c695-20e3-44ba-ae34-57688fc6ed91
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1050178048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1050178048
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.808189904
Short name T12
Test name
Test status
Simulation time 11548584 ps
CPU time 0.41 seconds
Started Mar 14 12:19:22 PM PDT 24
Finished Mar 14 12:19:22 PM PDT 24
Peak memory 145648 kb
Host smart-c4a6c719-cff2-4691-bb8c-5568d2241814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808189904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.808189904
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3039764319
Short name T22
Test name
Test status
Simulation time 11269893 ps
CPU time 0.41 seconds
Started Mar 14 12:18:37 PM PDT 24
Finished Mar 14 12:18:37 PM PDT 24
Peak memory 145504 kb
Host smart-bf305a44-fb87-4479-ad22-440db7fe2b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039764319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3039764319
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2415184668
Short name T50
Test name
Test status
Simulation time 10633589 ps
CPU time 0.43 seconds
Started Mar 14 12:18:32 PM PDT 24
Finished Mar 14 12:18:32 PM PDT 24
Peak memory 145592 kb
Host smart-ca62f0f4-ba33-4cbc-95d7-d4f64bd3d263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415184668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2415184668
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2516135077
Short name T7
Test name
Test status
Simulation time 11125281 ps
CPU time 0.38 seconds
Started Mar 14 12:18:38 PM PDT 24
Finished Mar 14 12:18:39 PM PDT 24
Peak memory 145952 kb
Host smart-87dac491-621e-457a-8232-465c76ef6e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516135077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2516135077
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1591789727
Short name T24
Test name
Test status
Simulation time 10646309 ps
CPU time 0.39 seconds
Started Mar 14 12:21:14 PM PDT 24
Finished Mar 14 12:21:14 PM PDT 24
Peak memory 145740 kb
Host smart-08d3f61e-3935-4c83-b6ad-e2f647d59f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591789727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1591789727
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2309745161
Short name T3
Test name
Test status
Simulation time 11410758 ps
CPU time 0.43 seconds
Started Mar 14 12:18:35 PM PDT 24
Finished Mar 14 12:18:36 PM PDT 24
Peak memory 145680 kb
Host smart-be6dadc2-2422-4452-a553-2096a7559f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309745161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2309745161
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1385243003
Short name T18
Test name
Test status
Simulation time 10959037 ps
CPU time 0.4 seconds
Started Mar 14 12:21:02 PM PDT 24
Finished Mar 14 12:21:03 PM PDT 24
Peak memory 145464 kb
Host smart-1191369f-3620-4b9f-8afe-97c2491f928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385243003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1385243003
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1543243952
Short name T23
Test name
Test status
Simulation time 10964083 ps
CPU time 0.42 seconds
Started Mar 14 12:18:35 PM PDT 24
Finished Mar 14 12:18:36 PM PDT 24
Peak memory 145680 kb
Host smart-632b5323-808e-4192-a59b-a873b7d63a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543243952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1543243952
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.606118516
Short name T13
Test name
Test status
Simulation time 13110709 ps
CPU time 0.4 seconds
Started Mar 14 12:18:38 PM PDT 24
Finished Mar 14 12:18:38 PM PDT 24
Peak memory 145500 kb
Host smart-1b4c744d-11ab-45b7-9b9e-a3776e3493e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606118516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.606118516
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2863358363
Short name T28
Test name
Test status
Simulation time 11691426 ps
CPU time 0.38 seconds
Started Mar 14 12:18:42 PM PDT 24
Finished Mar 14 12:18:43 PM PDT 24
Peak memory 145664 kb
Host smart-d86ab407-e6df-48f2-8f9e-e2918fe17e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863358363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2863358363
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.781956935
Short name T16
Test name
Test status
Simulation time 11162365 ps
CPU time 0.4 seconds
Started Mar 14 12:18:37 PM PDT 24
Finished Mar 14 12:18:37 PM PDT 24
Peak memory 145568 kb
Host smart-7a300b23-1f20-430c-aef0-f0e7ceac508a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781956935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.781956935
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3583036125
Short name T14
Test name
Test status
Simulation time 12337071 ps
CPU time 0.5 seconds
Started Mar 14 12:18:23 PM PDT 24
Finished Mar 14 12:18:24 PM PDT 24
Peak memory 144652 kb
Host smart-1f95552f-6bc3-4f76-8b41-58990ff262c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583036125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3583036125
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.23903259
Short name T1
Test name
Test status
Simulation time 10614851 ps
CPU time 0.42 seconds
Started Mar 14 12:19:22 PM PDT 24
Finished Mar 14 12:19:23 PM PDT 24
Peak memory 145636 kb
Host smart-7491cd29-8a3b-4b19-b2b7-f9d33802b53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23903259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.23903259
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.499493051
Short name T21
Test name
Test status
Simulation time 10209656 ps
CPU time 0.46 seconds
Started Mar 14 12:18:23 PM PDT 24
Finished Mar 14 12:18:24 PM PDT 24
Peak memory 144524 kb
Host smart-5590d264-a824-4979-8f82-1181f001e708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499493051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.499493051
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.44121324
Short name T19
Test name
Test status
Simulation time 10855592 ps
CPU time 0.39 seconds
Started Mar 14 12:18:36 PM PDT 24
Finished Mar 14 12:18:36 PM PDT 24
Peak memory 145512 kb
Host smart-5ba703a0-e83e-4d28-904d-85c62b19cebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44121324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.44121324
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.770706695
Short name T15
Test name
Test status
Simulation time 10649454 ps
CPU time 0.39 seconds
Started Mar 14 12:18:33 PM PDT 24
Finished Mar 14 12:18:34 PM PDT 24
Peak memory 145584 kb
Host smart-49fbe1e8-1dea-404e-90ce-bdd5552b23cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770706695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.770706695
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1248377212
Short name T20
Test name
Test status
Simulation time 10530974 ps
CPU time 0.48 seconds
Started Mar 14 12:18:24 PM PDT 24
Finished Mar 14 12:18:25 PM PDT 24
Peak memory 144136 kb
Host smart-58633fc8-d3b9-4e26-881d-07c4bd74b65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248377212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1248377212
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2897657789
Short name T9
Test name
Test status
Simulation time 11243969 ps
CPU time 0.38 seconds
Started Mar 14 12:18:36 PM PDT 24
Finished Mar 14 12:18:36 PM PDT 24
Peak memory 145952 kb
Host smart-73a7d417-ce12-4c13-b888-b752d1aabeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897657789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2897657789
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3946062500
Short name T2
Test name
Test status
Simulation time 11391793 ps
CPU time 0.44 seconds
Started Mar 14 12:18:33 PM PDT 24
Finished Mar 14 12:18:34 PM PDT 24
Peak memory 145580 kb
Host smart-1cbbe3cd-6adf-4a13-ace4-13b2412419b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946062500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3946062500
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1879338155
Short name T43
Test name
Test status
Simulation time 30945758 ps
CPU time 0.43 seconds
Started Mar 14 01:06:02 PM PDT 24
Finished Mar 14 01:06:03 PM PDT 24
Peak memory 145748 kb
Host smart-706b74e3-4ce3-45d8-947b-ad2859890e54
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1879338155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1879338155
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3230902910
Short name T25
Test name
Test status
Simulation time 29395574 ps
CPU time 0.41 seconds
Started Mar 14 01:05:58 PM PDT 24
Finished Mar 14 01:05:59 PM PDT 24
Peak memory 145800 kb
Host smart-561edf7d-f571-4118-ad91-6553c7f5967b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3230902910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3230902910
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3894176070
Short name T47
Test name
Test status
Simulation time 28790549 ps
CPU time 0.4 seconds
Started Mar 14 01:05:58 PM PDT 24
Finished Mar 14 01:05:59 PM PDT 24
Peak memory 145796 kb
Host smart-76330b70-5722-4624-a3ef-80c9403ae6f7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3894176070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3894176070
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.936636340
Short name T26
Test name
Test status
Simulation time 30781955 ps
CPU time 0.42 seconds
Started Mar 14 01:06:01 PM PDT 24
Finished Mar 14 01:06:02 PM PDT 24
Peak memory 145872 kb
Host smart-5a0c747f-ef3c-4315-a30d-356b5be9ec33
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=936636340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.936636340
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.155202187
Short name T44
Test name
Test status
Simulation time 29656034 ps
CPU time 0.4 seconds
Started Mar 14 01:05:56 PM PDT 24
Finished Mar 14 01:05:57 PM PDT 24
Peak memory 145764 kb
Host smart-930eab07-e878-4e7a-ac8a-3d26bb4020ba
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=155202187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.155202187
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.707146265
Short name T51
Test name
Test status
Simulation time 31431350 ps
CPU time 0.48 seconds
Started Mar 14 01:06:01 PM PDT 24
Finished Mar 14 01:06:02 PM PDT 24
Peak memory 145796 kb
Host smart-c8367cc7-25a5-4274-b751-7c5f7cdafbbc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=707146265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.707146265
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3100479204
Short name T17
Test name
Test status
Simulation time 28399108 ps
CPU time 0.4 seconds
Started Mar 14 01:05:59 PM PDT 24
Finished Mar 14 01:06:00 PM PDT 24
Peak memory 145784 kb
Host smart-4e427eb8-9436-44fe-9dde-a6775cba2917
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3100479204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3100479204
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1177152537
Short name T55
Test name
Test status
Simulation time 31470965 ps
CPU time 0.41 seconds
Started Mar 14 01:05:57 PM PDT 24
Finished Mar 14 01:05:59 PM PDT 24
Peak memory 145780 kb
Host smart-55d12b6d-40aa-4206-81be-8a45046f31b5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1177152537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1177152537
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3335263591
Short name T52
Test name
Test status
Simulation time 32921829 ps
CPU time 0.41 seconds
Started Mar 14 01:05:59 PM PDT 24
Finished Mar 14 01:06:00 PM PDT 24
Peak memory 145812 kb
Host smart-78b5230e-b0e2-45f0-9f2b-7584290e30e0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3335263591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3335263591
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3100332385
Short name T46
Test name
Test status
Simulation time 30032837 ps
CPU time 0.41 seconds
Started Mar 14 01:05:58 PM PDT 24
Finished Mar 14 01:05:59 PM PDT 24
Peak memory 145804 kb
Host smart-6f23ab9f-1c04-4249-bafb-8069b78667e3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3100332385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3100332385
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1381134146
Short name T53
Test name
Test status
Simulation time 28362956 ps
CPU time 0.42 seconds
Started Mar 14 01:05:59 PM PDT 24
Finished Mar 14 01:06:00 PM PDT 24
Peak memory 145748 kb
Host smart-b9a6f3c7-327d-4c50-a627-cc97f5d0f8ec
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1381134146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1381134146
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1005950457
Short name T57
Test name
Test status
Simulation time 29811607 ps
CPU time 0.39 seconds
Started Mar 14 01:05:58 PM PDT 24
Finished Mar 14 01:05:59 PM PDT 24
Peak memory 145796 kb
Host smart-1a1faf7e-e4c5-4889-ae2f-b892604acdd2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1005950457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1005950457
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1958819701
Short name T56
Test name
Test status
Simulation time 30419193 ps
CPU time 0.41 seconds
Started Mar 14 01:05:58 PM PDT 24
Finished Mar 14 01:05:59 PM PDT 24
Peak memory 145800 kb
Host smart-14612716-6ff9-4df7-bd29-4752c5315cb5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1958819701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1958819701
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1502765848
Short name T27
Test name
Test status
Simulation time 31270824 ps
CPU time 0.4 seconds
Started Mar 14 01:05:59 PM PDT 24
Finished Mar 14 01:06:00 PM PDT 24
Peak memory 145700 kb
Host smart-819acdda-c95e-4d19-bcf7-828d15d59535
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1502765848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1502765848
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.295054553
Short name T58
Test name
Test status
Simulation time 31302730 ps
CPU time 0.41 seconds
Started Mar 14 01:06:01 PM PDT 24
Finished Mar 14 01:06:02 PM PDT 24
Peak memory 145872 kb
Host smart-1e2b270e-9aed-4826-92fb-969d490071ad
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=295054553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.295054553
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3872926973
Short name T48
Test name
Test status
Simulation time 31571473 ps
CPU time 0.38 seconds
Started Mar 14 01:05:56 PM PDT 24
Finished Mar 14 01:05:57 PM PDT 24
Peak memory 145700 kb
Host smart-01cd0a4f-a19e-410e-859e-d64e774d0376
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3872926973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3872926973
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2170712036
Short name T49
Test name
Test status
Simulation time 30434005 ps
CPU time 0.4 seconds
Started Mar 14 01:05:56 PM PDT 24
Finished Mar 14 01:05:57 PM PDT 24
Peak memory 145784 kb
Host smart-900c01b9-7756-47b0-ad46-edf426566eca
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2170712036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2170712036
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3866507890
Short name T54
Test name
Test status
Simulation time 28920508 ps
CPU time 0.4 seconds
Started Mar 14 01:06:01 PM PDT 24
Finished Mar 14 01:06:02 PM PDT 24
Peak memory 145856 kb
Host smart-d9fbcc52-5479-4deb-8d43-7cdcacc5d9e1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3866507890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3866507890
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3700396550
Short name T4
Test name
Test status
Simulation time 29389341 ps
CPU time 0.4 seconds
Started Mar 14 01:05:57 PM PDT 24
Finished Mar 14 01:05:57 PM PDT 24
Peak memory 145760 kb
Host smart-15b47310-d19b-436d-a5f9-1b45581d43d9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3700396550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3700396550
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3395682256
Short name T40
Test name
Test status
Simulation time 9408609 ps
CPU time 0.4 seconds
Started Mar 14 12:18:37 PM PDT 24
Finished Mar 14 12:18:38 PM PDT 24
Peak memory 144660 kb
Host smart-07867024-f98b-4910-981c-0ef528cfe892
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3395682256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3395682256
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3747874619
Short name T10
Test name
Test status
Simulation time 8888785 ps
CPU time 0.39 seconds
Started Mar 14 12:18:51 PM PDT 24
Finished Mar 14 12:18:53 PM PDT 24
Peak memory 144756 kb
Host smart-f341f8dc-382f-4e58-83a6-cc50ec171dc7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3747874619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3747874619
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3721897889
Short name T61
Test name
Test status
Simulation time 10000506 ps
CPU time 0.41 seconds
Started Mar 14 12:22:34 PM PDT 24
Finished Mar 14 12:22:34 PM PDT 24
Peak memory 145032 kb
Host smart-6b898d84-2908-463a-96ab-ceed8bab5d2a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3721897889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3721897889
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.920017189
Short name T63
Test name
Test status
Simulation time 9266361 ps
CPU time 0.36 seconds
Started Mar 14 12:24:18 PM PDT 24
Finished Mar 14 12:24:19 PM PDT 24
Peak memory 144888 kb
Host smart-8235c8f7-cce5-4e38-8704-942e3b480928
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=920017189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.920017189
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3080569754
Short name T38
Test name
Test status
Simulation time 8812109 ps
CPU time 0.37 seconds
Started Mar 14 12:21:02 PM PDT 24
Finished Mar 14 12:21:03 PM PDT 24
Peak memory 145224 kb
Host smart-dc38a5c8-4482-4570-8985-6df4fb9c30ba
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3080569754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3080569754
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.4051087396
Short name T36
Test name
Test status
Simulation time 8655737 ps
CPU time 0.41 seconds
Started Mar 14 12:18:42 PM PDT 24
Finished Mar 14 12:18:43 PM PDT 24
Peak memory 144948 kb
Host smart-5dd56d7f-dbe3-4321-b6bf-3fd73fecb506
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4051087396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.4051087396
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1732376310
Short name T41
Test name
Test status
Simulation time 9202828 ps
CPU time 0.39 seconds
Started Mar 14 12:18:47 PM PDT 24
Finished Mar 14 12:18:47 PM PDT 24
Peak memory 145016 kb
Host smart-7e1276cb-545f-487d-a791-11e3a8a987d6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1732376310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1732376310
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3133020890
Short name T34
Test name
Test status
Simulation time 9803533 ps
CPU time 0.39 seconds
Started Mar 14 12:18:38 PM PDT 24
Finished Mar 14 12:18:39 PM PDT 24
Peak memory 144652 kb
Host smart-aa11cd0a-54b8-4135-b0c9-c087924c9b9c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3133020890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3133020890
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2869748835
Short name T32
Test name
Test status
Simulation time 9267214 ps
CPU time 0.39 seconds
Started Mar 14 12:20:04 PM PDT 24
Finished Mar 14 12:20:05 PM PDT 24
Peak memory 144924 kb
Host smart-d0cf28be-4936-44bd-afab-5129fc656c65
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2869748835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2869748835
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2924328424
Short name T30
Test name
Test status
Simulation time 9495092 ps
CPU time 0.37 seconds
Started Mar 14 12:23:26 PM PDT 24
Finished Mar 14 12:23:26 PM PDT 24
Peak memory 145720 kb
Host smart-7e579cf3-e289-4c67-8b13-1cb217c1c2b3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2924328424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2924328424
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.591910944
Short name T33
Test name
Test status
Simulation time 9322927 ps
CPU time 0.38 seconds
Started Mar 14 12:19:09 PM PDT 24
Finished Mar 14 12:19:10 PM PDT 24
Peak memory 144860 kb
Host smart-8145951c-6b9f-44ad-9b01-941da50aa8b6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=591910944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.591910944
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3630252382
Short name T35
Test name
Test status
Simulation time 8901173 ps
CPU time 0.39 seconds
Started Mar 14 12:19:10 PM PDT 24
Finished Mar 14 12:19:11 PM PDT 24
Peak memory 145024 kb
Host smart-0e33e621-0d20-4c8f-820a-a521eb3ee94e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3630252382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3630252382
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.800118958
Short name T62
Test name
Test status
Simulation time 8965516 ps
CPU time 0.4 seconds
Started Mar 14 12:21:13 PM PDT 24
Finished Mar 14 12:21:14 PM PDT 24
Peak memory 144916 kb
Host smart-78264904-357a-4fbc-90f4-8355dcbd8d15
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=800118958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.800118958
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3791239022
Short name T60
Test name
Test status
Simulation time 9299094 ps
CPU time 0.42 seconds
Started Mar 14 12:20:01 PM PDT 24
Finished Mar 14 12:20:01 PM PDT 24
Peak memory 144912 kb
Host smart-e835a820-72ee-424e-9b6b-96f4827a0b99
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3791239022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3791239022
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1434271342
Short name T64
Test name
Test status
Simulation time 10455443 ps
CPU time 0.41 seconds
Started Mar 14 12:21:13 PM PDT 24
Finished Mar 14 12:21:14 PM PDT 24
Peak memory 144920 kb
Host smart-9d786c96-f59a-46a2-a0c6-0e9d77ad292a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1434271342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1434271342
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2246903178
Short name T29
Test name
Test status
Simulation time 10797502 ps
CPU time 0.38 seconds
Started Mar 14 12:18:51 PM PDT 24
Finished Mar 14 12:18:53 PM PDT 24
Peak memory 144700 kb
Host smart-dfbfdb57-445b-4e8d-a7c4-2f86b160651c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2246903178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2246903178
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1207797888
Short name T42
Test name
Test status
Simulation time 10323253 ps
CPU time 0.41 seconds
Started Mar 14 12:20:12 PM PDT 24
Finished Mar 14 12:20:13 PM PDT 24
Peak memory 145028 kb
Host smart-5fa4dfb0-7ce8-4216-9142-ab5af93757a2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1207797888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1207797888
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2959889397
Short name T31
Test name
Test status
Simulation time 10339531 ps
CPU time 0.38 seconds
Started Mar 14 12:19:59 PM PDT 24
Finished Mar 14 12:19:59 PM PDT 24
Peak memory 145028 kb
Host smart-3e2b6f4d-3347-4b3a-9719-ee4d01c51017
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2959889397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2959889397
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1080693076
Short name T59
Test name
Test status
Simulation time 9238767 ps
CPU time 0.43 seconds
Started Mar 14 12:19:22 PM PDT 24
Finished Mar 14 12:19:23 PM PDT 24
Peak memory 144920 kb
Host smart-25ec905f-b273-4d35-aefd-f51d30504af2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1080693076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1080693076
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.199857845
Short name T75
Test name
Test status
Simulation time 27639442 ps
CPU time 0.41 seconds
Started Mar 14 12:18:50 PM PDT 24
Finished Mar 14 12:18:52 PM PDT 24
Peak memory 144700 kb
Host smart-bdc8c562-9c2c-40bb-ba69-d9c09422f230
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=199857845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.199857845
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2013617904
Short name T76
Test name
Test status
Simulation time 27529839 ps
CPU time 0.4 seconds
Started Mar 14 12:24:06 PM PDT 24
Finished Mar 14 12:24:07 PM PDT 24
Peak memory 144880 kb
Host smart-86ae9d23-cda9-4f3a-9359-5c9e99283939
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2013617904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2013617904
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.118934797
Short name T11
Test name
Test status
Simulation time 26510098 ps
CPU time 0.4 seconds
Started Mar 14 12:19:35 PM PDT 24
Finished Mar 14 12:19:36 PM PDT 24
Peak memory 145024 kb
Host smart-9af0c545-da9a-456d-87ef-373e264efc71
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=118934797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.118934797
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2723092453
Short name T78
Test name
Test status
Simulation time 29123419 ps
CPU time 0.4 seconds
Started Mar 14 12:19:09 PM PDT 24
Finished Mar 14 12:19:10 PM PDT 24
Peak memory 144880 kb
Host smart-09db7b5e-bc80-48f0-b4af-2e7f2039acda
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2723092453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2723092453
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1471473589
Short name T6
Test name
Test status
Simulation time 26014068 ps
CPU time 0.41 seconds
Started Mar 14 12:18:37 PM PDT 24
Finished Mar 14 12:18:37 PM PDT 24
Peak memory 144888 kb
Host smart-06c81a7e-6839-4d90-b40a-786fe925578a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1471473589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1471473589
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1325161522
Short name T79
Test name
Test status
Simulation time 26529472 ps
CPU time 0.4 seconds
Started Mar 14 12:20:20 PM PDT 24
Finished Mar 14 12:20:21 PM PDT 24
Peak memory 144924 kb
Host smart-1e6e929f-4ece-4f2e-b82c-8d21f110331f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1325161522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1325161522
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3787638857
Short name T80
Test name
Test status
Simulation time 26149135 ps
CPU time 0.4 seconds
Started Mar 14 12:19:52 PM PDT 24
Finished Mar 14 12:19:53 PM PDT 24
Peak memory 144924 kb
Host smart-f7c1f694-6c86-4308-950c-1d1bc811e7d6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3787638857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3787638857
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2369890156
Short name T37
Test name
Test status
Simulation time 28615311 ps
CPU time 0.41 seconds
Started Mar 14 12:19:32 PM PDT 24
Finished Mar 14 12:19:32 PM PDT 24
Peak memory 145232 kb
Host smart-436df46d-d0e6-4664-b28c-e1bf063b8ab7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2369890156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2369890156
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3559485300
Short name T77
Test name
Test status
Simulation time 25925922 ps
CPU time 0.42 seconds
Started Mar 14 12:21:12 PM PDT 24
Finished Mar 14 12:21:13 PM PDT 24
Peak memory 144924 kb
Host smart-07d68ad9-5d9b-4e43-9881-f59562103273
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3559485300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3559485300
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3894675925
Short name T73
Test name
Test status
Simulation time 27631754 ps
CPU time 0.42 seconds
Started Mar 14 12:18:56 PM PDT 24
Finished Mar 14 12:18:56 PM PDT 24
Peak memory 145040 kb
Host smart-34522134-a1c4-42ff-8b9c-e0b9a3e4cdcd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3894675925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3894675925
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2425672578
Short name T67
Test name
Test status
Simulation time 27215299 ps
CPU time 0.4 seconds
Started Mar 14 12:18:43 PM PDT 24
Finished Mar 14 12:18:44 PM PDT 24
Peak memory 145012 kb
Host smart-91524212-c85e-4df1-8199-a1d6c3e3ab78
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2425672578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2425672578
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2277620944
Short name T68
Test name
Test status
Simulation time 29031470 ps
CPU time 0.4 seconds
Started Mar 14 12:18:40 PM PDT 24
Finished Mar 14 12:18:41 PM PDT 24
Peak memory 144688 kb
Host smart-392d4a0d-a2e0-44bd-b02b-7603a5d9c2ed
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2277620944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2277620944
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3599720954
Short name T66
Test name
Test status
Simulation time 24265619 ps
CPU time 0.43 seconds
Started Mar 14 12:18:52 PM PDT 24
Finished Mar 14 12:18:53 PM PDT 24
Peak memory 144728 kb
Host smart-cba21a38-6fd9-470d-a07e-ab939184c1b3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3599720954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3599720954
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.215707697
Short name T69
Test name
Test status
Simulation time 26745029 ps
CPU time 0.4 seconds
Started Mar 14 12:18:49 PM PDT 24
Finished Mar 14 12:18:49 PM PDT 24
Peak memory 145020 kb
Host smart-3715fc6a-89ca-40e0-86d7-b3b4e722298f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=215707697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.215707697
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.137842525
Short name T65
Test name
Test status
Simulation time 27109692 ps
CPU time 0.45 seconds
Started Mar 14 12:20:01 PM PDT 24
Finished Mar 14 12:20:01 PM PDT 24
Peak memory 144920 kb
Host smart-5073fee9-8112-4050-9b51-152e3123b973
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=137842525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.137842525
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.457585128
Short name T74
Test name
Test status
Simulation time 26869943 ps
CPU time 0.4 seconds
Started Mar 14 12:20:20 PM PDT 24
Finished Mar 14 12:20:20 PM PDT 24
Peak memory 144932 kb
Host smart-fcc9c137-dd10-4622-8368-1e0cbdef9421
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=457585128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.457585128
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2959244142
Short name T70
Test name
Test status
Simulation time 27062617 ps
CPU time 0.43 seconds
Started Mar 14 12:18:42 PM PDT 24
Finished Mar 14 12:18:43 PM PDT 24
Peak memory 144944 kb
Host smart-c97c67dd-50df-4b8d-bfb4-62383381f709
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2959244142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2959244142
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.22835813
Short name T72
Test name
Test status
Simulation time 27499458 ps
CPU time 0.4 seconds
Started Mar 14 12:18:43 PM PDT 24
Finished Mar 14 12:18:43 PM PDT 24
Peak memory 144992 kb
Host smart-3fbb5c3f-5cbd-41e5-b611-9ad280fd1876
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=22835813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.22835813
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1709780029
Short name T71
Test name
Test status
Simulation time 27215049 ps
CPU time 0.4 seconds
Started Mar 14 12:19:18 PM PDT 24
Finished Mar 14 12:19:19 PM PDT 24
Peak memory 145240 kb
Host smart-399cf42d-a92e-424b-b80b-8dcff5922cff
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1709780029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1709780029
Directory /workspace/9.prim_sync_fatal_alert/latest
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