Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.53 88.53 100.00 100.00 91.67 91.67 96.43 96.43 82.14 82.14 95.83 95.83 65.12 65.12 /workspace/coverage/default/13.prim_async_alert.3673429545
91.06 2.53 100.00 0.00 91.67 0.00 96.43 0.00 85.71 3.57 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/15.prim_sync_alert.1875197053
93.21 2.15 100.00 0.00 91.67 0.00 100.00 3.57 85.71 0.00 95.83 0.00 86.05 9.30 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3000011912
94.15 0.94 100.00 0.00 93.75 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/17.prim_async_alert.3173791688
94.50 0.35 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/1.prim_async_alert.1364170607
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3937376488

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2510755353
/workspace/coverage/default/10.prim_async_alert.3277837690
/workspace/coverage/default/11.prim_async_alert.3549997252
/workspace/coverage/default/12.prim_async_alert.1205891036
/workspace/coverage/default/14.prim_async_alert.3488862998
/workspace/coverage/default/15.prim_async_alert.453493842
/workspace/coverage/default/16.prim_async_alert.4155738543
/workspace/coverage/default/18.prim_async_alert.2266176847
/workspace/coverage/default/19.prim_async_alert.1076317531
/workspace/coverage/default/2.prim_async_alert.2220898914
/workspace/coverage/default/3.prim_async_alert.2321341129
/workspace/coverage/default/4.prim_async_alert.215943953
/workspace/coverage/default/5.prim_async_alert.3757056168
/workspace/coverage/default/6.prim_async_alert.1496385110
/workspace/coverage/default/7.prim_async_alert.4078711697
/workspace/coverage/default/8.prim_async_alert.3688690418
/workspace/coverage/default/9.prim_async_alert.2760746268
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4083856285
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3377802337
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1410875987
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2439315568
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.433694326
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2724555830
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2287038606
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2715561150
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.636932606
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.593402633
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1286932819
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3474813632
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1159787656
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3501849101
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1229684949
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.783544747
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.944569771
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1988729770
/workspace/coverage/sync_alert/0.prim_sync_alert.620543307
/workspace/coverage/sync_alert/1.prim_sync_alert.1243007355
/workspace/coverage/sync_alert/10.prim_sync_alert.3361327134
/workspace/coverage/sync_alert/11.prim_sync_alert.482935806
/workspace/coverage/sync_alert/12.prim_sync_alert.1266330059
/workspace/coverage/sync_alert/13.prim_sync_alert.715569012
/workspace/coverage/sync_alert/14.prim_sync_alert.123677024
/workspace/coverage/sync_alert/16.prim_sync_alert.2028766275
/workspace/coverage/sync_alert/17.prim_sync_alert.1702891779
/workspace/coverage/sync_alert/18.prim_sync_alert.1856812557
/workspace/coverage/sync_alert/19.prim_sync_alert.3008079282
/workspace/coverage/sync_alert/2.prim_sync_alert.1445351245
/workspace/coverage/sync_alert/3.prim_sync_alert.1157636208
/workspace/coverage/sync_alert/4.prim_sync_alert.74618728
/workspace/coverage/sync_alert/5.prim_sync_alert.116987597
/workspace/coverage/sync_alert/6.prim_sync_alert.1477270701
/workspace/coverage/sync_alert/7.prim_sync_alert.3976145377
/workspace/coverage/sync_alert/8.prim_sync_alert.1276864897
/workspace/coverage/sync_alert/9.prim_sync_alert.1324306346
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.280664634
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.385523551
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1788590537
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1335781546
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3858474274
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.110250098
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3485011713
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2275694920
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3363469694
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1542642075
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.63200826
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1346831205
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.499714564
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3317549725
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4170056422
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3596365811
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1596201965
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.781757635
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3179333744



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/13.prim_async_alert.3673429545 Mar 17 12:27:52 PM PDT 24 Mar 17 12:27:53 PM PDT 24 11233514 ps
T2 /workspace/coverage/default/7.prim_async_alert.4078711697 Mar 17 12:24:16 PM PDT 24 Mar 17 12:24:17 PM PDT 24 11281606 ps
T3 /workspace/coverage/default/4.prim_async_alert.215943953 Mar 17 12:25:08 PM PDT 24 Mar 17 12:25:09 PM PDT 24 11459355 ps
T7 /workspace/coverage/default/9.prim_async_alert.2760746268 Mar 17 12:25:11 PM PDT 24 Mar 17 12:25:12 PM PDT 24 11831604 ps
T8 /workspace/coverage/default/19.prim_async_alert.1076317531 Mar 17 12:24:53 PM PDT 24 Mar 17 12:24:53 PM PDT 24 11033747 ps
T16 /workspace/coverage/default/3.prim_async_alert.2321341129 Mar 17 12:23:17 PM PDT 24 Mar 17 12:23:18 PM PDT 24 10217539 ps
T17 /workspace/coverage/default/2.prim_async_alert.2220898914 Mar 17 12:25:11 PM PDT 24 Mar 17 12:25:11 PM PDT 24 12020989 ps
T9 /workspace/coverage/default/17.prim_async_alert.3173791688 Mar 17 12:27:59 PM PDT 24 Mar 17 12:28:01 PM PDT 24 11849067 ps
T10 /workspace/coverage/default/6.prim_async_alert.1496385110 Mar 17 12:27:45 PM PDT 24 Mar 17 12:27:46 PM PDT 24 11228024 ps
T18 /workspace/coverage/default/16.prim_async_alert.4155738543 Mar 17 12:25:23 PM PDT 24 Mar 17 12:25:23 PM PDT 24 11408196 ps
T14 /workspace/coverage/default/15.prim_async_alert.453493842 Mar 17 12:27:52 PM PDT 24 Mar 17 12:27:53 PM PDT 24 10987807 ps
T11 /workspace/coverage/default/0.prim_async_alert.2510755353 Mar 17 12:27:40 PM PDT 24 Mar 17 12:27:40 PM PDT 24 12045214 ps
T19 /workspace/coverage/default/10.prim_async_alert.3277837690 Mar 17 12:24:01 PM PDT 24 Mar 17 12:24:02 PM PDT 24 10780040 ps
T25 /workspace/coverage/default/5.prim_async_alert.3757056168 Mar 17 12:27:58 PM PDT 24 Mar 17 12:28:00 PM PDT 24 11566195 ps
T20 /workspace/coverage/default/12.prim_async_alert.1205891036 Mar 17 12:24:29 PM PDT 24 Mar 17 12:24:30 PM PDT 24 11246297 ps
T47 /workspace/coverage/default/1.prim_async_alert.1364170607 Mar 17 12:26:06 PM PDT 24 Mar 17 12:26:07 PM PDT 24 11274443 ps
T21 /workspace/coverage/default/18.prim_async_alert.2266176847 Mar 17 12:28:06 PM PDT 24 Mar 17 12:28:07 PM PDT 24 11120382 ps
T15 /workspace/coverage/default/14.prim_async_alert.3488862998 Mar 17 12:27:24 PM PDT 24 Mar 17 12:27:25 PM PDT 24 11932356 ps
T22 /workspace/coverage/default/8.prim_async_alert.3688690418 Mar 17 12:24:14 PM PDT 24 Mar 17 12:24:15 PM PDT 24 12241731 ps
T48 /workspace/coverage/default/11.prim_async_alert.3549997252 Mar 17 12:24:29 PM PDT 24 Mar 17 12:24:30 PM PDT 24 11148963 ps
T39 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1988729770 Mar 17 12:24:58 PM PDT 24 Mar 17 12:24:59 PM PDT 24 28348058 ps
T23 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2287038606 Mar 17 12:28:07 PM PDT 24 Mar 17 12:28:08 PM PDT 24 29147327 ps
T40 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2715561150 Mar 17 12:26:21 PM PDT 24 Mar 17 12:26:22 PM PDT 24 32239656 ps
T24 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3000011912 Mar 17 12:28:06 PM PDT 24 Mar 17 12:28:08 PM PDT 24 30683466 ps
T41 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2724555830 Mar 17 12:26:22 PM PDT 24 Mar 17 12:26:23 PM PDT 24 30700245 ps
T42 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.944569771 Mar 17 12:27:43 PM PDT 24 Mar 17 12:27:43 PM PDT 24 30766048 ps
T43 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3501849101 Mar 17 12:25:08 PM PDT 24 Mar 17 12:25:09 PM PDT 24 29131478 ps
T44 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1229684949 Mar 17 12:25:20 PM PDT 24 Mar 17 12:25:21 PM PDT 24 29050852 ps
T45 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.593402633 Mar 17 12:28:08 PM PDT 24 Mar 17 12:28:10 PM PDT 24 28519857 ps
T46 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1410875987 Mar 17 12:24:29 PM PDT 24 Mar 17 12:24:30 PM PDT 24 30198594 ps
T12 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3474813632 Mar 17 12:27:59 PM PDT 24 Mar 17 12:28:01 PM PDT 24 28413143 ps
T49 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2439315568 Mar 17 12:25:57 PM PDT 24 Mar 17 12:25:57 PM PDT 24 29973555 ps
T50 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.433694326 Mar 17 12:28:07 PM PDT 24 Mar 17 12:28:08 PM PDT 24 29820091 ps
T51 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1159787656 Mar 17 12:23:41 PM PDT 24 Mar 17 12:23:42 PM PDT 24 29826427 ps
T52 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4083856285 Mar 17 12:27:32 PM PDT 24 Mar 17 12:27:32 PM PDT 24 32559890 ps
T53 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.783544747 Mar 17 12:28:07 PM PDT 24 Mar 17 12:28:08 PM PDT 24 29943252 ps
T54 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3377802337 Mar 17 12:23:46 PM PDT 24 Mar 17 12:23:47 PM PDT 24 29657653 ps
T38 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.636932606 Mar 17 12:23:32 PM PDT 24 Mar 17 12:23:33 PM PDT 24 31720012 ps
T55 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1286932819 Mar 17 12:24:29 PM PDT 24 Mar 17 12:24:30 PM PDT 24 30911332 ps
T26 /workspace/coverage/sync_alert/6.prim_sync_alert.1477270701 Mar 17 12:21:22 PM PDT 24 Mar 17 12:21:23 PM PDT 24 8889002 ps
T27 /workspace/coverage/sync_alert/2.prim_sync_alert.1445351245 Mar 17 12:21:17 PM PDT 24 Mar 17 12:21:17 PM PDT 24 8982201 ps
T28 /workspace/coverage/sync_alert/19.prim_sync_alert.3008079282 Mar 17 12:21:17 PM PDT 24 Mar 17 12:21:17 PM PDT 24 8717417 ps
T36 /workspace/coverage/sync_alert/15.prim_sync_alert.1875197053 Mar 17 12:21:21 PM PDT 24 Mar 17 12:21:21 PM PDT 24 8931142 ps
T29 /workspace/coverage/sync_alert/9.prim_sync_alert.1324306346 Mar 17 12:21:17 PM PDT 24 Mar 17 12:21:18 PM PDT 24 9147753 ps
T30 /workspace/coverage/sync_alert/7.prim_sync_alert.3976145377 Mar 17 12:21:18 PM PDT 24 Mar 17 12:21:19 PM PDT 24 8782983 ps
T31 /workspace/coverage/sync_alert/17.prim_sync_alert.1702891779 Mar 17 12:21:30 PM PDT 24 Mar 17 12:21:30 PM PDT 24 9302021 ps
T32 /workspace/coverage/sync_alert/1.prim_sync_alert.1243007355 Mar 17 12:21:17 PM PDT 24 Mar 17 12:21:18 PM PDT 24 9646909 ps
T37 /workspace/coverage/sync_alert/8.prim_sync_alert.1276864897 Mar 17 12:21:20 PM PDT 24 Mar 17 12:21:21 PM PDT 24 8957159 ps
T33 /workspace/coverage/sync_alert/16.prim_sync_alert.2028766275 Mar 17 12:21:30 PM PDT 24 Mar 17 12:21:30 PM PDT 24 10204624 ps
T34 /workspace/coverage/sync_alert/13.prim_sync_alert.715569012 Mar 17 12:21:19 PM PDT 24 Mar 17 12:21:19 PM PDT 24 9832790 ps
T35 /workspace/coverage/sync_alert/3.prim_sync_alert.1157636208 Mar 17 12:21:19 PM PDT 24 Mar 17 12:21:19 PM PDT 24 9852984 ps
T13 /workspace/coverage/sync_alert/14.prim_sync_alert.123677024 Mar 17 12:21:27 PM PDT 24 Mar 17 12:21:28 PM PDT 24 10154861 ps
T56 /workspace/coverage/sync_alert/4.prim_sync_alert.74618728 Mar 17 12:21:19 PM PDT 24 Mar 17 12:21:19 PM PDT 24 9804027 ps
T57 /workspace/coverage/sync_alert/5.prim_sync_alert.116987597 Mar 17 12:21:21 PM PDT 24 Mar 17 12:21:21 PM PDT 24 8808717 ps
T58 /workspace/coverage/sync_alert/18.prim_sync_alert.1856812557 Mar 17 12:21:19 PM PDT 24 Mar 17 12:21:20 PM PDT 24 9044037 ps
T59 /workspace/coverage/sync_alert/0.prim_sync_alert.620543307 Mar 17 12:21:09 PM PDT 24 Mar 17 12:21:10 PM PDT 24 10037317 ps
T60 /workspace/coverage/sync_alert/11.prim_sync_alert.482935806 Mar 17 12:21:18 PM PDT 24 Mar 17 12:21:19 PM PDT 24 8795149 ps
T61 /workspace/coverage/sync_alert/12.prim_sync_alert.1266330059 Mar 17 12:21:19 PM PDT 24 Mar 17 12:21:20 PM PDT 24 9007132 ps
T62 /workspace/coverage/sync_alert/10.prim_sync_alert.3361327134 Mar 17 12:21:22 PM PDT 24 Mar 17 12:21:22 PM PDT 24 9368336 ps
T4 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3363469694 Mar 17 12:39:21 PM PDT 24 Mar 17 12:39:21 PM PDT 24 28087806 ps
T63 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3596365811 Mar 17 12:39:18 PM PDT 24 Mar 17 12:39:19 PM PDT 24 29086879 ps
T64 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3485011713 Mar 17 12:39:25 PM PDT 24 Mar 17 12:39:25 PM PDT 24 26897579 ps
T65 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3317549725 Mar 17 12:39:17 PM PDT 24 Mar 17 12:39:17 PM PDT 24 25749776 ps
T66 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.110250098 Mar 17 12:39:23 PM PDT 24 Mar 17 12:39:23 PM PDT 24 26519425 ps
T67 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2275694920 Mar 17 12:39:21 PM PDT 24 Mar 17 12:39:22 PM PDT 24 28832660 ps
T5 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3937376488 Mar 17 12:39:26 PM PDT 24 Mar 17 12:39:26 PM PDT 24 26981625 ps
T68 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3858474274 Mar 17 12:39:23 PM PDT 24 Mar 17 12:39:24 PM PDT 24 28399607 ps
T69 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1596201965 Mar 17 12:39:17 PM PDT 24 Mar 17 12:39:17 PM PDT 24 27928425 ps
T70 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.781757635 Mar 17 12:39:17 PM PDT 24 Mar 17 12:39:17 PM PDT 24 25640244 ps
T71 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3179333744 Mar 17 12:39:14 PM PDT 24 Mar 17 12:39:15 PM PDT 24 26203952 ps
T72 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.385523551 Mar 17 12:39:16 PM PDT 24 Mar 17 12:39:16 PM PDT 24 29666012 ps
T73 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1335781546 Mar 17 12:39:22 PM PDT 24 Mar 17 12:39:22 PM PDT 24 28511589 ps
T74 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1788590537 Mar 17 12:39:18 PM PDT 24 Mar 17 12:39:19 PM PDT 24 28188772 ps
T6 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1542642075 Mar 17 12:39:20 PM PDT 24 Mar 17 12:39:20 PM PDT 24 26027961 ps
T75 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.280664634 Mar 17 12:39:19 PM PDT 24 Mar 17 12:39:19 PM PDT 24 28414166 ps
T76 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4170056422 Mar 17 12:39:16 PM PDT 24 Mar 17 12:39:16 PM PDT 24 25890661 ps
T77 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.499714564 Mar 17 12:39:17 PM PDT 24 Mar 17 12:39:18 PM PDT 24 26973303 ps
T78 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1346831205 Mar 17 12:39:17 PM PDT 24 Mar 17 12:39:18 PM PDT 24 27624911 ps
T79 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.63200826 Mar 17 12:39:25 PM PDT 24 Mar 17 12:39:25 PM PDT 24 26519615 ps

Test location /workspace/coverage/default/13.prim_async_alert.3673429545
Short name T1
Test name
Test status
Simulation time 11233514 ps
CPU time 0.44 seconds
Started Mar 17 12:27:52 PM PDT 24
Finished Mar 17 12:27:53 PM PDT 24
Peak memory 143844 kb
Host smart-b8960bd5-eae5-4ca9-8729-8539c03e3abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673429545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3673429545
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1875197053
Short name T36
Test name
Test status
Simulation time 8931142 ps
CPU time 0.39 seconds
Started Mar 17 12:21:21 PM PDT 24
Finished Mar 17 12:21:21 PM PDT 24
Peak memory 145040 kb
Host smart-f647e57d-a1fb-4fe6-b291-0759bddb1971
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1875197053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1875197053
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3000011912
Short name T24
Test name
Test status
Simulation time 30683466 ps
CPU time 0.39 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 145628 kb
Host smart-e2d79c6c-67f4-43ca-88e3-cf1241d5cb3c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3000011912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3000011912
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3173791688
Short name T9
Test name
Test status
Simulation time 11849067 ps
CPU time 0.4 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:01 PM PDT 24
Peak memory 145236 kb
Host smart-7e5f3ee0-603b-4d29-a421-66629306076f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173791688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3173791688
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1364170607
Short name T47
Test name
Test status
Simulation time 11274443 ps
CPU time 0.43 seconds
Started Mar 17 12:26:06 PM PDT 24
Finished Mar 17 12:26:07 PM PDT 24
Peak memory 144076 kb
Host smart-b7d8a63a-2b67-4b93-a919-dd9d56a54481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364170607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1364170607
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3937376488
Short name T5
Test name
Test status
Simulation time 26981625 ps
CPU time 0.4 seconds
Started Mar 17 12:39:26 PM PDT 24
Finished Mar 17 12:39:26 PM PDT 24
Peak memory 144984 kb
Host smart-9263fe58-3d32-4c77-89b3-1eac5e373c9c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3937376488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3937376488
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2510755353
Short name T11
Test name
Test status
Simulation time 12045214 ps
CPU time 0.38 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:27:40 PM PDT 24
Peak memory 145652 kb
Host smart-721d34d3-00f4-4387-b0ef-2e62dc082994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510755353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2510755353
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3277837690
Short name T19
Test name
Test status
Simulation time 10780040 ps
CPU time 0.42 seconds
Started Mar 17 12:24:01 PM PDT 24
Finished Mar 17 12:24:02 PM PDT 24
Peak memory 145632 kb
Host smart-364dbc42-26c6-4230-8519-03f1e1058ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277837690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3277837690
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3549997252
Short name T48
Test name
Test status
Simulation time 11148963 ps
CPU time 0.39 seconds
Started Mar 17 12:24:29 PM PDT 24
Finished Mar 17 12:24:30 PM PDT 24
Peak memory 145696 kb
Host smart-3cebb2dd-82cc-4755-947b-ca9ebef3aaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549997252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3549997252
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1205891036
Short name T20
Test name
Test status
Simulation time 11246297 ps
CPU time 0.4 seconds
Started Mar 17 12:24:29 PM PDT 24
Finished Mar 17 12:24:30 PM PDT 24
Peak memory 145696 kb
Host smart-db980e2e-ec54-4a84-8e91-ad9fbac60cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205891036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1205891036
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3488862998
Short name T15
Test name
Test status
Simulation time 11932356 ps
CPU time 0.4 seconds
Started Mar 17 12:27:24 PM PDT 24
Finished Mar 17 12:27:25 PM PDT 24
Peak memory 145192 kb
Host smart-0ab90a39-ed4d-44a4-b350-4fcca80ca7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488862998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3488862998
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.453493842
Short name T14
Test name
Test status
Simulation time 10987807 ps
CPU time 0.43 seconds
Started Mar 17 12:27:52 PM PDT 24
Finished Mar 17 12:27:53 PM PDT 24
Peak memory 143648 kb
Host smart-dec2b83f-e8e0-4505-aefa-5e25a613b5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453493842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.453493842
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.4155738543
Short name T18
Test name
Test status
Simulation time 11408196 ps
CPU time 0.39 seconds
Started Mar 17 12:25:23 PM PDT 24
Finished Mar 17 12:25:23 PM PDT 24
Peak memory 145688 kb
Host smart-ee2f977b-8d8c-4e19-b015-6a6fb3abc3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155738543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.4155738543
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2266176847
Short name T21
Test name
Test status
Simulation time 11120382 ps
CPU time 0.37 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:07 PM PDT 24
Peak memory 145608 kb
Host smart-2ab6cdc2-2f15-4666-bfa1-6ed4d449efd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266176847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2266176847
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1076317531
Short name T8
Test name
Test status
Simulation time 11033747 ps
CPU time 0.45 seconds
Started Mar 17 12:24:53 PM PDT 24
Finished Mar 17 12:24:53 PM PDT 24
Peak memory 145720 kb
Host smart-182ed0e4-e9cf-4c6b-90bc-0eedb916efe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076317531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1076317531
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2220898914
Short name T17
Test name
Test status
Simulation time 12020989 ps
CPU time 0.4 seconds
Started Mar 17 12:25:11 PM PDT 24
Finished Mar 17 12:25:11 PM PDT 24
Peak memory 145720 kb
Host smart-0adf99e5-b729-4a2a-9355-7ee87d686a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220898914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2220898914
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2321341129
Short name T16
Test name
Test status
Simulation time 10217539 ps
CPU time 0.49 seconds
Started Mar 17 12:23:17 PM PDT 24
Finished Mar 17 12:23:18 PM PDT 24
Peak memory 144444 kb
Host smart-43147861-4411-4e7b-8a25-028602501940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321341129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2321341129
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.215943953
Short name T3
Test name
Test status
Simulation time 11459355 ps
CPU time 0.41 seconds
Started Mar 17 12:25:08 PM PDT 24
Finished Mar 17 12:25:09 PM PDT 24
Peak memory 145608 kb
Host smart-7d284600-fe6e-4bad-b28f-db2a3500cdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215943953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.215943953
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3757056168
Short name T25
Test name
Test status
Simulation time 11566195 ps
CPU time 0.45 seconds
Started Mar 17 12:27:58 PM PDT 24
Finished Mar 17 12:28:00 PM PDT 24
Peak memory 143756 kb
Host smart-946a6506-96a1-476c-a37b-8d418cca8d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757056168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3757056168
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1496385110
Short name T10
Test name
Test status
Simulation time 11228024 ps
CPU time 0.44 seconds
Started Mar 17 12:27:45 PM PDT 24
Finished Mar 17 12:27:46 PM PDT 24
Peak memory 144304 kb
Host smart-a9ad9787-7d93-4e05-94cf-4555379c0a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496385110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1496385110
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.4078711697
Short name T2
Test name
Test status
Simulation time 11281606 ps
CPU time 0.38 seconds
Started Mar 17 12:24:16 PM PDT 24
Finished Mar 17 12:24:17 PM PDT 24
Peak memory 145672 kb
Host smart-f818b8db-f47c-4ba4-9619-3068a029d1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078711697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.4078711697
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3688690418
Short name T22
Test name
Test status
Simulation time 12241731 ps
CPU time 0.41 seconds
Started Mar 17 12:24:14 PM PDT 24
Finished Mar 17 12:24:15 PM PDT 24
Peak memory 145712 kb
Host smart-d4e47682-17b3-4a9f-831f-d43f20eead8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688690418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3688690418
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2760746268
Short name T7
Test name
Test status
Simulation time 11831604 ps
CPU time 0.41 seconds
Started Mar 17 12:25:11 PM PDT 24
Finished Mar 17 12:25:12 PM PDT 24
Peak memory 145800 kb
Host smart-7e7d7364-4de8-4669-afa2-0cdc89fd30a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760746268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2760746268
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4083856285
Short name T52
Test name
Test status
Simulation time 32559890 ps
CPU time 0.39 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:27:32 PM PDT 24
Peak memory 145628 kb
Host smart-3d8eb6d2-b25e-48ee-a67d-2d58bb986511
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4083856285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4083856285
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3377802337
Short name T54
Test name
Test status
Simulation time 29657653 ps
CPU time 0.48 seconds
Started Mar 17 12:23:46 PM PDT 24
Finished Mar 17 12:23:47 PM PDT 24
Peak memory 143852 kb
Host smart-f110f1cd-a2c7-4846-9b78-67be2789d7bc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3377802337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3377802337
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1410875987
Short name T46
Test name
Test status
Simulation time 30198594 ps
CPU time 0.41 seconds
Started Mar 17 12:24:29 PM PDT 24
Finished Mar 17 12:24:30 PM PDT 24
Peak memory 145680 kb
Host smart-f7d4edde-f77f-4543-9f8f-c2606cdd76f6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1410875987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1410875987
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2439315568
Short name T49
Test name
Test status
Simulation time 29973555 ps
CPU time 0.41 seconds
Started Mar 17 12:25:57 PM PDT 24
Finished Mar 17 12:25:57 PM PDT 24
Peak memory 145972 kb
Host smart-a9fb5c5f-a2ca-4860-8d7a-59cef1984602
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2439315568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2439315568
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.433694326
Short name T50
Test name
Test status
Simulation time 29820091 ps
CPU time 0.41 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 145644 kb
Host smart-515551bf-b213-43b1-8570-c9d5560d2045
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=433694326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.433694326
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2724555830
Short name T41
Test name
Test status
Simulation time 30700245 ps
CPU time 0.41 seconds
Started Mar 17 12:26:22 PM PDT 24
Finished Mar 17 12:26:23 PM PDT 24
Peak memory 145616 kb
Host smart-bd7435f4-4c1f-4d51-aa26-ee2b7213323f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2724555830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2724555830
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2287038606
Short name T23
Test name
Test status
Simulation time 29147327 ps
CPU time 0.42 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 145628 kb
Host smart-b58ddabc-66ae-4079-84b4-dba210ebd1b0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2287038606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2287038606
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2715561150
Short name T40
Test name
Test status
Simulation time 32239656 ps
CPU time 0.41 seconds
Started Mar 17 12:26:21 PM PDT 24
Finished Mar 17 12:26:22 PM PDT 24
Peak memory 145604 kb
Host smart-6fafb7b2-f007-402a-b2b9-386e2816f46b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2715561150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2715561150
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.636932606
Short name T38
Test name
Test status
Simulation time 31720012 ps
CPU time 0.42 seconds
Started Mar 17 12:23:32 PM PDT 24
Finished Mar 17 12:23:33 PM PDT 24
Peak memory 145656 kb
Host smart-ea04c535-616a-4042-84c3-a6488d9f72bc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=636932606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.636932606
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.593402633
Short name T45
Test name
Test status
Simulation time 28519857 ps
CPU time 0.38 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 145632 kb
Host smart-56ef150d-6fa4-4523-a87e-6075f898972a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=593402633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.593402633
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1286932819
Short name T55
Test name
Test status
Simulation time 30911332 ps
CPU time 0.42 seconds
Started Mar 17 12:24:29 PM PDT 24
Finished Mar 17 12:24:30 PM PDT 24
Peak memory 145820 kb
Host smart-026a447a-a5b3-465b-8b69-7b69facdc2f1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1286932819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1286932819
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3474813632
Short name T12
Test name
Test status
Simulation time 28413143 ps
CPU time 0.41 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:01 PM PDT 24
Peak memory 145344 kb
Host smart-d3eceef9-e729-454c-b547-fcc2ffcd9d74
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3474813632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3474813632
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1159787656
Short name T51
Test name
Test status
Simulation time 29826427 ps
CPU time 0.54 seconds
Started Mar 17 12:23:41 PM PDT 24
Finished Mar 17 12:23:42 PM PDT 24
Peak memory 143620 kb
Host smart-2118f6a9-8de7-408c-8466-3e8d5355c389
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1159787656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1159787656
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3501849101
Short name T43
Test name
Test status
Simulation time 29131478 ps
CPU time 0.43 seconds
Started Mar 17 12:25:08 PM PDT 24
Finished Mar 17 12:25:09 PM PDT 24
Peak memory 145740 kb
Host smart-ed9e2639-3ede-4ef4-86a9-b54feb289c4f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3501849101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3501849101
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1229684949
Short name T44
Test name
Test status
Simulation time 29050852 ps
CPU time 0.42 seconds
Started Mar 17 12:25:20 PM PDT 24
Finished Mar 17 12:25:21 PM PDT 24
Peak memory 145632 kb
Host smart-498b00cd-dff3-42fd-8a79-98ef96643171
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1229684949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1229684949
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.783544747
Short name T53
Test name
Test status
Simulation time 29943252 ps
CPU time 0.4 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 145644 kb
Host smart-51eef1a9-957c-4a2d-8902-87a4182780b4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=783544747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.783544747
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.944569771
Short name T42
Test name
Test status
Simulation time 30766048 ps
CPU time 0.4 seconds
Started Mar 17 12:27:43 PM PDT 24
Finished Mar 17 12:27:43 PM PDT 24
Peak memory 145428 kb
Host smart-d4d078e9-03d0-468c-864d-e296246b6dbe
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=944569771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.944569771
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1988729770
Short name T39
Test name
Test status
Simulation time 28348058 ps
CPU time 0.41 seconds
Started Mar 17 12:24:58 PM PDT 24
Finished Mar 17 12:24:59 PM PDT 24
Peak memory 145740 kb
Host smart-bbd04122-3f23-47b1-939b-3c9e79ebb5a7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1988729770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1988729770
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.620543307
Short name T59
Test name
Test status
Simulation time 10037317 ps
CPU time 0.37 seconds
Started Mar 17 12:21:09 PM PDT 24
Finished Mar 17 12:21:10 PM PDT 24
Peak memory 145216 kb
Host smart-7bfa05bd-6856-4adf-8244-ed19b45f5618
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=620543307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.620543307
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1243007355
Short name T32
Test name
Test status
Simulation time 9646909 ps
CPU time 0.39 seconds
Started Mar 17 12:21:17 PM PDT 24
Finished Mar 17 12:21:18 PM PDT 24
Peak memory 144576 kb
Host smart-8727f9e4-131c-4c09-97f1-2634151c77de
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1243007355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1243007355
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3361327134
Short name T62
Test name
Test status
Simulation time 9368336 ps
CPU time 0.39 seconds
Started Mar 17 12:21:22 PM PDT 24
Finished Mar 17 12:21:22 PM PDT 24
Peak memory 145040 kb
Host smart-abf74e6c-dc5d-43f6-b905-71ed33061958
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3361327134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3361327134
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.482935806
Short name T60
Test name
Test status
Simulation time 8795149 ps
CPU time 0.4 seconds
Started Mar 17 12:21:18 PM PDT 24
Finished Mar 17 12:21:19 PM PDT 24
Peak memory 144728 kb
Host smart-1e648650-ea24-41f5-a2ac-844e502915d3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=482935806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.482935806
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1266330059
Short name T61
Test name
Test status
Simulation time 9007132 ps
CPU time 0.41 seconds
Started Mar 17 12:21:19 PM PDT 24
Finished Mar 17 12:21:20 PM PDT 24
Peak memory 144740 kb
Host smart-47d482b0-8445-4045-8b42-d58c9db2c98b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1266330059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1266330059
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.715569012
Short name T34
Test name
Test status
Simulation time 9832790 ps
CPU time 0.37 seconds
Started Mar 17 12:21:19 PM PDT 24
Finished Mar 17 12:21:19 PM PDT 24
Peak memory 143872 kb
Host smart-794a6443-e844-40b3-a4c0-9e05bebe0b13
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=715569012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.715569012
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.123677024
Short name T13
Test name
Test status
Simulation time 10154861 ps
CPU time 0.37 seconds
Started Mar 17 12:21:27 PM PDT 24
Finished Mar 17 12:21:28 PM PDT 24
Peak memory 144736 kb
Host smart-86e6d1aa-4ac8-44b9-9393-d0f87c1115eb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=123677024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.123677024
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2028766275
Short name T33
Test name
Test status
Simulation time 10204624 ps
CPU time 0.37 seconds
Started Mar 17 12:21:30 PM PDT 24
Finished Mar 17 12:21:30 PM PDT 24
Peak memory 144972 kb
Host smart-8762a2de-f931-4e90-a421-f0692125a1cb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2028766275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2028766275
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1702891779
Short name T31
Test name
Test status
Simulation time 9302021 ps
CPU time 0.37 seconds
Started Mar 17 12:21:30 PM PDT 24
Finished Mar 17 12:21:30 PM PDT 24
Peak memory 144892 kb
Host smart-65cace63-7a7c-4b51-ad5a-98e8fa0632a1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1702891779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1702891779
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1856812557
Short name T58
Test name
Test status
Simulation time 9044037 ps
CPU time 0.41 seconds
Started Mar 17 12:21:19 PM PDT 24
Finished Mar 17 12:21:20 PM PDT 24
Peak memory 144620 kb
Host smart-b46b322d-4b03-40e6-9282-630e42c1bacf
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1856812557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1856812557
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3008079282
Short name T28
Test name
Test status
Simulation time 8717417 ps
CPU time 0.4 seconds
Started Mar 17 12:21:17 PM PDT 24
Finished Mar 17 12:21:17 PM PDT 24
Peak memory 144608 kb
Host smart-8154d9b1-45d6-4314-83ed-15e6a1111971
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3008079282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3008079282
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1445351245
Short name T27
Test name
Test status
Simulation time 8982201 ps
CPU time 0.54 seconds
Started Mar 17 12:21:17 PM PDT 24
Finished Mar 17 12:21:17 PM PDT 24
Peak memory 144232 kb
Host smart-4d8eaaab-4413-440f-b33c-30ba48cc28da
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1445351245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1445351245
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1157636208
Short name T35
Test name
Test status
Simulation time 9852984 ps
CPU time 0.38 seconds
Started Mar 17 12:21:19 PM PDT 24
Finished Mar 17 12:21:19 PM PDT 24
Peak memory 143900 kb
Host smart-e767cb83-4d41-45c6-9654-cc0aaa9d671d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1157636208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1157636208
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.74618728
Short name T56
Test name
Test status
Simulation time 9804027 ps
CPU time 0.38 seconds
Started Mar 17 12:21:19 PM PDT 24
Finished Mar 17 12:21:19 PM PDT 24
Peak memory 144544 kb
Host smart-37cb39c0-1118-4c6c-b003-682ccf00e247
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=74618728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.74618728
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.116987597
Short name T57
Test name
Test status
Simulation time 8808717 ps
CPU time 0.39 seconds
Started Mar 17 12:21:21 PM PDT 24
Finished Mar 17 12:21:21 PM PDT 24
Peak memory 145032 kb
Host smart-bd8351de-1647-4235-aa86-d9055362c57a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=116987597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.116987597
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1477270701
Short name T26
Test name
Test status
Simulation time 8889002 ps
CPU time 0.42 seconds
Started Mar 17 12:21:22 PM PDT 24
Finished Mar 17 12:21:23 PM PDT 24
Peak memory 145428 kb
Host smart-a720ac7b-47b7-4624-9632-af1bc2fa8b17
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1477270701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1477270701
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3976145377
Short name T30
Test name
Test status
Simulation time 8782983 ps
CPU time 0.38 seconds
Started Mar 17 12:21:18 PM PDT 24
Finished Mar 17 12:21:19 PM PDT 24
Peak memory 144740 kb
Host smart-3e4e7358-e601-4ba6-989b-d049c4bf11f2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3976145377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3976145377
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1276864897
Short name T37
Test name
Test status
Simulation time 8957159 ps
CPU time 0.38 seconds
Started Mar 17 12:21:20 PM PDT 24
Finished Mar 17 12:21:21 PM PDT 24
Peak memory 144740 kb
Host smart-a9025b23-0471-48fc-b860-a6835c7711bb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1276864897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1276864897
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1324306346
Short name T29
Test name
Test status
Simulation time 9147753 ps
CPU time 0.37 seconds
Started Mar 17 12:21:17 PM PDT 24
Finished Mar 17 12:21:18 PM PDT 24
Peak memory 144536 kb
Host smart-77fe202d-2f85-4e99-beb2-f13d0119b30c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1324306346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1324306346
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.280664634
Short name T75
Test name
Test status
Simulation time 28414166 ps
CPU time 0.43 seconds
Started Mar 17 12:39:19 PM PDT 24
Finished Mar 17 12:39:19 PM PDT 24
Peak memory 144936 kb
Host smart-f28b694d-6c62-4493-9961-00b65846cc5f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=280664634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.280664634
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.385523551
Short name T72
Test name
Test status
Simulation time 29666012 ps
CPU time 0.38 seconds
Started Mar 17 12:39:16 PM PDT 24
Finished Mar 17 12:39:16 PM PDT 24
Peak memory 144964 kb
Host smart-be13dc1c-982d-4652-9189-07e7d3639180
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=385523551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.385523551
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1788590537
Short name T74
Test name
Test status
Simulation time 28188772 ps
CPU time 0.38 seconds
Started Mar 17 12:39:18 PM PDT 24
Finished Mar 17 12:39:19 PM PDT 24
Peak memory 145016 kb
Host smart-78102e62-0adf-42dd-9d75-616ef77ba75b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1788590537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1788590537
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1335781546
Short name T73
Test name
Test status
Simulation time 28511589 ps
CPU time 0.4 seconds
Started Mar 17 12:39:22 PM PDT 24
Finished Mar 17 12:39:22 PM PDT 24
Peak memory 144964 kb
Host smart-2b856271-72bb-4b98-8821-55343bc86aaf
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1335781546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1335781546
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3858474274
Short name T68
Test name
Test status
Simulation time 28399607 ps
CPU time 0.39 seconds
Started Mar 17 12:39:23 PM PDT 24
Finished Mar 17 12:39:24 PM PDT 24
Peak memory 144960 kb
Host smart-0673f0f8-bf35-4537-a185-fc5c93080eb7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3858474274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3858474274
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.110250098
Short name T66
Test name
Test status
Simulation time 26519425 ps
CPU time 0.38 seconds
Started Mar 17 12:39:23 PM PDT 24
Finished Mar 17 12:39:23 PM PDT 24
Peak memory 145000 kb
Host smart-63c5cb08-e000-4451-9638-31f01f4dea10
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=110250098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.110250098
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3485011713
Short name T64
Test name
Test status
Simulation time 26897579 ps
CPU time 0.39 seconds
Started Mar 17 12:39:25 PM PDT 24
Finished Mar 17 12:39:25 PM PDT 24
Peak memory 144948 kb
Host smart-33c01cb4-aae2-4c35-904e-6fac603e1774
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3485011713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3485011713
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2275694920
Short name T67
Test name
Test status
Simulation time 28832660 ps
CPU time 0.38 seconds
Started Mar 17 12:39:21 PM PDT 24
Finished Mar 17 12:39:22 PM PDT 24
Peak memory 144948 kb
Host smart-4a96710b-73df-4320-a505-dd302cd9c628
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2275694920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2275694920
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3363469694
Short name T4
Test name
Test status
Simulation time 28087806 ps
CPU time 0.39 seconds
Started Mar 17 12:39:21 PM PDT 24
Finished Mar 17 12:39:21 PM PDT 24
Peak memory 144968 kb
Host smart-b1f55128-98c6-4e6e-af80-3261f2059ea2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3363469694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3363469694
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1542642075
Short name T6
Test name
Test status
Simulation time 26027961 ps
CPU time 0.37 seconds
Started Mar 17 12:39:20 PM PDT 24
Finished Mar 17 12:39:20 PM PDT 24
Peak memory 144952 kb
Host smart-503e991b-1c36-4366-926c-115c68688f3e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1542642075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1542642075
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.63200826
Short name T79
Test name
Test status
Simulation time 26519615 ps
CPU time 0.39 seconds
Started Mar 17 12:39:25 PM PDT 24
Finished Mar 17 12:39:25 PM PDT 24
Peak memory 144948 kb
Host smart-04efa07c-6ce3-4d6f-a196-0b199b94bb0f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=63200826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.63200826
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1346831205
Short name T78
Test name
Test status
Simulation time 27624911 ps
CPU time 0.39 seconds
Started Mar 17 12:39:17 PM PDT 24
Finished Mar 17 12:39:18 PM PDT 24
Peak memory 145008 kb
Host smart-579fde02-8678-4425-bf14-23c1b5c37ac4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1346831205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1346831205
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.499714564
Short name T77
Test name
Test status
Simulation time 26973303 ps
CPU time 0.41 seconds
Started Mar 17 12:39:17 PM PDT 24
Finished Mar 17 12:39:18 PM PDT 24
Peak memory 144984 kb
Host smart-cf041b69-5379-4fed-9d5d-cab7a7f2438f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=499714564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.499714564
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3317549725
Short name T65
Test name
Test status
Simulation time 25749776 ps
CPU time 0.37 seconds
Started Mar 17 12:39:17 PM PDT 24
Finished Mar 17 12:39:17 PM PDT 24
Peak memory 144976 kb
Host smart-5b7df553-e544-4df6-aaa4-5881193bb1e7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3317549725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3317549725
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4170056422
Short name T76
Test name
Test status
Simulation time 25890661 ps
CPU time 0.37 seconds
Started Mar 17 12:39:16 PM PDT 24
Finished Mar 17 12:39:16 PM PDT 24
Peak memory 144956 kb
Host smart-09bd104d-cd6f-471a-ada2-cc548acee05e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4170056422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.4170056422
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3596365811
Short name T63
Test name
Test status
Simulation time 29086879 ps
CPU time 0.41 seconds
Started Mar 17 12:39:18 PM PDT 24
Finished Mar 17 12:39:19 PM PDT 24
Peak memory 144948 kb
Host smart-443ce822-6515-43c1-b69f-4b3b3e6ca79d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3596365811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3596365811
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1596201965
Short name T69
Test name
Test status
Simulation time 27928425 ps
CPU time 0.38 seconds
Started Mar 17 12:39:17 PM PDT 24
Finished Mar 17 12:39:17 PM PDT 24
Peak memory 144844 kb
Host smart-209ae4ed-4dcc-40e9-bd07-dbcfe8c61536
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1596201965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1596201965
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.781757635
Short name T70
Test name
Test status
Simulation time 25640244 ps
CPU time 0.38 seconds
Started Mar 17 12:39:17 PM PDT 24
Finished Mar 17 12:39:17 PM PDT 24
Peak memory 145036 kb
Host smart-f73205d6-aa42-41de-ba68-5f94169ba9b1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=781757635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.781757635
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3179333744
Short name T71
Test name
Test status
Simulation time 26203952 ps
CPU time 0.4 seconds
Started Mar 17 12:39:14 PM PDT 24
Finished Mar 17 12:39:15 PM PDT 24
Peak memory 145096 kb
Host smart-ca8edcfe-6eba-4021-899b-631bb218bb66
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3179333744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3179333744
Directory /workspace/9.prim_sync_fatal_alert/latest
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