| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 89.02 | 89.02 | 100.00 | 100.00 | 95.83 | 95.83 | 96.43 | 96.43 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/7.prim_async_alert.1801572353 |
| 92.49 | 3.48 | 100.00 | 0.00 | 97.92 | 2.08 | 96.43 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/8.prim_sync_alert.2947684889 |
| 94.85 | 2.35 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 3.57 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2744659270 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3429060434 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.3038054566 |
| /workspace/coverage/default/1.prim_async_alert.3049186762 |
| /workspace/coverage/default/10.prim_async_alert.3490243939 |
| /workspace/coverage/default/11.prim_async_alert.635971207 |
| /workspace/coverage/default/12.prim_async_alert.3015818296 |
| /workspace/coverage/default/13.prim_async_alert.1246043949 |
| /workspace/coverage/default/14.prim_async_alert.460569722 |
| /workspace/coverage/default/15.prim_async_alert.890575777 |
| /workspace/coverage/default/16.prim_async_alert.2105048980 |
| /workspace/coverage/default/17.prim_async_alert.3730340795 |
| /workspace/coverage/default/18.prim_async_alert.1010267632 |
| /workspace/coverage/default/19.prim_async_alert.71219219 |
| /workspace/coverage/default/3.prim_async_alert.3375032274 |
| /workspace/coverage/default/4.prim_async_alert.2968434958 |
| /workspace/coverage/default/5.prim_async_alert.3051035036 |
| /workspace/coverage/default/6.prim_async_alert.4185550945 |
| /workspace/coverage/default/8.prim_async_alert.2377925440 |
| /workspace/coverage/default/9.prim_async_alert.1062737686 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3345756404 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1273136896 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1906766810 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2817761685 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.789668616 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2603755537 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2597068965 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3867050415 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.436423844 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1321179903 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3941423120 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1240022257 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.440351414 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3014418782 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.413943532 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.269173124 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.3518198109 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.2312452423 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1048865764 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3444699299 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.2286604552 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.3301881268 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.4088143071 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.341730369 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.2544197991 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.4200626954 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.1467143945 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.3093862284 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3952062117 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.870409149 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.3786026042 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.758728527 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.3241493553 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.4199110951 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.205605374 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2546269558 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1284871605 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1622735184 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2950922863 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1603199185 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3772023881 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.847803399 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2931593550 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1636226303 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1037897571 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4056260833 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.993451107 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.4073683405 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1268191953 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2923785629 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4090598731 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.460818847 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3451525832 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3948863992 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/7.prim_async_alert.1801572353 | Mar 19 12:26:39 PM PDT 24 | Mar 19 12:26:41 PM PDT 24 | 11033401 ps | ||
| T2 | /workspace/coverage/default/11.prim_async_alert.635971207 | Mar 19 12:26:02 PM PDT 24 | Mar 19 12:26:04 PM PDT 24 | 11712216 ps | ||
| T3 | /workspace/coverage/default/19.prim_async_alert.71219219 | Mar 19 12:26:09 PM PDT 24 | Mar 19 12:26:10 PM PDT 24 | 10698142 ps | ||
| T7 | /workspace/coverage/default/4.prim_async_alert.2968434958 | Mar 19 12:26:16 PM PDT 24 | Mar 19 12:26:17 PM PDT 24 | 11920228 ps | ||
| T19 | /workspace/coverage/default/16.prim_async_alert.2105048980 | Mar 19 12:26:12 PM PDT 24 | Mar 19 12:26:13 PM PDT 24 | 11412650 ps | ||
| T20 | /workspace/coverage/default/18.prim_async_alert.1010267632 | Mar 19 12:26:15 PM PDT 24 | Mar 19 12:26:16 PM PDT 24 | 11186716 ps | ||
| T9 | /workspace/coverage/default/14.prim_async_alert.460569722 | Mar 19 12:26:51 PM PDT 24 | Mar 19 12:26:52 PM PDT 24 | 11260147 ps | ||
| T11 | /workspace/coverage/default/10.prim_async_alert.3490243939 | Mar 19 12:26:21 PM PDT 24 | Mar 19 12:26:22 PM PDT 24 | 12086631 ps | ||
| T8 | /workspace/coverage/default/17.prim_async_alert.3730340795 | Mar 19 12:26:23 PM PDT 24 | Mar 19 12:26:24 PM PDT 24 | 10697704 ps | ||
| T12 | /workspace/coverage/default/1.prim_async_alert.3049186762 | Mar 19 12:26:02 PM PDT 24 | Mar 19 12:26:04 PM PDT 24 | 11756814 ps | ||
| T21 | /workspace/coverage/default/0.prim_async_alert.3038054566 | Mar 19 12:25:56 PM PDT 24 | Mar 19 12:25:57 PM PDT 24 | 10391256 ps | ||
| T46 | /workspace/coverage/default/13.prim_async_alert.1246043949 | Mar 19 12:26:16 PM PDT 24 | Mar 19 12:26:16 PM PDT 24 | 10441409 ps | ||
| T22 | /workspace/coverage/default/12.prim_async_alert.3015818296 | Mar 19 12:26:18 PM PDT 24 | Mar 19 12:26:18 PM PDT 24 | 11592097 ps | ||
| T47 | /workspace/coverage/default/6.prim_async_alert.4185550945 | Mar 19 12:26:34 PM PDT 24 | Mar 19 12:26:34 PM PDT 24 | 11532258 ps | ||
| T48 | /workspace/coverage/default/9.prim_async_alert.1062737686 | Mar 19 12:26:30 PM PDT 24 | Mar 19 12:26:32 PM PDT 24 | 11670343 ps | ||
| T17 | /workspace/coverage/default/8.prim_async_alert.2377925440 | Mar 19 12:26:19 PM PDT 24 | Mar 19 12:26:20 PM PDT 24 | 11120271 ps | ||
| T23 | /workspace/coverage/default/15.prim_async_alert.890575777 | Mar 19 12:26:13 PM PDT 24 | Mar 19 12:26:13 PM PDT 24 | 11080058 ps | ||
| T24 | /workspace/coverage/default/3.prim_async_alert.3375032274 | Mar 19 12:27:13 PM PDT 24 | Mar 19 12:27:15 PM PDT 24 | 10846890 ps | ||
| T25 | /workspace/coverage/default/5.prim_async_alert.3051035036 | Mar 19 12:26:07 PM PDT 24 | Mar 19 12:26:08 PM PDT 24 | 11240155 ps | ||
| T4 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1240022257 | Mar 19 12:24:13 PM PDT 24 | Mar 19 12:24:14 PM PDT 24 | 30827243 ps | ||
| T26 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1321179903 | Mar 19 12:19:37 PM PDT 24 | Mar 19 12:19:38 PM PDT 24 | 30629924 ps | ||
| T5 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.436423844 | Mar 19 12:23:05 PM PDT 24 | Mar 19 12:23:07 PM PDT 24 | 32536945 ps | ||
| T6 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3429060434 | Mar 19 12:19:02 PM PDT 24 | Mar 19 12:19:03 PM PDT 24 | 30371087 ps | ||
| T13 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2744659270 | Mar 19 12:23:55 PM PDT 24 | Mar 19 12:23:56 PM PDT 24 | 30872446 ps | ||
| T43 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2817761685 | Mar 19 12:24:19 PM PDT 24 | Mar 19 12:24:19 PM PDT 24 | 30849714 ps | ||
| T44 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1273136896 | Mar 19 12:24:44 PM PDT 24 | Mar 19 12:24:45 PM PDT 24 | 31528567 ps | ||
| T16 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.413943532 | Mar 19 12:17:55 PM PDT 24 | Mar 19 12:17:56 PM PDT 24 | 30921806 ps | ||
| T45 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2597068965 | Mar 19 12:18:00 PM PDT 24 | Mar 19 12:18:01 PM PDT 24 | 29532779 ps | ||
| T42 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.440351414 | Mar 19 12:24:25 PM PDT 24 | Mar 19 12:24:26 PM PDT 24 | 30212872 ps | ||
| T49 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3345756404 | Mar 19 12:19:48 PM PDT 24 | Mar 19 12:19:48 PM PDT 24 | 29824492 ps | ||
| T50 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1906766810 | Mar 19 12:18:02 PM PDT 24 | Mar 19 12:18:03 PM PDT 24 | 31508017 ps | ||
| T51 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3867050415 | Mar 19 12:18:08 PM PDT 24 | Mar 19 12:18:08 PM PDT 24 | 29428940 ps | ||
| T14 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2603755537 | Mar 19 12:18:08 PM PDT 24 | Mar 19 12:18:09 PM PDT 24 | 32141238 ps | ||
| T52 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3941423120 | Mar 19 12:18:22 PM PDT 24 | Mar 19 12:18:23 PM PDT 24 | 31134097 ps | ||
| T53 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3014418782 | Mar 19 12:24:13 PM PDT 24 | Mar 19 12:24:14 PM PDT 24 | 30939555 ps | ||
| T18 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.789668616 | Mar 19 12:24:15 PM PDT 24 | Mar 19 12:24:16 PM PDT 24 | 31043872 ps | ||
| T27 | /workspace/coverage/sync_alert/16.prim_sync_alert.341730369 | Mar 19 12:26:51 PM PDT 24 | Mar 19 12:26:51 PM PDT 24 | 9846869 ps | ||
| T37 | /workspace/coverage/sync_alert/17.prim_sync_alert.2544197991 | Mar 19 12:26:18 PM PDT 24 | Mar 19 12:26:19 PM PDT 24 | 9276745 ps | ||
| T38 | /workspace/coverage/sync_alert/5.prim_sync_alert.3786026042 | Mar 19 12:26:39 PM PDT 24 | Mar 19 12:26:40 PM PDT 24 | 9505422 ps | ||
| T39 | /workspace/coverage/sync_alert/7.prim_sync_alert.3241493553 | Mar 19 12:26:26 PM PDT 24 | Mar 19 12:26:26 PM PDT 24 | 8248621 ps | ||
| T28 | /workspace/coverage/sync_alert/14.prim_sync_alert.3301881268 | Mar 19 12:27:41 PM PDT 24 | Mar 19 12:27:41 PM PDT 24 | 10637517 ps | ||
| T40 | /workspace/coverage/sync_alert/2.prim_sync_alert.3093862284 | Mar 19 12:27:25 PM PDT 24 | Mar 19 12:27:26 PM PDT 24 | 8805320 ps | ||
| T41 | /workspace/coverage/sync_alert/18.prim_sync_alert.4200626954 | Mar 19 12:26:22 PM PDT 24 | Mar 19 12:26:23 PM PDT 24 | 9851729 ps | ||
| T10 | /workspace/coverage/sync_alert/8.prim_sync_alert.2947684889 | Mar 19 12:26:17 PM PDT 24 | Mar 19 12:26:17 PM PDT 24 | 8436042 ps | ||
| T29 | /workspace/coverage/sync_alert/11.prim_sync_alert.1048865764 | Mar 19 12:26:14 PM PDT 24 | Mar 19 12:26:14 PM PDT 24 | 9692562 ps | ||
| T30 | /workspace/coverage/sync_alert/0.prim_sync_alert.269173124 | Mar 19 12:27:41 PM PDT 24 | Mar 19 12:27:41 PM PDT 24 | 9826308 ps | ||
| T54 | /workspace/coverage/sync_alert/13.prim_sync_alert.2286604552 | Mar 19 12:26:40 PM PDT 24 | Mar 19 12:26:41 PM PDT 24 | 8909304 ps | ||
| T55 | /workspace/coverage/sync_alert/3.prim_sync_alert.3952062117 | Mar 19 12:26:19 PM PDT 24 | Mar 19 12:26:19 PM PDT 24 | 8871598 ps | ||
| T31 | /workspace/coverage/sync_alert/15.prim_sync_alert.4088143071 | Mar 19 12:27:09 PM PDT 24 | Mar 19 12:27:13 PM PDT 24 | 9051368 ps | ||
| T56 | /workspace/coverage/sync_alert/9.prim_sync_alert.4199110951 | Mar 19 12:26:17 PM PDT 24 | Mar 19 12:26:18 PM PDT 24 | 10005355 ps | ||
| T32 | /workspace/coverage/sync_alert/6.prim_sync_alert.758728527 | Mar 19 12:26:30 PM PDT 24 | Mar 19 12:26:30 PM PDT 24 | 8721182 ps | ||
| T57 | /workspace/coverage/sync_alert/10.prim_sync_alert.2312452423 | Mar 19 12:26:33 PM PDT 24 | Mar 19 12:26:34 PM PDT 24 | 8350141 ps | ||
| T33 | /workspace/coverage/sync_alert/12.prim_sync_alert.3444699299 | Mar 19 12:27:26 PM PDT 24 | Mar 19 12:27:26 PM PDT 24 | 9436910 ps | ||
| T34 | /workspace/coverage/sync_alert/1.prim_sync_alert.3518198109 | Mar 19 12:27:25 PM PDT 24 | Mar 19 12:27:26 PM PDT 24 | 9325956 ps | ||
| T58 | /workspace/coverage/sync_alert/4.prim_sync_alert.870409149 | Mar 19 12:26:40 PM PDT 24 | Mar 19 12:26:40 PM PDT 24 | 9210867 ps | ||
| T35 | /workspace/coverage/sync_alert/19.prim_sync_alert.1467143945 | Mar 19 12:27:25 PM PDT 24 | Mar 19 12:27:26 PM PDT 24 | 9470713 ps | ||
| T59 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4090598731 | Mar 19 12:18:53 PM PDT 24 | Mar 19 12:18:54 PM PDT 24 | 27447890 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.847803399 | Mar 19 12:19:33 PM PDT 24 | Mar 19 12:19:34 PM PDT 24 | 27184389 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3948863992 | Mar 19 12:24:13 PM PDT 24 | Mar 19 12:24:14 PM PDT 24 | 26490253 ps | ||
| T36 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2950922863 | Mar 19 12:24:07 PM PDT 24 | Mar 19 12:24:07 PM PDT 24 | 26751850 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2546269558 | Mar 19 12:20:24 PM PDT 24 | Mar 19 12:20:25 PM PDT 24 | 28944252 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2931593550 | Mar 19 12:19:41 PM PDT 24 | Mar 19 12:19:42 PM PDT 24 | 27124946 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4056260833 | Mar 19 12:19:41 PM PDT 24 | Mar 19 12:19:42 PM PDT 24 | 26835218 ps | ||
| T15 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.205605374 | Mar 19 12:18:11 PM PDT 24 | Mar 19 12:18:11 PM PDT 24 | 29015301 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.993451107 | Mar 19 12:18:05 PM PDT 24 | Mar 19 12:18:06 PM PDT 24 | 26974332 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2923785629 | Mar 19 12:24:14 PM PDT 24 | Mar 19 12:24:14 PM PDT 24 | 27074562 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.460818847 | Mar 19 12:24:12 PM PDT 24 | Mar 19 12:24:13 PM PDT 24 | 26973959 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1037897571 | Mar 19 12:24:02 PM PDT 24 | Mar 19 12:24:03 PM PDT 24 | 27593735 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1636226303 | Mar 19 12:24:12 PM PDT 24 | Mar 19 12:24:13 PM PDT 24 | 27275585 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1622735184 | Mar 19 12:24:13 PM PDT 24 | Mar 19 12:24:14 PM PDT 24 | 29763198 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3772023881 | Mar 19 12:24:07 PM PDT 24 | Mar 19 12:24:07 PM PDT 24 | 27961917 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.4073683405 | Mar 19 12:18:05 PM PDT 24 | Mar 19 12:18:06 PM PDT 24 | 27389556 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1284871605 | Mar 19 12:24:14 PM PDT 24 | Mar 19 12:24:14 PM PDT 24 | 28385910 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1268191953 | Mar 19 12:23:05 PM PDT 24 | Mar 19 12:23:07 PM PDT 24 | 26853117 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3451525832 | Mar 19 12:18:08 PM PDT 24 | Mar 19 12:18:08 PM PDT 24 | 28235569 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1603199185 | Mar 19 12:19:22 PM PDT 24 | Mar 19 12:19:23 PM PDT 24 | 27606002 ps |
| Test location | /workspace/coverage/default/7.prim_async_alert.1801572353 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11033401 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:26:39 PM PDT 24 |
| Finished | Mar 19 12:26:41 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-cb482b4c-359e-4094-a736-7c5395191880 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1801572353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1801572353 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.2947684889 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8436042 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:26:17 PM PDT 24 |
| Finished | Mar 19 12:26:17 PM PDT 24 |
| Peak memory | 145292 kb |
| Host | smart-af1d8cf3-50c4-4a16-9043-8f8bc892e7d9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2947684889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2947684889 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2744659270 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 30872446 ps |
| CPU time | 0.49 seconds |
| Started | Mar 19 12:23:55 PM PDT 24 |
| Finished | Mar 19 12:23:56 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-ad6f803d-fa33-4b1d-9c7e-48ea55a63c95 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2744659270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2744659270 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3429060434 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 30371087 ps |
| CPU time | 0.41 seconds |
| Started | Mar 19 12:19:02 PM PDT 24 |
| Finished | Mar 19 12:19:03 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-df1906f9-faa1-46d6-8559-a27ea1db9008 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3429060434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3429060434 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.3038054566 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10391256 ps |
| CPU time | 0.39 seconds |
| Started | Mar 19 12:25:56 PM PDT 24 |
| Finished | Mar 19 12:25:57 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-78b9db84-37ea-4954-95ff-cd98443ce4d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3038054566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3038054566 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.3049186762 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11756814 ps |
| CPU time | 0.38 seconds |
| Started | Mar 19 12:26:02 PM PDT 24 |
| Finished | Mar 19 12:26:04 PM PDT 24 |
| Peak memory | 145508 kb |
| Host | smart-19401b2c-9061-4478-a3af-14242879b37a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3049186762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3049186762 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.3490243939 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12086631 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:26:21 PM PDT 24 |
| Finished | Mar 19 12:26:22 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-bcfe3a20-a992-477c-bb14-e18dbc4a882d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3490243939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3490243939 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.635971207 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11712216 ps |
| CPU time | 0.39 seconds |
| Started | Mar 19 12:26:02 PM PDT 24 |
| Finished | Mar 19 12:26:04 PM PDT 24 |
| Peak memory | 145516 kb |
| Host | smart-08bb1cf0-7bef-4de8-b7e2-f1f6d3361867 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=635971207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.635971207 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3015818296 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11592097 ps |
| CPU time | 0.38 seconds |
| Started | Mar 19 12:26:18 PM PDT 24 |
| Finished | Mar 19 12:26:18 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-b2edde35-2fd5-4c3c-9393-89d5970cb6d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015818296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3015818296 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1246043949 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10441409 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:26:16 PM PDT 24 |
| Finished | Mar 19 12:26:16 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-590dc786-c1ea-46d4-861a-b48d82a20257 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246043949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1246043949 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.460569722 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11260147 ps |
| CPU time | 0.38 seconds |
| Started | Mar 19 12:26:51 PM PDT 24 |
| Finished | Mar 19 12:26:52 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-55a20b00-d751-41c8-a493-f2dae35b6ae3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=460569722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.460569722 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.890575777 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11080058 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:26:13 PM PDT 24 |
| Finished | Mar 19 12:26:13 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-b0d122e4-1d50-413e-9f7f-c03cf27e1b0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=890575777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.890575777 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.2105048980 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11412650 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:26:12 PM PDT 24 |
| Finished | Mar 19 12:26:13 PM PDT 24 |
| Peak memory | 145420 kb |
| Host | smart-5b6ed96d-9660-4d01-b91c-ee9d7df1ab21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105048980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2105048980 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.3730340795 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10697704 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:26:23 PM PDT 24 |
| Finished | Mar 19 12:26:24 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-7314f093-ac5a-42bf-aedb-75e1c1d9a43f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730340795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3730340795 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.1010267632 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11186716 ps |
| CPU time | 0.45 seconds |
| Started | Mar 19 12:26:15 PM PDT 24 |
| Finished | Mar 19 12:26:16 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-ee64b814-a029-4084-b9a7-cde0f9aefcf3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1010267632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1010267632 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.71219219 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10698142 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:26:09 PM PDT 24 |
| Finished | Mar 19 12:26:10 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-82dbded0-8ee3-48bc-8fb4-078e061d9855 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71219219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.71219219 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.3375032274 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10846890 ps |
| CPU time | 0.39 seconds |
| Started | Mar 19 12:27:13 PM PDT 24 |
| Finished | Mar 19 12:27:15 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-1f9baf4d-85dd-4bfc-b771-d0a60b8804f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3375032274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3375032274 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.2968434958 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11920228 ps |
| CPU time | 0.45 seconds |
| Started | Mar 19 12:26:16 PM PDT 24 |
| Finished | Mar 19 12:26:17 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-6f0c40ba-ecca-4542-8e98-bd156f774176 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2968434958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2968434958 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3051035036 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11240155 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:26:07 PM PDT 24 |
| Finished | Mar 19 12:26:08 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-4b4d9b4a-cd97-4670-a9a3-349a3b87e78c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051035036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3051035036 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.4185550945 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11532258 ps |
| CPU time | 0.39 seconds |
| Started | Mar 19 12:26:34 PM PDT 24 |
| Finished | Mar 19 12:26:34 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-937fba74-4537-4d90-9f4c-d0bfa7615841 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4185550945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.4185550945 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2377925440 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11120271 ps |
| CPU time | 0.41 seconds |
| Started | Mar 19 12:26:19 PM PDT 24 |
| Finished | Mar 19 12:26:20 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-6c29dc5a-d78e-4b32-8711-9430db4f43a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377925440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2377925440 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1062737686 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11670343 ps |
| CPU time | 0.39 seconds |
| Started | Mar 19 12:26:30 PM PDT 24 |
| Finished | Mar 19 12:26:32 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-535a553b-1a09-4250-9b33-39117428fe6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1062737686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1062737686 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3345756404 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29824492 ps |
| CPU time | 0.42 seconds |
| Started | Mar 19 12:19:48 PM PDT 24 |
| Finished | Mar 19 12:19:48 PM PDT 24 |
| Peak memory | 145524 kb |
| Host | smart-c403bb12-e7a7-45d1-a2d5-a8db5132db22 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3345756404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3345756404 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1273136896 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 31528567 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:24:44 PM PDT 24 |
| Finished | Mar 19 12:24:45 PM PDT 24 |
| Peak memory | 145488 kb |
| Host | smart-b67e0547-dcc7-4602-8334-92dc3865ab5f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1273136896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1273136896 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1906766810 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 31508017 ps |
| CPU time | 0.41 seconds |
| Started | Mar 19 12:18:02 PM PDT 24 |
| Finished | Mar 19 12:18:03 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-b325258a-e88f-41d1-80f2-03ef13b76898 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1906766810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1906766810 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2817761685 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30849714 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:24:19 PM PDT 24 |
| Finished | Mar 19 12:24:19 PM PDT 24 |
| Peak memory | 145912 kb |
| Host | smart-a108aaba-b910-4948-9fc7-733045f5bb22 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2817761685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2817761685 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.789668616 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 31043872 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:24:15 PM PDT 24 |
| Finished | Mar 19 12:24:16 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-704c36b6-d31b-4a23-83cb-1af7679afbbc |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=789668616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.789668616 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2603755537 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 32141238 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:18:08 PM PDT 24 |
| Finished | Mar 19 12:18:09 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-f5ec7dde-d70b-4947-805f-164366a8d013 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2603755537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2603755537 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2597068965 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29532779 ps |
| CPU time | 0.44 seconds |
| Started | Mar 19 12:18:00 PM PDT 24 |
| Finished | Mar 19 12:18:01 PM PDT 24 |
| Peak memory | 144744 kb |
| Host | smart-748349bb-d341-40ee-8889-68e0f601320e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2597068965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2597068965 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3867050415 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29428940 ps |
| CPU time | 0.41 seconds |
| Started | Mar 19 12:18:08 PM PDT 24 |
| Finished | Mar 19 12:18:08 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-5a996e73-4ca4-4d99-9958-b8fcb8e31398 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3867050415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3867050415 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.436423844 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 32536945 ps |
| CPU time | 0.58 seconds |
| Started | Mar 19 12:23:05 PM PDT 24 |
| Finished | Mar 19 12:23:07 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-d7dd0df6-25fa-4f11-b6ac-b38200781e37 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=436423844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.436423844 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1321179903 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 30629924 ps |
| CPU time | 0.45 seconds |
| Started | Mar 19 12:19:37 PM PDT 24 |
| Finished | Mar 19 12:19:38 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-b2dbf7de-27d6-4899-836f-4eb1bc34c05c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1321179903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1321179903 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3941423120 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 31134097 ps |
| CPU time | 0.47 seconds |
| Started | Mar 19 12:18:22 PM PDT 24 |
| Finished | Mar 19 12:18:23 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-593793a8-934e-4ef1-b0ff-a5356beb3659 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3941423120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3941423120 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1240022257 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30827243 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:24:13 PM PDT 24 |
| Finished | Mar 19 12:24:14 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-d2ada01b-7e0f-4614-95a2-3721179a2131 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1240022257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1240022257 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.440351414 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30212872 ps |
| CPU time | 0.42 seconds |
| Started | Mar 19 12:24:25 PM PDT 24 |
| Finished | Mar 19 12:24:26 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-67dc99fc-18bb-4f5d-968b-1cd633c84b29 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=440351414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.440351414 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3014418782 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30939555 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:24:13 PM PDT 24 |
| Finished | Mar 19 12:24:14 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-a485997e-6da4-4dbb-80a0-e614aa414244 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3014418782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3014418782 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.413943532 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 30921806 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:17:55 PM PDT 24 |
| Finished | Mar 19 12:17:56 PM PDT 24 |
| Peak memory | 146000 kb |
| Host | smart-5786a9ee-973c-4afd-a73e-7b896e69e38a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=413943532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.413943532 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.269173124 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9826308 ps |
| CPU time | 0.37 seconds |
| Started | Mar 19 12:27:41 PM PDT 24 |
| Finished | Mar 19 12:27:41 PM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-490242d3-fc21-4e5a-8d2a-b92ad23a1fbf |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=269173124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.269173124 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.3518198109 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9325956 ps |
| CPU time | 0.39 seconds |
| Started | Mar 19 12:27:25 PM PDT 24 |
| Finished | Mar 19 12:27:26 PM PDT 24 |
| Peak memory | 144744 kb |
| Host | smart-2cf92866-ea95-4588-b966-2f84830d055b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3518198109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3518198109 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.2312452423 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8350141 ps |
| CPU time | 0.38 seconds |
| Started | Mar 19 12:26:33 PM PDT 24 |
| Finished | Mar 19 12:26:34 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-1bdba876-f3ea-4769-ae06-c4d393a41bad |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2312452423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2312452423 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1048865764 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9692562 ps |
| CPU time | 0.42 seconds |
| Started | Mar 19 12:26:14 PM PDT 24 |
| Finished | Mar 19 12:26:14 PM PDT 24 |
| Peak memory | 145348 kb |
| Host | smart-b75d1e90-ef2d-4b2a-b9f9-52bda7d614f4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1048865764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1048865764 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3444699299 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9436910 ps |
| CPU time | 0.38 seconds |
| Started | Mar 19 12:27:26 PM PDT 24 |
| Finished | Mar 19 12:27:26 PM PDT 24 |
| Peak memory | 143856 kb |
| Host | smart-4284587b-74a8-4051-acab-41bd80f9b911 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3444699299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3444699299 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.2286604552 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 8909304 ps |
| CPU time | 0.38 seconds |
| Started | Mar 19 12:26:40 PM PDT 24 |
| Finished | Mar 19 12:26:41 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-eb287153-0f02-4647-9733-40edd24f62dc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2286604552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2286604552 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.3301881268 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10637517 ps |
| CPU time | 0.38 seconds |
| Started | Mar 19 12:27:41 PM PDT 24 |
| Finished | Mar 19 12:27:41 PM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-68af8bd8-5504-4866-800a-6ea20bf34825 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3301881268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3301881268 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.4088143071 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9051368 ps |
| CPU time | 0.37 seconds |
| Started | Mar 19 12:27:09 PM PDT 24 |
| Finished | Mar 19 12:27:13 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-6c1c7e5e-5071-41c7-a250-a70cb4067c66 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4088143071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.4088143071 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.341730369 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9846869 ps |
| CPU time | 0.41 seconds |
| Started | Mar 19 12:26:51 PM PDT 24 |
| Finished | Mar 19 12:26:51 PM PDT 24 |
| Peak memory | 144804 kb |
| Host | smart-d2e12aca-ac71-4388-9993-5d8ebfe355a8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=341730369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.341730369 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.2544197991 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9276745 ps |
| CPU time | 0.37 seconds |
| Started | Mar 19 12:26:18 PM PDT 24 |
| Finished | Mar 19 12:26:19 PM PDT 24 |
| Peak memory | 144644 kb |
| Host | smart-5a390d3d-d4de-47b2-8669-7fda18a598e6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2544197991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2544197991 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.4200626954 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9851729 ps |
| CPU time | 0.49 seconds |
| Started | Mar 19 12:26:22 PM PDT 24 |
| Finished | Mar 19 12:26:23 PM PDT 24 |
| Peak memory | 145336 kb |
| Host | smart-06b4856a-f30d-4d47-8f8e-82a348b0518c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4200626954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.4200626954 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.1467143945 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9470713 ps |
| CPU time | 0.45 seconds |
| Started | Mar 19 12:27:25 PM PDT 24 |
| Finished | Mar 19 12:27:26 PM PDT 24 |
| Peak memory | 143004 kb |
| Host | smart-43e42ac1-2d28-49b6-8c7d-1c04d7a252b6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1467143945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1467143945 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3093862284 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8805320 ps |
| CPU time | 0.45 seconds |
| Started | Mar 19 12:27:25 PM PDT 24 |
| Finished | Mar 19 12:27:26 PM PDT 24 |
| Peak memory | 142972 kb |
| Host | smart-d936c8ff-021d-40aa-95af-83c5745a0eae |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3093862284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3093862284 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3952062117 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 8871598 ps |
| CPU time | 0.37 seconds |
| Started | Mar 19 12:26:19 PM PDT 24 |
| Finished | Mar 19 12:26:19 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-711fcfd1-e2de-4360-aa59-b9cd08532539 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3952062117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3952062117 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.870409149 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9210867 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:26:40 PM PDT 24 |
| Finished | Mar 19 12:26:40 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-44a4c195-ac4a-4571-9047-8aab6be9283d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=870409149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.870409149 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.3786026042 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9505422 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:26:39 PM PDT 24 |
| Finished | Mar 19 12:26:40 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-f39c13f7-28a4-4b0c-9a66-d66591782419 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3786026042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3786026042 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.758728527 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8721182 ps |
| CPU time | 0.41 seconds |
| Started | Mar 19 12:26:30 PM PDT 24 |
| Finished | Mar 19 12:26:30 PM PDT 24 |
| Peak memory | 145344 kb |
| Host | smart-1f5a3c21-e74c-4a4f-b5b9-7e9e2598cc25 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=758728527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.758728527 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.3241493553 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8248621 ps |
| CPU time | 0.35 seconds |
| Started | Mar 19 12:26:26 PM PDT 24 |
| Finished | Mar 19 12:26:26 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-6c422455-135b-4a43-8ce1-8fd217db9eb2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3241493553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3241493553 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.4199110951 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 10005355 ps |
| CPU time | 0.45 seconds |
| Started | Mar 19 12:26:17 PM PDT 24 |
| Finished | Mar 19 12:26:18 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-531c20dc-c7f5-48e7-a7dc-a699670c10ad |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4199110951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.4199110951 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.205605374 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 29015301 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:18:11 PM PDT 24 |
| Finished | Mar 19 12:18:11 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-aa37f824-b41e-4aa3-855f-4f6463e36ede |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=205605374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.205605374 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2546269558 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 28944252 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:20:24 PM PDT 24 |
| Finished | Mar 19 12:20:25 PM PDT 24 |
| Peak memory | 144704 kb |
| Host | smart-09139786-b65d-41d1-9ed4-033f1107c1f2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2546269558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2546269558 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1284871605 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 28385910 ps |
| CPU time | 0.39 seconds |
| Started | Mar 19 12:24:14 PM PDT 24 |
| Finished | Mar 19 12:24:14 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-2e151c7a-6224-465b-9014-f7b3cd9bb4d0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1284871605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1284871605 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1622735184 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 29763198 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:24:13 PM PDT 24 |
| Finished | Mar 19 12:24:14 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-8b7b2b27-0d36-4090-8cdc-ecdbfae1f8c0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1622735184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1622735184 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2950922863 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 26751850 ps |
| CPU time | 0.39 seconds |
| Started | Mar 19 12:24:07 PM PDT 24 |
| Finished | Mar 19 12:24:07 PM PDT 24 |
| Peak memory | 144564 kb |
| Host | smart-b6594a38-57bf-4256-9db6-726a799f92b2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2950922863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2950922863 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1603199185 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27606002 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:19:22 PM PDT 24 |
| Finished | Mar 19 12:19:23 PM PDT 24 |
| Peak memory | 144736 kb |
| Host | smart-c971025f-008a-41d5-b0bf-bf62946672ff |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1603199185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1603199185 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3772023881 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27961917 ps |
| CPU time | 0.41 seconds |
| Started | Mar 19 12:24:07 PM PDT 24 |
| Finished | Mar 19 12:24:07 PM PDT 24 |
| Peak memory | 144584 kb |
| Host | smart-16e3886f-8392-4bf0-9b3a-9e7af5bd2d5b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3772023881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3772023881 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.847803399 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 27184389 ps |
| CPU time | 0.46 seconds |
| Started | Mar 19 12:19:33 PM PDT 24 |
| Finished | Mar 19 12:19:34 PM PDT 24 |
| Peak memory | 144708 kb |
| Host | smart-0d73aca0-d684-4099-b467-603f5fec0fbd |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=847803399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.847803399 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2931593550 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27124946 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:19:41 PM PDT 24 |
| Finished | Mar 19 12:19:42 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-f430e181-89fb-461e-9552-94f827978980 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2931593550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2931593550 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1636226303 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27275585 ps |
| CPU time | 0.49 seconds |
| Started | Mar 19 12:24:12 PM PDT 24 |
| Finished | Mar 19 12:24:13 PM PDT 24 |
| Peak memory | 143220 kb |
| Host | smart-b2363451-944c-4373-9573-41ee7454b0ab |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1636226303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1636226303 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1037897571 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27593735 ps |
| CPU time | 0.46 seconds |
| Started | Mar 19 12:24:02 PM PDT 24 |
| Finished | Mar 19 12:24:03 PM PDT 24 |
| Peak memory | 145352 kb |
| Host | smart-50693cea-1d91-4027-a590-293e31a2018e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1037897571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1037897571 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4056260833 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26835218 ps |
| CPU time | 0.4 seconds |
| Started | Mar 19 12:19:41 PM PDT 24 |
| Finished | Mar 19 12:19:42 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-cb959a72-f46a-475e-be52-4a7e95227dbe |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4056260833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4056260833 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.993451107 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 26974332 ps |
| CPU time | 0.41 seconds |
| Started | Mar 19 12:18:05 PM PDT 24 |
| Finished | Mar 19 12:18:06 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-da766010-de9e-44e5-9af5-80cacbd54970 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=993451107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.993451107 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.4073683405 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27389556 ps |
| CPU time | 0.39 seconds |
| Started | Mar 19 12:18:05 PM PDT 24 |
| Finished | Mar 19 12:18:06 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-6d6497ad-849b-4784-9662-627d22e37ca1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4073683405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.4073683405 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1268191953 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26853117 ps |
| CPU time | 0.5 seconds |
| Started | Mar 19 12:23:05 PM PDT 24 |
| Finished | Mar 19 12:23:07 PM PDT 24 |
| Peak memory | 144716 kb |
| Host | smart-f405dbfc-da57-4a34-a17a-e7fcb6de84b2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1268191953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1268191953 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2923785629 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27074562 ps |
| CPU time | 0.38 seconds |
| Started | Mar 19 12:24:14 PM PDT 24 |
| Finished | Mar 19 12:24:14 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-ffb463c2-3c26-4793-afec-7e91f03c8e0e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2923785629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2923785629 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4090598731 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 27447890 ps |
| CPU time | 0.47 seconds |
| Started | Mar 19 12:18:53 PM PDT 24 |
| Finished | Mar 19 12:18:54 PM PDT 24 |
| Peak memory | 145324 kb |
| Host | smart-c458b18d-3f33-48f4-8ba5-ea49052050be |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4090598731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.4090598731 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.460818847 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26973959 ps |
| CPU time | 0.5 seconds |
| Started | Mar 19 12:24:12 PM PDT 24 |
| Finished | Mar 19 12:24:13 PM PDT 24 |
| Peak memory | 143256 kb |
| Host | smart-f625e9b1-b0ee-4d63-9112-65a91690b8fa |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=460818847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.460818847 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3451525832 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 28235569 ps |
| CPU time | 0.39 seconds |
| Started | Mar 19 12:18:08 PM PDT 24 |
| Finished | Mar 19 12:18:08 PM PDT 24 |
| Peak memory | 145392 kb |
| Host | smart-cb43c79c-870a-4056-9d58-fbd54af65df3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3451525832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3451525832 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3948863992 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 26490253 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:24:13 PM PDT 24 |
| Finished | Mar 19 12:24:14 PM PDT 24 |
| Peak memory | 144624 kb |
| Host | smart-a7528150-f416-40e0-bb70-61fde6b76bb1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3948863992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3948863992 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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