| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 89.27 | 89.27 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/4.prim_async_alert.12124313 |
| 93.34 | 4.07 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 10.71 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/17.prim_sync_alert.563414709 |
| 94.50 | 1.16 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2457957091 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.382269703 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.3374838164 |
| /workspace/coverage/default/1.prim_async_alert.3790383453 |
| /workspace/coverage/default/10.prim_async_alert.1360436933 |
| /workspace/coverage/default/11.prim_async_alert.3788400543 |
| /workspace/coverage/default/12.prim_async_alert.473041140 |
| /workspace/coverage/default/13.prim_async_alert.1815022396 |
| /workspace/coverage/default/14.prim_async_alert.3829004825 |
| /workspace/coverage/default/15.prim_async_alert.1232743365 |
| /workspace/coverage/default/16.prim_async_alert.1071960055 |
| /workspace/coverage/default/18.prim_async_alert.933694958 |
| /workspace/coverage/default/19.prim_async_alert.2167623359 |
| /workspace/coverage/default/2.prim_async_alert.2355200712 |
| /workspace/coverage/default/3.prim_async_alert.1353048162 |
| /workspace/coverage/default/5.prim_async_alert.2121669544 |
| /workspace/coverage/default/6.prim_async_alert.2459476124 |
| /workspace/coverage/default/7.prim_async_alert.1314180827 |
| /workspace/coverage/default/8.prim_async_alert.482298185 |
| /workspace/coverage/default/9.prim_async_alert.2791029882 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.720049933 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4021401343 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3256248542 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1291532161 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.601033710 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3449069563 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.229148779 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1039704556 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2369337103 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4068659806 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.710901536 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1530591898 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2737990482 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1842281888 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1863924099 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1714244786 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4064975044 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.473122965 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.2618546002 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3762907991 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.4067520317 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.1547631201 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.149284403 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1014544056 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.2516278304 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.852805802 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.1195931035 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.116321965 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2851767252 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.1801031550 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.3503914822 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.3848924038 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.3096451981 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1698955229 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.1251071302 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.2189545835 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.475939501 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2466429466 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2240209071 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3055814833 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2586466081 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1397245187 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.570777366 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1908365950 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2741862756 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1837166021 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3200546280 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1526246981 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3401382619 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2689942510 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.347232648 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3395249177 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1836960332 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.901621951 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3469311287 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/14.prim_async_alert.3829004825 | Mar 21 12:24:45 PM PDT 24 | Mar 21 12:24:46 PM PDT 24 | 10311603 ps | ||
| T2 | /workspace/coverage/default/11.prim_async_alert.3788400543 | Mar 21 12:24:43 PM PDT 24 | Mar 21 12:24:44 PM PDT 24 | 10927517 ps | ||
| T3 | /workspace/coverage/default/0.prim_async_alert.3374838164 | Mar 21 12:24:47 PM PDT 24 | Mar 21 12:24:48 PM PDT 24 | 12513194 ps | ||
| T11 | /workspace/coverage/default/12.prim_async_alert.473041140 | Mar 21 12:24:47 PM PDT 24 | Mar 21 12:24:48 PM PDT 24 | 10746690 ps | ||
| T19 | /workspace/coverage/default/8.prim_async_alert.482298185 | Mar 21 12:24:59 PM PDT 24 | Mar 21 12:25:00 PM PDT 24 | 11596994 ps | ||
| T5 | /workspace/coverage/default/19.prim_async_alert.2167623359 | Mar 21 12:24:52 PM PDT 24 | Mar 21 12:24:52 PM PDT 24 | 10648942 ps | ||
| T10 | /workspace/coverage/default/16.prim_async_alert.1071960055 | Mar 21 12:24:47 PM PDT 24 | Mar 21 12:24:48 PM PDT 24 | 11335837 ps | ||
| T6 | /workspace/coverage/default/4.prim_async_alert.12124313 | Mar 21 12:24:54 PM PDT 24 | Mar 21 12:24:54 PM PDT 24 | 12548054 ps | ||
| T7 | /workspace/coverage/default/5.prim_async_alert.2121669544 | Mar 21 12:24:44 PM PDT 24 | Mar 21 12:24:45 PM PDT 24 | 11576216 ps | ||
| T12 | /workspace/coverage/default/10.prim_async_alert.1360436933 | Mar 21 12:24:49 PM PDT 24 | Mar 21 12:24:49 PM PDT 24 | 11509504 ps | ||
| T17 | /workspace/coverage/default/6.prim_async_alert.2459476124 | Mar 21 12:25:05 PM PDT 24 | Mar 21 12:25:06 PM PDT 24 | 11674944 ps | ||
| T20 | /workspace/coverage/default/7.prim_async_alert.1314180827 | Mar 21 12:24:46 PM PDT 24 | Mar 21 12:24:47 PM PDT 24 | 11115381 ps | ||
| T23 | /workspace/coverage/default/2.prim_async_alert.2355200712 | Mar 21 12:24:45 PM PDT 24 | Mar 21 12:24:46 PM PDT 24 | 11030176 ps | ||
| T21 | /workspace/coverage/default/3.prim_async_alert.1353048162 | Mar 21 12:24:36 PM PDT 24 | Mar 21 12:24:37 PM PDT 24 | 12613521 ps | ||
| T18 | /workspace/coverage/default/18.prim_async_alert.933694958 | Mar 21 12:24:58 PM PDT 24 | Mar 21 12:24:58 PM PDT 24 | 11054660 ps | ||
| T14 | /workspace/coverage/default/13.prim_async_alert.1815022396 | Mar 21 12:24:46 PM PDT 24 | Mar 21 12:24:46 PM PDT 24 | 11180333 ps | ||
| T22 | /workspace/coverage/default/15.prim_async_alert.1232743365 | Mar 21 12:24:39 PM PDT 24 | Mar 21 12:24:39 PM PDT 24 | 11384858 ps | ||
| T8 | /workspace/coverage/default/9.prim_async_alert.2791029882 | Mar 21 12:24:45 PM PDT 24 | Mar 21 12:24:46 PM PDT 24 | 12175816 ps | ||
| T46 | /workspace/coverage/default/1.prim_async_alert.3790383453 | Mar 21 12:24:46 PM PDT 24 | Mar 21 12:24:46 PM PDT 24 | 10801113 ps | ||
| T9 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2457957091 | Mar 21 12:24:45 PM PDT 24 | Mar 21 12:24:46 PM PDT 24 | 28568695 ps | ||
| T38 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1530591898 | Mar 21 12:24:48 PM PDT 24 | Mar 21 12:24:49 PM PDT 24 | 29808942 ps | ||
| T39 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.229148779 | Mar 21 12:24:47 PM PDT 24 | Mar 21 12:24:48 PM PDT 24 | 30225013 ps | ||
| T40 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4064975044 | Mar 21 12:24:47 PM PDT 24 | Mar 21 12:24:48 PM PDT 24 | 31315944 ps | ||
| T15 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1842281888 | Mar 21 12:25:11 PM PDT 24 | Mar 21 12:25:11 PM PDT 24 | 28136468 ps | ||
| T41 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1863924099 | Mar 21 12:24:52 PM PDT 24 | Mar 21 12:24:53 PM PDT 24 | 27628677 ps | ||
| T42 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4068659806 | Mar 21 12:25:02 PM PDT 24 | Mar 21 12:25:03 PM PDT 24 | 31233508 ps | ||
| T43 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2369337103 | Mar 21 12:24:47 PM PDT 24 | Mar 21 12:24:47 PM PDT 24 | 29570517 ps | ||
| T44 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1291532161 | Mar 21 12:25:01 PM PDT 24 | Mar 21 12:25:01 PM PDT 24 | 30622353 ps | ||
| T45 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.601033710 | Mar 21 12:24:47 PM PDT 24 | Mar 21 12:24:48 PM PDT 24 | 31215211 ps | ||
| T47 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3449069563 | Mar 21 12:25:00 PM PDT 24 | Mar 21 12:25:00 PM PDT 24 | 29438844 ps | ||
| T16 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3256248542 | Mar 21 12:24:45 PM PDT 24 | Mar 21 12:24:45 PM PDT 24 | 30210307 ps | ||
| T48 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.720049933 | Mar 21 12:24:50 PM PDT 24 | Mar 21 12:24:51 PM PDT 24 | 30365505 ps | ||
| T49 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2737990482 | Mar 21 12:24:44 PM PDT 24 | Mar 21 12:24:45 PM PDT 24 | 29243241 ps | ||
| T50 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1039704556 | Mar 21 12:25:14 PM PDT 24 | Mar 21 12:25:15 PM PDT 24 | 31930499 ps | ||
| T51 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1714244786 | Mar 21 12:24:45 PM PDT 24 | Mar 21 12:24:46 PM PDT 24 | 31049661 ps | ||
| T13 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.710901536 | Mar 21 12:24:42 PM PDT 24 | Mar 21 12:24:43 PM PDT 24 | 29550186 ps | ||
| T52 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4021401343 | Mar 21 12:25:02 PM PDT 24 | Mar 21 12:25:03 PM PDT 24 | 30358739 ps | ||
| T24 | /workspace/coverage/sync_alert/18.prim_sync_alert.1195931035 | Mar 21 12:24:51 PM PDT 24 | Mar 21 12:24:52 PM PDT 24 | 9036205 ps | ||
| T34 | /workspace/coverage/sync_alert/15.prim_sync_alert.2516278304 | Mar 21 12:25:05 PM PDT 24 | Mar 21 12:25:05 PM PDT 24 | 9753675 ps | ||
| T25 | /workspace/coverage/sync_alert/4.prim_sync_alert.3503914822 | Mar 21 12:24:45 PM PDT 24 | Mar 21 12:24:46 PM PDT 24 | 9329721 ps | ||
| T35 | /workspace/coverage/sync_alert/5.prim_sync_alert.3848924038 | Mar 21 12:25:02 PM PDT 24 | Mar 21 12:25:03 PM PDT 24 | 8988040 ps | ||
| T26 | /workspace/coverage/sync_alert/17.prim_sync_alert.563414709 | Mar 21 12:25:02 PM PDT 24 | Mar 21 12:25:03 PM PDT 24 | 10168856 ps | ||
| T27 | /workspace/coverage/sync_alert/6.prim_sync_alert.3096451981 | Mar 21 12:24:56 PM PDT 24 | Mar 21 12:24:56 PM PDT 24 | 8852635 ps | ||
| T36 | /workspace/coverage/sync_alert/10.prim_sync_alert.3762907991 | Mar 21 12:25:09 PM PDT 24 | Mar 21 12:25:10 PM PDT 24 | 9224733 ps | ||
| T37 | /workspace/coverage/sync_alert/16.prim_sync_alert.852805802 | Mar 21 12:24:45 PM PDT 24 | Mar 21 12:24:45 PM PDT 24 | 9642793 ps | ||
| T28 | /workspace/coverage/sync_alert/11.prim_sync_alert.4067520317 | Mar 21 12:24:47 PM PDT 24 | Mar 21 12:24:48 PM PDT 24 | 9385271 ps | ||
| T29 | /workspace/coverage/sync_alert/7.prim_sync_alert.1698955229 | Mar 21 12:24:47 PM PDT 24 | Mar 21 12:24:47 PM PDT 24 | 8720082 ps | ||
| T53 | /workspace/coverage/sync_alert/12.prim_sync_alert.1547631201 | Mar 21 12:24:48 PM PDT 24 | Mar 21 12:24:49 PM PDT 24 | 9506356 ps | ||
| T30 | /workspace/coverage/sync_alert/1.prim_sync_alert.2618546002 | Mar 21 12:24:47 PM PDT 24 | Mar 21 12:24:48 PM PDT 24 | 8578741 ps | ||
| T31 | /workspace/coverage/sync_alert/3.prim_sync_alert.1801031550 | Mar 21 12:24:55 PM PDT 24 | Mar 21 12:24:55 PM PDT 24 | 11064233 ps | ||
| T32 | /workspace/coverage/sync_alert/13.prim_sync_alert.149284403 | Mar 21 12:24:56 PM PDT 24 | Mar 21 12:24:57 PM PDT 24 | 7909618 ps | ||
| T54 | /workspace/coverage/sync_alert/19.prim_sync_alert.116321965 | Mar 21 12:24:47 PM PDT 24 | Mar 21 12:24:47 PM PDT 24 | 9998662 ps | ||
| T33 | /workspace/coverage/sync_alert/2.prim_sync_alert.2851767252 | Mar 21 12:25:07 PM PDT 24 | Mar 21 12:25:08 PM PDT 24 | 9560313 ps | ||
| T55 | /workspace/coverage/sync_alert/14.prim_sync_alert.1014544056 | Mar 21 12:24:48 PM PDT 24 | Mar 21 12:24:54 PM PDT 24 | 8603435 ps | ||
| T56 | /workspace/coverage/sync_alert/0.prim_sync_alert.473122965 | Mar 21 12:25:03 PM PDT 24 | Mar 21 12:25:04 PM PDT 24 | 9874306 ps | ||
| T57 | /workspace/coverage/sync_alert/8.prim_sync_alert.1251071302 | Mar 21 12:25:02 PM PDT 24 | Mar 21 12:25:03 PM PDT 24 | 9443619 ps | ||
| T58 | /workspace/coverage/sync_alert/9.prim_sync_alert.2189545835 | Mar 21 12:25:04 PM PDT 24 | Mar 21 12:25:05 PM PDT 24 | 8835197 ps | ||
| T59 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3395249177 | Mar 21 12:26:18 PM PDT 24 | Mar 21 12:26:19 PM PDT 24 | 27912242 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2741862756 | Mar 21 12:26:18 PM PDT 24 | Mar 21 12:26:19 PM PDT 24 | 26354044 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3469311287 | Mar 21 12:26:15 PM PDT 24 | Mar 21 12:26:16 PM PDT 24 | 27322781 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1397245187 | Mar 21 12:26:14 PM PDT 24 | Mar 21 12:26:15 PM PDT 24 | 26173704 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1837166021 | Mar 21 12:26:20 PM PDT 24 | Mar 21 12:26:21 PM PDT 24 | 28603317 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1836960332 | Mar 21 12:26:14 PM PDT 24 | Mar 21 12:26:15 PM PDT 24 | 27395703 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3401382619 | Mar 21 12:26:17 PM PDT 24 | Mar 21 12:26:18 PM PDT 24 | 28806555 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3200546280 | Mar 21 12:26:18 PM PDT 24 | Mar 21 12:26:19 PM PDT 24 | 26329480 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.901621951 | Mar 21 12:26:16 PM PDT 24 | Mar 21 12:26:16 PM PDT 24 | 26572910 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1908365950 | Mar 21 12:26:26 PM PDT 24 | Mar 21 12:26:27 PM PDT 24 | 27369362 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2466429466 | Mar 21 12:26:26 PM PDT 24 | Mar 21 12:26:27 PM PDT 24 | 27916864 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.347232648 | Mar 21 12:26:12 PM PDT 24 | Mar 21 12:26:13 PM PDT 24 | 25939126 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1526246981 | Mar 21 12:26:17 PM PDT 24 | Mar 21 12:26:17 PM PDT 24 | 24980978 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2689942510 | Mar 21 12:26:23 PM PDT 24 | Mar 21 12:26:24 PM PDT 24 | 26491811 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3055814833 | Mar 21 12:26:05 PM PDT 24 | Mar 21 12:26:06 PM PDT 24 | 29350750 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.475939501 | Mar 21 12:26:15 PM PDT 24 | Mar 21 12:26:16 PM PDT 24 | 28207601 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2586466081 | Mar 21 12:26:19 PM PDT 24 | Mar 21 12:26:20 PM PDT 24 | 26647328 ps | ||
| T4 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.382269703 | Mar 21 12:26:20 PM PDT 24 | Mar 21 12:26:20 PM PDT 24 | 26759984 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2240209071 | Mar 21 12:26:16 PM PDT 24 | Mar 21 12:26:17 PM PDT 24 | 26690416 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.570777366 | Mar 21 12:26:23 PM PDT 24 | Mar 21 12:26:23 PM PDT 24 | 29555076 ps |
| Test location | /workspace/coverage/default/4.prim_async_alert.12124313 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12548054 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:54 PM PDT 24 |
| Finished | Mar 21 12:24:54 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-1d4f06ae-a6ab-436b-8995-de2fffd566a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12124313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.12124313 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.563414709 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10168856 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:25:02 PM PDT 24 |
| Finished | Mar 21 12:25:03 PM PDT 24 |
| Peak memory | 144452 kb |
| Host | smart-042ea227-5566-4ae1-9ca0-9b208005885e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=563414709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.563414709 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2457957091 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 28568695 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:24:45 PM PDT 24 |
| Finished | Mar 21 12:24:46 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-dfc60d63-2ea4-4768-b32e-1dfdd9467e1f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2457957091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2457957091 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.382269703 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 26759984 ps |
| CPU time | 0.37 seconds |
| Started | Mar 21 12:26:20 PM PDT 24 |
| Finished | Mar 21 12:26:20 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-ccedd3ca-34e4-45b7-8bf8-b591782a4004 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=382269703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.382269703 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.3374838164 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12513194 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:24:47 PM PDT 24 |
| Finished | Mar 21 12:24:48 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-b12b6e8e-7a36-45ca-a270-6600218c09d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3374838164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3374838164 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.3790383453 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10801113 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:24:46 PM PDT 24 |
| Finished | Mar 21 12:24:46 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-a11efae5-51be-4c0a-87b5-3c9998f96459 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3790383453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3790383453 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.1360436933 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11509504 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:24:49 PM PDT 24 |
| Finished | Mar 21 12:24:49 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-2bcd9983-8d43-4d94-a28f-3ddcf74692a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1360436933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1360436933 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3788400543 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10927517 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:24:43 PM PDT 24 |
| Finished | Mar 21 12:24:44 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-5aa01a37-789a-4639-bfc3-f7899a84e24e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3788400543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3788400543 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.473041140 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10746690 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:47 PM PDT 24 |
| Finished | Mar 21 12:24:48 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-9c7eb225-d4e0-4e1b-a0ec-a85a8d54afe6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=473041140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.473041140 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1815022396 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11180333 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:24:46 PM PDT 24 |
| Finished | Mar 21 12:24:46 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-f4fa088d-34fb-4e51-902a-f804554deca9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815022396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1815022396 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.3829004825 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10311603 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:45 PM PDT 24 |
| Finished | Mar 21 12:24:46 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-4a6d61bd-25c8-44ba-b75f-79a1f9479248 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829004825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3829004825 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1232743365 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11384858 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:24:39 PM PDT 24 |
| Finished | Mar 21 12:24:39 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-a49c290d-ef3a-4f3a-88fc-382dc1064017 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1232743365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1232743365 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.1071960055 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11335837 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:24:47 PM PDT 24 |
| Finished | Mar 21 12:24:48 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-0389f21b-c6c2-441b-9acc-a0b5a52086c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071960055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1071960055 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.933694958 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11054660 ps |
| CPU time | 0.37 seconds |
| Started | Mar 21 12:24:58 PM PDT 24 |
| Finished | Mar 21 12:24:58 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-5bc9eca7-32a1-4421-928e-4d681a90c7e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933694958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.933694958 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.2167623359 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 10648942 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:24:52 PM PDT 24 |
| Finished | Mar 21 12:24:52 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-0aab7ac8-adc8-4820-aaff-7bb081f1539e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167623359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2167623359 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.2355200712 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11030176 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:45 PM PDT 24 |
| Finished | Mar 21 12:24:46 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-65051acc-2081-452e-8c21-1299e4ac4864 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2355200712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2355200712 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.1353048162 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12613521 ps |
| CPU time | 0.42 seconds |
| Started | Mar 21 12:24:36 PM PDT 24 |
| Finished | Mar 21 12:24:37 PM PDT 24 |
| Peak memory | 145860 kb |
| Host | smart-845c4093-7c90-4ea4-9889-189c36d7a87b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1353048162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1353048162 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.2121669544 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11576216 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:44 PM PDT 24 |
| Finished | Mar 21 12:24:45 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-ab019457-0203-4c5f-a61c-ea01ab0fedfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2121669544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2121669544 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2459476124 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11674944 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:25:05 PM PDT 24 |
| Finished | Mar 21 12:25:06 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-5bfd2a62-b6ed-44e0-b8ca-b3e2a982a7e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2459476124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2459476124 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.1314180827 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11115381 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:24:46 PM PDT 24 |
| Finished | Mar 21 12:24:47 PM PDT 24 |
| Peak memory | 145692 kb |
| Host | smart-66774380-a66a-48d9-89fc-a405cb4dcd4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1314180827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1314180827 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.482298185 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11596994 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:59 PM PDT 24 |
| Finished | Mar 21 12:25:00 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-c9ba6dab-bb82-4c51-9c9d-0d5cfd74a300 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482298185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.482298185 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.2791029882 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12175816 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:45 PM PDT 24 |
| Finished | Mar 21 12:24:46 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-8d6279c8-438d-4d28-8433-4af9d5af149b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2791029882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2791029882 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.720049933 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30365505 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:50 PM PDT 24 |
| Finished | Mar 21 12:24:51 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-040fb958-fc75-40d4-913a-eb74ccc6cda4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=720049933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.720049933 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4021401343 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30358739 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:25:02 PM PDT 24 |
| Finished | Mar 21 12:25:03 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-017576e6-53b5-4bb2-aa9a-aa2b59187573 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4021401343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.4021401343 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3256248542 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 30210307 ps |
| CPU time | 0.41 seconds |
| Started | Mar 21 12:24:45 PM PDT 24 |
| Finished | Mar 21 12:24:45 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-4c8e0637-31ac-4941-891a-a85842751717 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3256248542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3256248542 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1291532161 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30622353 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:25:01 PM PDT 24 |
| Finished | Mar 21 12:25:01 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-b297e06a-1955-4dcb-af67-520444fe2276 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1291532161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1291532161 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.601033710 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 31215211 ps |
| CPU time | 0.43 seconds |
| Started | Mar 21 12:24:47 PM PDT 24 |
| Finished | Mar 21 12:24:48 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-65cc73bb-81cc-4635-9d7d-1c88dc2d6451 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=601033710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.601033710 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3449069563 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 29438844 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:25:00 PM PDT 24 |
| Finished | Mar 21 12:25:00 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-7c339d60-c6cf-405b-9f3b-79a2c4302bf0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3449069563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3449069563 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.229148779 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 30225013 ps |
| CPU time | 0.41 seconds |
| Started | Mar 21 12:24:47 PM PDT 24 |
| Finished | Mar 21 12:24:48 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-dec1e506-baf4-4891-a3c0-0d3fb5224dbc |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=229148779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.229148779 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1039704556 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 31930499 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:25:14 PM PDT 24 |
| Finished | Mar 21 12:25:15 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-b5200c78-d00a-40c0-99bf-c03f9cd76f80 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1039704556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1039704556 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2369337103 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 29570517 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:24:47 PM PDT 24 |
| Finished | Mar 21 12:24:47 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-248d1a08-aa75-43e8-a67b-36a5376ed76f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2369337103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2369337103 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4068659806 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 31233508 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:25:02 PM PDT 24 |
| Finished | Mar 21 12:25:03 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-fdb7e0f3-a347-4ff4-9dcb-8b0d92939816 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4068659806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.4068659806 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.710901536 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 29550186 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:24:42 PM PDT 24 |
| Finished | Mar 21 12:24:43 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-706fac4f-fe28-4261-a9a5-9d51a53b707c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=710901536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.710901536 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1530591898 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 29808942 ps |
| CPU time | 0.41 seconds |
| Started | Mar 21 12:24:48 PM PDT 24 |
| Finished | Mar 21 12:24:49 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-177650a3-c867-4df1-ac27-62f3ce087621 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1530591898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1530591898 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2737990482 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29243241 ps |
| CPU time | 0.44 seconds |
| Started | Mar 21 12:24:44 PM PDT 24 |
| Finished | Mar 21 12:24:45 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-bf4e365b-7942-47c7-9b38-7f193a50f754 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2737990482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2737990482 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1842281888 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 28136468 ps |
| CPU time | 0.41 seconds |
| Started | Mar 21 12:25:11 PM PDT 24 |
| Finished | Mar 21 12:25:11 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-adb6e2f8-7d43-4723-84e1-4a0f705fec58 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1842281888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1842281888 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1863924099 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 27628677 ps |
| CPU time | 0.42 seconds |
| Started | Mar 21 12:24:52 PM PDT 24 |
| Finished | Mar 21 12:24:53 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-f4844f9b-ad26-46c0-935c-c9400e6d141d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1863924099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1863924099 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1714244786 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 31049661 ps |
| CPU time | 0.41 seconds |
| Started | Mar 21 12:24:45 PM PDT 24 |
| Finished | Mar 21 12:24:46 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-bbd24d96-c6d2-4d0a-b94f-1e27a1dc7a6a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1714244786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1714244786 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4064975044 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 31315944 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:24:47 PM PDT 24 |
| Finished | Mar 21 12:24:48 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-865d1b3b-e4ab-477c-a1d7-1b15e9e4382d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4064975044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.4064975044 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.473122965 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9874306 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:25:03 PM PDT 24 |
| Finished | Mar 21 12:25:04 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-91a91e62-a2b7-4238-aaf5-aae61156f9eb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=473122965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.473122965 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.2618546002 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8578741 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:47 PM PDT 24 |
| Finished | Mar 21 12:24:48 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-259d7d39-ddd8-4e99-b69d-4b8d98dcf177 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2618546002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2618546002 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3762907991 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9224733 ps |
| CPU time | 0.37 seconds |
| Started | Mar 21 12:25:09 PM PDT 24 |
| Finished | Mar 21 12:25:10 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-d9c9d5a6-8d7d-421f-b1de-e50150088ff1 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3762907991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3762907991 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.4067520317 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9385271 ps |
| CPU time | 0.41 seconds |
| Started | Mar 21 12:24:47 PM PDT 24 |
| Finished | Mar 21 12:24:48 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-2b330915-62d0-44e7-930b-73df3762439e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4067520317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.4067520317 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.1547631201 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 9506356 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:48 PM PDT 24 |
| Finished | Mar 21 12:24:49 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-1428188e-b5e5-464e-92cb-cb7edcdb7a37 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1547631201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1547631201 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.149284403 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7909618 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:24:56 PM PDT 24 |
| Finished | Mar 21 12:24:57 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-50d52878-c62f-4878-a2ef-f5116cee88c8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=149284403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.149284403 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1014544056 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 8603435 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:24:48 PM PDT 24 |
| Finished | Mar 21 12:24:54 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-ae0824ec-0a37-4773-b9d1-42e83e356f91 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1014544056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1014544056 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.2516278304 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9753675 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:25:05 PM PDT 24 |
| Finished | Mar 21 12:25:05 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-b12cff08-deff-4e98-89d9-d0ed70a03f34 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2516278304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2516278304 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.852805802 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9642793 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:45 PM PDT 24 |
| Finished | Mar 21 12:24:45 PM PDT 24 |
| Peak memory | 144712 kb |
| Host | smart-2d27f62f-801a-49cf-80f9-703aa0042f37 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=852805802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.852805802 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.1195931035 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9036205 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:24:51 PM PDT 24 |
| Finished | Mar 21 12:24:52 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-e20b77d2-5216-4f1d-b2cc-3716671107c3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1195931035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1195931035 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.116321965 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 9998662 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:24:47 PM PDT 24 |
| Finished | Mar 21 12:24:47 PM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-81be3377-7478-421a-99bf-6564c91aa231 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=116321965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.116321965 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2851767252 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9560313 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:25:07 PM PDT 24 |
| Finished | Mar 21 12:25:08 PM PDT 24 |
| Peak memory | 144844 kb |
| Host | smart-34d4527a-5851-41a1-a382-6a88222465de |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2851767252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2851767252 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.1801031550 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 11064233 ps |
| CPU time | 0.37 seconds |
| Started | Mar 21 12:24:55 PM PDT 24 |
| Finished | Mar 21 12:24:55 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-820b36f7-8478-4690-9914-4d5568ea1712 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1801031550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1801031550 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.3503914822 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9329721 ps |
| CPU time | 0.37 seconds |
| Started | Mar 21 12:24:45 PM PDT 24 |
| Finished | Mar 21 12:24:46 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-974828c8-ef24-47b5-aa57-5260deee2a08 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3503914822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3503914822 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.3848924038 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8988040 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:25:02 PM PDT 24 |
| Finished | Mar 21 12:25:03 PM PDT 24 |
| Peak memory | 144388 kb |
| Host | smart-2a714f48-d5cc-413d-9344-c697c78f3453 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3848924038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3848924038 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.3096451981 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8852635 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:56 PM PDT 24 |
| Finished | Mar 21 12:24:56 PM PDT 24 |
| Peak memory | 144856 kb |
| Host | smart-ed67ef36-5195-4786-9d00-9ec512f31d36 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3096451981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3096451981 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1698955229 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8720082 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:24:47 PM PDT 24 |
| Finished | Mar 21 12:24:47 PM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-51e13a94-cf58-4391-af3f-ea6aa40b5603 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1698955229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1698955229 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1251071302 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9443619 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:25:02 PM PDT 24 |
| Finished | Mar 21 12:25:03 PM PDT 24 |
| Peak memory | 144896 kb |
| Host | smart-e28a3d82-bb95-4053-9054-e988b22e1c4a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1251071302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1251071302 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.2189545835 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8835197 ps |
| CPU time | 0.46 seconds |
| Started | Mar 21 12:25:04 PM PDT 24 |
| Finished | Mar 21 12:25:05 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-b4a5e2a8-cb2a-48fc-bb3e-e5385cafb7d6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2189545835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2189545835 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.475939501 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28207601 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:26:15 PM PDT 24 |
| Finished | Mar 21 12:26:16 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-963641bf-fa05-483b-bd5e-7409ef0aed68 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=475939501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.475939501 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2466429466 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27916864 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:26:26 PM PDT 24 |
| Finished | Mar 21 12:26:27 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-cc450095-d9f2-4903-afd2-22f728bbdd1f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2466429466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2466429466 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2240209071 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 26690416 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:26:16 PM PDT 24 |
| Finished | Mar 21 12:26:17 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-2ff4a1a5-fb8e-43f1-9783-444fbbf9e9ed |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2240209071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2240209071 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3055814833 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 29350750 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:26:05 PM PDT 24 |
| Finished | Mar 21 12:26:06 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-489fad82-e4f8-4b36-978e-c70e4f845444 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3055814833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3055814833 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2586466081 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26647328 ps |
| CPU time | 0.42 seconds |
| Started | Mar 21 12:26:19 PM PDT 24 |
| Finished | Mar 21 12:26:20 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-c94012e7-779a-4640-9abf-87e9667a8516 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2586466081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2586466081 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1397245187 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 26173704 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:26:14 PM PDT 24 |
| Finished | Mar 21 12:26:15 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-5801ec06-3854-480b-ae20-8ab7e65646cb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1397245187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1397245187 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.570777366 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 29555076 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:26:23 PM PDT 24 |
| Finished | Mar 21 12:26:23 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-347edb56-1d94-44f0-89f8-f2db2c3a4855 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=570777366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.570777366 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1908365950 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27369362 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:26:26 PM PDT 24 |
| Finished | Mar 21 12:26:27 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-2d43ca76-b3ff-40ca-b1aa-cd8d4eb99dbd |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1908365950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1908365950 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2741862756 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 26354044 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:26:18 PM PDT 24 |
| Finished | Mar 21 12:26:19 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-da2518a6-a1ba-42c2-9caa-fa8783aa99b4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2741862756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2741862756 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1837166021 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 28603317 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:26:20 PM PDT 24 |
| Finished | Mar 21 12:26:21 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-f8f84535-efc5-46d7-9ec0-c047a99e791a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1837166021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1837166021 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3200546280 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26329480 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:26:18 PM PDT 24 |
| Finished | Mar 21 12:26:19 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-28f29bc2-6b29-4318-a68d-a986aa23ef11 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3200546280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3200546280 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1526246981 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 24980978 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:26:17 PM PDT 24 |
| Finished | Mar 21 12:26:17 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-f6536488-7839-4213-9173-7930677d1a2a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1526246981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1526246981 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3401382619 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28806555 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:26:17 PM PDT 24 |
| Finished | Mar 21 12:26:18 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-d7c7ba43-54cb-47e0-ab9b-8bf5199ca29b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3401382619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3401382619 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2689942510 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26491811 ps |
| CPU time | 0.39 seconds |
| Started | Mar 21 12:26:23 PM PDT 24 |
| Finished | Mar 21 12:26:24 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-ac0a9c97-a83f-43b3-ab7f-3bb93ff7318e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2689942510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2689942510 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.347232648 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 25939126 ps |
| CPU time | 0.47 seconds |
| Started | Mar 21 12:26:12 PM PDT 24 |
| Finished | Mar 21 12:26:13 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-46072dd8-8848-4c57-8bb4-96231fc93eda |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=347232648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.347232648 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3395249177 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 27912242 ps |
| CPU time | 0.41 seconds |
| Started | Mar 21 12:26:18 PM PDT 24 |
| Finished | Mar 21 12:26:19 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-ccc91096-8255-4698-88d9-66ce88dc4e37 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3395249177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3395249177 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1836960332 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27395703 ps |
| CPU time | 0.4 seconds |
| Started | Mar 21 12:26:14 PM PDT 24 |
| Finished | Mar 21 12:26:15 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-54d5c98f-3f60-4ec2-af74-4535fcc45514 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1836960332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1836960332 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.901621951 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26572910 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:26:16 PM PDT 24 |
| Finished | Mar 21 12:26:16 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-49a3391d-2687-4141-8755-5a42b92c8b2a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=901621951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.901621951 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3469311287 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 27322781 ps |
| CPU time | 0.38 seconds |
| Started | Mar 21 12:26:15 PM PDT 24 |
| Finished | Mar 21 12:26:16 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-f4959f89-0a36-4068-8fe9-9dab6b4dc12d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3469311287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3469311287 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |