Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.42 88.42 100.00 100.00 95.83 95.83 96.43 96.43 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/11.prim_async_alert.1528434061
91.55 3.13 100.00 0.00 95.83 0.00 96.43 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/1.prim_sync_alert.2754228425
93.90 2.35 100.00 0.00 95.83 0.00 100.00 3.57 85.71 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2939603481
94.85 0.94 100.00 0.00 97.92 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/3.prim_sync_alert.903938654
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.805491404

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.3986137718
/workspace/coverage/default/10.prim_async_alert.2770450363
/workspace/coverage/default/12.prim_async_alert.176436268
/workspace/coverage/default/13.prim_async_alert.1069339163
/workspace/coverage/default/14.prim_async_alert.2804575656
/workspace/coverage/default/15.prim_async_alert.1532411016
/workspace/coverage/default/16.prim_async_alert.4033913469
/workspace/coverage/default/17.prim_async_alert.3734153857
/workspace/coverage/default/18.prim_async_alert.643393860
/workspace/coverage/default/19.prim_async_alert.1976402179
/workspace/coverage/default/2.prim_async_alert.1711453962
/workspace/coverage/default/3.prim_async_alert.558982780
/workspace/coverage/default/4.prim_async_alert.109882023
/workspace/coverage/default/5.prim_async_alert.2427842609
/workspace/coverage/default/6.prim_async_alert.205208456
/workspace/coverage/default/7.prim_async_alert.1614415785
/workspace/coverage/default/8.prim_async_alert.1708283926
/workspace/coverage/default/9.prim_async_alert.211638530
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.370331842
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3559367491
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.319105544
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1831695591
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3118476411
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2217336724
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1347938702
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3214522792
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1882045091
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1586337783
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2788863122
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.724046881
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3897309421
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.996533731
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3457204234
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3017566027
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2704561492
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2056028762
/workspace/coverage/sync_alert/0.prim_sync_alert.4172516621
/workspace/coverage/sync_alert/10.prim_sync_alert.569841315
/workspace/coverage/sync_alert/11.prim_sync_alert.1483332320
/workspace/coverage/sync_alert/12.prim_sync_alert.2549387399
/workspace/coverage/sync_alert/13.prim_sync_alert.980454634
/workspace/coverage/sync_alert/14.prim_sync_alert.2200206619
/workspace/coverage/sync_alert/15.prim_sync_alert.1682685072
/workspace/coverage/sync_alert/16.prim_sync_alert.4042914187
/workspace/coverage/sync_alert/17.prim_sync_alert.2084170338
/workspace/coverage/sync_alert/18.prim_sync_alert.3518297317
/workspace/coverage/sync_alert/19.prim_sync_alert.2951706901
/workspace/coverage/sync_alert/2.prim_sync_alert.3443022492
/workspace/coverage/sync_alert/4.prim_sync_alert.3448475758
/workspace/coverage/sync_alert/5.prim_sync_alert.3103581276
/workspace/coverage/sync_alert/6.prim_sync_alert.397139462
/workspace/coverage/sync_alert/7.prim_sync_alert.2348522294
/workspace/coverage/sync_alert/8.prim_sync_alert.2550337353
/workspace/coverage/sync_alert/9.prim_sync_alert.1371396193
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2847513731
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1275510293
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3416010189
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2903688485
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3138221529
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.453740251
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3945957861
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.848789054
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4165893322
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2899418319
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3644323225
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2615749088
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.123181409
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.8573624
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.825769363
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.972935618
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1405189708
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3871520104
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.35915844
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2588382746



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.prim_async_alert.2770450363 Mar 24 12:16:14 PM PDT 24 Mar 24 12:16:15 PM PDT 24 12138855 ps
T2 /workspace/coverage/default/13.prim_async_alert.1069339163 Mar 24 12:18:19 PM PDT 24 Mar 24 12:18:19 PM PDT 24 11033418 ps
T3 /workspace/coverage/default/19.prim_async_alert.1976402179 Mar 24 12:21:37 PM PDT 24 Mar 24 12:21:38 PM PDT 24 11156710 ps
T9 /workspace/coverage/default/1.prim_async_alert.3986137718 Mar 24 12:20:04 PM PDT 24 Mar 24 12:20:06 PM PDT 24 10910233 ps
T7 /workspace/coverage/default/11.prim_async_alert.1528434061 Mar 24 12:18:51 PM PDT 24 Mar 24 12:18:51 PM PDT 24 11036552 ps
T20 /workspace/coverage/default/6.prim_async_alert.205208456 Mar 24 12:18:34 PM PDT 24 Mar 24 12:18:35 PM PDT 24 10805411 ps
T21 /workspace/coverage/default/3.prim_async_alert.558982780 Mar 24 12:18:55 PM PDT 24 Mar 24 12:18:56 PM PDT 24 11041754 ps
T22 /workspace/coverage/default/7.prim_async_alert.1614415785 Mar 24 12:20:59 PM PDT 24 Mar 24 12:21:00 PM PDT 24 11364858 ps
T8 /workspace/coverage/default/5.prim_async_alert.2427842609 Mar 24 12:18:55 PM PDT 24 Mar 24 12:18:56 PM PDT 24 11063234 ps
T16 /workspace/coverage/default/17.prim_async_alert.3734153857 Mar 24 12:20:05 PM PDT 24 Mar 24 12:20:06 PM PDT 24 11136618 ps
T19 /workspace/coverage/default/8.prim_async_alert.1708283926 Mar 24 12:17:26 PM PDT 24 Mar 24 12:17:26 PM PDT 24 11335722 ps
T11 /workspace/coverage/default/18.prim_async_alert.643393860 Mar 24 12:19:19 PM PDT 24 Mar 24 12:19:20 PM PDT 24 12223847 ps
T12 /workspace/coverage/default/2.prim_async_alert.1711453962 Mar 24 12:17:01 PM PDT 24 Mar 24 12:17:01 PM PDT 24 12515007 ps
T17 /workspace/coverage/default/15.prim_async_alert.1532411016 Mar 24 12:21:54 PM PDT 24 Mar 24 12:21:55 PM PDT 24 10629053 ps
T13 /workspace/coverage/default/12.prim_async_alert.176436268 Mar 24 12:17:59 PM PDT 24 Mar 24 12:18:00 PM PDT 24 12232217 ps
T51 /workspace/coverage/default/4.prim_async_alert.109882023 Mar 24 12:18:14 PM PDT 24 Mar 24 12:18:15 PM PDT 24 11858885 ps
T23 /workspace/coverage/default/16.prim_async_alert.4033913469 Mar 24 12:20:04 PM PDT 24 Mar 24 12:20:06 PM PDT 24 11872142 ps
T18 /workspace/coverage/default/14.prim_async_alert.2804575656 Mar 24 12:20:04 PM PDT 24 Mar 24 12:20:06 PM PDT 24 11434143 ps
T52 /workspace/coverage/default/9.prim_async_alert.211638530 Mar 24 12:17:26 PM PDT 24 Mar 24 12:17:26 PM PDT 24 13669947 ps
T24 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1347938702 Mar 24 12:20:18 PM PDT 24 Mar 24 12:20:19 PM PDT 24 30521894 ps
T46 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2704561492 Mar 24 12:20:35 PM PDT 24 Mar 24 12:20:35 PM PDT 24 30074708 ps
T47 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2939603481 Mar 24 12:20:29 PM PDT 24 Mar 24 12:20:30 PM PDT 24 29472271 ps
T25 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1831695591 Mar 24 12:20:34 PM PDT 24 Mar 24 12:20:34 PM PDT 24 31086454 ps
T26 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1882045091 Mar 24 12:21:15 PM PDT 24 Mar 24 12:21:16 PM PDT 24 30173099 ps
T48 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3214522792 Mar 24 12:17:33 PM PDT 24 Mar 24 12:17:34 PM PDT 24 30719479 ps
T45 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2788863122 Mar 24 12:20:53 PM PDT 24 Mar 24 12:20:54 PM PDT 24 28712666 ps
T49 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2217336724 Mar 24 12:20:34 PM PDT 24 Mar 24 12:20:35 PM PDT 24 29609472 ps
T50 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.996533731 Mar 24 12:15:31 PM PDT 24 Mar 24 12:15:32 PM PDT 24 31624967 ps
T4 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.805491404 Mar 24 12:20:44 PM PDT 24 Mar 24 12:20:45 PM PDT 24 32376120 ps
T53 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3897309421 Mar 24 12:17:59 PM PDT 24 Mar 24 12:18:00 PM PDT 24 29471226 ps
T54 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2056028762 Mar 24 12:17:59 PM PDT 24 Mar 24 12:18:00 PM PDT 24 32073873 ps
T55 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.319105544 Mar 24 12:18:16 PM PDT 24 Mar 24 12:18:17 PM PDT 24 31061630 ps
T56 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3118476411 Mar 24 12:18:16 PM PDT 24 Mar 24 12:18:16 PM PDT 24 30060959 ps
T14 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3017566027 Mar 24 12:20:34 PM PDT 24 Mar 24 12:20:34 PM PDT 24 32506472 ps
T57 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.724046881 Mar 24 12:16:59 PM PDT 24 Mar 24 12:17:00 PM PDT 24 31242457 ps
T58 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1586337783 Mar 24 12:22:39 PM PDT 24 Mar 24 12:22:40 PM PDT 24 29590838 ps
T59 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3457204234 Mar 24 12:15:31 PM PDT 24 Mar 24 12:15:32 PM PDT 24 30335069 ps
T60 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3559367491 Mar 24 12:21:06 PM PDT 24 Mar 24 12:21:07 PM PDT 24 29688984 ps
T61 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.370331842 Mar 24 12:20:53 PM PDT 24 Mar 24 12:20:54 PM PDT 24 30167397 ps
T27 /workspace/coverage/sync_alert/14.prim_sync_alert.2200206619 Mar 24 12:18:54 PM PDT 24 Mar 24 12:18:54 PM PDT 24 9828958 ps
T37 /workspace/coverage/sync_alert/9.prim_sync_alert.1371396193 Mar 24 12:20:07 PM PDT 24 Mar 24 12:20:09 PM PDT 24 9584806 ps
T38 /workspace/coverage/sync_alert/7.prim_sync_alert.2348522294 Mar 24 12:23:08 PM PDT 24 Mar 24 12:23:09 PM PDT 24 9354430 ps
T39 /workspace/coverage/sync_alert/4.prim_sync_alert.3448475758 Mar 24 12:21:59 PM PDT 24 Mar 24 12:22:00 PM PDT 24 9244116 ps
T40 /workspace/coverage/sync_alert/1.prim_sync_alert.2754228425 Mar 24 12:22:36 PM PDT 24 Mar 24 12:22:37 PM PDT 24 8576084 ps
T41 /workspace/coverage/sync_alert/18.prim_sync_alert.3518297317 Mar 24 12:18:55 PM PDT 24 Mar 24 12:18:55 PM PDT 24 8820702 ps
T42 /workspace/coverage/sync_alert/6.prim_sync_alert.397139462 Mar 24 12:21:57 PM PDT 24 Mar 24 12:21:58 PM PDT 24 8845476 ps
T43 /workspace/coverage/sync_alert/2.prim_sync_alert.3443022492 Mar 24 12:20:23 PM PDT 24 Mar 24 12:20:24 PM PDT 24 8418278 ps
T44 /workspace/coverage/sync_alert/17.prim_sync_alert.2084170338 Mar 24 12:18:53 PM PDT 24 Mar 24 12:18:53 PM PDT 24 8947839 ps
T28 /workspace/coverage/sync_alert/16.prim_sync_alert.4042914187 Mar 24 12:20:05 PM PDT 24 Mar 24 12:20:06 PM PDT 24 10568263 ps
T29 /workspace/coverage/sync_alert/0.prim_sync_alert.4172516621 Mar 24 12:19:09 PM PDT 24 Mar 24 12:19:09 PM PDT 24 8474582 ps
T30 /workspace/coverage/sync_alert/15.prim_sync_alert.1682685072 Mar 24 12:21:02 PM PDT 24 Mar 24 12:21:02 PM PDT 24 9114971 ps
T31 /workspace/coverage/sync_alert/5.prim_sync_alert.3103581276 Mar 24 12:22:26 PM PDT 24 Mar 24 12:22:27 PM PDT 24 9328183 ps
T15 /workspace/coverage/sync_alert/11.prim_sync_alert.1483332320 Mar 24 12:20:43 PM PDT 24 Mar 24 12:20:44 PM PDT 24 9301578 ps
T62 /workspace/coverage/sync_alert/10.prim_sync_alert.569841315 Mar 24 12:20:08 PM PDT 24 Mar 24 12:20:09 PM PDT 24 8863911 ps
T32 /workspace/coverage/sync_alert/13.prim_sync_alert.980454634 Mar 24 12:20:08 PM PDT 24 Mar 24 12:20:09 PM PDT 24 8541586 ps
T33 /workspace/coverage/sync_alert/19.prim_sync_alert.2951706901 Mar 24 12:18:54 PM PDT 24 Mar 24 12:18:54 PM PDT 24 9247563 ps
T63 /workspace/coverage/sync_alert/12.prim_sync_alert.2549387399 Mar 24 12:19:51 PM PDT 24 Mar 24 12:19:52 PM PDT 24 9039898 ps
T64 /workspace/coverage/sync_alert/8.prim_sync_alert.2550337353 Mar 24 12:18:35 PM PDT 24 Mar 24 12:18:36 PM PDT 24 9216513 ps
T10 /workspace/coverage/sync_alert/3.prim_sync_alert.903938654 Mar 24 12:20:20 PM PDT 24 Mar 24 12:20:20 PM PDT 24 10229168 ps
T34 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1405189708 Mar 24 12:21:11 PM PDT 24 Mar 24 12:21:12 PM PDT 24 28169282 ps
T65 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2899418319 Mar 24 12:20:46 PM PDT 24 Mar 24 12:20:46 PM PDT 24 27732126 ps
T5 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.848789054 Mar 24 12:20:46 PM PDT 24 Mar 24 12:20:46 PM PDT 24 25763449 ps
T66 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.8573624 Mar 24 12:20:45 PM PDT 24 Mar 24 12:20:46 PM PDT 24 25746229 ps
T67 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3644323225 Mar 24 12:20:53 PM PDT 24 Mar 24 12:20:54 PM PDT 24 27248059 ps
T68 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2615749088 Mar 24 12:19:43 PM PDT 24 Mar 24 12:19:43 PM PDT 24 29726401 ps
T35 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.123181409 Mar 24 12:20:59 PM PDT 24 Mar 24 12:21:00 PM PDT 24 26606371 ps
T69 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.972935618 Mar 24 12:18:53 PM PDT 24 Mar 24 12:18:53 PM PDT 24 29606667 ps
T70 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3871520104 Mar 24 12:20:04 PM PDT 24 Mar 24 12:20:06 PM PDT 24 27919347 ps
T36 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4165893322 Mar 24 12:20:53 PM PDT 24 Mar 24 12:20:54 PM PDT 24 26353283 ps
T71 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2588382746 Mar 24 12:18:52 PM PDT 24 Mar 24 12:18:52 PM PDT 24 27996784 ps
T72 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2847513731 Mar 24 12:20:59 PM PDT 24 Mar 24 12:21:00 PM PDT 24 27126619 ps
T6 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.825769363 Mar 24 12:18:08 PM PDT 24 Mar 24 12:18:09 PM PDT 24 26988724 ps
T73 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3416010189 Mar 24 12:16:42 PM PDT 24 Mar 24 12:16:43 PM PDT 24 27851351 ps
T74 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1275510293 Mar 24 12:18:55 PM PDT 24 Mar 24 12:18:56 PM PDT 24 25465612 ps
T75 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.453740251 Mar 24 12:21:54 PM PDT 24 Mar 24 12:21:55 PM PDT 24 26942421 ps
T76 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3945957861 Mar 24 12:20:46 PM PDT 24 Mar 24 12:20:46 PM PDT 24 28882626 ps
T77 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2903688485 Mar 24 12:15:40 PM PDT 24 Mar 24 12:15:41 PM PDT 24 26446641 ps
T78 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.35915844 Mar 24 12:20:05 PM PDT 24 Mar 24 12:20:06 PM PDT 24 25230976 ps
T79 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3138221529 Mar 24 12:20:45 PM PDT 24 Mar 24 12:20:45 PM PDT 24 27081500 ps

Test location /workspace/coverage/default/11.prim_async_alert.1528434061
Short name T7
Test name
Test status
Simulation time 11036552 ps
CPU time 0.39 seconds
Started Mar 24 12:18:51 PM PDT 24
Finished Mar 24 12:18:51 PM PDT 24
Peak memory 145464 kb
Host smart-e4a968ce-5058-47f9-9c35-3ad44e5894ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528434061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1528434061
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2754228425
Short name T40
Test name
Test status
Simulation time 8576084 ps
CPU time 0.45 seconds
Started Mar 24 12:22:36 PM PDT 24
Finished Mar 24 12:22:37 PM PDT 24
Peak memory 143936 kb
Host smart-c815ed75-410f-4373-bef9-ea245380ebb6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2754228425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2754228425
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2939603481
Short name T47
Test name
Test status
Simulation time 29472271 ps
CPU time 0.4 seconds
Started Mar 24 12:20:29 PM PDT 24
Finished Mar 24 12:20:30 PM PDT 24
Peak memory 145636 kb
Host smart-e9404b30-bf41-4f09-a981-e32f0c7e34ad
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2939603481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2939603481
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.903938654
Short name T10
Test name
Test status
Simulation time 10229168 ps
CPU time 0.4 seconds
Started Mar 24 12:20:20 PM PDT 24
Finished Mar 24 12:20:20 PM PDT 24
Peak memory 144988 kb
Host smart-9e5ca628-ed6e-45b7-a214-12fe75faa124
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=903938654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.903938654
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.805491404
Short name T4
Test name
Test status
Simulation time 32376120 ps
CPU time 0.49 seconds
Started Mar 24 12:20:44 PM PDT 24
Finished Mar 24 12:20:45 PM PDT 24
Peak memory 145260 kb
Host smart-66cefb0a-519c-452c-9876-22566d9fd65e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=805491404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.805491404
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3986137718
Short name T9
Test name
Test status
Simulation time 10910233 ps
CPU time 0.42 seconds
Started Mar 24 12:20:04 PM PDT 24
Finished Mar 24 12:20:06 PM PDT 24
Peak memory 144092 kb
Host smart-48c6e1f6-7449-4d3d-902b-db6adf435e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986137718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3986137718
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2770450363
Short name T1
Test name
Test status
Simulation time 12138855 ps
CPU time 0.41 seconds
Started Mar 24 12:16:14 PM PDT 24
Finished Mar 24 12:16:15 PM PDT 24
Peak memory 145908 kb
Host smart-c7b4fb5b-66d9-4377-9955-bbaa0dbc3bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770450363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2770450363
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.176436268
Short name T13
Test name
Test status
Simulation time 12232217 ps
CPU time 0.4 seconds
Started Mar 24 12:17:59 PM PDT 24
Finished Mar 24 12:18:00 PM PDT 24
Peak memory 145908 kb
Host smart-b1488cf3-047c-43cb-8fd7-80802228a48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176436268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.176436268
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1069339163
Short name T2
Test name
Test status
Simulation time 11033418 ps
CPU time 0.44 seconds
Started Mar 24 12:18:19 PM PDT 24
Finished Mar 24 12:18:19 PM PDT 24
Peak memory 145696 kb
Host smart-9a3ac8cc-31a7-4282-b721-ab8b4fae2431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069339163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1069339163
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2804575656
Short name T18
Test name
Test status
Simulation time 11434143 ps
CPU time 0.41 seconds
Started Mar 24 12:20:04 PM PDT 24
Finished Mar 24 12:20:06 PM PDT 24
Peak memory 144832 kb
Host smart-761ff96b-f010-43fb-9ca0-3db0cb892fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804575656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2804575656
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1532411016
Short name T17
Test name
Test status
Simulation time 10629053 ps
CPU time 0.38 seconds
Started Mar 24 12:21:54 PM PDT 24
Finished Mar 24 12:21:55 PM PDT 24
Peak memory 145572 kb
Host smart-f5b5ef26-4345-4f93-8a5a-e15e3de52223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532411016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1532411016
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.4033913469
Short name T23
Test name
Test status
Simulation time 11872142 ps
CPU time 0.41 seconds
Started Mar 24 12:20:04 PM PDT 24
Finished Mar 24 12:20:06 PM PDT 24
Peak memory 144660 kb
Host smart-c9cd218a-d250-4dd9-9910-5f5218e06041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033913469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.4033913469
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3734153857
Short name T16
Test name
Test status
Simulation time 11136618 ps
CPU time 0.38 seconds
Started Mar 24 12:20:05 PM PDT 24
Finished Mar 24 12:20:06 PM PDT 24
Peak memory 144904 kb
Host smart-66e4f0de-ddbf-4b1e-981a-8580fdb58041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734153857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3734153857
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.643393860
Short name T11
Test name
Test status
Simulation time 12223847 ps
CPU time 0.4 seconds
Started Mar 24 12:19:19 PM PDT 24
Finished Mar 24 12:19:20 PM PDT 24
Peak memory 145908 kb
Host smart-072de162-4ffa-4d0d-bbbe-11dc2c178204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643393860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.643393860
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1976402179
Short name T3
Test name
Test status
Simulation time 11156710 ps
CPU time 0.4 seconds
Started Mar 24 12:21:37 PM PDT 24
Finished Mar 24 12:21:38 PM PDT 24
Peak memory 145192 kb
Host smart-3bde499b-f37a-4f02-8ee7-8a77be15099e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976402179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1976402179
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.1711453962
Short name T12
Test name
Test status
Simulation time 12515007 ps
CPU time 0.44 seconds
Started Mar 24 12:17:01 PM PDT 24
Finished Mar 24 12:17:01 PM PDT 24
Peak memory 145700 kb
Host smart-629d9631-02dc-4ad5-946a-466767566b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711453962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1711453962
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.558982780
Short name T21
Test name
Test status
Simulation time 11041754 ps
CPU time 0.38 seconds
Started Mar 24 12:18:55 PM PDT 24
Finished Mar 24 12:18:56 PM PDT 24
Peak memory 145580 kb
Host smart-174f4245-010c-4eed-8e56-c89197f67977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558982780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.558982780
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.109882023
Short name T51
Test name
Test status
Simulation time 11858885 ps
CPU time 0.4 seconds
Started Mar 24 12:18:14 PM PDT 24
Finished Mar 24 12:18:15 PM PDT 24
Peak memory 146008 kb
Host smart-553f09ac-baab-4b0f-9c89-32ca9c85678d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109882023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.109882023
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2427842609
Short name T8
Test name
Test status
Simulation time 11063234 ps
CPU time 0.38 seconds
Started Mar 24 12:18:55 PM PDT 24
Finished Mar 24 12:18:56 PM PDT 24
Peak memory 145596 kb
Host smart-6ee98e18-86de-4e65-8f80-1ab9e6ba5857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427842609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2427842609
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.205208456
Short name T20
Test name
Test status
Simulation time 10805411 ps
CPU time 0.46 seconds
Started Mar 24 12:18:34 PM PDT 24
Finished Mar 24 12:18:35 PM PDT 24
Peak memory 145696 kb
Host smart-37f97491-8c17-4b8c-b484-04b00b1f2ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205208456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.205208456
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1614415785
Short name T22
Test name
Test status
Simulation time 11364858 ps
CPU time 0.39 seconds
Started Mar 24 12:20:59 PM PDT 24
Finished Mar 24 12:21:00 PM PDT 24
Peak memory 145552 kb
Host smart-f80090f3-f125-41e9-85af-7d093c54ba83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614415785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1614415785
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1708283926
Short name T19
Test name
Test status
Simulation time 11335722 ps
CPU time 0.39 seconds
Started Mar 24 12:17:26 PM PDT 24
Finished Mar 24 12:17:26 PM PDT 24
Peak memory 145752 kb
Host smart-6f1ba8d2-b14f-4c38-9d57-9b721d19a236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708283926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1708283926
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.211638530
Short name T52
Test name
Test status
Simulation time 13669947 ps
CPU time 0.41 seconds
Started Mar 24 12:17:26 PM PDT 24
Finished Mar 24 12:17:26 PM PDT 24
Peak memory 145748 kb
Host smart-2f87cd26-1ad2-493d-84a8-6306650011fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211638530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.211638530
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.370331842
Short name T61
Test name
Test status
Simulation time 30167397 ps
CPU time 0.4 seconds
Started Mar 24 12:20:53 PM PDT 24
Finished Mar 24 12:20:54 PM PDT 24
Peak memory 144404 kb
Host smart-80369082-7c27-4950-b379-ed15a2e02350
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=370331842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.370331842
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3559367491
Short name T60
Test name
Test status
Simulation time 29688984 ps
CPU time 0.4 seconds
Started Mar 24 12:21:06 PM PDT 24
Finished Mar 24 12:21:07 PM PDT 24
Peak memory 145640 kb
Host smart-539aa05c-e75e-47cd-a970-88e014202b0a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3559367491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3559367491
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.319105544
Short name T55
Test name
Test status
Simulation time 31061630 ps
CPU time 0.4 seconds
Started Mar 24 12:18:16 PM PDT 24
Finished Mar 24 12:18:17 PM PDT 24
Peak memory 145528 kb
Host smart-b64459b5-7340-41fb-b701-bbe49856e750
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=319105544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.319105544
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1831695591
Short name T25
Test name
Test status
Simulation time 31086454 ps
CPU time 0.4 seconds
Started Mar 24 12:20:34 PM PDT 24
Finished Mar 24 12:20:34 PM PDT 24
Peak memory 145624 kb
Host smart-31280ca5-e45d-4c2e-9f1e-fdb064a33368
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1831695591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1831695591
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3118476411
Short name T56
Test name
Test status
Simulation time 30060959 ps
CPU time 0.4 seconds
Started Mar 24 12:18:16 PM PDT 24
Finished Mar 24 12:18:16 PM PDT 24
Peak memory 145392 kb
Host smart-72af26b0-75c5-479f-a4c7-e0f6d14e49e7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3118476411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3118476411
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2217336724
Short name T49
Test name
Test status
Simulation time 29609472 ps
CPU time 0.41 seconds
Started Mar 24 12:20:34 PM PDT 24
Finished Mar 24 12:20:35 PM PDT 24
Peak memory 145620 kb
Host smart-b941ebe7-c5de-415f-b4bc-79bf91bda33f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2217336724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2217336724
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1347938702
Short name T24
Test name
Test status
Simulation time 30521894 ps
CPU time 0.49 seconds
Started Mar 24 12:20:18 PM PDT 24
Finished Mar 24 12:20:19 PM PDT 24
Peak memory 144196 kb
Host smart-a648a33d-db2f-4a12-b419-cf69ff11a76e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1347938702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1347938702
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3214522792
Short name T48
Test name
Test status
Simulation time 30719479 ps
CPU time 0.41 seconds
Started Mar 24 12:17:33 PM PDT 24
Finished Mar 24 12:17:34 PM PDT 24
Peak memory 146012 kb
Host smart-e31b4551-6663-4151-b625-fc506d3c9e6f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3214522792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3214522792
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1882045091
Short name T26
Test name
Test status
Simulation time 30173099 ps
CPU time 0.43 seconds
Started Mar 24 12:21:15 PM PDT 24
Finished Mar 24 12:21:16 PM PDT 24
Peak memory 145256 kb
Host smart-f700eb2d-a742-4816-a7e7-770eae092b72
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1882045091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1882045091
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1586337783
Short name T58
Test name
Test status
Simulation time 29590838 ps
CPU time 0.39 seconds
Started Mar 24 12:22:39 PM PDT 24
Finished Mar 24 12:22:40 PM PDT 24
Peak memory 145252 kb
Host smart-e5f9f080-e54c-4101-87f2-64135b292d28
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1586337783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1586337783
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2788863122
Short name T45
Test name
Test status
Simulation time 28712666 ps
CPU time 0.43 seconds
Started Mar 24 12:20:53 PM PDT 24
Finished Mar 24 12:20:54 PM PDT 24
Peak memory 144616 kb
Host smart-e83b08c5-3a42-4b9c-be9c-20465eae79fb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2788863122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2788863122
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.724046881
Short name T57
Test name
Test status
Simulation time 31242457 ps
CPU time 0.43 seconds
Started Mar 24 12:16:59 PM PDT 24
Finished Mar 24 12:17:00 PM PDT 24
Peak memory 145764 kb
Host smart-c7c7159c-9568-4b93-b66c-b55ed3b5d06a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=724046881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.724046881
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3897309421
Short name T53
Test name
Test status
Simulation time 29471226 ps
CPU time 0.44 seconds
Started Mar 24 12:17:59 PM PDT 24
Finished Mar 24 12:18:00 PM PDT 24
Peak memory 144540 kb
Host smart-fb9c50f7-bb4e-4bd0-8555-28437b91a199
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3897309421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3897309421
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.996533731
Short name T50
Test name
Test status
Simulation time 31624967 ps
CPU time 0.42 seconds
Started Mar 24 12:15:31 PM PDT 24
Finished Mar 24 12:15:32 PM PDT 24
Peak memory 146016 kb
Host smart-e9845d99-220c-47d7-bb7d-bdb8f9efc6a0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=996533731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.996533731
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3457204234
Short name T59
Test name
Test status
Simulation time 30335069 ps
CPU time 0.49 seconds
Started Mar 24 12:15:31 PM PDT 24
Finished Mar 24 12:15:32 PM PDT 24
Peak memory 146016 kb
Host smart-1de63c55-99e4-4b23-b143-f22efc00a902
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3457204234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3457204234
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3017566027
Short name T14
Test name
Test status
Simulation time 32506472 ps
CPU time 0.39 seconds
Started Mar 24 12:20:34 PM PDT 24
Finished Mar 24 12:20:34 PM PDT 24
Peak memory 145624 kb
Host smart-07909f63-80c6-4d63-aa9b-85444567b6ea
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3017566027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3017566027
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2704561492
Short name T46
Test name
Test status
Simulation time 30074708 ps
CPU time 0.41 seconds
Started Mar 24 12:20:35 PM PDT 24
Finished Mar 24 12:20:35 PM PDT 24
Peak memory 145628 kb
Host smart-57a30116-d102-4bb6-9e9f-14b2e04e78e0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2704561492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2704561492
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2056028762
Short name T54
Test name
Test status
Simulation time 32073873 ps
CPU time 0.44 seconds
Started Mar 24 12:17:59 PM PDT 24
Finished Mar 24 12:18:00 PM PDT 24
Peak memory 145676 kb
Host smart-5227b693-0216-4a5c-830e-4c15c4c5842a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2056028762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2056028762
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.4172516621
Short name T29
Test name
Test status
Simulation time 8474582 ps
CPU time 0.38 seconds
Started Mar 24 12:19:09 PM PDT 24
Finished Mar 24 12:19:09 PM PDT 24
Peak memory 144896 kb
Host smart-c8db1a3e-f09e-4028-b5ba-2e78eaa4a0a4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4172516621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4172516621
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.569841315
Short name T62
Test name
Test status
Simulation time 8863911 ps
CPU time 0.37 seconds
Started Mar 24 12:20:08 PM PDT 24
Finished Mar 24 12:20:09 PM PDT 24
Peak memory 144696 kb
Host smart-07639459-4284-4acf-9c7d-5fa1349ba2b5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=569841315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.569841315
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1483332320
Short name T15
Test name
Test status
Simulation time 9301578 ps
CPU time 0.4 seconds
Started Mar 24 12:20:43 PM PDT 24
Finished Mar 24 12:20:44 PM PDT 24
Peak memory 143412 kb
Host smart-440746b2-572f-4122-9209-ac97c125b7a9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1483332320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1483332320
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2549387399
Short name T63
Test name
Test status
Simulation time 9039898 ps
CPU time 0.42 seconds
Started Mar 24 12:19:51 PM PDT 24
Finished Mar 24 12:19:52 PM PDT 24
Peak memory 145348 kb
Host smart-6f5b6257-182b-403f-99d6-69a861fa23d3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2549387399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2549387399
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.980454634
Short name T32
Test name
Test status
Simulation time 8541586 ps
CPU time 0.37 seconds
Started Mar 24 12:20:08 PM PDT 24
Finished Mar 24 12:20:09 PM PDT 24
Peak memory 144700 kb
Host smart-e2a7664a-58f6-4c8e-9abb-76f3d5e0a5a1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=980454634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.980454634
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2200206619
Short name T27
Test name
Test status
Simulation time 9828958 ps
CPU time 0.37 seconds
Started Mar 24 12:18:54 PM PDT 24
Finished Mar 24 12:18:54 PM PDT 24
Peak memory 144796 kb
Host smart-d6fab097-a52d-470b-bc2c-38fa68901b9f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2200206619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2200206619
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1682685072
Short name T30
Test name
Test status
Simulation time 9114971 ps
CPU time 0.4 seconds
Started Mar 24 12:21:02 PM PDT 24
Finished Mar 24 12:21:02 PM PDT 24
Peak memory 144896 kb
Host smart-3773e87f-3a03-4263-a721-79c1c24e32e1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1682685072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1682685072
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.4042914187
Short name T28
Test name
Test status
Simulation time 10568263 ps
CPU time 0.37 seconds
Started Mar 24 12:20:05 PM PDT 24
Finished Mar 24 12:20:06 PM PDT 24
Peak memory 144428 kb
Host smart-db1e1e96-2ef2-4ba5-8655-6383ca25ecab
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4042914187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.4042914187
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2084170338
Short name T44
Test name
Test status
Simulation time 8947839 ps
CPU time 0.4 seconds
Started Mar 24 12:18:53 PM PDT 24
Finished Mar 24 12:18:53 PM PDT 24
Peak memory 144988 kb
Host smart-587866d0-2b76-44d8-852a-e9d55730bb24
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2084170338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2084170338
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3518297317
Short name T41
Test name
Test status
Simulation time 8820702 ps
CPU time 0.39 seconds
Started Mar 24 12:18:55 PM PDT 24
Finished Mar 24 12:18:55 PM PDT 24
Peak memory 144888 kb
Host smart-228fe3d8-066a-400d-aa69-0e6653a942fc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3518297317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3518297317
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2951706901
Short name T33
Test name
Test status
Simulation time 9247563 ps
CPU time 0.38 seconds
Started Mar 24 12:18:54 PM PDT 24
Finished Mar 24 12:18:54 PM PDT 24
Peak memory 144868 kb
Host smart-916f4435-f51b-4c5e-aa2a-4ffcc0f3d5fa
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2951706901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2951706901
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3443022492
Short name T43
Test name
Test status
Simulation time 8418278 ps
CPU time 0.43 seconds
Started Mar 24 12:20:23 PM PDT 24
Finished Mar 24 12:20:24 PM PDT 24
Peak memory 144864 kb
Host smart-7c4a4e09-a7bb-4849-b1ee-bfd0f86a5a4b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3443022492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3443022492
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3448475758
Short name T39
Test name
Test status
Simulation time 9244116 ps
CPU time 0.42 seconds
Started Mar 24 12:21:59 PM PDT 24
Finished Mar 24 12:22:00 PM PDT 24
Peak memory 145060 kb
Host smart-51661ae7-b677-41e6-a943-3b5bde4b8a50
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3448475758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3448475758
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3103581276
Short name T31
Test name
Test status
Simulation time 9328183 ps
CPU time 0.39 seconds
Started Mar 24 12:22:26 PM PDT 24
Finished Mar 24 12:22:27 PM PDT 24
Peak memory 144856 kb
Host smart-82acd270-c017-4691-8ecd-a8709e06b5fe
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3103581276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3103581276
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.397139462
Short name T42
Test name
Test status
Simulation time 8845476 ps
CPU time 0.39 seconds
Started Mar 24 12:21:57 PM PDT 24
Finished Mar 24 12:21:58 PM PDT 24
Peak memory 144724 kb
Host smart-0de4d2ee-d2bd-4c16-a9fa-f0aa71b1dc4d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=397139462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.397139462
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2348522294
Short name T38
Test name
Test status
Simulation time 9354430 ps
CPU time 0.38 seconds
Started Mar 24 12:23:08 PM PDT 24
Finished Mar 24 12:23:09 PM PDT 24
Peak memory 144856 kb
Host smart-3b2d0501-ab44-4e99-89c5-33100c3d8390
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2348522294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2348522294
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2550337353
Short name T64
Test name
Test status
Simulation time 9216513 ps
CPU time 0.4 seconds
Started Mar 24 12:18:35 PM PDT 24
Finished Mar 24 12:18:36 PM PDT 24
Peak memory 145188 kb
Host smart-aceee8eb-b8cd-4549-8b42-3de68729408d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2550337353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2550337353
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1371396193
Short name T37
Test name
Test status
Simulation time 9584806 ps
CPU time 0.38 seconds
Started Mar 24 12:20:07 PM PDT 24
Finished Mar 24 12:20:09 PM PDT 24
Peak memory 144656 kb
Host smart-a6c0b484-7851-4a27-ae10-1ffef56ee266
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1371396193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1371396193
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2847513731
Short name T72
Test name
Test status
Simulation time 27126619 ps
CPU time 0.42 seconds
Started Mar 24 12:20:59 PM PDT 24
Finished Mar 24 12:21:00 PM PDT 24
Peak memory 144904 kb
Host smart-fc97968a-90bb-49a2-8137-bd14399ea0f4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2847513731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2847513731
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1275510293
Short name T74
Test name
Test status
Simulation time 25465612 ps
CPU time 0.43 seconds
Started Mar 24 12:18:55 PM PDT 24
Finished Mar 24 12:18:56 PM PDT 24
Peak memory 145032 kb
Host smart-8822fe56-47dc-4ca1-9d80-42c3233298a2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1275510293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1275510293
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3416010189
Short name T73
Test name
Test status
Simulation time 27851351 ps
CPU time 0.46 seconds
Started Mar 24 12:16:42 PM PDT 24
Finished Mar 24 12:16:43 PM PDT 24
Peak memory 145020 kb
Host smart-8dbabb34-bcb8-4659-bb22-74ee8711477d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3416010189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3416010189
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2903688485
Short name T77
Test name
Test status
Simulation time 26446641 ps
CPU time 0.48 seconds
Started Mar 24 12:15:40 PM PDT 24
Finished Mar 24 12:15:41 PM PDT 24
Peak memory 145020 kb
Host smart-00d6c761-f9bd-41b6-b55a-ac7695ce9695
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2903688485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2903688485
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3138221529
Short name T79
Test name
Test status
Simulation time 27081500 ps
CPU time 0.42 seconds
Started Mar 24 12:20:45 PM PDT 24
Finished Mar 24 12:20:45 PM PDT 24
Peak memory 144492 kb
Host smart-f2e44aff-d109-42db-87a6-aee057eb3b5b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3138221529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3138221529
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.453740251
Short name T75
Test name
Test status
Simulation time 26942421 ps
CPU time 0.4 seconds
Started Mar 24 12:21:54 PM PDT 24
Finished Mar 24 12:21:55 PM PDT 24
Peak memory 144904 kb
Host smart-72d93242-f776-4d70-9fb9-01efacf3586d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=453740251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.453740251
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3945957861
Short name T76
Test name
Test status
Simulation time 28882626 ps
CPU time 0.43 seconds
Started Mar 24 12:20:46 PM PDT 24
Finished Mar 24 12:20:46 PM PDT 24
Peak memory 144896 kb
Host smart-111db882-0d33-4f1c-9a7c-2012b36f23d9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3945957861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3945957861
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.848789054
Short name T5
Test name
Test status
Simulation time 25763449 ps
CPU time 0.39 seconds
Started Mar 24 12:20:46 PM PDT 24
Finished Mar 24 12:20:46 PM PDT 24
Peak memory 144916 kb
Host smart-7d5c66b1-3cca-4a87-87e5-ca2b946c62be
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=848789054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.848789054
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4165893322
Short name T36
Test name
Test status
Simulation time 26353283 ps
CPU time 0.39 seconds
Started Mar 24 12:20:53 PM PDT 24
Finished Mar 24 12:20:54 PM PDT 24
Peak memory 144080 kb
Host smart-be0439e4-3ae9-4aa2-9ae4-c28368723153
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4165893322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.4165893322
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2899418319
Short name T65
Test name
Test status
Simulation time 27732126 ps
CPU time 0.4 seconds
Started Mar 24 12:20:46 PM PDT 24
Finished Mar 24 12:20:46 PM PDT 24
Peak memory 144936 kb
Host smart-72387465-0970-4881-85b8-071bcc4bcb2f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2899418319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2899418319
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3644323225
Short name T67
Test name
Test status
Simulation time 27248059 ps
CPU time 0.42 seconds
Started Mar 24 12:20:53 PM PDT 24
Finished Mar 24 12:20:54 PM PDT 24
Peak memory 144308 kb
Host smart-b5704fe1-e4dd-413a-8c04-04cae7d2a3e9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3644323225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3644323225
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2615749088
Short name T68
Test name
Test status
Simulation time 29726401 ps
CPU time 0.43 seconds
Started Mar 24 12:19:43 PM PDT 24
Finished Mar 24 12:19:43 PM PDT 24
Peak memory 144940 kb
Host smart-dace0dba-1490-4bd9-9361-c04b3379b39c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2615749088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2615749088
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.123181409
Short name T35
Test name
Test status
Simulation time 26606371 ps
CPU time 0.39 seconds
Started Mar 24 12:20:59 PM PDT 24
Finished Mar 24 12:21:00 PM PDT 24
Peak memory 144900 kb
Host smart-b793c916-92ed-480b-9994-72211bc7fc6d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=123181409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.123181409
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.8573624
Short name T66
Test name
Test status
Simulation time 25746229 ps
CPU time 0.4 seconds
Started Mar 24 12:20:45 PM PDT 24
Finished Mar 24 12:20:46 PM PDT 24
Peak memory 144880 kb
Host smart-d68ec6bf-ffd0-46c4-81ab-d8d6bb3d453d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=8573624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.8573624
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.825769363
Short name T6
Test name
Test status
Simulation time 26988724 ps
CPU time 0.42 seconds
Started Mar 24 12:18:08 PM PDT 24
Finished Mar 24 12:18:09 PM PDT 24
Peak memory 145036 kb
Host smart-153dd508-e5f8-4881-85b9-d17abd6ce831
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=825769363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.825769363
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.972935618
Short name T69
Test name
Test status
Simulation time 29606667 ps
CPU time 0.4 seconds
Started Mar 24 12:18:53 PM PDT 24
Finished Mar 24 12:18:53 PM PDT 24
Peak memory 144672 kb
Host smart-e3d67f7a-2bbe-450b-8196-4fcbe1c7be15
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=972935618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.972935618
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1405189708
Short name T34
Test name
Test status
Simulation time 28169282 ps
CPU time 0.4 seconds
Started Mar 24 12:21:11 PM PDT 24
Finished Mar 24 12:21:12 PM PDT 24
Peak memory 144920 kb
Host smart-35546a10-9b87-4b2c-af6a-fe5bef5ada13
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1405189708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1405189708
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3871520104
Short name T70
Test name
Test status
Simulation time 27919347 ps
CPU time 0.39 seconds
Started Mar 24 12:20:04 PM PDT 24
Finished Mar 24 12:20:06 PM PDT 24
Peak memory 144408 kb
Host smart-735190cf-f773-4213-bd44-8072a5c57d31
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3871520104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3871520104
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.35915844
Short name T78
Test name
Test status
Simulation time 25230976 ps
CPU time 0.38 seconds
Started Mar 24 12:20:05 PM PDT 24
Finished Mar 24 12:20:06 PM PDT 24
Peak memory 144444 kb
Host smart-1c5b4879-4a77-4fa4-a86b-400e2e920ffe
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=35915844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.35915844
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2588382746
Short name T71
Test name
Test status
Simulation time 27996784 ps
CPU time 0.41 seconds
Started Mar 24 12:18:52 PM PDT 24
Finished Mar 24 12:18:52 PM PDT 24
Peak memory 145028 kb
Host smart-c8bce91d-1104-4e31-9d58-967428fff197
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2588382746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2588382746
Directory /workspace/9.prim_sync_fatal_alert/latest
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