Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 78
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 96.43 96.43 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/3.prim_async_alert.1493377786
91.80 3.13 100.00 0.00 93.75 0.00 96.43 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/10.prim_sync_alert.1578598406
94.50 2.70 100.00 0.00 95.83 2.08 100.00 3.57 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3794840645
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.156731641

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3603136805
/workspace/coverage/default/1.prim_async_alert.3728282678
/workspace/coverage/default/10.prim_async_alert.2167904867
/workspace/coverage/default/11.prim_async_alert.2104416678
/workspace/coverage/default/12.prim_async_alert.1551281559
/workspace/coverage/default/13.prim_async_alert.843160735
/workspace/coverage/default/14.prim_async_alert.989917901
/workspace/coverage/default/15.prim_async_alert.818969190
/workspace/coverage/default/17.prim_async_alert.993667352
/workspace/coverage/default/18.prim_async_alert.2317217185
/workspace/coverage/default/19.prim_async_alert.522622481
/workspace/coverage/default/2.prim_async_alert.3592817111
/workspace/coverage/default/4.prim_async_alert.3434639087
/workspace/coverage/default/5.prim_async_alert.3741906650
/workspace/coverage/default/6.prim_async_alert.3567026085
/workspace/coverage/default/7.prim_async_alert.2917429170
/workspace/coverage/default/9.prim_async_alert.3871864484
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4027585592
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.35101383
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2647889002
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2262399580
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2716548158
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1668332560
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1246579848
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2407408603
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1530273741
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4240833687
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3037539595
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3278477818
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2163665922
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.671979158
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3608552663
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3376196734
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3277891591
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1537205091
/workspace/coverage/sync_alert/0.prim_sync_alert.3711730181
/workspace/coverage/sync_alert/1.prim_sync_alert.3203541952
/workspace/coverage/sync_alert/11.prim_sync_alert.836707890
/workspace/coverage/sync_alert/12.prim_sync_alert.192069446
/workspace/coverage/sync_alert/13.prim_sync_alert.3111109227
/workspace/coverage/sync_alert/14.prim_sync_alert.415442871
/workspace/coverage/sync_alert/15.prim_sync_alert.337319800
/workspace/coverage/sync_alert/16.prim_sync_alert.1230190566
/workspace/coverage/sync_alert/17.prim_sync_alert.3320213179
/workspace/coverage/sync_alert/18.prim_sync_alert.2448175089
/workspace/coverage/sync_alert/19.prim_sync_alert.1586861164
/workspace/coverage/sync_alert/2.prim_sync_alert.3353521190
/workspace/coverage/sync_alert/3.prim_sync_alert.3803020991
/workspace/coverage/sync_alert/4.prim_sync_alert.2760299342
/workspace/coverage/sync_alert/5.prim_sync_alert.1544493429
/workspace/coverage/sync_alert/6.prim_sync_alert.378482443
/workspace/coverage/sync_alert/7.prim_sync_alert.1835260745
/workspace/coverage/sync_alert/8.prim_sync_alert.2744119921
/workspace/coverage/sync_alert/9.prim_sync_alert.4075448780
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4203242563
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.350403812
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2045010008
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3502577717
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2591455269
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1240021332
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2792985073
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1760111357
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3834923882
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1100960404
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3145136050
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3283176970
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2457467230
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3425228165
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.288731777
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3810742267
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3723314438
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.178827517
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1319225338
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3795002812



Total test records in report: 78
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/5.prim_async_alert.3741906650 Mar 26 12:20:17 PM PDT 24 Mar 26 12:20:18 PM PDT 24 11064361 ps
T2 /workspace/coverage/default/7.prim_async_alert.2917429170 Mar 26 12:20:17 PM PDT 24 Mar 26 12:20:18 PM PDT 24 11261269 ps
T3 /workspace/coverage/default/10.prim_async_alert.2167904867 Mar 26 12:21:55 PM PDT 24 Mar 26 12:21:55 PM PDT 24 11679060 ps
T15 /workspace/coverage/default/0.prim_async_alert.3603136805 Mar 26 12:20:06 PM PDT 24 Mar 26 12:20:07 PM PDT 24 11111475 ps
T10 /workspace/coverage/default/4.prim_async_alert.3434639087 Mar 26 12:20:18 PM PDT 24 Mar 26 12:20:19 PM PDT 24 10360353 ps
T11 /workspace/coverage/default/9.prim_async_alert.3871864484 Mar 26 12:20:16 PM PDT 24 Mar 26 12:20:17 PM PDT 24 11983963 ps
T7 /workspace/coverage/default/6.prim_async_alert.3567026085 Mar 26 12:20:17 PM PDT 24 Mar 26 12:20:18 PM PDT 24 10570027 ps
T12 /workspace/coverage/default/15.prim_async_alert.818969190 Mar 26 12:23:15 PM PDT 24 Mar 26 12:23:16 PM PDT 24 11375413 ps
T16 /workspace/coverage/default/3.prim_async_alert.1493377786 Mar 26 12:20:20 PM PDT 24 Mar 26 12:20:21 PM PDT 24 11824697 ps
T17 /workspace/coverage/default/11.prim_async_alert.2104416678 Mar 26 12:22:26 PM PDT 24 Mar 26 12:22:27 PM PDT 24 11418733 ps
T8 /workspace/coverage/default/2.prim_async_alert.3592817111 Mar 26 12:20:20 PM PDT 24 Mar 26 12:20:21 PM PDT 24 11584519 ps
T9 /workspace/coverage/default/12.prim_async_alert.1551281559 Mar 26 12:27:06 PM PDT 24 Mar 26 12:27:07 PM PDT 24 10998815 ps
T18 /workspace/coverage/default/17.prim_async_alert.993667352 Mar 26 12:27:06 PM PDT 24 Mar 26 12:27:07 PM PDT 24 10965271 ps
T13 /workspace/coverage/default/19.prim_async_alert.522622481 Mar 26 12:25:28 PM PDT 24 Mar 26 12:25:29 PM PDT 24 12043760 ps
T19 /workspace/coverage/default/1.prim_async_alert.3728282678 Mar 26 12:20:17 PM PDT 24 Mar 26 12:20:18 PM PDT 24 10011958 ps
T14 /workspace/coverage/default/14.prim_async_alert.989917901 Mar 26 12:27:06 PM PDT 24 Mar 26 12:27:07 PM PDT 24 11584572 ps
T45 /workspace/coverage/default/13.prim_async_alert.843160735 Mar 26 12:21:08 PM PDT 24 Mar 26 12:21:09 PM PDT 24 12012489 ps
T20 /workspace/coverage/default/18.prim_async_alert.2317217185 Mar 26 12:27:06 PM PDT 24 Mar 26 12:27:07 PM PDT 24 10937838 ps
T36 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1246579848 Mar 26 12:25:45 PM PDT 24 Mar 26 12:25:46 PM PDT 24 28690027 ps
T37 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3794840645 Mar 26 12:20:17 PM PDT 24 Mar 26 12:20:18 PM PDT 24 31491631 ps
T38 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3037539595 Mar 26 12:25:45 PM PDT 24 Mar 26 12:25:46 PM PDT 24 29424351 ps
T21 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4027585592 Mar 26 12:20:13 PM PDT 24 Mar 26 12:20:14 PM PDT 24 28106133 ps
T39 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2163665922 Mar 26 12:20:13 PM PDT 24 Mar 26 12:20:14 PM PDT 24 29650985 ps
T40 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3277891591 Mar 26 12:20:11 PM PDT 24 Mar 26 12:20:11 PM PDT 24 30761059 ps
T41 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.671979158 Mar 26 12:20:04 PM PDT 24 Mar 26 12:20:05 PM PDT 24 29820954 ps
T42 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3278477818 Mar 26 12:20:17 PM PDT 24 Mar 26 12:20:18 PM PDT 24 29252320 ps
T43 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2407408603 Mar 26 12:25:25 PM PDT 24 Mar 26 12:25:26 PM PDT 24 31757449 ps
T44 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2262399580 Mar 26 12:23:51 PM PDT 24 Mar 26 12:23:52 PM PDT 24 30643271 ps
T46 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3608552663 Mar 26 12:20:20 PM PDT 24 Mar 26 12:20:21 PM PDT 24 28450024 ps
T47 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3376196734 Mar 26 12:20:17 PM PDT 24 Mar 26 12:20:18 PM PDT 24 31616415 ps
T4 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.156731641 Mar 26 12:20:18 PM PDT 24 Mar 26 12:20:19 PM PDT 24 28753993 ps
T48 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2716548158 Mar 26 12:25:44 PM PDT 24 Mar 26 12:25:45 PM PDT 24 30660436 ps
T49 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2647889002 Mar 26 12:25:38 PM PDT 24 Mar 26 12:25:38 PM PDT 24 29122869 ps
T50 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.35101383 Mar 26 12:22:30 PM PDT 24 Mar 26 12:22:30 PM PDT 24 29791508 ps
T51 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1537205091 Mar 26 12:20:11 PM PDT 24 Mar 26 12:20:12 PM PDT 24 31869761 ps
T52 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1530273741 Mar 26 12:26:14 PM PDT 24 Mar 26 12:26:15 PM PDT 24 29680306 ps
T53 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4240833687 Mar 26 12:23:33 PM PDT 24 Mar 26 12:23:33 PM PDT 24 31570708 ps
T54 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1668332560 Mar 26 12:23:31 PM PDT 24 Mar 26 12:23:32 PM PDT 24 29755686 ps
T22 /workspace/coverage/sync_alert/18.prim_sync_alert.2448175089 Mar 26 12:26:12 PM PDT 24 Mar 26 12:26:13 PM PDT 24 8582737 ps
T23 /workspace/coverage/sync_alert/15.prim_sync_alert.337319800 Mar 26 12:23:24 PM PDT 24 Mar 26 12:23:25 PM PDT 24 8347727 ps
T24 /workspace/coverage/sync_alert/10.prim_sync_alert.1578598406 Mar 26 12:26:13 PM PDT 24 Mar 26 12:26:14 PM PDT 24 9658901 ps
T32 /workspace/coverage/sync_alert/0.prim_sync_alert.3711730181 Mar 26 12:22:27 PM PDT 24 Mar 26 12:22:27 PM PDT 24 9220655 ps
T33 /workspace/coverage/sync_alert/12.prim_sync_alert.192069446 Mar 26 12:24:54 PM PDT 24 Mar 26 12:24:55 PM PDT 24 8391251 ps
T25 /workspace/coverage/sync_alert/6.prim_sync_alert.378482443 Mar 26 12:25:44 PM PDT 24 Mar 26 12:25:44 PM PDT 24 8970779 ps
T26 /workspace/coverage/sync_alert/7.prim_sync_alert.1835260745 Mar 26 12:25:43 PM PDT 24 Mar 26 12:25:44 PM PDT 24 9173853 ps
T27 /workspace/coverage/sync_alert/8.prim_sync_alert.2744119921 Mar 26 12:26:37 PM PDT 24 Mar 26 12:26:38 PM PDT 24 10264477 ps
T34 /workspace/coverage/sync_alert/17.prim_sync_alert.3320213179 Mar 26 12:26:13 PM PDT 24 Mar 26 12:26:14 PM PDT 24 9316085 ps
T35 /workspace/coverage/sync_alert/14.prim_sync_alert.415442871 Mar 26 12:26:54 PM PDT 24 Mar 26 12:26:55 PM PDT 24 9186314 ps
T28 /workspace/coverage/sync_alert/13.prim_sync_alert.3111109227 Mar 26 12:26:22 PM PDT 24 Mar 26 12:26:22 PM PDT 24 8554637 ps
T29 /workspace/coverage/sync_alert/11.prim_sync_alert.836707890 Mar 26 12:26:20 PM PDT 24 Mar 26 12:26:21 PM PDT 24 9890618 ps
T30 /workspace/coverage/sync_alert/3.prim_sync_alert.3803020991 Mar 26 12:26:19 PM PDT 24 Mar 26 12:26:19 PM PDT 24 8847131 ps
T31 /workspace/coverage/sync_alert/5.prim_sync_alert.1544493429 Mar 26 12:23:20 PM PDT 24 Mar 26 12:23:21 PM PDT 24 9989070 ps
T55 /workspace/coverage/sync_alert/4.prim_sync_alert.2760299342 Mar 26 12:26:18 PM PDT 24 Mar 26 12:26:18 PM PDT 24 9012625 ps
T56 /workspace/coverage/sync_alert/2.prim_sync_alert.3353521190 Mar 26 12:26:01 PM PDT 24 Mar 26 12:26:02 PM PDT 24 9286877 ps
T57 /workspace/coverage/sync_alert/16.prim_sync_alert.1230190566 Mar 26 12:26:55 PM PDT 24 Mar 26 12:26:55 PM PDT 24 9360827 ps
T58 /workspace/coverage/sync_alert/1.prim_sync_alert.3203541952 Mar 26 12:26:19 PM PDT 24 Mar 26 12:26:19 PM PDT 24 9449403 ps
T59 /workspace/coverage/sync_alert/19.prim_sync_alert.1586861164 Mar 26 12:23:51 PM PDT 24 Mar 26 12:23:52 PM PDT 24 9537471 ps
T60 /workspace/coverage/sync_alert/9.prim_sync_alert.4075448780 Mar 26 12:25:25 PM PDT 24 Mar 26 12:25:27 PM PDT 24 9894375 ps
T61 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3425228165 Mar 26 12:22:19 PM PDT 24 Mar 26 12:22:19 PM PDT 24 28873929 ps
T62 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3795002812 Mar 26 12:25:21 PM PDT 24 Mar 26 12:25:22 PM PDT 24 27788185 ps
T63 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2045010008 Mar 26 12:20:48 PM PDT 24 Mar 26 12:20:48 PM PDT 24 27287563 ps
T64 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1319225338 Mar 26 12:26:30 PM PDT 24 Mar 26 12:26:32 PM PDT 24 27077212 ps
T65 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.350403812 Mar 26 12:25:09 PM PDT 24 Mar 26 12:25:10 PM PDT 24 28352808 ps
T66 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4203242563 Mar 26 12:25:49 PM PDT 24 Mar 26 12:25:49 PM PDT 24 28250566 ps
T67 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3810742267 Mar 26 12:27:20 PM PDT 24 Mar 26 12:27:21 PM PDT 24 28852571 ps
T68 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.288731777 Mar 26 12:25:49 PM PDT 24 Mar 26 12:25:49 PM PDT 24 28573169 ps
T69 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3834923882 Mar 26 12:25:29 PM PDT 24 Mar 26 12:25:30 PM PDT 24 26281218 ps
T5 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3723314438 Mar 26 12:25:48 PM PDT 24 Mar 26 12:25:49 PM PDT 24 27047057 ps
T70 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1240021332 Mar 26 12:21:08 PM PDT 24 Mar 26 12:21:09 PM PDT 24 27839432 ps
T6 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.178827517 Mar 26 12:26:30 PM PDT 24 Mar 26 12:26:32 PM PDT 24 27484006 ps
T71 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2591455269 Mar 26 12:27:06 PM PDT 24 Mar 26 12:27:07 PM PDT 24 28238194 ps
T72 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3145136050 Mar 26 12:22:26 PM PDT 24 Mar 26 12:22:27 PM PDT 24 26538760 ps
T73 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2792985073 Mar 26 12:22:21 PM PDT 24 Mar 26 12:22:22 PM PDT 24 27158899 ps
T74 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3502577717 Mar 26 12:23:22 PM PDT 24 Mar 26 12:23:23 PM PDT 24 29449534 ps
T75 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1100960404 Mar 26 12:23:18 PM PDT 24 Mar 26 12:23:19 PM PDT 24 28537603 ps
T76 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1760111357 Mar 26 12:26:43 PM PDT 24 Mar 26 12:26:44 PM PDT 24 27953359 ps
T77 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2457467230 Mar 26 12:26:21 PM PDT 24 Mar 26 12:26:22 PM PDT 24 27280712 ps
T78 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3283176970 Mar 26 12:25:28 PM PDT 24 Mar 26 12:25:29 PM PDT 24 26226727 ps

Test location /workspace/coverage/default/3.prim_async_alert.1493377786
Short name T16
Test name
Test status
Simulation time 11824697 ps
CPU time 0.49 seconds
Started Mar 26 12:20:20 PM PDT 24
Finished Mar 26 12:20:21 PM PDT 24
Peak memory 144504 kb
Host smart-c1434a55-c115-4264-98cf-1dbdb3046c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493377786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1493377786
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1578598406
Short name T24
Test name
Test status
Simulation time 9658901 ps
CPU time 0.38 seconds
Started Mar 26 12:26:13 PM PDT 24
Finished Mar 26 12:26:14 PM PDT 24
Peak memory 144660 kb
Host smart-804cbff3-b5e6-4d8b-9b9e-e855c21cac6e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1578598406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1578598406
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3794840645
Short name T37
Test name
Test status
Simulation time 31491631 ps
CPU time 0.42 seconds
Started Mar 26 12:20:17 PM PDT 24
Finished Mar 26 12:20:18 PM PDT 24
Peak memory 145428 kb
Host smart-f23f7d22-80cf-42fa-ad1c-caea652b5027
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3794840645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3794840645
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.156731641
Short name T4
Test name
Test status
Simulation time 28753993 ps
CPU time 0.46 seconds
Started Mar 26 12:20:18 PM PDT 24
Finished Mar 26 12:20:19 PM PDT 24
Peak memory 145816 kb
Host smart-60522acb-3fa1-48e8-866b-2afcf3186a1e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=156731641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.156731641
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3603136805
Short name T15
Test name
Test status
Simulation time 11111475 ps
CPU time 0.39 seconds
Started Mar 26 12:20:06 PM PDT 24
Finished Mar 26 12:20:07 PM PDT 24
Peak memory 145956 kb
Host smart-1f11a56f-0592-4688-a9ba-4d08eb815d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603136805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3603136805
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3728282678
Short name T19
Test name
Test status
Simulation time 10011958 ps
CPU time 0.39 seconds
Started Mar 26 12:20:17 PM PDT 24
Finished Mar 26 12:20:18 PM PDT 24
Peak memory 145412 kb
Host smart-5f131446-5136-478e-9a26-76496054ef30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728282678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3728282678
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2167904867
Short name T3
Test name
Test status
Simulation time 11679060 ps
CPU time 0.43 seconds
Started Mar 26 12:21:55 PM PDT 24
Finished Mar 26 12:21:55 PM PDT 24
Peak memory 145732 kb
Host smart-180077fe-67b4-404a-9f19-d411ec9447ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167904867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2167904867
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2104416678
Short name T17
Test name
Test status
Simulation time 11418733 ps
CPU time 0.4 seconds
Started Mar 26 12:22:26 PM PDT 24
Finished Mar 26 12:22:27 PM PDT 24
Peak memory 145732 kb
Host smart-3d106f20-3b3a-4db3-b7bf-c3e56c925776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104416678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2104416678
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1551281559
Short name T9
Test name
Test status
Simulation time 10998815 ps
CPU time 0.43 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:27:07 PM PDT 24
Peak memory 144164 kb
Host smart-0e5fff87-7d71-4767-ac6c-87ac6e1b7214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551281559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1551281559
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.843160735
Short name T45
Test name
Test status
Simulation time 12012489 ps
CPU time 0.39 seconds
Started Mar 26 12:21:08 PM PDT 24
Finished Mar 26 12:21:09 PM PDT 24
Peak memory 145644 kb
Host smart-31f8733e-5235-4248-9454-57436e8ceb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843160735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.843160735
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.989917901
Short name T14
Test name
Test status
Simulation time 11584572 ps
CPU time 0.41 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:27:07 PM PDT 24
Peak memory 144132 kb
Host smart-81edc0a7-dfc7-4cae-8ba0-95fc08cfe530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989917901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.989917901
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.818969190
Short name T12
Test name
Test status
Simulation time 11375413 ps
CPU time 0.39 seconds
Started Mar 26 12:23:15 PM PDT 24
Finished Mar 26 12:23:16 PM PDT 24
Peak memory 145960 kb
Host smart-0e03c47b-20e0-44e5-982a-bd5eb704da01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818969190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.818969190
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.993667352
Short name T18
Test name
Test status
Simulation time 10965271 ps
CPU time 0.43 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:27:07 PM PDT 24
Peak memory 144404 kb
Host smart-c3acb195-ede4-413a-bdc3-3c8f0c1c098b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993667352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.993667352
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2317217185
Short name T20
Test name
Test status
Simulation time 10937838 ps
CPU time 0.42 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:27:07 PM PDT 24
Peak memory 144452 kb
Host smart-e152f882-3e72-437d-8707-34cbcfbee65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317217185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2317217185
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.522622481
Short name T13
Test name
Test status
Simulation time 12043760 ps
CPU time 0.38 seconds
Started Mar 26 12:25:28 PM PDT 24
Finished Mar 26 12:25:29 PM PDT 24
Peak memory 145608 kb
Host smart-a0355c47-df10-49b5-9545-a2f89a87b9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522622481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.522622481
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3592817111
Short name T8
Test name
Test status
Simulation time 11584519 ps
CPU time 0.53 seconds
Started Mar 26 12:20:20 PM PDT 24
Finished Mar 26 12:20:21 PM PDT 24
Peak memory 143960 kb
Host smart-ebe525ab-a1cf-4080-908c-9451e00548fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592817111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3592817111
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3434639087
Short name T10
Test name
Test status
Simulation time 10360353 ps
CPU time 0.45 seconds
Started Mar 26 12:20:18 PM PDT 24
Finished Mar 26 12:20:19 PM PDT 24
Peak memory 145884 kb
Host smart-d7ad6d60-4600-4169-bd01-4e6ba92bdc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434639087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3434639087
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3741906650
Short name T1
Test name
Test status
Simulation time 11064361 ps
CPU time 0.38 seconds
Started Mar 26 12:20:17 PM PDT 24
Finished Mar 26 12:20:18 PM PDT 24
Peak memory 145872 kb
Host smart-aa3235ac-a5bc-4fec-bf2f-14b2306465ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741906650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3741906650
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3567026085
Short name T7
Test name
Test status
Simulation time 10570027 ps
CPU time 0.38 seconds
Started Mar 26 12:20:17 PM PDT 24
Finished Mar 26 12:20:18 PM PDT 24
Peak memory 145412 kb
Host smart-55552cfe-7d64-4a57-ba3a-1aa87e0d9c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567026085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3567026085
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2917429170
Short name T2
Test name
Test status
Simulation time 11261269 ps
CPU time 0.38 seconds
Started Mar 26 12:20:17 PM PDT 24
Finished Mar 26 12:20:18 PM PDT 24
Peak memory 145396 kb
Host smart-6803a9ee-ff91-48d4-b875-bac3539ad2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917429170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2917429170
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3871864484
Short name T11
Test name
Test status
Simulation time 11983963 ps
CPU time 0.42 seconds
Started Mar 26 12:20:16 PM PDT 24
Finished Mar 26 12:20:17 PM PDT 24
Peak memory 144948 kb
Host smart-a8fd2fe1-c280-4e8f-9b9b-d8078492ebcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871864484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3871864484
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4027585592
Short name T21
Test name
Test status
Simulation time 28106133 ps
CPU time 0.43 seconds
Started Mar 26 12:20:13 PM PDT 24
Finished Mar 26 12:20:14 PM PDT 24
Peak memory 145684 kb
Host smart-86782b34-f31b-45aa-8c67-b817904ff04e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4027585592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.4027585592
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.35101383
Short name T50
Test name
Test status
Simulation time 29791508 ps
CPU time 0.41 seconds
Started Mar 26 12:22:30 PM PDT 24
Finished Mar 26 12:22:30 PM PDT 24
Peak memory 145696 kb
Host smart-eee5eb09-2fd4-446e-8bc9-ca9825dd8398
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=35101383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.35101383
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2647889002
Short name T49
Test name
Test status
Simulation time 29122869 ps
CPU time 0.41 seconds
Started Mar 26 12:25:38 PM PDT 24
Finished Mar 26 12:25:38 PM PDT 24
Peak memory 145628 kb
Host smart-ca785d82-85ff-46a8-b27d-65f8c512f22e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2647889002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2647889002
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2262399580
Short name T44
Test name
Test status
Simulation time 30643271 ps
CPU time 0.4 seconds
Started Mar 26 12:23:51 PM PDT 24
Finished Mar 26 12:23:52 PM PDT 24
Peak memory 145632 kb
Host smart-bc9e3fa7-4fb7-4160-94b6-b905a8630439
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2262399580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2262399580
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2716548158
Short name T48
Test name
Test status
Simulation time 30660436 ps
CPU time 0.39 seconds
Started Mar 26 12:25:44 PM PDT 24
Finished Mar 26 12:25:45 PM PDT 24
Peak memory 145432 kb
Host smart-df66abff-b295-483f-b785-31936dee2c7e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2716548158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2716548158
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1668332560
Short name T54
Test name
Test status
Simulation time 29755686 ps
CPU time 0.41 seconds
Started Mar 26 12:23:31 PM PDT 24
Finished Mar 26 12:23:32 PM PDT 24
Peak memory 145632 kb
Host smart-30e3b700-a080-476a-9cf1-f310e862bea3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1668332560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1668332560
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1246579848
Short name T36
Test name
Test status
Simulation time 28690027 ps
CPU time 0.41 seconds
Started Mar 26 12:25:45 PM PDT 24
Finished Mar 26 12:25:46 PM PDT 24
Peak memory 145648 kb
Host smart-402f2667-a253-4f04-bdc3-9a5da6b6f656
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1246579848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1246579848
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2407408603
Short name T43
Test name
Test status
Simulation time 31757449 ps
CPU time 0.4 seconds
Started Mar 26 12:25:25 PM PDT 24
Finished Mar 26 12:25:26 PM PDT 24
Peak memory 145648 kb
Host smart-1d424a3c-bd56-4e8b-ba2c-117058d2f091
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2407408603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2407408603
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1530273741
Short name T52
Test name
Test status
Simulation time 29680306 ps
CPU time 0.39 seconds
Started Mar 26 12:26:14 PM PDT 24
Finished Mar 26 12:26:15 PM PDT 24
Peak memory 145452 kb
Host smart-efb0f285-c6e3-4771-8324-5d41ea095d98
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1530273741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1530273741
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4240833687
Short name T53
Test name
Test status
Simulation time 31570708 ps
CPU time 0.45 seconds
Started Mar 26 12:23:33 PM PDT 24
Finished Mar 26 12:23:33 PM PDT 24
Peak memory 145664 kb
Host smart-8f17ad32-e48f-4cfd-92f1-8b77f57a8bf2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4240833687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.4240833687
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3037539595
Short name T38
Test name
Test status
Simulation time 29424351 ps
CPU time 0.39 seconds
Started Mar 26 12:25:45 PM PDT 24
Finished Mar 26 12:25:46 PM PDT 24
Peak memory 145644 kb
Host smart-691669bc-5b64-4edf-b2dc-cab9f1d012bf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3037539595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3037539595
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3278477818
Short name T42
Test name
Test status
Simulation time 29252320 ps
CPU time 0.39 seconds
Started Mar 26 12:20:17 PM PDT 24
Finished Mar 26 12:20:18 PM PDT 24
Peak memory 145428 kb
Host smart-1bcd550e-119d-410c-b913-4b78f8b887c3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3278477818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3278477818
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2163665922
Short name T39
Test name
Test status
Simulation time 29650985 ps
CPU time 0.44 seconds
Started Mar 26 12:20:13 PM PDT 24
Finished Mar 26 12:20:14 PM PDT 24
Peak memory 145668 kb
Host smart-c89e8cd0-cdf4-4467-9652-eabd4922df9f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2163665922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2163665922
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.671979158
Short name T41
Test name
Test status
Simulation time 29820954 ps
CPU time 0.44 seconds
Started Mar 26 12:20:04 PM PDT 24
Finished Mar 26 12:20:05 PM PDT 24
Peak memory 144624 kb
Host smart-403c9ffd-d9ac-434a-99f1-efb136285cfa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=671979158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.671979158
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3608552663
Short name T46
Test name
Test status
Simulation time 28450024 ps
CPU time 0.51 seconds
Started Mar 26 12:20:20 PM PDT 24
Finished Mar 26 12:20:21 PM PDT 24
Peak memory 145136 kb
Host smart-6c0e714f-b9aa-4547-b9eb-a7b3d73e7c5b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3608552663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3608552663
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3376196734
Short name T47
Test name
Test status
Simulation time 31616415 ps
CPU time 0.4 seconds
Started Mar 26 12:20:17 PM PDT 24
Finished Mar 26 12:20:18 PM PDT 24
Peak memory 145888 kb
Host smart-5803c783-02eb-46ff-beea-48d450653d7d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3376196734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3376196734
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3277891591
Short name T40
Test name
Test status
Simulation time 30761059 ps
CPU time 0.41 seconds
Started Mar 26 12:20:11 PM PDT 24
Finished Mar 26 12:20:11 PM PDT 24
Peak memory 145968 kb
Host smart-424f6d55-687a-43c2-94b9-85e52dc6cc20
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3277891591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3277891591
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1537205091
Short name T51
Test name
Test status
Simulation time 31869761 ps
CPU time 0.41 seconds
Started Mar 26 12:20:11 PM PDT 24
Finished Mar 26 12:20:12 PM PDT 24
Peak memory 145968 kb
Host smart-cddf5770-b833-40d4-af60-bc1b9f9fa916
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1537205091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1537205091
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3711730181
Short name T32
Test name
Test status
Simulation time 9220655 ps
CPU time 0.39 seconds
Started Mar 26 12:22:27 PM PDT 24
Finished Mar 26 12:22:27 PM PDT 24
Peak memory 145016 kb
Host smart-10543716-7903-461e-a0a7-1db61ad6ceb7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3711730181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3711730181
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3203541952
Short name T58
Test name
Test status
Simulation time 9449403 ps
CPU time 0.37 seconds
Started Mar 26 12:26:19 PM PDT 24
Finished Mar 26 12:26:19 PM PDT 24
Peak memory 144848 kb
Host smart-46c57dd2-5abe-4742-ab49-a911288e0629
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3203541952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3203541952
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.836707890
Short name T29
Test name
Test status
Simulation time 9890618 ps
CPU time 0.43 seconds
Started Mar 26 12:26:20 PM PDT 24
Finished Mar 26 12:26:21 PM PDT 24
Peak memory 145332 kb
Host smart-84c583c6-3a36-4a04-946c-9392663814c3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=836707890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.836707890
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.192069446
Short name T33
Test name
Test status
Simulation time 8391251 ps
CPU time 0.39 seconds
Started Mar 26 12:24:54 PM PDT 24
Finished Mar 26 12:24:55 PM PDT 24
Peak memory 144912 kb
Host smart-cbb5674d-f959-4451-93d8-7e11ff3d6c3e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=192069446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.192069446
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3111109227
Short name T28
Test name
Test status
Simulation time 8554637 ps
CPU time 0.39 seconds
Started Mar 26 12:26:22 PM PDT 24
Finished Mar 26 12:26:22 PM PDT 24
Peak memory 144644 kb
Host smart-002e69ab-efa8-4fe7-998e-8b54f7d7b694
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3111109227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3111109227
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.415442871
Short name T35
Test name
Test status
Simulation time 9186314 ps
CPU time 0.38 seconds
Started Mar 26 12:26:54 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 144908 kb
Host smart-d15a2912-7502-4433-b3f0-574f2fb7cf0b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=415442871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.415442871
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.337319800
Short name T23
Test name
Test status
Simulation time 8347727 ps
CPU time 0.38 seconds
Started Mar 26 12:23:24 PM PDT 24
Finished Mar 26 12:23:25 PM PDT 24
Peak memory 144880 kb
Host smart-5aceef2a-0321-44e5-b5b2-3af7350c333c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=337319800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.337319800
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1230190566
Short name T57
Test name
Test status
Simulation time 9360827 ps
CPU time 0.38 seconds
Started Mar 26 12:26:55 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 144912 kb
Host smart-29b0ad28-917f-46e3-99bd-e1d8c9c733df
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1230190566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1230190566
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3320213179
Short name T34
Test name
Test status
Simulation time 9316085 ps
CPU time 0.37 seconds
Started Mar 26 12:26:13 PM PDT 24
Finished Mar 26 12:26:14 PM PDT 24
Peak memory 144652 kb
Host smart-df288664-a023-4e2e-a25e-4fa7c7e26cf2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3320213179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3320213179
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2448175089
Short name T22
Test name
Test status
Simulation time 8582737 ps
CPU time 0.43 seconds
Started Mar 26 12:26:12 PM PDT 24
Finished Mar 26 12:26:13 PM PDT 24
Peak memory 145348 kb
Host smart-65f2272c-542f-4674-af43-8cf10e8bb131
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2448175089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2448175089
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1586861164
Short name T59
Test name
Test status
Simulation time 9537471 ps
CPU time 0.39 seconds
Started Mar 26 12:23:51 PM PDT 24
Finished Mar 26 12:23:52 PM PDT 24
Peak memory 144912 kb
Host smart-e3290bc0-fda3-48da-8eaf-8d5435f43dfd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1586861164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1586861164
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3353521190
Short name T56
Test name
Test status
Simulation time 9286877 ps
CPU time 0.41 seconds
Started Mar 26 12:26:01 PM PDT 24
Finished Mar 26 12:26:02 PM PDT 24
Peak memory 145328 kb
Host smart-35fd7685-6360-4f28-9f68-351b2d46ac75
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3353521190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3353521190
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3803020991
Short name T30
Test name
Test status
Simulation time 8847131 ps
CPU time 0.37 seconds
Started Mar 26 12:26:19 PM PDT 24
Finished Mar 26 12:26:19 PM PDT 24
Peak memory 144848 kb
Host smart-3e2d0420-e91d-4c7e-b63f-76f9040583b3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3803020991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3803020991
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2760299342
Short name T55
Test name
Test status
Simulation time 9012625 ps
CPU time 0.39 seconds
Started Mar 26 12:26:18 PM PDT 24
Finished Mar 26 12:26:18 PM PDT 24
Peak memory 144632 kb
Host smart-8169bf89-544a-4772-8cee-95d2de93ce7c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2760299342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2760299342
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1544493429
Short name T31
Test name
Test status
Simulation time 9989070 ps
CPU time 0.41 seconds
Started Mar 26 12:23:20 PM PDT 24
Finished Mar 26 12:23:21 PM PDT 24
Peak memory 144908 kb
Host smart-7c24cacc-4ddc-4a84-84e3-58d7e870a352
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1544493429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1544493429
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.378482443
Short name T25
Test name
Test status
Simulation time 8970779 ps
CPU time 0.37 seconds
Started Mar 26 12:25:44 PM PDT 24
Finished Mar 26 12:25:44 PM PDT 24
Peak memory 144632 kb
Host smart-dfb29c89-ba8f-4073-8214-a8e301bd91d2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=378482443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.378482443
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1835260745
Short name T26
Test name
Test status
Simulation time 9173853 ps
CPU time 0.38 seconds
Started Mar 26 12:25:43 PM PDT 24
Finished Mar 26 12:25:44 PM PDT 24
Peak memory 144592 kb
Host smart-2bbcc77e-6429-4e25-9442-b860e3ab0799
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1835260745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1835260745
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2744119921
Short name T27
Test name
Test status
Simulation time 10264477 ps
CPU time 0.49 seconds
Started Mar 26 12:26:37 PM PDT 24
Finished Mar 26 12:26:38 PM PDT 24
Peak memory 145324 kb
Host smart-222965af-ff5a-44d7-95c4-7a817e7f4e98
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2744119921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2744119921
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.4075448780
Short name T60
Test name
Test status
Simulation time 9894375 ps
CPU time 0.4 seconds
Started Mar 26 12:25:25 PM PDT 24
Finished Mar 26 12:25:27 PM PDT 24
Peak memory 145324 kb
Host smart-002b8810-b389-4e63-a693-f33dde4f3f7b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4075448780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.4075448780
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4203242563
Short name T66
Test name
Test status
Simulation time 28250566 ps
CPU time 0.38 seconds
Started Mar 26 12:25:49 PM PDT 24
Finished Mar 26 12:25:49 PM PDT 24
Peak memory 144156 kb
Host smart-fcc29059-52cb-4885-80c0-778a47a5c528
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4203242563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4203242563
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.350403812
Short name T65
Test name
Test status
Simulation time 28352808 ps
CPU time 0.37 seconds
Started Mar 26 12:25:09 PM PDT 24
Finished Mar 26 12:25:10 PM PDT 24
Peak memory 144332 kb
Host smart-e98447d7-88b6-4712-88c7-1cc168222edd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=350403812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.350403812
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2045010008
Short name T63
Test name
Test status
Simulation time 27287563 ps
CPU time 0.41 seconds
Started Mar 26 12:20:48 PM PDT 24
Finished Mar 26 12:20:48 PM PDT 24
Peak memory 145796 kb
Host smart-f8b600a0-5e20-4798-8a74-9f65dba16e4b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2045010008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2045010008
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3502577717
Short name T74
Test name
Test status
Simulation time 29449534 ps
CPU time 0.41 seconds
Started Mar 26 12:23:22 PM PDT 24
Finished Mar 26 12:23:23 PM PDT 24
Peak memory 144912 kb
Host smart-3d586396-e95c-470a-a621-99edd4950f13
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3502577717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3502577717
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2591455269
Short name T71
Test name
Test status
Simulation time 28238194 ps
CPU time 0.39 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:27:07 PM PDT 24
Peak memory 143860 kb
Host smart-34e41fd4-b542-4893-bae0-c4489c310f29
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2591455269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2591455269
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1240021332
Short name T70
Test name
Test status
Simulation time 27839432 ps
CPU time 0.4 seconds
Started Mar 26 12:21:08 PM PDT 24
Finished Mar 26 12:21:09 PM PDT 24
Peak memory 145164 kb
Host smart-1fe06303-86a5-47f5-81f5-1ad5544218a1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1240021332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1240021332
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2792985073
Short name T73
Test name
Test status
Simulation time 27158899 ps
CPU time 0.42 seconds
Started Mar 26 12:22:21 PM PDT 24
Finished Mar 26 12:22:22 PM PDT 24
Peak memory 145164 kb
Host smart-539cd971-7898-4f19-8e3c-2eac1cabf748
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2792985073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2792985073
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1760111357
Short name T76
Test name
Test status
Simulation time 27953359 ps
CPU time 0.4 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:44 PM PDT 24
Peak memory 144912 kb
Host smart-6ae42732-bbdb-46be-b6c0-b6dc11857df0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1760111357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1760111357
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3834923882
Short name T69
Test name
Test status
Simulation time 26281218 ps
CPU time 0.42 seconds
Started Mar 26 12:25:29 PM PDT 24
Finished Mar 26 12:25:30 PM PDT 24
Peak memory 145352 kb
Host smart-cd61a81b-81a8-4dc7-b506-09963ac798ab
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3834923882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3834923882
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1100960404
Short name T75
Test name
Test status
Simulation time 28537603 ps
CPU time 0.41 seconds
Started Mar 26 12:23:18 PM PDT 24
Finished Mar 26 12:23:19 PM PDT 24
Peak memory 144936 kb
Host smart-87fb8c4a-0ff3-4106-87b8-b735083a35c0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1100960404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1100960404
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3145136050
Short name T72
Test name
Test status
Simulation time 26538760 ps
CPU time 0.45 seconds
Started Mar 26 12:22:26 PM PDT 24
Finished Mar 26 12:22:27 PM PDT 24
Peak memory 145004 kb
Host smart-1da61976-08f8-49f5-806f-1d7233f79974
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3145136050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3145136050
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3283176970
Short name T78
Test name
Test status
Simulation time 26226727 ps
CPU time 0.47 seconds
Started Mar 26 12:25:28 PM PDT 24
Finished Mar 26 12:25:29 PM PDT 24
Peak memory 145352 kb
Host smart-63888237-9a28-4f05-9fbf-cfd7999e2a2a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3283176970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3283176970
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2457467230
Short name T77
Test name
Test status
Simulation time 27280712 ps
CPU time 0.44 seconds
Started Mar 26 12:26:21 PM PDT 24
Finished Mar 26 12:26:22 PM PDT 24
Peak memory 145344 kb
Host smart-457afc3c-59ca-46bc-9961-a3377e1ce920
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2457467230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2457467230
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3425228165
Short name T61
Test name
Test status
Simulation time 28873929 ps
CPU time 0.4 seconds
Started Mar 26 12:22:19 PM PDT 24
Finished Mar 26 12:22:19 PM PDT 24
Peak memory 144888 kb
Host smart-fe479788-4e39-4d82-b937-9e01e696ff93
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3425228165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3425228165
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.288731777
Short name T68
Test name
Test status
Simulation time 28573169 ps
CPU time 0.39 seconds
Started Mar 26 12:25:49 PM PDT 24
Finished Mar 26 12:25:49 PM PDT 24
Peak memory 144648 kb
Host smart-80cb5855-fe32-4a6c-8645-25388f583d0c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=288731777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.288731777
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3810742267
Short name T67
Test name
Test status
Simulation time 28852571 ps
CPU time 0.37 seconds
Started Mar 26 12:27:20 PM PDT 24
Finished Mar 26 12:27:21 PM PDT 24
Peak memory 144648 kb
Host smart-34da58d0-fa70-4b19-9493-ad66a315afaa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3810742267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3810742267
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3723314438
Short name T5
Test name
Test status
Simulation time 27047057 ps
CPU time 0.41 seconds
Started Mar 26 12:25:48 PM PDT 24
Finished Mar 26 12:25:49 PM PDT 24
Peak memory 143736 kb
Host smart-4a5682b6-d856-4e3b-a5ba-b31d9173ea41
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3723314438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3723314438
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.178827517
Short name T6
Test name
Test status
Simulation time 27484006 ps
CPU time 0.46 seconds
Started Mar 26 12:26:30 PM PDT 24
Finished Mar 26 12:26:32 PM PDT 24
Peak memory 145044 kb
Host smart-037c28fa-7a94-4fa8-8753-bde8ffbabd20
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=178827517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.178827517
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1319225338
Short name T64
Test name
Test status
Simulation time 27077212 ps
CPU time 0.44 seconds
Started Mar 26 12:26:30 PM PDT 24
Finished Mar 26 12:26:32 PM PDT 24
Peak memory 145000 kb
Host smart-1173b3a1-a1c3-4dfc-8046-b0f655ccbdaa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1319225338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1319225338
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3795002812
Short name T62
Test name
Test status
Simulation time 27788185 ps
CPU time 0.43 seconds
Started Mar 26 12:25:21 PM PDT 24
Finished Mar 26 12:25:22 PM PDT 24
Peak memory 143896 kb
Host smart-3d880408-f245-4cb9-bc43-3ea324fb7b18
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3795002812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3795002812
Directory /workspace/9.prim_sync_fatal_alert/latest
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