| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.88 | 88.88 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/5.prim_async_alert.2457222837 |
| 92.01 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/14.prim_sync_alert.560693487 |
| 93.86 | 1.86 | 100.00 | 0.00 | 97.92 | 4.17 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 83.72 | 6.98 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2718827128 |
| 94.46 | 0.60 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 83.72 | 0.00 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3838067885 |
| 94.85 | 0.39 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 2.33 | /workspace/coverage/default/11.prim_async_alert.3288062045 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.748375534 |
| /workspace/coverage/default/1.prim_async_alert.199610079 |
| /workspace/coverage/default/10.prim_async_alert.985276870 |
| /workspace/coverage/default/12.prim_async_alert.2972391054 |
| /workspace/coverage/default/13.prim_async_alert.3024810201 |
| /workspace/coverage/default/14.prim_async_alert.1319509170 |
| /workspace/coverage/default/15.prim_async_alert.3104361626 |
| /workspace/coverage/default/16.prim_async_alert.537447089 |
| /workspace/coverage/default/17.prim_async_alert.3207900373 |
| /workspace/coverage/default/18.prim_async_alert.414741542 |
| /workspace/coverage/default/19.prim_async_alert.3124700584 |
| /workspace/coverage/default/3.prim_async_alert.1796214834 |
| /workspace/coverage/default/4.prim_async_alert.4174751119 |
| /workspace/coverage/default/6.prim_async_alert.2523321657 |
| /workspace/coverage/default/7.prim_async_alert.2596681060 |
| /workspace/coverage/default/8.prim_async_alert.1647580294 |
| /workspace/coverage/default/9.prim_async_alert.2713694667 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3813880144 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4191038812 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.321629114 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1753685185 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.594366818 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1104624557 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2312377929 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3267031415 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3558752932 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4025138082 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3174988438 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3363061720 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.615195333 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3421662813 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2112610381 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.417294719 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.2184146366 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.2445104593 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3419982018 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.500132073 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.488034359 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.3690179078 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.416649329 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.2389492576 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.1757863951 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.3023023673 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.342460991 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2999113842 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.2618397306 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.1020590572 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.3720457399 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.2658605954 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1346763742 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.3818116535 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.2251782119 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2622582833 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2790126881 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.891744503 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3450020057 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3987936096 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3662292669 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1547106482 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3413318385 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3473402111 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.374400194 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2885824548 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3303673605 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1813389359 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1762290667 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.449402920 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1235537896 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2127381818 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2464919017 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2598465726 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3951153715 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/15.prim_async_alert.3104361626 | Apr 02 12:20:39 PM PDT 24 | Apr 02 12:20:40 PM PDT 24 | 11776532 ps | ||
| T2 | /workspace/coverage/default/8.prim_async_alert.1647580294 | Apr 02 12:22:30 PM PDT 24 | Apr 02 12:22:31 PM PDT 24 | 10655377 ps | ||
| T3 | /workspace/coverage/default/6.prim_async_alert.2523321657 | Apr 02 12:22:12 PM PDT 24 | Apr 02 12:22:13 PM PDT 24 | 12599130 ps | ||
| T7 | /workspace/coverage/default/9.prim_async_alert.2713694667 | Apr 02 12:22:48 PM PDT 24 | Apr 02 12:22:50 PM PDT 24 | 12183887 ps | ||
| T8 | /workspace/coverage/default/16.prim_async_alert.537447089 | Apr 02 12:22:30 PM PDT 24 | Apr 02 12:22:30 PM PDT 24 | 10933904 ps | ||
| T9 | /workspace/coverage/default/3.prim_async_alert.1796214834 | Apr 02 12:20:08 PM PDT 24 | Apr 02 12:20:09 PM PDT 24 | 11257002 ps | ||
| T10 | /workspace/coverage/default/19.prim_async_alert.3124700584 | Apr 02 12:20:08 PM PDT 24 | Apr 02 12:20:09 PM PDT 24 | 10512372 ps | ||
| T18 | /workspace/coverage/default/7.prim_async_alert.2596681060 | Apr 02 12:22:14 PM PDT 24 | Apr 02 12:22:15 PM PDT 24 | 10921765 ps | ||
| T19 | /workspace/coverage/default/17.prim_async_alert.3207900373 | Apr 02 12:20:41 PM PDT 24 | Apr 02 12:20:42 PM PDT 24 | 11571031 ps | ||
| T11 | /workspace/coverage/default/5.prim_async_alert.2457222837 | Apr 02 12:22:12 PM PDT 24 | Apr 02 12:22:13 PM PDT 24 | 11673822 ps | ||
| T17 | /workspace/coverage/default/11.prim_async_alert.3288062045 | Apr 02 12:20:08 PM PDT 24 | Apr 02 12:20:09 PM PDT 24 | 11504653 ps | ||
| T43 | /workspace/coverage/default/10.prim_async_alert.985276870 | Apr 02 12:20:08 PM PDT 24 | Apr 02 12:20:09 PM PDT 24 | 10851145 ps | ||
| T44 | /workspace/coverage/default/13.prim_async_alert.3024810201 | Apr 02 12:19:09 PM PDT 24 | Apr 02 12:19:10 PM PDT 24 | 11427481 ps | ||
| T15 | /workspace/coverage/default/0.prim_async_alert.748375534 | Apr 02 12:22:15 PM PDT 24 | Apr 02 12:22:16 PM PDT 24 | 11973494 ps | ||
| T45 | /workspace/coverage/default/1.prim_async_alert.199610079 | Apr 02 12:22:20 PM PDT 24 | Apr 02 12:22:21 PM PDT 24 | 11597782 ps | ||
| T20 | /workspace/coverage/default/14.prim_async_alert.1319509170 | Apr 02 12:24:10 PM PDT 24 | Apr 02 12:24:10 PM PDT 24 | 11299898 ps | ||
| T46 | /workspace/coverage/default/12.prim_async_alert.2972391054 | Apr 02 12:20:09 PM PDT 24 | Apr 02 12:20:10 PM PDT 24 | 11368597 ps | ||
| T16 | /workspace/coverage/default/4.prim_async_alert.4174751119 | Apr 02 12:22:30 PM PDT 24 | Apr 02 12:22:31 PM PDT 24 | 10926090 ps | ||
| T21 | /workspace/coverage/default/18.prim_async_alert.414741542 | Apr 02 12:22:30 PM PDT 24 | Apr 02 12:22:31 PM PDT 24 | 11240882 ps | ||
| T22 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3267031415 | Apr 02 12:17:32 PM PDT 24 | Apr 02 12:17:33 PM PDT 24 | 30973929 ps | ||
| T23 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.594366818 | Apr 02 12:17:31 PM PDT 24 | Apr 02 12:17:32 PM PDT 24 | 29103229 ps | ||
| T12 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3421662813 | Apr 02 12:17:35 PM PDT 24 | Apr 02 12:17:36 PM PDT 24 | 30893543 ps | ||
| T38 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3558752932 | Apr 02 12:17:25 PM PDT 24 | Apr 02 12:17:25 PM PDT 24 | 29706695 ps | ||
| T4 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2718827128 | Apr 02 12:17:24 PM PDT 24 | Apr 02 12:17:25 PM PDT 24 | 28399351 ps | ||
| T39 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4025138082 | Apr 02 12:17:32 PM PDT 24 | Apr 02 12:17:33 PM PDT 24 | 30641551 ps | ||
| T40 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4191038812 | Apr 02 12:17:35 PM PDT 24 | Apr 02 12:17:36 PM PDT 24 | 32413629 ps | ||
| T41 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1104624557 | Apr 02 12:17:34 PM PDT 24 | Apr 02 12:17:34 PM PDT 24 | 29677226 ps | ||
| T42 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3174988438 | Apr 02 12:17:24 PM PDT 24 | Apr 02 12:17:24 PM PDT 24 | 31873320 ps | ||
| T37 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3813880144 | Apr 02 12:17:33 PM PDT 24 | Apr 02 12:17:33 PM PDT 24 | 31669662 ps | ||
| T47 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.615195333 | Apr 02 12:17:32 PM PDT 24 | Apr 02 12:17:33 PM PDT 24 | 28794602 ps | ||
| T13 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3838067885 | Apr 02 12:17:35 PM PDT 24 | Apr 02 12:17:35 PM PDT 24 | 31191790 ps | ||
| T48 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.321629114 | Apr 02 12:17:33 PM PDT 24 | Apr 02 12:17:34 PM PDT 24 | 30400540 ps | ||
| T49 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3363061720 | Apr 02 12:17:26 PM PDT 24 | Apr 02 12:17:27 PM PDT 24 | 30853553 ps | ||
| T50 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1753685185 | Apr 02 12:17:24 PM PDT 24 | Apr 02 12:17:24 PM PDT 24 | 31414997 ps | ||
| T14 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2112610381 | Apr 02 12:17:19 PM PDT 24 | Apr 02 12:17:20 PM PDT 24 | 32406627 ps | ||
| T51 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2312377929 | Apr 02 12:17:26 PM PDT 24 | Apr 02 12:17:27 PM PDT 24 | 30958401 ps | ||
| T52 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.417294719 | Apr 02 12:17:33 PM PDT 24 | Apr 02 12:17:33 PM PDT 24 | 29200017 ps | ||
| T24 | /workspace/coverage/sync_alert/9.prim_sync_alert.2251782119 | Apr 02 12:17:32 PM PDT 24 | Apr 02 12:17:32 PM PDT 24 | 8901450 ps | ||
| T25 | /workspace/coverage/sync_alert/2.prim_sync_alert.2999113842 | Apr 02 12:17:25 PM PDT 24 | Apr 02 12:17:26 PM PDT 24 | 10066273 ps | ||
| T34 | /workspace/coverage/sync_alert/8.prim_sync_alert.3818116535 | Apr 02 12:17:30 PM PDT 24 | Apr 02 12:17:30 PM PDT 24 | 10169610 ps | ||
| T26 | /workspace/coverage/sync_alert/5.prim_sync_alert.3720457399 | Apr 02 12:17:25 PM PDT 24 | Apr 02 12:17:25 PM PDT 24 | 9648258 ps | ||
| T27 | /workspace/coverage/sync_alert/10.prim_sync_alert.3419982018 | Apr 02 12:17:20 PM PDT 24 | Apr 02 12:17:20 PM PDT 24 | 8290273 ps | ||
| T28 | /workspace/coverage/sync_alert/14.prim_sync_alert.560693487 | Apr 02 12:17:24 PM PDT 24 | Apr 02 12:17:25 PM PDT 24 | 9452300 ps | ||
| T35 | /workspace/coverage/sync_alert/13.prim_sync_alert.3690179078 | Apr 02 12:17:24 PM PDT 24 | Apr 02 12:17:25 PM PDT 24 | 9462898 ps | ||
| T29 | /workspace/coverage/sync_alert/15.prim_sync_alert.416649329 | Apr 02 12:17:25 PM PDT 24 | Apr 02 12:17:25 PM PDT 24 | 9245295 ps | ||
| T30 | /workspace/coverage/sync_alert/4.prim_sync_alert.1020590572 | Apr 02 12:17:23 PM PDT 24 | Apr 02 12:17:24 PM PDT 24 | 9333071 ps | ||
| T36 | /workspace/coverage/sync_alert/18.prim_sync_alert.3023023673 | Apr 02 12:17:34 PM PDT 24 | Apr 02 12:17:35 PM PDT 24 | 8632904 ps | ||
| T31 | /workspace/coverage/sync_alert/3.prim_sync_alert.2618397306 | Apr 02 12:17:32 PM PDT 24 | Apr 02 12:17:33 PM PDT 24 | 9250783 ps | ||
| T53 | /workspace/coverage/sync_alert/16.prim_sync_alert.2389492576 | Apr 02 12:17:32 PM PDT 24 | Apr 02 12:17:33 PM PDT 24 | 8510866 ps | ||
| T32 | /workspace/coverage/sync_alert/1.prim_sync_alert.2445104593 | Apr 02 12:17:24 PM PDT 24 | Apr 02 12:17:25 PM PDT 24 | 9039050 ps | ||
| T54 | /workspace/coverage/sync_alert/11.prim_sync_alert.500132073 | Apr 02 12:17:28 PM PDT 24 | Apr 02 12:17:28 PM PDT 24 | 9139281 ps | ||
| T33 | /workspace/coverage/sync_alert/12.prim_sync_alert.488034359 | Apr 02 12:17:16 PM PDT 24 | Apr 02 12:17:17 PM PDT 24 | 9598685 ps | ||
| T55 | /workspace/coverage/sync_alert/17.prim_sync_alert.1757863951 | Apr 02 12:17:24 PM PDT 24 | Apr 02 12:17:25 PM PDT 24 | 9384575 ps | ||
| T56 | /workspace/coverage/sync_alert/0.prim_sync_alert.2184146366 | Apr 02 12:17:24 PM PDT 24 | Apr 02 12:17:25 PM PDT 24 | 8770434 ps | ||
| T57 | /workspace/coverage/sync_alert/7.prim_sync_alert.1346763742 | Apr 02 12:17:25 PM PDT 24 | Apr 02 12:17:26 PM PDT 24 | 8627303 ps | ||
| T58 | /workspace/coverage/sync_alert/19.prim_sync_alert.342460991 | Apr 02 12:17:34 PM PDT 24 | Apr 02 12:17:35 PM PDT 24 | 8918281 ps | ||
| T59 | /workspace/coverage/sync_alert/6.prim_sync_alert.2658605954 | Apr 02 12:17:16 PM PDT 24 | Apr 02 12:17:16 PM PDT 24 | 9274675 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3987936096 | Apr 02 12:22:30 PM PDT 24 | Apr 02 12:22:31 PM PDT 24 | 29436698 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2127381818 | Apr 02 12:22:20 PM PDT 24 | Apr 02 12:22:21 PM PDT 24 | 26650865 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3413318385 | Apr 02 12:22:48 PM PDT 24 | Apr 02 12:22:50 PM PDT 24 | 29100616 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1762290667 | Apr 02 12:22:30 PM PDT 24 | Apr 02 12:22:31 PM PDT 24 | 26614002 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1547106482 | Apr 02 12:22:19 PM PDT 24 | Apr 02 12:22:20 PM PDT 24 | 30321442 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1235537896 | Apr 02 12:22:30 PM PDT 24 | Apr 02 12:22:31 PM PDT 24 | 27027742 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.449402920 | Apr 02 12:20:08 PM PDT 24 | Apr 02 12:20:09 PM PDT 24 | 29300949 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.374400194 | Apr 02 12:22:19 PM PDT 24 | Apr 02 12:22:20 PM PDT 24 | 29231788 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.891744503 | Apr 02 12:19:58 PM PDT 24 | Apr 02 12:19:59 PM PDT 24 | 28086954 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3303673605 | Apr 02 12:21:31 PM PDT 24 | Apr 02 12:21:31 PM PDT 24 | 27257577 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3951153715 | Apr 02 12:22:49 PM PDT 24 | Apr 02 12:22:50 PM PDT 24 | 26166505 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2464919017 | Apr 02 12:20:08 PM PDT 24 | Apr 02 12:20:09 PM PDT 24 | 25459602 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2885824548 | Apr 02 12:19:58 PM PDT 24 | Apr 02 12:19:59 PM PDT 24 | 28413901 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2790126881 | Apr 02 12:22:14 PM PDT 24 | Apr 02 12:22:15 PM PDT 24 | 28345354 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3450020057 | Apr 02 12:21:14 PM PDT 24 | Apr 02 12:21:15 PM PDT 24 | 26916860 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2622582833 | Apr 02 12:19:59 PM PDT 24 | Apr 02 12:19:59 PM PDT 24 | 27853037 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1813389359 | Apr 02 12:22:14 PM PDT 24 | Apr 02 12:22:15 PM PDT 24 | 27847767 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2598465726 | Apr 02 12:20:08 PM PDT 24 | Apr 02 12:20:09 PM PDT 24 | 27094477 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3662292669 | Apr 02 12:22:30 PM PDT 24 | Apr 02 12:22:31 PM PDT 24 | 28204458 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3473402111 | Apr 02 12:21:45 PM PDT 24 | Apr 02 12:21:45 PM PDT 24 | 28475710 ps |
| Test location | /workspace/coverage/default/5.prim_async_alert.2457222837 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11673822 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:22:12 PM PDT 24 |
| Finished | Apr 02 12:22:13 PM PDT 24 |
| Peak memory | 144192 kb |
| Host | smart-740eba0f-4a93-4964-930d-214d38450762 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2457222837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2457222837 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.560693487 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9452300 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:24 PM PDT 24 |
| Finished | Apr 02 12:17:25 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-f2b331be-a4e9-41ce-a07b-a5af2347a14b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=560693487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.560693487 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2718827128 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28399351 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:17:24 PM PDT 24 |
| Finished | Apr 02 12:17:25 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-ff87ab68-ec3a-4f38-ad4d-f48fb32900b3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2718827128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2718827128 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3838067885 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 31191790 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:17:35 PM PDT 24 |
| Finished | Apr 02 12:17:35 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-a8b9323c-62c6-451b-9c07-9179ac6a3f95 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3838067885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3838067885 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3288062045 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11504653 ps |
| CPU time | 0.44 seconds |
| Started | Apr 02 12:20:08 PM PDT 24 |
| Finished | Apr 02 12:20:09 PM PDT 24 |
| Peak memory | 143348 kb |
| Host | smart-47a4a311-69eb-4d7b-ab16-bbd7c6f57835 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3288062045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3288062045 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.748375534 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11973494 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:22:15 PM PDT 24 |
| Finished | Apr 02 12:22:16 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-3edc6a5b-9d16-42d5-bfec-4d0245589db9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=748375534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.748375534 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.199610079 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11597782 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:22:20 PM PDT 24 |
| Finished | Apr 02 12:22:21 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-1c533beb-6245-45f1-9794-de6958f49706 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=199610079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.199610079 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.985276870 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 10851145 ps |
| CPU time | 0.48 seconds |
| Started | Apr 02 12:20:08 PM PDT 24 |
| Finished | Apr 02 12:20:09 PM PDT 24 |
| Peak memory | 143224 kb |
| Host | smart-c44b8d52-4cb8-4892-b5c4-76555457f337 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985276870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.985276870 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.2972391054 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11368597 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:20:09 PM PDT 24 |
| Finished | Apr 02 12:20:10 PM PDT 24 |
| Peak memory | 145516 kb |
| Host | smart-6689f3c8-dd05-4c37-9940-57946a2778f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2972391054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2972391054 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3024810201 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11427481 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:19:09 PM PDT 24 |
| Finished | Apr 02 12:19:10 PM PDT 24 |
| Peak memory | 145692 kb |
| Host | smart-9e20fd74-d63a-4bd1-b456-00dff53ea690 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3024810201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3024810201 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1319509170 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11299898 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:24:10 PM PDT 24 |
| Finished | Apr 02 12:24:10 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-80f85554-620f-4e7d-b39d-169524ef9ed1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1319509170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1319509170 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3104361626 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11776532 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:20:39 PM PDT 24 |
| Finished | Apr 02 12:20:40 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-af38147e-616e-45df-9f88-f41c816231a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3104361626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3104361626 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.537447089 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10933904 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:22:30 PM PDT 24 |
| Finished | Apr 02 12:22:30 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-af9eb784-56b5-4665-a5d2-3e806881296a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537447089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.537447089 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.3207900373 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11571031 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:20:41 PM PDT 24 |
| Finished | Apr 02 12:20:42 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-881c81a0-3e76-4da3-9b27-aee1c60e7a65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207900373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3207900373 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.414741542 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11240882 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:22:30 PM PDT 24 |
| Finished | Apr 02 12:22:31 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-a322865b-1a54-4f0a-b31e-7284a92a5765 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414741542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.414741542 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3124700584 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10512372 ps |
| CPU time | 0.49 seconds |
| Started | Apr 02 12:20:08 PM PDT 24 |
| Finished | Apr 02 12:20:09 PM PDT 24 |
| Peak memory | 142808 kb |
| Host | smart-4ac3f815-0b39-470d-adbe-ec1880f6377a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3124700584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3124700584 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.1796214834 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11257002 ps |
| CPU time | 0.47 seconds |
| Started | Apr 02 12:20:08 PM PDT 24 |
| Finished | Apr 02 12:20:09 PM PDT 24 |
| Peak memory | 142980 kb |
| Host | smart-d56a8cd4-85cf-4803-91d9-6286896750c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796214834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1796214834 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.4174751119 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10926090 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:22:30 PM PDT 24 |
| Finished | Apr 02 12:22:31 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-5b6f6c17-c38f-4e0b-96ed-ff8e4e8eca2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174751119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.4174751119 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2523321657 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12599130 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:22:12 PM PDT 24 |
| Finished | Apr 02 12:22:13 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-46d38be4-3bf4-4c3a-9fa3-5a32a7f3b09d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2523321657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2523321657 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.2596681060 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10921765 ps |
| CPU time | 0.46 seconds |
| Started | Apr 02 12:22:14 PM PDT 24 |
| Finished | Apr 02 12:22:15 PM PDT 24 |
| Peak memory | 143080 kb |
| Host | smart-ef916253-89f6-43d5-b2fb-74f494c1b120 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596681060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2596681060 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.1647580294 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10655377 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:22:30 PM PDT 24 |
| Finished | Apr 02 12:22:31 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-710ca8df-b055-4250-89b8-62adcd305554 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647580294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1647580294 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.2713694667 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12183887 ps |
| CPU time | 0.42 seconds |
| Started | Apr 02 12:22:48 PM PDT 24 |
| Finished | Apr 02 12:22:50 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-99e6455e-4f6d-452c-a783-564771a226d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713694667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2713694667 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3813880144 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 31669662 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:17:33 PM PDT 24 |
| Finished | Apr 02 12:17:33 PM PDT 24 |
| Peak memory | 145728 kb |
| Host | smart-b51118b4-2b82-47a8-a21e-a5a8b725deca |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3813880144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3813880144 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4191038812 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 32413629 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:17:35 PM PDT 24 |
| Finished | Apr 02 12:17:36 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-90547588-4f75-45b7-be29-104e65d15279 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4191038812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.4191038812 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.321629114 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30400540 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:33 PM PDT 24 |
| Finished | Apr 02 12:17:34 PM PDT 24 |
| Peak memory | 145520 kb |
| Host | smart-ff13b527-4219-467f-b7eb-ca49ad45058b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=321629114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.321629114 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1753685185 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 31414997 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:17:24 PM PDT 24 |
| Finished | Apr 02 12:17:24 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-085e7191-4a77-484c-b9bc-723c87a3afd9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1753685185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1753685185 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.594366818 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 29103229 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:17:31 PM PDT 24 |
| Finished | Apr 02 12:17:32 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-e4466e8a-1f27-4401-bb1a-9d940568af32 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=594366818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.594366818 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1104624557 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29677226 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:17:34 PM PDT 24 |
| Finished | Apr 02 12:17:34 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-7fcaac66-013b-49b5-8c6b-bda8bcf5baa6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1104624557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1104624557 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2312377929 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30958401 ps |
| CPU time | 0.42 seconds |
| Started | Apr 02 12:17:26 PM PDT 24 |
| Finished | Apr 02 12:17:27 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-0a46f72c-248d-4054-90bf-be51fbce9bc9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2312377929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2312377929 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3267031415 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 30973929 ps |
| CPU time | 0.42 seconds |
| Started | Apr 02 12:17:32 PM PDT 24 |
| Finished | Apr 02 12:17:33 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-6bbefb40-f47f-4d3d-81da-feefc00879bb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3267031415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3267031415 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3558752932 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 29706695 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:17:25 PM PDT 24 |
| Finished | Apr 02 12:17:25 PM PDT 24 |
| Peak memory | 145660 kb |
| Host | smart-e365105e-023a-454e-9410-a2fa100740fe |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3558752932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3558752932 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4025138082 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 30641551 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:17:32 PM PDT 24 |
| Finished | Apr 02 12:17:33 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-77171514-0fd3-498d-8e37-f76197c0aba6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4025138082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4025138082 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3174988438 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 31873320 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:17:24 PM PDT 24 |
| Finished | Apr 02 12:17:24 PM PDT 24 |
| Peak memory | 144804 kb |
| Host | smart-819edf4b-a859-4df8-9801-953b0de94f9c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3174988438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3174988438 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3363061720 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 30853553 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:17:26 PM PDT 24 |
| Finished | Apr 02 12:17:27 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-8a2c43c6-027c-4f41-9e88-46e841e810ab |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3363061720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3363061720 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.615195333 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 28794602 ps |
| CPU time | 0.43 seconds |
| Started | Apr 02 12:17:32 PM PDT 24 |
| Finished | Apr 02 12:17:33 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-94a49544-0094-4de0-bdbf-186ca3fd3b0c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=615195333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.615195333 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3421662813 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 30893543 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:17:35 PM PDT 24 |
| Finished | Apr 02 12:17:36 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-64120abd-84c5-4e4e-b451-f61ec09bd759 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3421662813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3421662813 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2112610381 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 32406627 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:17:19 PM PDT 24 |
| Finished | Apr 02 12:17:20 PM PDT 24 |
| Peak memory | 145848 kb |
| Host | smart-7914b7f6-235c-4f1f-b1fa-4672c32396cf |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2112610381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2112610381 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.417294719 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 29200017 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:17:33 PM PDT 24 |
| Finished | Apr 02 12:17:33 PM PDT 24 |
| Peak memory | 145728 kb |
| Host | smart-3d15c4d5-e7d0-4dd3-8654-7c07e0e9908c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=417294719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.417294719 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.2184146366 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8770434 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:24 PM PDT 24 |
| Finished | Apr 02 12:17:25 PM PDT 24 |
| Peak memory | 144492 kb |
| Host | smart-3d0b5190-96ed-42d2-9b0e-4c07dac86774 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2184146366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2184146366 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.2445104593 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9039050 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:24 PM PDT 24 |
| Finished | Apr 02 12:17:25 PM PDT 24 |
| Peak memory | 144636 kb |
| Host | smart-c9445546-d0ea-4554-a06d-ec7601c92b45 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2445104593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2445104593 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3419982018 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8290273 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:17:20 PM PDT 24 |
| Finished | Apr 02 12:17:20 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-3c70d20f-50d6-4c53-a920-efb04fe3bc32 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3419982018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3419982018 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.500132073 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 9139281 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:17:28 PM PDT 24 |
| Finished | Apr 02 12:17:28 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-706062f1-73a9-475a-a4f2-7eff5d26c36b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=500132073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.500132073 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.488034359 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9598685 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:17:16 PM PDT 24 |
| Finished | Apr 02 12:17:17 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-54f8cfa1-1830-4da6-9b07-27cb7e27f2ca |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=488034359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.488034359 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.3690179078 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9462898 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:24 PM PDT 24 |
| Finished | Apr 02 12:17:25 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-de8cc388-f59a-4f18-9180-cc32a3710c53 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3690179078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3690179078 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.416649329 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9245295 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:17:25 PM PDT 24 |
| Finished | Apr 02 12:17:25 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-dfc04a1e-2b58-4185-8e3b-f04c9c7abfa5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=416649329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.416649329 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.2389492576 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 8510866 ps |
| CPU time | 0.42 seconds |
| Started | Apr 02 12:17:32 PM PDT 24 |
| Finished | Apr 02 12:17:33 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-d398ed20-cbd5-40ab-9637-d3da3ca90c9c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2389492576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2389492576 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.1757863951 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9384575 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:17:24 PM PDT 24 |
| Finished | Apr 02 12:17:25 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-590369ae-0157-44fe-a46f-f04c554102a7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1757863951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1757863951 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.3023023673 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8632904 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:17:34 PM PDT 24 |
| Finished | Apr 02 12:17:35 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-c8107cde-5c96-4976-9cf8-d95ac4975e77 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3023023673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3023023673 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.342460991 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8918281 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:17:34 PM PDT 24 |
| Finished | Apr 02 12:17:35 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-e7b49048-eec0-44dd-a64c-5c4b2a1039a9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=342460991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.342460991 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2999113842 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10066273 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:17:25 PM PDT 24 |
| Finished | Apr 02 12:17:26 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-b02a2978-614a-4b8d-8f97-3d092fc81f9a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2999113842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2999113842 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.2618397306 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9250783 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:17:32 PM PDT 24 |
| Finished | Apr 02 12:17:33 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-8cccb677-60d7-40a1-94b0-2b987b5209c8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2618397306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2618397306 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.1020590572 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9333071 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:17:23 PM PDT 24 |
| Finished | Apr 02 12:17:24 PM PDT 24 |
| Peak memory | 143996 kb |
| Host | smart-151714a0-444b-41ff-bcee-7633c823c39d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1020590572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1020590572 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.3720457399 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9648258 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:25 PM PDT 24 |
| Finished | Apr 02 12:17:25 PM PDT 24 |
| Peak memory | 144848 kb |
| Host | smart-93ea55a5-f73c-4446-af91-6ad8470ba237 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3720457399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3720457399 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.2658605954 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9274675 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:16 PM PDT 24 |
| Finished | Apr 02 12:17:16 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-ef9404b8-55e5-415d-ac4a-4cd452a874a4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2658605954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2658605954 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1346763742 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8627303 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:17:25 PM PDT 24 |
| Finished | Apr 02 12:17:26 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-e731af48-eeff-4e59-bd45-f6eed10ae098 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1346763742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1346763742 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.3818116535 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10169610 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:30 PM PDT 24 |
| Finished | Apr 02 12:17:30 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-1c374e67-42d5-4340-b2e1-f3dac682ba71 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3818116535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3818116535 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.2251782119 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8901450 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:17:32 PM PDT 24 |
| Finished | Apr 02 12:17:32 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-d7ee389a-c8f1-4259-93ae-d9925639794f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2251782119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2251782119 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2622582833 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27853037 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:19:59 PM PDT 24 |
| Finished | Apr 02 12:19:59 PM PDT 24 |
| Peak memory | 144852 kb |
| Host | smart-cbc2bd6b-3002-4f78-bfc6-59a2062b4c86 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2622582833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2622582833 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2790126881 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28345354 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:22:14 PM PDT 24 |
| Finished | Apr 02 12:22:15 PM PDT 24 |
| Peak memory | 143284 kb |
| Host | smart-52e69c87-04c1-4777-8f9c-ac718e8306b0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2790126881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2790126881 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.891744503 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28086954 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:19:58 PM PDT 24 |
| Finished | Apr 02 12:19:59 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-ca5a3d69-92c5-4863-a93f-b5fe4424acc4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=891744503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.891744503 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3450020057 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26916860 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:21:14 PM PDT 24 |
| Finished | Apr 02 12:21:15 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-1c48bee7-5a0c-44f0-b42e-5c6520ee4281 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3450020057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3450020057 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3987936096 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 29436698 ps |
| CPU time | 0.4 seconds |
| Started | Apr 02 12:22:30 PM PDT 24 |
| Finished | Apr 02 12:22:31 PM PDT 24 |
| Peak memory | 144656 kb |
| Host | smart-b6fd33d3-e2aa-40c8-bffa-a2d6448c6455 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3987936096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3987936096 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3662292669 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 28204458 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:22:30 PM PDT 24 |
| Finished | Apr 02 12:22:31 PM PDT 24 |
| Peak memory | 144540 kb |
| Host | smart-e32a15b3-e4d1-428a-b79a-0b33b078f59b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3662292669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3662292669 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1547106482 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 30321442 ps |
| CPU time | 0.44 seconds |
| Started | Apr 02 12:22:19 PM PDT 24 |
| Finished | Apr 02 12:22:20 PM PDT 24 |
| Peak memory | 143672 kb |
| Host | smart-a3145e5f-39db-4238-812a-a70cd8820b5d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1547106482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1547106482 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3413318385 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 29100616 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:22:48 PM PDT 24 |
| Finished | Apr 02 12:22:50 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-53c55e8f-500e-411b-887e-7ac33d85c137 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3413318385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3413318385 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3473402111 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 28475710 ps |
| CPU time | 0.42 seconds |
| Started | Apr 02 12:21:45 PM PDT 24 |
| Finished | Apr 02 12:21:45 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-9c2f1dce-7104-417e-b8e0-94d164f21a6a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3473402111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3473402111 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.374400194 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 29231788 ps |
| CPU time | 0.43 seconds |
| Started | Apr 02 12:22:19 PM PDT 24 |
| Finished | Apr 02 12:22:20 PM PDT 24 |
| Peak memory | 143684 kb |
| Host | smart-37660037-e56a-4b42-be52-c0626a721b66 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=374400194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.374400194 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2885824548 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28413901 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:19:58 PM PDT 24 |
| Finished | Apr 02 12:19:59 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-84ada48b-b931-4fb7-acb3-ec5ebfa8c5b7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2885824548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2885824548 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3303673605 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27257577 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:21:31 PM PDT 24 |
| Finished | Apr 02 12:21:31 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-2d83c29d-f8ea-46f5-a736-c9c267d545e3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3303673605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3303673605 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1813389359 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27847767 ps |
| CPU time | 0.47 seconds |
| Started | Apr 02 12:22:14 PM PDT 24 |
| Finished | Apr 02 12:22:15 PM PDT 24 |
| Peak memory | 142684 kb |
| Host | smart-ffe00896-7d5b-466c-b16f-87304b579afc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1813389359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1813389359 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1762290667 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 26614002 ps |
| CPU time | 0.41 seconds |
| Started | Apr 02 12:22:30 PM PDT 24 |
| Finished | Apr 02 12:22:31 PM PDT 24 |
| Peak memory | 144436 kb |
| Host | smart-bf60e8bd-90e0-4dcb-8b18-55cf8fea0f4e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1762290667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1762290667 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.449402920 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 29300949 ps |
| CPU time | 0.5 seconds |
| Started | Apr 02 12:20:08 PM PDT 24 |
| Finished | Apr 02 12:20:09 PM PDT 24 |
| Peak memory | 142376 kb |
| Host | smart-9b988a5b-0241-42c6-98b2-9cc2a48d21b2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=449402920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.449402920 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1235537896 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27027742 ps |
| CPU time | 0.38 seconds |
| Started | Apr 02 12:22:30 PM PDT 24 |
| Finished | Apr 02 12:22:31 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-40635ceb-dab5-4aa4-8448-3a8b777b4c97 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1235537896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1235537896 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2127381818 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 26650865 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:22:20 PM PDT 24 |
| Finished | Apr 02 12:22:21 PM PDT 24 |
| Peak memory | 144832 kb |
| Host | smart-aa4a9e9a-9fe0-4ee9-9488-fa927cf6c3f2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2127381818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2127381818 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2464919017 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 25459602 ps |
| CPU time | 0.47 seconds |
| Started | Apr 02 12:20:08 PM PDT 24 |
| Finished | Apr 02 12:20:09 PM PDT 24 |
| Peak memory | 141992 kb |
| Host | smart-8557fbfa-290d-4b3a-b0c9-f06a8767d07b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2464919017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2464919017 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2598465726 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27094477 ps |
| CPU time | 0.48 seconds |
| Started | Apr 02 12:20:08 PM PDT 24 |
| Finished | Apr 02 12:20:09 PM PDT 24 |
| Peak memory | 141808 kb |
| Host | smart-5c240933-0535-441e-bd49-b72ed3d98013 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2598465726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2598465726 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3951153715 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 26166505 ps |
| CPU time | 0.39 seconds |
| Started | Apr 02 12:22:49 PM PDT 24 |
| Finished | Apr 02 12:22:50 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-5d6bbfd3-27f7-4ab8-b143-3ce3158782a8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3951153715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3951153715 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |