| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 89.27 | 89.27 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/10.prim_async_alert.3644985616 |
| 92.39 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/0.prim_sync_alert.2395265917 |
| 93.90 | 1.51 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.499226263 |
| 94.50 | 0.60 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/0.prim_async_alert.2139500620 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1250061019 |
| Name |
|---|
| /workspace/coverage/default/11.prim_async_alert.1892840706 |
| /workspace/coverage/default/12.prim_async_alert.2612544779 |
| /workspace/coverage/default/13.prim_async_alert.1222759957 |
| /workspace/coverage/default/14.prim_async_alert.1162842635 |
| /workspace/coverage/default/15.prim_async_alert.1042231788 |
| /workspace/coverage/default/17.prim_async_alert.76693679 |
| /workspace/coverage/default/18.prim_async_alert.398251451 |
| /workspace/coverage/default/19.prim_async_alert.3005760768 |
| /workspace/coverage/default/2.prim_async_alert.2262456213 |
| /workspace/coverage/default/3.prim_async_alert.1074300828 |
| /workspace/coverage/default/4.prim_async_alert.1820635667 |
| /workspace/coverage/default/5.prim_async_alert.1586261000 |
| /workspace/coverage/default/6.prim_async_alert.1194527269 |
| /workspace/coverage/default/7.prim_async_alert.2348503886 |
| /workspace/coverage/default/8.prim_async_alert.2935860329 |
| /workspace/coverage/default/9.prim_async_alert.3846386545 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2003707421 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.560493632 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2213217410 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.732274428 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3136827606 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3780453701 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2699190548 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3967237768 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2332236712 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2625434171 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3810108933 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.408122641 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4170500264 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1781479074 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1902344630 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2920873420 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1148017392 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.961207862 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.3432301960 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.2607752459 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1090087851 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3631323673 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.611522184 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1043074949 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.521490669 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.2198720921 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.3921748324 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.1976176246 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.71368769 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.4185249645 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3127383142 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.2024601145 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.2480839492 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1832004178 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.243026271 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.3263718359 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.2049085643 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1773544769 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1379459920 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2577634291 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3886223026 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1163556634 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1315466219 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.514224589 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3580352990 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2284322841 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2967492863 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.150032494 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3259735055 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1640065527 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.511985972 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.755908702 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4204783571 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3426814250 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3242923994 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.706310842 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.198380916 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/2.prim_async_alert.2262456213 | Apr 04 03:46:03 PM PDT 24 | Apr 04 03:46:04 PM PDT 24 | 11611196 ps | ||
| T2 | /workspace/coverage/default/12.prim_async_alert.2612544779 | Apr 04 03:46:16 PM PDT 24 | Apr 04 03:46:17 PM PDT 24 | 11195871 ps | ||
| T3 | /workspace/coverage/default/18.prim_async_alert.398251451 | Apr 04 03:46:15 PM PDT 24 | Apr 04 03:46:15 PM PDT 24 | 11868634 ps | ||
| T7 | /workspace/coverage/default/3.prim_async_alert.1074300828 | Apr 04 03:46:02 PM PDT 24 | Apr 04 03:46:02 PM PDT 24 | 10893453 ps | ||
| T9 | /workspace/coverage/default/7.prim_async_alert.2348503886 | Apr 04 03:46:11 PM PDT 24 | Apr 04 03:46:11 PM PDT 24 | 11360830 ps | ||
| T10 | /workspace/coverage/default/8.prim_async_alert.2935860329 | Apr 04 03:46:11 PM PDT 24 | Apr 04 03:46:12 PM PDT 24 | 11690388 ps | ||
| T8 | /workspace/coverage/default/10.prim_async_alert.3644985616 | Apr 04 03:46:11 PM PDT 24 | Apr 04 03:46:12 PM PDT 24 | 11750210 ps | ||
| T15 | /workspace/coverage/default/6.prim_async_alert.1194527269 | Apr 04 03:46:11 PM PDT 24 | Apr 04 03:46:12 PM PDT 24 | 11270256 ps | ||
| T12 | /workspace/coverage/default/4.prim_async_alert.1820635667 | Apr 04 03:46:01 PM PDT 24 | Apr 04 03:46:02 PM PDT 24 | 11525358 ps | ||
| T13 | /workspace/coverage/default/0.prim_async_alert.2139500620 | Apr 04 03:46:11 PM PDT 24 | Apr 04 03:46:11 PM PDT 24 | 10912617 ps | ||
| T16 | /workspace/coverage/default/15.prim_async_alert.1042231788 | Apr 04 03:46:13 PM PDT 24 | Apr 04 03:46:14 PM PDT 24 | 11326509 ps | ||
| T17 | /workspace/coverage/default/13.prim_async_alert.1222759957 | Apr 04 03:46:11 PM PDT 24 | Apr 04 03:46:12 PM PDT 24 | 11023745 ps | ||
| T18 | /workspace/coverage/default/14.prim_async_alert.1162842635 | Apr 04 03:46:16 PM PDT 24 | Apr 04 03:46:17 PM PDT 24 | 10516909 ps | ||
| T40 | /workspace/coverage/default/5.prim_async_alert.1586261000 | Apr 04 03:46:11 PM PDT 24 | Apr 04 03:46:11 PM PDT 24 | 12616875 ps | ||
| T11 | /workspace/coverage/default/19.prim_async_alert.3005760768 | Apr 04 03:46:15 PM PDT 24 | Apr 04 03:46:15 PM PDT 24 | 12361900 ps | ||
| T41 | /workspace/coverage/default/11.prim_async_alert.1892840706 | Apr 04 03:46:18 PM PDT 24 | Apr 04 03:46:19 PM PDT 24 | 11223460 ps | ||
| T42 | /workspace/coverage/default/17.prim_async_alert.76693679 | Apr 04 03:46:15 PM PDT 24 | Apr 04 03:46:15 PM PDT 24 | 11464677 ps | ||
| T43 | /workspace/coverage/default/9.prim_async_alert.3846386545 | Apr 04 03:46:11 PM PDT 24 | Apr 04 03:46:12 PM PDT 24 | 11085010 ps | ||
| T33 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1902344630 | Apr 04 12:16:21 PM PDT 24 | Apr 04 12:16:22 PM PDT 24 | 30704586 ps | ||
| T34 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.560493632 | Apr 04 12:16:12 PM PDT 24 | Apr 04 12:16:13 PM PDT 24 | 31244035 ps | ||
| T35 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3780453701 | Apr 04 12:16:19 PM PDT 24 | Apr 04 12:16:19 PM PDT 24 | 29580905 ps | ||
| T14 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2699190548 | Apr 04 12:16:14 PM PDT 24 | Apr 04 12:16:14 PM PDT 24 | 32207124 ps | ||
| T36 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2625434171 | Apr 04 12:16:13 PM PDT 24 | Apr 04 12:16:14 PM PDT 24 | 30111932 ps | ||
| T37 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.961207862 | Apr 04 12:17:11 PM PDT 24 | Apr 04 12:17:12 PM PDT 24 | 29161318 ps | ||
| T38 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.499226263 | Apr 04 12:16:12 PM PDT 24 | Apr 04 12:16:13 PM PDT 24 | 29875640 ps | ||
| T39 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3967237768 | Apr 04 12:19:32 PM PDT 24 | Apr 04 12:19:33 PM PDT 24 | 28893912 ps | ||
| T31 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2332236712 | Apr 04 12:17:15 PM PDT 24 | Apr 04 12:17:16 PM PDT 24 | 28404881 ps | ||
| T4 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1781479074 | Apr 04 12:16:19 PM PDT 24 | Apr 04 12:16:20 PM PDT 24 | 30294131 ps | ||
| T44 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3136827606 | Apr 04 12:16:12 PM PDT 24 | Apr 04 12:16:13 PM PDT 24 | 29759023 ps | ||
| T45 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2213217410 | Apr 04 12:16:22 PM PDT 24 | Apr 04 12:16:22 PM PDT 24 | 30055567 ps | ||
| T46 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1148017392 | Apr 04 12:16:20 PM PDT 24 | Apr 04 12:16:20 PM PDT 24 | 29692584 ps | ||
| T47 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.408122641 | Apr 04 12:16:28 PM PDT 24 | Apr 04 12:16:29 PM PDT 24 | 30674231 ps | ||
| T48 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.732274428 | Apr 04 12:16:11 PM PDT 24 | Apr 04 12:16:11 PM PDT 24 | 30562505 ps | ||
| T49 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2003707421 | Apr 04 12:16:19 PM PDT 24 | Apr 04 12:16:19 PM PDT 24 | 29510509 ps | ||
| T32 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3810108933 | Apr 04 12:16:15 PM PDT 24 | Apr 04 12:16:15 PM PDT 24 | 29480051 ps | ||
| T5 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1250061019 | Apr 04 12:16:20 PM PDT 24 | Apr 04 12:16:20 PM PDT 24 | 30296920 ps | ||
| T50 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2920873420 | Apr 04 12:20:03 PM PDT 24 | Apr 04 12:20:03 PM PDT 24 | 30610030 ps | ||
| T51 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4170500264 | Apr 04 12:18:33 PM PDT 24 | Apr 04 12:18:33 PM PDT 24 | 30257745 ps | ||
| T28 | /workspace/coverage/sync_alert/15.prim_sync_alert.521490669 | Apr 04 02:01:11 PM PDT 24 | Apr 04 02:01:12 PM PDT 24 | 9249927 ps | ||
| T19 | /workspace/coverage/sync_alert/11.prim_sync_alert.1090087851 | Apr 04 02:01:12 PM PDT 24 | Apr 04 02:01:13 PM PDT 24 | 9159522 ps | ||
| T20 | /workspace/coverage/sync_alert/3.prim_sync_alert.3127383142 | Apr 04 02:00:57 PM PDT 24 | Apr 04 02:00:57 PM PDT 24 | 9240480 ps | ||
| T21 | /workspace/coverage/sync_alert/16.prim_sync_alert.2198720921 | Apr 04 02:01:12 PM PDT 24 | Apr 04 02:01:12 PM PDT 24 | 8762806 ps | ||
| T29 | /workspace/coverage/sync_alert/17.prim_sync_alert.3921748324 | Apr 04 02:01:11 PM PDT 24 | Apr 04 02:01:11 PM PDT 24 | 8147868 ps | ||
| T22 | /workspace/coverage/sync_alert/18.prim_sync_alert.1976176246 | Apr 04 02:01:13 PM PDT 24 | Apr 04 02:01:14 PM PDT 24 | 9188823 ps | ||
| T30 | /workspace/coverage/sync_alert/5.prim_sync_alert.2480839492 | Apr 04 02:00:57 PM PDT 24 | Apr 04 02:00:58 PM PDT 24 | 9486836 ps | ||
| T23 | /workspace/coverage/sync_alert/10.prim_sync_alert.2607752459 | Apr 04 02:01:12 PM PDT 24 | Apr 04 02:01:12 PM PDT 24 | 9413920 ps | ||
| T24 | /workspace/coverage/sync_alert/0.prim_sync_alert.2395265917 | Apr 04 02:00:59 PM PDT 24 | Apr 04 02:01:00 PM PDT 24 | 10691359 ps | ||
| T25 | /workspace/coverage/sync_alert/4.prim_sync_alert.2024601145 | Apr 04 02:00:58 PM PDT 24 | Apr 04 02:00:59 PM PDT 24 | 8821896 ps | ||
| T26 | /workspace/coverage/sync_alert/19.prim_sync_alert.71368769 | Apr 04 02:01:11 PM PDT 24 | Apr 04 02:01:11 PM PDT 24 | 10238890 ps | ||
| T52 | /workspace/coverage/sync_alert/1.prim_sync_alert.3432301960 | Apr 04 02:01:00 PM PDT 24 | Apr 04 02:01:01 PM PDT 24 | 8881735 ps | ||
| T53 | /workspace/coverage/sync_alert/12.prim_sync_alert.3631323673 | Apr 04 02:01:12 PM PDT 24 | Apr 04 02:01:13 PM PDT 24 | 9183532 ps | ||
| T54 | /workspace/coverage/sync_alert/14.prim_sync_alert.1043074949 | Apr 04 02:01:15 PM PDT 24 | Apr 04 02:01:15 PM PDT 24 | 9137269 ps | ||
| T27 | /workspace/coverage/sync_alert/9.prim_sync_alert.2049085643 | Apr 04 02:01:12 PM PDT 24 | Apr 04 02:01:12 PM PDT 24 | 9641516 ps | ||
| T55 | /workspace/coverage/sync_alert/2.prim_sync_alert.4185249645 | Apr 04 02:00:58 PM PDT 24 | Apr 04 02:00:59 PM PDT 24 | 9300735 ps | ||
| T56 | /workspace/coverage/sync_alert/6.prim_sync_alert.1832004178 | Apr 04 02:00:59 PM PDT 24 | Apr 04 02:01:00 PM PDT 24 | 10809576 ps | ||
| T57 | /workspace/coverage/sync_alert/7.prim_sync_alert.243026271 | Apr 04 02:01:12 PM PDT 24 | Apr 04 02:01:13 PM PDT 24 | 9395685 ps | ||
| T58 | /workspace/coverage/sync_alert/13.prim_sync_alert.611522184 | Apr 04 02:01:12 PM PDT 24 | Apr 04 02:01:12 PM PDT 24 | 9238025 ps | ||
| T59 | /workspace/coverage/sync_alert/8.prim_sync_alert.3263718359 | Apr 04 02:01:12 PM PDT 24 | Apr 04 02:01:12 PM PDT 24 | 9112694 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.706310842 | Apr 04 12:16:27 PM PDT 24 | Apr 04 12:16:27 PM PDT 24 | 26090267 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1315466219 | Apr 04 12:16:14 PM PDT 24 | Apr 04 12:16:15 PM PDT 24 | 26173107 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4204783571 | Apr 04 12:21:18 PM PDT 24 | Apr 04 12:21:19 PM PDT 24 | 27501224 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3242923994 | Apr 04 12:16:21 PM PDT 24 | Apr 04 12:16:22 PM PDT 24 | 25181593 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1379459920 | Apr 04 12:16:20 PM PDT 24 | Apr 04 12:16:21 PM PDT 24 | 26523140 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.514224589 | Apr 04 12:19:32 PM PDT 24 | Apr 04 12:19:33 PM PDT 24 | 27544991 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.511985972 | Apr 04 12:16:19 PM PDT 24 | Apr 04 12:16:19 PM PDT 24 | 28431760 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2967492863 | Apr 04 12:16:19 PM PDT 24 | Apr 04 12:16:19 PM PDT 24 | 27601174 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3886223026 | Apr 04 12:16:18 PM PDT 24 | Apr 04 12:16:18 PM PDT 24 | 30208583 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2284322841 | Apr 04 12:16:28 PM PDT 24 | Apr 04 12:16:29 PM PDT 24 | 27486282 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1163556634 | Apr 04 12:16:20 PM PDT 24 | Apr 04 12:16:20 PM PDT 24 | 27318437 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3580352990 | Apr 04 12:20:16 PM PDT 24 | Apr 04 12:20:16 PM PDT 24 | 28457115 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.755908702 | Apr 04 12:16:22 PM PDT 24 | Apr 04 12:16:22 PM PDT 24 | 27649621 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3259735055 | Apr 04 12:16:22 PM PDT 24 | Apr 04 12:16:22 PM PDT 24 | 28010732 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.198380916 | Apr 04 12:16:25 PM PDT 24 | Apr 04 12:16:25 PM PDT 24 | 25617560 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1640065527 | Apr 04 12:16:19 PM PDT 24 | Apr 04 12:16:19 PM PDT 24 | 29546060 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3426814250 | Apr 04 12:16:19 PM PDT 24 | Apr 04 12:16:19 PM PDT 24 | 27163003 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.150032494 | Apr 04 12:17:14 PM PDT 24 | Apr 04 12:17:15 PM PDT 24 | 26111254 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1773544769 | Apr 04 12:16:34 PM PDT 24 | Apr 04 12:16:35 PM PDT 24 | 28902067 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2577634291 | Apr 04 12:16:22 PM PDT 24 | Apr 04 12:16:22 PM PDT 24 | 28846980 ps |
| Test location | /workspace/coverage/default/10.prim_async_alert.3644985616 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11750210 ps |
| CPU time | 0.43 seconds |
| Started | Apr 04 03:46:11 PM PDT 24 |
| Finished | Apr 04 03:46:12 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-c89c9885-d5fa-46c7-a2de-beb76383e18f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644985616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3644985616 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.2395265917 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10691359 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:00:59 PM PDT 24 |
| Finished | Apr 04 02:01:00 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-dd6165b2-00c6-4577-a040-7ae93a2a974d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2395265917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2395265917 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.499226263 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 29875640 ps |
| CPU time | 0.45 seconds |
| Started | Apr 04 12:16:12 PM PDT 24 |
| Finished | Apr 04 12:16:13 PM PDT 24 |
| Peak memory | 144052 kb |
| Host | smart-152e3f71-3c77-454b-baeb-eb96f1f3244e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=499226263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.499226263 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.2139500620 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10912617 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 03:46:11 PM PDT 24 |
| Finished | Apr 04 03:46:11 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-3bc7d2f3-fe50-41dd-8dae-0fa11c8c4d6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139500620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2139500620 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1250061019 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30296920 ps |
| CPU time | 0.42 seconds |
| Started | Apr 04 12:16:20 PM PDT 24 |
| Finished | Apr 04 12:16:20 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-69cba0ba-fe75-437f-a48d-e9c9ff1dc759 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1250061019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1250061019 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.1892840706 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11223460 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 03:46:18 PM PDT 24 |
| Finished | Apr 04 03:46:19 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-d263bb2d-7161-41f7-bf14-499e6c0c1f5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1892840706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1892840706 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.2612544779 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11195871 ps |
| CPU time | 0.39 seconds |
| Started | Apr 04 03:46:16 PM PDT 24 |
| Finished | Apr 04 03:46:17 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-f5819616-9da9-405d-9d17-77b885539a8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2612544779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2612544779 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1222759957 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11023745 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 03:46:11 PM PDT 24 |
| Finished | Apr 04 03:46:12 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-f81bf2e8-f1b4-4ed1-bff0-7980ac67e4b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222759957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1222759957 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1162842635 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10516909 ps |
| CPU time | 0.41 seconds |
| Started | Apr 04 03:46:16 PM PDT 24 |
| Finished | Apr 04 03:46:17 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-4afa8dda-6907-4c05-9e64-77f0acb2455e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1162842635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1162842635 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1042231788 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11326509 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 03:46:13 PM PDT 24 |
| Finished | Apr 04 03:46:14 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-06796eca-30e4-4003-abc6-ae8268f33c1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042231788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1042231788 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.76693679 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11464677 ps |
| CPU time | 0.39 seconds |
| Started | Apr 04 03:46:15 PM PDT 24 |
| Finished | Apr 04 03:46:15 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-6fac3510-3671-4326-8a2d-73f8038c9833 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76693679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.76693679 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.398251451 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11868634 ps |
| CPU time | 0.43 seconds |
| Started | Apr 04 03:46:15 PM PDT 24 |
| Finished | Apr 04 03:46:15 PM PDT 24 |
| Peak memory | 145700 kb |
| Host | smart-c3774bc5-60ff-4c9b-a07f-5aed901ce47c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398251451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.398251451 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3005760768 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12361900 ps |
| CPU time | 0.4 seconds |
| Started | Apr 04 03:46:15 PM PDT 24 |
| Finished | Apr 04 03:46:15 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-66386849-b22b-4a33-95a2-4af1359288fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005760768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3005760768 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.2262456213 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11611196 ps |
| CPU time | 0.39 seconds |
| Started | Apr 04 03:46:03 PM PDT 24 |
| Finished | Apr 04 03:46:04 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-df308d62-cffa-4b1a-be60-70dc53a7c6d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2262456213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2262456213 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.1074300828 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10893453 ps |
| CPU time | 0.4 seconds |
| Started | Apr 04 03:46:02 PM PDT 24 |
| Finished | Apr 04 03:46:02 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-63d423a6-5293-422a-915b-39907f99d662 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1074300828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1074300828 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.1820635667 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11525358 ps |
| CPU time | 0.43 seconds |
| Started | Apr 04 03:46:01 PM PDT 24 |
| Finished | Apr 04 03:46:02 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-6de9cbec-2d30-45ee-a032-c50cd2d52bbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820635667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1820635667 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1586261000 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12616875 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 03:46:11 PM PDT 24 |
| Finished | Apr 04 03:46:11 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-1a331236-7e62-4de4-81fe-e9c291a5f6c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1586261000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1586261000 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.1194527269 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11270256 ps |
| CPU time | 0.39 seconds |
| Started | Apr 04 03:46:11 PM PDT 24 |
| Finished | Apr 04 03:46:12 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-f560bd67-728a-460a-b6ae-49e87fde6754 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1194527269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1194527269 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.2348503886 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11360830 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 03:46:11 PM PDT 24 |
| Finished | Apr 04 03:46:11 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-9e4b5634-8bf2-434d-9efd-e99ce5bb2248 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348503886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2348503886 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2935860329 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11690388 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 03:46:11 PM PDT 24 |
| Finished | Apr 04 03:46:12 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-d5d1e7da-e43a-4737-bc6e-c7580f278c0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935860329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2935860329 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.3846386545 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11085010 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 03:46:11 PM PDT 24 |
| Finished | Apr 04 03:46:12 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-d0bfd9ac-2d39-46e7-8238-1940a634f2bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846386545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3846386545 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2003707421 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29510509 ps |
| CPU time | 0.44 seconds |
| Started | Apr 04 12:16:19 PM PDT 24 |
| Finished | Apr 04 12:16:19 PM PDT 24 |
| Peak memory | 145508 kb |
| Host | smart-1575f0a0-2400-4984-8d56-d34c562059e5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2003707421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2003707421 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.560493632 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 31244035 ps |
| CPU time | 0.45 seconds |
| Started | Apr 04 12:16:12 PM PDT 24 |
| Finished | Apr 04 12:16:13 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-315c2373-ade8-4ed9-b282-a5a79a7a0d74 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=560493632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.560493632 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2213217410 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30055567 ps |
| CPU time | 0.51 seconds |
| Started | Apr 04 12:16:22 PM PDT 24 |
| Finished | Apr 04 12:16:22 PM PDT 24 |
| Peak memory | 143776 kb |
| Host | smart-5093e4f5-4ba4-4603-a028-8e0b56306d17 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2213217410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2213217410 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.732274428 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30562505 ps |
| CPU time | 0.41 seconds |
| Started | Apr 04 12:16:11 PM PDT 24 |
| Finished | Apr 04 12:16:11 PM PDT 24 |
| Peak memory | 145912 kb |
| Host | smart-147fe145-1b11-49db-978b-4d43da8ab014 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=732274428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.732274428 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3136827606 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 29759023 ps |
| CPU time | 0.48 seconds |
| Started | Apr 04 12:16:12 PM PDT 24 |
| Finished | Apr 04 12:16:13 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-b27e8556-0c5f-491d-bc97-f2a52c276c3c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3136827606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3136827606 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3780453701 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 29580905 ps |
| CPU time | 0.42 seconds |
| Started | Apr 04 12:16:19 PM PDT 24 |
| Finished | Apr 04 12:16:19 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-1ad4f730-6b89-4763-a1fd-452b76c6a503 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3780453701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3780453701 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2699190548 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 32207124 ps |
| CPU time | 0.42 seconds |
| Started | Apr 04 12:16:14 PM PDT 24 |
| Finished | Apr 04 12:16:14 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-37b80339-d826-4dd8-b2af-ea582f07bf42 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2699190548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2699190548 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3967237768 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 28893912 ps |
| CPU time | 0.49 seconds |
| Started | Apr 04 12:19:32 PM PDT 24 |
| Finished | Apr 04 12:19:33 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-a36cc576-e6f0-4fd2-a79e-59636d1d4bb3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3967237768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3967237768 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2332236712 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 28404881 ps |
| CPU time | 0.42 seconds |
| Started | Apr 04 12:17:15 PM PDT 24 |
| Finished | Apr 04 12:17:16 PM PDT 24 |
| Peak memory | 145508 kb |
| Host | smart-75b93dec-c6d4-44ea-8248-7dc2da1ee3d8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2332236712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2332236712 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2625434171 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 30111932 ps |
| CPU time | 0.41 seconds |
| Started | Apr 04 12:16:13 PM PDT 24 |
| Finished | Apr 04 12:16:14 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-d77552e2-2009-4b68-a417-46a560b831cf |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2625434171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2625434171 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3810108933 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 29480051 ps |
| CPU time | 0.41 seconds |
| Started | Apr 04 12:16:15 PM PDT 24 |
| Finished | Apr 04 12:16:15 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-82b8739f-f9ed-4bc4-ad9e-8cd0028ce77b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3810108933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3810108933 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.408122641 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 30674231 ps |
| CPU time | 0.43 seconds |
| Started | Apr 04 12:16:28 PM PDT 24 |
| Finished | Apr 04 12:16:29 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-5c4daac2-fc7e-4dd7-af13-e964ca8a1532 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=408122641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.408122641 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4170500264 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30257745 ps |
| CPU time | 0.42 seconds |
| Started | Apr 04 12:18:33 PM PDT 24 |
| Finished | Apr 04 12:18:33 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-5c3f04be-c2d6-46a2-ba01-7bf2601bde8b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4170500264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.4170500264 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1781479074 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30294131 ps |
| CPU time | 0.41 seconds |
| Started | Apr 04 12:16:19 PM PDT 24 |
| Finished | Apr 04 12:16:20 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-e673a59f-60b4-4be0-a52e-8fe87e58f6e5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1781479074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1781479074 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1902344630 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 30704586 ps |
| CPU time | 0.39 seconds |
| Started | Apr 04 12:16:21 PM PDT 24 |
| Finished | Apr 04 12:16:22 PM PDT 24 |
| Peak memory | 145692 kb |
| Host | smart-8d01c1bc-8bfa-4501-b59a-90a1240bc38e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1902344630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1902344630 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2920873420 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30610030 ps |
| CPU time | 0.4 seconds |
| Started | Apr 04 12:20:03 PM PDT 24 |
| Finished | Apr 04 12:20:03 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-efb98fc4-dc6a-47ab-9d03-20bccd13029a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2920873420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2920873420 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1148017392 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29692584 ps |
| CPU time | 0.48 seconds |
| Started | Apr 04 12:16:20 PM PDT 24 |
| Finished | Apr 04 12:16:20 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-0e5e1501-272f-42cf-8487-ac9b329615df |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1148017392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1148017392 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.961207862 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 29161318 ps |
| CPU time | 0.44 seconds |
| Started | Apr 04 12:17:11 PM PDT 24 |
| Finished | Apr 04 12:17:12 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-784e1b2b-b64d-414a-bd4b-d8a56ea4e6ea |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=961207862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.961207862 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.3432301960 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 8881735 ps |
| CPU time | 0.39 seconds |
| Started | Apr 04 02:01:00 PM PDT 24 |
| Finished | Apr 04 02:01:01 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-12d193a4-e37f-4767-a1f9-88b8875ac8dc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3432301960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3432301960 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.2607752459 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9413920 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:01:12 PM PDT 24 |
| Finished | Apr 04 02:01:12 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-677f8dd8-b6b3-4199-b619-5518deb904ed |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2607752459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2607752459 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1090087851 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9159522 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:01:12 PM PDT 24 |
| Finished | Apr 04 02:01:13 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-67abb9e1-146e-4f18-a458-9fb38e534c24 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1090087851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1090087851 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3631323673 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 9183532 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:01:12 PM PDT 24 |
| Finished | Apr 04 02:01:13 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-cc3b65d9-c454-4984-9b6b-b940cf9ecc2b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3631323673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3631323673 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.611522184 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9238025 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:01:12 PM PDT 24 |
| Finished | Apr 04 02:01:12 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-2f7f354b-a813-4256-9d61-7c219f86faf0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=611522184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.611522184 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1043074949 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 9137269 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:01:15 PM PDT 24 |
| Finished | Apr 04 02:01:15 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-06432054-9324-444b-9a2b-7db05e952660 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1043074949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1043074949 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.521490669 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9249927 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:01:11 PM PDT 24 |
| Finished | Apr 04 02:01:12 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-f246cf63-51f5-4b13-be85-aedef001569c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=521490669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.521490669 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.2198720921 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8762806 ps |
| CPU time | 0.39 seconds |
| Started | Apr 04 02:01:12 PM PDT 24 |
| Finished | Apr 04 02:01:12 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-0523ab2a-7cfa-418a-aa4d-e0f87ce9d7b5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2198720921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2198720921 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.3921748324 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8147868 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:01:11 PM PDT 24 |
| Finished | Apr 04 02:01:11 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-a000b494-1545-4afd-92aa-73f9e6d1c5c0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3921748324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3921748324 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.1976176246 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9188823 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:01:13 PM PDT 24 |
| Finished | Apr 04 02:01:14 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-356b365a-504c-4770-a022-73c6afefaada |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1976176246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1976176246 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.71368769 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10238890 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:01:11 PM PDT 24 |
| Finished | Apr 04 02:01:11 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-4cda5a59-8358-4fd1-9775-1bea0aac0626 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=71368769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.71368769 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.4185249645 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9300735 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:00:58 PM PDT 24 |
| Finished | Apr 04 02:00:59 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-94f02976-b24e-4876-95f8-377f0b57f914 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4185249645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.4185249645 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3127383142 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9240480 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:00:57 PM PDT 24 |
| Finished | Apr 04 02:00:57 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-05a6437e-73e0-4ada-a356-a33b628058c4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3127383142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3127383142 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.2024601145 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8821896 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:00:58 PM PDT 24 |
| Finished | Apr 04 02:00:59 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-d72fe1a7-bbeb-4456-b066-76f89df9b6a9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2024601145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2024601145 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.2480839492 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9486836 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:00:57 PM PDT 24 |
| Finished | Apr 04 02:00:58 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-f52cfb71-ce8d-437f-9da3-5bf0ccaf9122 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2480839492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2480839492 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1832004178 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 10809576 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:00:59 PM PDT 24 |
| Finished | Apr 04 02:01:00 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-760b0242-a5f2-4dcd-903b-a71b48953648 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1832004178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1832004178 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.243026271 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9395685 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:01:12 PM PDT 24 |
| Finished | Apr 04 02:01:13 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-0d0cf18d-d14b-4c28-9469-731fb71feb4b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=243026271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.243026271 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.3263718359 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9112694 ps |
| CPU time | 0.38 seconds |
| Started | Apr 04 02:01:12 PM PDT 24 |
| Finished | Apr 04 02:01:12 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-c752a6f3-3af1-48a2-80d5-e14dd6bb5307 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3263718359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3263718359 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.2049085643 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9641516 ps |
| CPU time | 0.37 seconds |
| Started | Apr 04 02:01:12 PM PDT 24 |
| Finished | Apr 04 02:01:12 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-4dbbd013-c946-4663-ae76-b71c8e895d04 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2049085643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2049085643 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1773544769 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 28902067 ps |
| CPU time | 0.44 seconds |
| Started | Apr 04 12:16:34 PM PDT 24 |
| Finished | Apr 04 12:16:35 PM PDT 24 |
| Peak memory | 144696 kb |
| Host | smart-aa3fd867-4622-4978-b7b7-8ab6ba1b2dec |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1773544769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1773544769 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1379459920 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26523140 ps |
| CPU time | 0.41 seconds |
| Started | Apr 04 12:16:20 PM PDT 24 |
| Finished | Apr 04 12:16:21 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-e9dfd942-dfe9-4607-bc11-d66c8113014a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1379459920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1379459920 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2577634291 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 28846980 ps |
| CPU time | 0.52 seconds |
| Started | Apr 04 12:16:22 PM PDT 24 |
| Finished | Apr 04 12:16:22 PM PDT 24 |
| Peak memory | 142480 kb |
| Host | smart-2da12f14-7742-4eab-afd5-485dadfa00c2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2577634291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2577634291 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3886223026 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 30208583 ps |
| CPU time | 0.4 seconds |
| Started | Apr 04 12:16:18 PM PDT 24 |
| Finished | Apr 04 12:16:18 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-8b3040ba-c389-4bc3-888d-5080977ab197 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3886223026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3886223026 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1163556634 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27318437 ps |
| CPU time | 0.42 seconds |
| Started | Apr 04 12:16:20 PM PDT 24 |
| Finished | Apr 04 12:16:20 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-b400ec0b-9d5f-4d67-96a9-3f72a10072c3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1163556634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1163556634 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1315466219 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 26173107 ps |
| CPU time | 0.4 seconds |
| Started | Apr 04 12:16:14 PM PDT 24 |
| Finished | Apr 04 12:16:15 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-24ebd5bd-f060-472b-a29e-742380061348 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1315466219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1315466219 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.514224589 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27544991 ps |
| CPU time | 0.42 seconds |
| Started | Apr 04 12:19:32 PM PDT 24 |
| Finished | Apr 04 12:19:33 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-7b67ca00-137a-4020-ab6e-0238b12a5b95 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=514224589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.514224589 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3580352990 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28457115 ps |
| CPU time | 0.39 seconds |
| Started | Apr 04 12:20:16 PM PDT 24 |
| Finished | Apr 04 12:20:16 PM PDT 24 |
| Peak memory | 144652 kb |
| Host | smart-dc7b4b34-c67b-460b-8218-e0e08e3435f6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3580352990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3580352990 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2284322841 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27486282 ps |
| CPU time | 0.42 seconds |
| Started | Apr 04 12:16:28 PM PDT 24 |
| Finished | Apr 04 12:16:29 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-effa3eed-01ca-4523-9ba4-91596024b572 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2284322841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2284322841 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2967492863 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27601174 ps |
| CPU time | 0.43 seconds |
| Started | Apr 04 12:16:19 PM PDT 24 |
| Finished | Apr 04 12:16:19 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-23294507-d288-47e0-9fbb-5f70e0abc084 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2967492863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2967492863 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.150032494 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 26111254 ps |
| CPU time | 0.4 seconds |
| Started | Apr 04 12:17:14 PM PDT 24 |
| Finished | Apr 04 12:17:15 PM PDT 24 |
| Peak memory | 144708 kb |
| Host | smart-aaf6fb56-ecc3-4b9b-b3ea-4ab332f8a804 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=150032494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.150032494 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3259735055 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28010732 ps |
| CPU time | 0.47 seconds |
| Started | Apr 04 12:16:22 PM PDT 24 |
| Finished | Apr 04 12:16:22 PM PDT 24 |
| Peak memory | 142724 kb |
| Host | smart-6f0713bb-8dcc-471d-8e84-5e06417df4ca |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3259735055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3259735055 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1640065527 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 29546060 ps |
| CPU time | 0.41 seconds |
| Started | Apr 04 12:16:19 PM PDT 24 |
| Finished | Apr 04 12:16:19 PM PDT 24 |
| Peak memory | 144876 kb |
| Host | smart-328ae5d8-6b13-4d34-aa0f-3b99a624b4d7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1640065527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1640065527 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.511985972 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 28431760 ps |
| CPU time | 0.42 seconds |
| Started | Apr 04 12:16:19 PM PDT 24 |
| Finished | Apr 04 12:16:19 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-3f06d755-b32c-4be5-961c-d4699a6a63bf |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=511985972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.511985972 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.755908702 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27649621 ps |
| CPU time | 0.54 seconds |
| Started | Apr 04 12:16:22 PM PDT 24 |
| Finished | Apr 04 12:16:22 PM PDT 24 |
| Peak memory | 143280 kb |
| Host | smart-a1404392-3e07-42a8-ace6-5a23125a3e27 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=755908702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.755908702 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4204783571 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27501224 ps |
| CPU time | 0.42 seconds |
| Started | Apr 04 12:21:18 PM PDT 24 |
| Finished | Apr 04 12:21:19 PM PDT 24 |
| Peak memory | 144616 kb |
| Host | smart-6aa27e00-3f9c-40bb-bb57-2fb1bfb2fc1a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4204783571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.4204783571 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3426814250 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27163003 ps |
| CPU time | 0.43 seconds |
| Started | Apr 04 12:16:19 PM PDT 24 |
| Finished | Apr 04 12:16:19 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-ca123ff3-a077-4330-baf9-71ba54b28cb4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3426814250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3426814250 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3242923994 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 25181593 ps |
| CPU time | 0.42 seconds |
| Started | Apr 04 12:16:21 PM PDT 24 |
| Finished | Apr 04 12:16:22 PM PDT 24 |
| Peak memory | 144596 kb |
| Host | smart-82b6b783-408c-4edd-bbf5-a9bb8a46fa3f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3242923994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3242923994 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.706310842 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 26090267 ps |
| CPU time | 0.41 seconds |
| Started | Apr 04 12:16:27 PM PDT 24 |
| Finished | Apr 04 12:16:27 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-ceb42ada-2374-4935-98ea-8d60e94c5b16 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=706310842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.706310842 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.198380916 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 25617560 ps |
| CPU time | 0.41 seconds |
| Started | Apr 04 12:16:25 PM PDT 24 |
| Finished | Apr 04 12:16:25 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-410693d6-0cd5-4cdc-8fd7-414b437c1252 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=198380916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.198380916 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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