| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.92 | 88.92 | 100.00 | 100.00 | 91.67 | 91.67 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/5.prim_async_alert.4099979100 |
| 92.64 | 3.72 | 100.00 | 0.00 | 91.67 | 0.00 | 100.00 | 0.00 | 89.29 | 10.71 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/0.prim_sync_alert.4050369049 |
| 94.50 | 1.86 | 100.00 | 0.00 | 95.83 | 4.17 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3552166884 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/1.prim_sync_alert.2002514325 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1711694773 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.4005949763 |
| /workspace/coverage/default/1.prim_async_alert.2039641373 |
| /workspace/coverage/default/10.prim_async_alert.1411302692 |
| /workspace/coverage/default/11.prim_async_alert.686420990 |
| /workspace/coverage/default/12.prim_async_alert.2175165435 |
| /workspace/coverage/default/13.prim_async_alert.1561179589 |
| /workspace/coverage/default/14.prim_async_alert.1463325668 |
| /workspace/coverage/default/15.prim_async_alert.3093509404 |
| /workspace/coverage/default/16.prim_async_alert.2590566618 |
| /workspace/coverage/default/17.prim_async_alert.856939933 |
| /workspace/coverage/default/18.prim_async_alert.413584118 |
| /workspace/coverage/default/19.prim_async_alert.3149187464 |
| /workspace/coverage/default/2.prim_async_alert.2708536003 |
| /workspace/coverage/default/3.prim_async_alert.2050573794 |
| /workspace/coverage/default/4.prim_async_alert.1891338978 |
| /workspace/coverage/default/6.prim_async_alert.4272137767 |
| /workspace/coverage/default/7.prim_async_alert.3585265076 |
| /workspace/coverage/default/8.prim_async_alert.3174798731 |
| /workspace/coverage/default/9.prim_async_alert.1561742226 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2441963833 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4092205510 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2272114198 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2510190846 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1173792927 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1891106642 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1502601323 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1049695195 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3008557356 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.865529542 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.748945027 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.968802200 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4277016813 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2554834907 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2137004760 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2377540186 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3681044332 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3081019440 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.779097867 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.2510855428 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3709396185 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.2321149505 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.2056434343 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.3506754594 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.4060457907 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.3993675513 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.1231225283 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.195983782 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.3804880138 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3982180021 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.3242758549 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.2371671897 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1939125615 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.2095867078 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.1970875016 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.2305993676 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1243210754 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2436887508 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4040197972 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.121182831 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.808402755 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2672332158 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2662624169 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3220408997 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1766980153 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.215800069 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2648997501 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3166432097 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3309554882 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1200801165 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.115087405 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2642788277 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.482262675 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.854896914 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2591292157 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_async_alert.1561742226 | Apr 15 12:14:05 PM PDT 24 | Apr 15 12:14:06 PM PDT 24 | 11823749 ps | ||
| T2 | /workspace/coverage/default/0.prim_async_alert.4005949763 | Apr 15 12:13:57 PM PDT 24 | Apr 15 12:13:59 PM PDT 24 | 10435537 ps | ||
| T3 | /workspace/coverage/default/11.prim_async_alert.686420990 | Apr 15 12:13:56 PM PDT 24 | Apr 15 12:13:57 PM PDT 24 | 11620531 ps | ||
| T15 | /workspace/coverage/default/8.prim_async_alert.3174798731 | Apr 15 12:13:56 PM PDT 24 | Apr 15 12:13:57 PM PDT 24 | 11152993 ps | ||
| T7 | /workspace/coverage/default/1.prim_async_alert.2039641373 | Apr 15 12:13:57 PM PDT 24 | Apr 15 12:13:59 PM PDT 24 | 11762307 ps | ||
| T10 | /workspace/coverage/default/5.prim_async_alert.4099979100 | Apr 15 12:13:58 PM PDT 24 | Apr 15 12:14:00 PM PDT 24 | 12193098 ps | ||
| T8 | /workspace/coverage/default/15.prim_async_alert.3093509404 | Apr 15 12:13:56 PM PDT 24 | Apr 15 12:13:58 PM PDT 24 | 11199662 ps | ||
| T6 | /workspace/coverage/default/17.prim_async_alert.856939933 | Apr 15 12:13:58 PM PDT 24 | Apr 15 12:14:00 PM PDT 24 | 10658210 ps | ||
| T14 | /workspace/coverage/default/7.prim_async_alert.3585265076 | Apr 15 12:13:59 PM PDT 24 | Apr 15 12:14:01 PM PDT 24 | 11295349 ps | ||
| T11 | /workspace/coverage/default/3.prim_async_alert.2050573794 | Apr 15 12:13:57 PM PDT 24 | Apr 15 12:13:59 PM PDT 24 | 11022535 ps | ||
| T12 | /workspace/coverage/default/19.prim_async_alert.3149187464 | Apr 15 12:14:03 PM PDT 24 | Apr 15 12:14:04 PM PDT 24 | 11113606 ps | ||
| T16 | /workspace/coverage/default/16.prim_async_alert.2590566618 | Apr 15 12:13:55 PM PDT 24 | Apr 15 12:13:56 PM PDT 24 | 11555787 ps | ||
| T17 | /workspace/coverage/default/18.prim_async_alert.413584118 | Apr 15 12:13:55 PM PDT 24 | Apr 15 12:13:56 PM PDT 24 | 11236737 ps | ||
| T18 | /workspace/coverage/default/13.prim_async_alert.1561179589 | Apr 15 12:13:54 PM PDT 24 | Apr 15 12:13:55 PM PDT 24 | 11241092 ps | ||
| T40 | /workspace/coverage/default/12.prim_async_alert.2175165435 | Apr 15 12:13:49 PM PDT 24 | Apr 15 12:13:50 PM PDT 24 | 11015036 ps | ||
| T13 | /workspace/coverage/default/2.prim_async_alert.2708536003 | Apr 15 12:13:57 PM PDT 24 | Apr 15 12:13:59 PM PDT 24 | 11159882 ps | ||
| T41 | /workspace/coverage/default/6.prim_async_alert.4272137767 | Apr 15 12:13:56 PM PDT 24 | Apr 15 12:13:58 PM PDT 24 | 11042551 ps | ||
| T42 | /workspace/coverage/default/4.prim_async_alert.1891338978 | Apr 15 12:13:58 PM PDT 24 | Apr 15 12:14:01 PM PDT 24 | 10729267 ps | ||
| T43 | /workspace/coverage/default/14.prim_async_alert.1463325668 | Apr 15 12:13:58 PM PDT 24 | Apr 15 12:14:00 PM PDT 24 | 12715049 ps | ||
| T44 | /workspace/coverage/default/10.prim_async_alert.1411302692 | Apr 15 12:13:55 PM PDT 24 | Apr 15 12:13:55 PM PDT 24 | 10453592 ps | ||
| T33 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2441963833 | Apr 15 12:13:58 PM PDT 24 | Apr 15 12:14:00 PM PDT 24 | 28506083 ps | ||
| T34 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2377540186 | Apr 15 12:13:57 PM PDT 24 | Apr 15 12:13:58 PM PDT 24 | 28543217 ps | ||
| T35 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3552166884 | Apr 15 12:13:58 PM PDT 24 | Apr 15 12:14:00 PM PDT 24 | 30404450 ps | ||
| T19 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1049695195 | Apr 15 12:13:55 PM PDT 24 | Apr 15 12:13:56 PM PDT 24 | 30289779 ps | ||
| T36 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3081019440 | Apr 15 12:14:05 PM PDT 24 | Apr 15 12:14:06 PM PDT 24 | 29822704 ps | ||
| T20 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2137004760 | Apr 15 12:13:48 PM PDT 24 | Apr 15 12:13:49 PM PDT 24 | 30744934 ps | ||
| T21 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1502601323 | Apr 15 12:13:55 PM PDT 24 | Apr 15 12:13:55 PM PDT 24 | 28706883 ps | ||
| T37 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4092205510 | Apr 15 12:13:56 PM PDT 24 | Apr 15 12:13:57 PM PDT 24 | 29600981 ps | ||
| T38 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.968802200 | Apr 15 12:14:05 PM PDT 24 | Apr 15 12:14:06 PM PDT 24 | 30984978 ps | ||
| T39 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3681044332 | Apr 15 12:13:58 PM PDT 24 | Apr 15 12:14:00 PM PDT 24 | 31412713 ps | ||
| T45 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3008557356 | Apr 15 12:13:55 PM PDT 24 | Apr 15 12:13:56 PM PDT 24 | 28330424 ps | ||
| T46 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2554834907 | Apr 15 12:13:58 PM PDT 24 | Apr 15 12:14:00 PM PDT 24 | 28449187 ps | ||
| T47 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.748945027 | Apr 15 12:13:55 PM PDT 24 | Apr 15 12:13:55 PM PDT 24 | 30959156 ps | ||
| T48 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4277016813 | Apr 15 12:13:57 PM PDT 24 | Apr 15 12:13:59 PM PDT 24 | 29596588 ps | ||
| T49 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.865529542 | Apr 15 12:13:59 PM PDT 24 | Apr 15 12:14:01 PM PDT 24 | 29860417 ps | ||
| T50 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2510190846 | Apr 15 12:13:56 PM PDT 24 | Apr 15 12:13:57 PM PDT 24 | 29495627 ps | ||
| T51 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1891106642 | Apr 15 12:13:59 PM PDT 24 | Apr 15 12:14:01 PM PDT 24 | 29954914 ps | ||
| T52 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2272114198 | Apr 15 12:13:56 PM PDT 24 | Apr 15 12:13:58 PM PDT 24 | 30319549 ps | ||
| T53 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1173792927 | Apr 15 12:13:57 PM PDT 24 | Apr 15 12:13:59 PM PDT 24 | 32832115 ps | ||
| T22 | /workspace/coverage/sync_alert/12.prim_sync_alert.3709396185 | Apr 15 12:13:58 PM PDT 24 | Apr 15 12:14:00 PM PDT 24 | 8791885 ps | ||
| T32 | /workspace/coverage/sync_alert/13.prim_sync_alert.2321149505 | Apr 15 12:13:58 PM PDT 24 | Apr 15 12:13:59 PM PDT 24 | 9292441 ps | ||
| T23 | /workspace/coverage/sync_alert/10.prim_sync_alert.779097867 | Apr 15 12:13:59 PM PDT 24 | Apr 15 12:14:01 PM PDT 24 | 8747578 ps | ||
| T24 | /workspace/coverage/sync_alert/4.prim_sync_alert.3242758549 | Apr 15 12:13:54 PM PDT 24 | Apr 15 12:13:55 PM PDT 24 | 9292534 ps | ||
| T25 | /workspace/coverage/sync_alert/0.prim_sync_alert.4050369049 | Apr 15 12:13:55 PM PDT 24 | Apr 15 12:13:56 PM PDT 24 | 10353644 ps | ||
| T26 | /workspace/coverage/sync_alert/9.prim_sync_alert.2305993676 | Apr 15 12:13:48 PM PDT 24 | Apr 15 12:13:49 PM PDT 24 | 9766201 ps | ||
| T27 | /workspace/coverage/sync_alert/15.prim_sync_alert.3506754594 | Apr 15 12:14:04 PM PDT 24 | Apr 15 12:14:05 PM PDT 24 | 8679619 ps | ||
| T9 | /workspace/coverage/sync_alert/1.prim_sync_alert.2002514325 | Apr 15 12:13:56 PM PDT 24 | Apr 15 12:13:58 PM PDT 24 | 8773334 ps | ||
| T28 | /workspace/coverage/sync_alert/11.prim_sync_alert.2510855428 | Apr 15 12:14:06 PM PDT 24 | Apr 15 12:14:07 PM PDT 24 | 9213138 ps | ||
| T29 | /workspace/coverage/sync_alert/16.prim_sync_alert.4060457907 | Apr 15 12:14:04 PM PDT 24 | Apr 15 12:14:05 PM PDT 24 | 9211985 ps | ||
| T30 | /workspace/coverage/sync_alert/19.prim_sync_alert.195983782 | Apr 15 12:14:01 PM PDT 24 | Apr 15 12:14:02 PM PDT 24 | 8931386 ps | ||
| T31 | /workspace/coverage/sync_alert/14.prim_sync_alert.2056434343 | Apr 15 12:13:57 PM PDT 24 | Apr 15 12:13:58 PM PDT 24 | 8908813 ps | ||
| T54 | /workspace/coverage/sync_alert/3.prim_sync_alert.3982180021 | Apr 15 12:13:57 PM PDT 24 | Apr 15 12:13:59 PM PDT 24 | 9782511 ps | ||
| T55 | /workspace/coverage/sync_alert/5.prim_sync_alert.2371671897 | Apr 15 12:13:58 PM PDT 24 | Apr 15 12:13:59 PM PDT 24 | 9887602 ps | ||
| T56 | /workspace/coverage/sync_alert/17.prim_sync_alert.3993675513 | Apr 15 12:13:56 PM PDT 24 | Apr 15 12:13:58 PM PDT 24 | 8965439 ps | ||
| T57 | /workspace/coverage/sync_alert/6.prim_sync_alert.1939125615 | Apr 15 12:14:05 PM PDT 24 | Apr 15 12:14:06 PM PDT 24 | 8662320 ps | ||
| T58 | /workspace/coverage/sync_alert/2.prim_sync_alert.3804880138 | Apr 15 12:13:56 PM PDT 24 | Apr 15 12:13:57 PM PDT 24 | 8148697 ps | ||
| T59 | /workspace/coverage/sync_alert/18.prim_sync_alert.1231225283 | Apr 15 12:13:57 PM PDT 24 | Apr 15 12:13:59 PM PDT 24 | 10769247 ps | ||
| T60 | /workspace/coverage/sync_alert/7.prim_sync_alert.2095867078 | Apr 15 12:13:55 PM PDT 24 | Apr 15 12:13:56 PM PDT 24 | 8536509 ps | ||
| T61 | /workspace/coverage/sync_alert/8.prim_sync_alert.1970875016 | Apr 15 12:14:05 PM PDT 24 | Apr 15 12:14:06 PM PDT 24 | 9500232 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.121182831 | Apr 15 12:19:11 PM PDT 24 | Apr 15 12:19:12 PM PDT 24 | 30294985 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.115087405 | Apr 15 12:19:10 PM PDT 24 | Apr 15 12:19:12 PM PDT 24 | 26281239 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3309554882 | Apr 15 12:19:31 PM PDT 24 | Apr 15 12:19:32 PM PDT 24 | 26647136 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1243210754 | Apr 15 12:19:41 PM PDT 24 | Apr 15 12:19:43 PM PDT 24 | 28608424 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.808402755 | Apr 15 12:19:09 PM PDT 24 | Apr 15 12:19:10 PM PDT 24 | 27343043 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.215800069 | Apr 15 12:18:51 PM PDT 24 | Apr 15 12:18:52 PM PDT 24 | 27375175 ps | ||
| T4 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1200801165 | Apr 15 12:19:10 PM PDT 24 | Apr 15 12:19:11 PM PDT 24 | 27951384 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2662624169 | Apr 15 12:19:43 PM PDT 24 | Apr 15 12:19:47 PM PDT 24 | 27893161 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2648997501 | Apr 15 12:18:51 PM PDT 24 | Apr 15 12:18:52 PM PDT 24 | 26828988 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1711694773 | Apr 15 12:19:10 PM PDT 24 | Apr 15 12:19:12 PM PDT 24 | 26500008 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4040197972 | Apr 15 12:19:10 PM PDT 24 | Apr 15 12:19:12 PM PDT 24 | 25217256 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.854896914 | Apr 15 12:18:28 PM PDT 24 | Apr 15 12:18:29 PM PDT 24 | 28248020 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1766980153 | Apr 15 12:19:44 PM PDT 24 | Apr 15 12:19:46 PM PDT 24 | 28220626 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.482262675 | Apr 15 12:19:10 PM PDT 24 | Apr 15 12:19:11 PM PDT 24 | 28253229 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3166432097 | Apr 15 12:17:57 PM PDT 24 | Apr 15 12:17:58 PM PDT 24 | 26853917 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3220408997 | Apr 15 12:19:02 PM PDT 24 | Apr 15 12:19:03 PM PDT 24 | 27019221 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2672332158 | Apr 15 12:18:50 PM PDT 24 | Apr 15 12:18:52 PM PDT 24 | 26187627 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2436887508 | Apr 15 12:19:42 PM PDT 24 | Apr 15 12:19:43 PM PDT 24 | 27059254 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2642788277 | Apr 15 12:19:09 PM PDT 24 | Apr 15 12:19:10 PM PDT 24 | 26520563 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2591292157 | Apr 15 12:19:10 PM PDT 24 | Apr 15 12:19:11 PM PDT 24 | 25339083 ps |
| Test location | /workspace/coverage/default/5.prim_async_alert.4099979100 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12193098 ps |
| CPU time | 0.37 seconds |
| Started | Apr 15 12:13:58 PM PDT 24 |
| Finished | Apr 15 12:14:00 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-28ae3e02-c955-433f-a7b6-332cf46d659c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4099979100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.4099979100 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.4050369049 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10353644 ps |
| CPU time | 0.43 seconds |
| Started | Apr 15 12:13:55 PM PDT 24 |
| Finished | Apr 15 12:13:56 PM PDT 24 |
| Peak memory | 144552 kb |
| Host | smart-ba472328-3d84-4424-9646-c2e1a01f5291 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4050369049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4050369049 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3552166884 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 30404450 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:13:58 PM PDT 24 |
| Finished | Apr 15 12:14:00 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-a92de79c-17a5-41cb-b55c-9ab8d6fbcf42 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3552166884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3552166884 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.2002514325 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8773334 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:13:56 PM PDT 24 |
| Finished | Apr 15 12:13:58 PM PDT 24 |
| Peak memory | 143996 kb |
| Host | smart-00a33135-2337-40c5-b96a-6061aaa2cb2a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2002514325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2002514325 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1711694773 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 26500008 ps |
| CPU time | 0.46 seconds |
| Started | Apr 15 12:19:10 PM PDT 24 |
| Finished | Apr 15 12:19:12 PM PDT 24 |
| Peak memory | 143644 kb |
| Host | smart-11acf246-cf16-4455-91d1-9d4c2c815435 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1711694773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1711694773 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.4005949763 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10435537 ps |
| CPU time | 0.37 seconds |
| Started | Apr 15 12:13:57 PM PDT 24 |
| Finished | Apr 15 12:13:59 PM PDT 24 |
| Peak memory | 144792 kb |
| Host | smart-7c183bac-1cb1-4717-a0a5-c4bbe8a348c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005949763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.4005949763 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.2039641373 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11762307 ps |
| CPU time | 0.42 seconds |
| Started | Apr 15 12:13:57 PM PDT 24 |
| Finished | Apr 15 12:13:59 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-568f21ff-bb37-4f21-b0cd-5b5f18dad0ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2039641373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2039641373 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.1411302692 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10453592 ps |
| CPU time | 0.37 seconds |
| Started | Apr 15 12:13:55 PM PDT 24 |
| Finished | Apr 15 12:13:55 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-77d2b577-2ba4-4f70-975c-c9eab3be5849 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1411302692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1411302692 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.686420990 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11620531 ps |
| CPU time | 0.42 seconds |
| Started | Apr 15 12:13:56 PM PDT 24 |
| Finished | Apr 15 12:13:57 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-92f08f63-37d2-443b-8d21-d0e36e6dba96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686420990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.686420990 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.2175165435 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11015036 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:13:49 PM PDT 24 |
| Finished | Apr 15 12:13:50 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-98d808bf-c736-47dc-b1b0-c03094006ae4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175165435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2175165435 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1561179589 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11241092 ps |
| CPU time | 0.44 seconds |
| Started | Apr 15 12:13:54 PM PDT 24 |
| Finished | Apr 15 12:13:55 PM PDT 24 |
| Peak memory | 144580 kb |
| Host | smart-70128d01-71e5-4912-8042-1d1086a51c79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561179589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1561179589 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1463325668 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12715049 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:13:58 PM PDT 24 |
| Finished | Apr 15 12:14:00 PM PDT 24 |
| Peak memory | 145388 kb |
| Host | smart-8cebf20e-fca0-4a10-8001-823966e50ac6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463325668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1463325668 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3093509404 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11199662 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:13:56 PM PDT 24 |
| Finished | Apr 15 12:13:58 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-e453e1f8-7f89-4abb-b15a-e120a85224af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093509404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3093509404 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.2590566618 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11555787 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:13:55 PM PDT 24 |
| Finished | Apr 15 12:13:56 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-ebef8d9c-ab49-4869-80ca-f56ce98b7b1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590566618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2590566618 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.856939933 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 10658210 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:13:58 PM PDT 24 |
| Finished | Apr 15 12:14:00 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-428b394e-f052-4aae-b4c5-bc68aa23ea54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856939933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.856939933 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.413584118 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11236737 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:13:55 PM PDT 24 |
| Finished | Apr 15 12:13:56 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-574ddb1f-71ea-4584-89bc-ca8d1e47563c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=413584118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.413584118 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3149187464 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11113606 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:14:03 PM PDT 24 |
| Finished | Apr 15 12:14:04 PM PDT 24 |
| Peak memory | 145868 kb |
| Host | smart-438051af-5c28-4f5b-8fec-69a654dfa3e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3149187464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3149187464 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.2708536003 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11159882 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:13:57 PM PDT 24 |
| Finished | Apr 15 12:13:59 PM PDT 24 |
| Peak memory | 146124 kb |
| Host | smart-0fd5c536-2c03-4e98-8c53-de533fd30fc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708536003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2708536003 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.2050573794 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11022535 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:13:57 PM PDT 24 |
| Finished | Apr 15 12:13:59 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-df3c679d-30f9-4dac-9bdf-9169345f978f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2050573794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2050573794 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.1891338978 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10729267 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:13:58 PM PDT 24 |
| Finished | Apr 15 12:14:01 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-be22fdeb-9d22-4835-96cd-ce71eedcc8bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1891338978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1891338978 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.4272137767 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11042551 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:13:56 PM PDT 24 |
| Finished | Apr 15 12:13:58 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-c4e43156-ba41-473b-9945-afef666352bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4272137767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.4272137767 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.3585265076 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11295349 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:13:59 PM PDT 24 |
| Finished | Apr 15 12:14:01 PM PDT 24 |
| Peak memory | 145512 kb |
| Host | smart-401cf81b-1ac3-46e6-af54-62e1a90a40c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3585265076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3585265076 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.3174798731 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11152993 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:13:56 PM PDT 24 |
| Finished | Apr 15 12:13:57 PM PDT 24 |
| Peak memory | 145880 kb |
| Host | smart-99cd297d-09e7-439b-98f4-7d4e69a654ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174798731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3174798731 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1561742226 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11823749 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:14:05 PM PDT 24 |
| Finished | Apr 15 12:14:06 PM PDT 24 |
| Peak memory | 145880 kb |
| Host | smart-d87082ab-38ad-48dc-8654-b3674bdf784c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561742226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1561742226 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2441963833 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 28506083 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:13:58 PM PDT 24 |
| Finished | Apr 15 12:14:00 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-7d210b42-4fac-48e8-b6b6-d041f001ab67 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2441963833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2441963833 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4092205510 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 29600981 ps |
| CPU time | 0.45 seconds |
| Started | Apr 15 12:13:56 PM PDT 24 |
| Finished | Apr 15 12:13:57 PM PDT 24 |
| Peak memory | 143800 kb |
| Host | smart-d8130be1-5516-40a7-ace1-1acf17294015 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4092205510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.4092205510 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2272114198 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30319549 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:13:56 PM PDT 24 |
| Finished | Apr 15 12:13:58 PM PDT 24 |
| Peak memory | 145508 kb |
| Host | smart-6f246a13-0b88-4921-af77-27a0d9e06b5e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2272114198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2272114198 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2510190846 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 29495627 ps |
| CPU time | 0.44 seconds |
| Started | Apr 15 12:13:56 PM PDT 24 |
| Finished | Apr 15 12:13:57 PM PDT 24 |
| Peak memory | 144396 kb |
| Host | smart-83acb2df-edf5-4a7e-8d48-63df7b6a7c7c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2510190846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2510190846 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1173792927 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 32832115 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:13:57 PM PDT 24 |
| Finished | Apr 15 12:13:59 PM PDT 24 |
| Peak memory | 145728 kb |
| Host | smart-12087311-7734-4993-9aa5-1445bb809560 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1173792927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1173792927 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1891106642 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29954914 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:13:59 PM PDT 24 |
| Finished | Apr 15 12:14:01 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-2f0f1c75-dea9-4d8d-894d-75c66b6e7273 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1891106642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1891106642 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1502601323 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 28706883 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:13:55 PM PDT 24 |
| Finished | Apr 15 12:13:55 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-e04f39f7-8c2d-43b9-a79e-fef9b9cb17fb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1502601323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1502601323 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1049695195 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 30289779 ps |
| CPU time | 0.42 seconds |
| Started | Apr 15 12:13:55 PM PDT 24 |
| Finished | Apr 15 12:13:56 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-980dc086-e3f7-4ae5-ade4-be46c405fedc |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1049695195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1049695195 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3008557356 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 28330424 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:13:55 PM PDT 24 |
| Finished | Apr 15 12:13:56 PM PDT 24 |
| Peak memory | 145908 kb |
| Host | smart-fb9e0651-5980-4474-8284-70066eee8e77 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3008557356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3008557356 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.865529542 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29860417 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:13:59 PM PDT 24 |
| Finished | Apr 15 12:14:01 PM PDT 24 |
| Peak memory | 145324 kb |
| Host | smart-1eab7fc9-e0af-4e05-b9ab-dd534f4d6379 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=865529542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.865529542 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.748945027 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 30959156 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:13:55 PM PDT 24 |
| Finished | Apr 15 12:13:55 PM PDT 24 |
| Peak memory | 146088 kb |
| Host | smart-02b35eca-91f5-4900-9a82-d85212c7849f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=748945027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.748945027 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.968802200 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 30984978 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:14:05 PM PDT 24 |
| Finished | Apr 15 12:14:06 PM PDT 24 |
| Peak memory | 145904 kb |
| Host | smart-e7dff451-2516-4640-a00e-19bf608ed8bd |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=968802200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.968802200 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4277016813 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29596588 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:13:57 PM PDT 24 |
| Finished | Apr 15 12:13:59 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-5882f7ed-119a-407d-8729-9ef2d2ed828a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4277016813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.4277016813 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2554834907 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 28449187 ps |
| CPU time | 0.44 seconds |
| Started | Apr 15 12:13:58 PM PDT 24 |
| Finished | Apr 15 12:14:00 PM PDT 24 |
| Peak memory | 144824 kb |
| Host | smart-447958bc-3abc-4e9a-b835-c1df5f114bdd |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2554834907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2554834907 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2137004760 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 30744934 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:13:48 PM PDT 24 |
| Finished | Apr 15 12:13:49 PM PDT 24 |
| Peak memory | 145700 kb |
| Host | smart-9fff06d5-57b1-4df0-9060-4d89387d19d6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2137004760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2137004760 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2377540186 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 28543217 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:13:57 PM PDT 24 |
| Finished | Apr 15 12:13:58 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-c9d93167-45f9-46ba-ab1c-d9038bbab728 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2377540186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2377540186 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3681044332 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 31412713 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:13:58 PM PDT 24 |
| Finished | Apr 15 12:14:00 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-1488c7b1-da49-41cb-ab02-a32987be308f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3681044332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3681044332 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3081019440 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 29822704 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:14:05 PM PDT 24 |
| Finished | Apr 15 12:14:06 PM PDT 24 |
| Peak memory | 145900 kb |
| Host | smart-51ce217c-0837-4ff3-a93b-0747ae9be45d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3081019440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3081019440 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.779097867 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8747578 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:13:59 PM PDT 24 |
| Finished | Apr 15 12:14:01 PM PDT 24 |
| Peak memory | 144616 kb |
| Host | smart-c8328599-4149-4b38-b407-e64b331cdba6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=779097867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.779097867 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.2510855428 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9213138 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:14:06 PM PDT 24 |
| Finished | Apr 15 12:14:07 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-505d30e1-0827-4c19-9b3a-7b41a6af1f49 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2510855428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2510855428 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3709396185 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8791885 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:13:58 PM PDT 24 |
| Finished | Apr 15 12:14:00 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-8405ad31-29ed-4b3f-9436-a1fc64e0e17c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3709396185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3709396185 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.2321149505 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9292441 ps |
| CPU time | 0.37 seconds |
| Started | Apr 15 12:13:58 PM PDT 24 |
| Finished | Apr 15 12:13:59 PM PDT 24 |
| Peak memory | 144512 kb |
| Host | smart-9bec27dc-b129-4eab-92bf-4994a2fc80cf |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2321149505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2321149505 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.2056434343 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8908813 ps |
| CPU time | 0.37 seconds |
| Started | Apr 15 12:13:57 PM PDT 24 |
| Finished | Apr 15 12:13:58 PM PDT 24 |
| Peak memory | 144520 kb |
| Host | smart-8e6a9e1c-23d0-4b8a-9e13-ddcda209bb76 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2056434343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2056434343 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3506754594 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8679619 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:14:04 PM PDT 24 |
| Finished | Apr 15 12:14:05 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-b3aa4a33-67e3-41e6-9fd8-3cd9e81d7a42 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3506754594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3506754594 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.4060457907 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9211985 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:14:04 PM PDT 24 |
| Finished | Apr 15 12:14:05 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-31f947a9-9f2c-4f9c-ac07-0708152883bd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4060457907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.4060457907 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.3993675513 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8965439 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:13:56 PM PDT 24 |
| Finished | Apr 15 12:13:58 PM PDT 24 |
| Peak memory | 144520 kb |
| Host | smart-ae47df1b-c670-44b0-b080-c4cc8443d2f8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3993675513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3993675513 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.1231225283 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 10769247 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:13:57 PM PDT 24 |
| Finished | Apr 15 12:13:59 PM PDT 24 |
| Peak memory | 144544 kb |
| Host | smart-7f47ae68-999e-4959-8fa8-e09800db49e1 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1231225283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1231225283 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.195983782 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8931386 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:14:01 PM PDT 24 |
| Finished | Apr 15 12:14:02 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-97866519-35de-4efd-a14b-eafba20ae78c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=195983782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.195983782 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3804880138 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8148697 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:13:56 PM PDT 24 |
| Finished | Apr 15 12:13:57 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-c0b89c40-b11c-408b-a686-d2ff88427901 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3804880138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3804880138 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3982180021 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 9782511 ps |
| CPU time | 0.41 seconds |
| Started | Apr 15 12:13:57 PM PDT 24 |
| Finished | Apr 15 12:13:59 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-2de094e6-b34d-461e-a533-2e2e0448b9ea |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3982180021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3982180021 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.3242758549 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9292534 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:13:54 PM PDT 24 |
| Finished | Apr 15 12:13:55 PM PDT 24 |
| Peak memory | 143772 kb |
| Host | smart-d47656d1-ce09-4be1-a0e0-3bc28745d2e8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3242758549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3242758549 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.2371671897 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9887602 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:13:58 PM PDT 24 |
| Finished | Apr 15 12:13:59 PM PDT 24 |
| Peak memory | 144704 kb |
| Host | smart-12e50bdf-4cc8-427f-888d-a89c20326fd7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2371671897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2371671897 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1939125615 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8662320 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:14:05 PM PDT 24 |
| Finished | Apr 15 12:14:06 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-eda36c96-a33e-4017-886d-1821f3d7a4c2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1939125615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1939125615 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.2095867078 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8536509 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:13:55 PM PDT 24 |
| Finished | Apr 15 12:13:56 PM PDT 24 |
| Peak memory | 144780 kb |
| Host | smart-34b1ce26-a05a-41b6-a09b-fa3e46fd3935 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2095867078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2095867078 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1970875016 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9500232 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:14:05 PM PDT 24 |
| Finished | Apr 15 12:14:06 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-87c8cec8-623f-438c-9830-81ef33a5e4e3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1970875016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1970875016 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.2305993676 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9766201 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:13:48 PM PDT 24 |
| Finished | Apr 15 12:13:49 PM PDT 24 |
| Peak memory | 144780 kb |
| Host | smart-9a62afc7-932e-466d-b9bf-397f142bb284 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2305993676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2305993676 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1243210754 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28608424 ps |
| CPU time | 0.46 seconds |
| Started | Apr 15 12:19:41 PM PDT 24 |
| Finished | Apr 15 12:19:43 PM PDT 24 |
| Peak memory | 144100 kb |
| Host | smart-9f688035-eb8a-4f17-bd68-f46ecd5b0d96 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1243210754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1243210754 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2436887508 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27059254 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:19:42 PM PDT 24 |
| Finished | Apr 15 12:19:43 PM PDT 24 |
| Peak memory | 145276 kb |
| Host | smart-8668bb67-cd20-4458-aa95-ca395185a41e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2436887508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2436887508 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4040197972 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 25217256 ps |
| CPU time | 0.44 seconds |
| Started | Apr 15 12:19:10 PM PDT 24 |
| Finished | Apr 15 12:19:12 PM PDT 24 |
| Peak memory | 142692 kb |
| Host | smart-b2617411-c764-4c20-b553-5cd36bacc535 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4040197972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4040197972 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.121182831 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 30294985 ps |
| CPU time | 0.42 seconds |
| Started | Apr 15 12:19:11 PM PDT 24 |
| Finished | Apr 15 12:19:12 PM PDT 24 |
| Peak memory | 144612 kb |
| Host | smart-0200bcd1-5c28-43a9-b0f1-341e84dda830 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=121182831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.121182831 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.808402755 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27343043 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:19:09 PM PDT 24 |
| Finished | Apr 15 12:19:10 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-2afc6246-de5c-4912-8759-5996b41bebc4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=808402755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.808402755 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2672332158 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 26187627 ps |
| CPU time | 0.51 seconds |
| Started | Apr 15 12:18:50 PM PDT 24 |
| Finished | Apr 15 12:18:52 PM PDT 24 |
| Peak memory | 143644 kb |
| Host | smart-c59602eb-82a5-45cc-869b-d6d3cc0f1847 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2672332158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2672332158 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2662624169 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27893161 ps |
| CPU time | 0.38 seconds |
| Started | Apr 15 12:19:43 PM PDT 24 |
| Finished | Apr 15 12:19:47 PM PDT 24 |
| Peak memory | 144728 kb |
| Host | smart-037579e8-cbf2-4483-8aea-7b6342267fa9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2662624169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2662624169 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3220408997 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27019221 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:19:02 PM PDT 24 |
| Finished | Apr 15 12:19:03 PM PDT 24 |
| Peak memory | 144864 kb |
| Host | smart-a29e9353-3165-44b5-8dcc-cf9d4acc771b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3220408997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3220408997 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1766980153 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28220626 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:19:44 PM PDT 24 |
| Finished | Apr 15 12:19:46 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-2ff4dd84-79a9-414a-a851-71477c67303d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1766980153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1766980153 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.215800069 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27375175 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:18:51 PM PDT 24 |
| Finished | Apr 15 12:18:52 PM PDT 24 |
| Peak memory | 144604 kb |
| Host | smart-656388c3-5526-4061-b03b-7dc80797c56f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=215800069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.215800069 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2648997501 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 26828988 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:18:51 PM PDT 24 |
| Finished | Apr 15 12:18:52 PM PDT 24 |
| Peak memory | 144636 kb |
| Host | smart-f882acc5-0202-4941-b44c-6d6ea7720b38 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2648997501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2648997501 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3166432097 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26853917 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:17:57 PM PDT 24 |
| Finished | Apr 15 12:17:58 PM PDT 24 |
| Peak memory | 144816 kb |
| Host | smart-dcf6161c-f603-456b-ac9a-b3402c954712 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3166432097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3166432097 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3309554882 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26647136 ps |
| CPU time | 0.44 seconds |
| Started | Apr 15 12:19:31 PM PDT 24 |
| Finished | Apr 15 12:19:32 PM PDT 24 |
| Peak memory | 144540 kb |
| Host | smart-814df404-7f49-42ef-8ba3-889d4625be99 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3309554882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3309554882 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1200801165 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 27951384 ps |
| CPU time | 0.42 seconds |
| Started | Apr 15 12:19:10 PM PDT 24 |
| Finished | Apr 15 12:19:11 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-5582d427-5655-4248-8fa7-d1586c83ef19 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1200801165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1200801165 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.115087405 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 26281239 ps |
| CPU time | 0.47 seconds |
| Started | Apr 15 12:19:10 PM PDT 24 |
| Finished | Apr 15 12:19:12 PM PDT 24 |
| Peak memory | 143468 kb |
| Host | smart-99fd9139-e15b-4bb4-bfbe-7344dd5e4bf6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=115087405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.115087405 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2642788277 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26520563 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:19:09 PM PDT 24 |
| Finished | Apr 15 12:19:10 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-43316b37-a686-47f8-9c90-4aee768fa795 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2642788277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2642788277 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.482262675 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 28253229 ps |
| CPU time | 0.39 seconds |
| Started | Apr 15 12:19:10 PM PDT 24 |
| Finished | Apr 15 12:19:11 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-04adfa4a-8f29-4e1d-afaf-a53fb41db327 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=482262675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.482262675 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.854896914 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28248020 ps |
| CPU time | 0.4 seconds |
| Started | Apr 15 12:18:28 PM PDT 24 |
| Finished | Apr 15 12:18:29 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-27dcf230-af03-4dc0-b37d-62a4c5d1219a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=854896914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.854896914 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2591292157 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 25339083 ps |
| CPU time | 0.42 seconds |
| Started | Apr 15 12:19:10 PM PDT 24 |
| Finished | Apr 15 12:19:11 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-c55fcb55-39e6-4b7b-902b-c1a2110bdca3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2591292157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2591292157 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |