Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/10.prim_async_alert.1725193432
91.80 3.13 100.00 0.00 93.75 0.00 100.00 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/16.prim_sync_alert.612038422
94.25 2.45 100.00 0.00 97.92 4.17 100.00 0.00 85.71 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.954091445
94.85 0.60 100.00 0.00 97.92 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.26134510

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1918825377
/workspace/coverage/default/1.prim_async_alert.2115445682
/workspace/coverage/default/11.prim_async_alert.738884677
/workspace/coverage/default/12.prim_async_alert.1257339443
/workspace/coverage/default/13.prim_async_alert.2766256007
/workspace/coverage/default/14.prim_async_alert.1613240060
/workspace/coverage/default/15.prim_async_alert.2935697647
/workspace/coverage/default/16.prim_async_alert.2977540695
/workspace/coverage/default/17.prim_async_alert.2638979046
/workspace/coverage/default/18.prim_async_alert.2220815139
/workspace/coverage/default/19.prim_async_alert.2723549852
/workspace/coverage/default/2.prim_async_alert.3910763093
/workspace/coverage/default/3.prim_async_alert.891108752
/workspace/coverage/default/4.prim_async_alert.1891553909
/workspace/coverage/default/5.prim_async_alert.1664378433
/workspace/coverage/default/6.prim_async_alert.1438808603
/workspace/coverage/default/7.prim_async_alert.640062789
/workspace/coverage/default/8.prim_async_alert.2301729885
/workspace/coverage/default/9.prim_async_alert.3866721183
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2776293689
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1194911043
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3708724348
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2898324907
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3031342126
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1683124442
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.416693375
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2689092491
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2268043565
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3046617194
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3546607518
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3618073020
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1402520297
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3487581743
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2685069369
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4236921978
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3598478482
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2492032016
/workspace/coverage/sync_alert/0.prim_sync_alert.118309752
/workspace/coverage/sync_alert/1.prim_sync_alert.2421106493
/workspace/coverage/sync_alert/10.prim_sync_alert.2996078823
/workspace/coverage/sync_alert/11.prim_sync_alert.503379367
/workspace/coverage/sync_alert/12.prim_sync_alert.4274390714
/workspace/coverage/sync_alert/13.prim_sync_alert.3407128668
/workspace/coverage/sync_alert/14.prim_sync_alert.3870711162
/workspace/coverage/sync_alert/15.prim_sync_alert.427713261
/workspace/coverage/sync_alert/17.prim_sync_alert.3904969618
/workspace/coverage/sync_alert/18.prim_sync_alert.3973438137
/workspace/coverage/sync_alert/19.prim_sync_alert.1455082471
/workspace/coverage/sync_alert/2.prim_sync_alert.1431580721
/workspace/coverage/sync_alert/3.prim_sync_alert.4016517963
/workspace/coverage/sync_alert/4.prim_sync_alert.3906225384
/workspace/coverage/sync_alert/5.prim_sync_alert.859922121
/workspace/coverage/sync_alert/6.prim_sync_alert.3644492739
/workspace/coverage/sync_alert/7.prim_sync_alert.1272060407
/workspace/coverage/sync_alert/8.prim_sync_alert.4203078553
/workspace/coverage/sync_alert/9.prim_sync_alert.3387732203
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.603432179
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2809999336
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2633978299
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4271246012
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1266682021
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2273152826
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1795197134
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3345199076
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.584180363
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3734912820
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.761326452
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4145774542
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1075470387
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2324794108
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.529796398
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.309570259
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1223687458
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2571299286
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1125723669
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3875914755



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.prim_async_alert.1725193432 Apr 16 01:05:43 PM PDT 24 Apr 16 01:05:45 PM PDT 24 12088600 ps
T2 /workspace/coverage/default/9.prim_async_alert.3866721183 Apr 16 01:05:41 PM PDT 24 Apr 16 01:05:42 PM PDT 24 11020398 ps
T3 /workspace/coverage/default/12.prim_async_alert.1257339443 Apr 16 01:05:49 PM PDT 24 Apr 16 01:05:51 PM PDT 24 11533254 ps
T16 /workspace/coverage/default/4.prim_async_alert.1891553909 Apr 16 01:05:43 PM PDT 24 Apr 16 01:05:45 PM PDT 24 10962701 ps
T9 /workspace/coverage/default/19.prim_async_alert.2723549852 Apr 16 01:05:41 PM PDT 24 Apr 16 01:05:42 PM PDT 24 11813615 ps
T17 /workspace/coverage/default/13.prim_async_alert.2766256007 Apr 16 01:05:45 PM PDT 24 Apr 16 01:05:46 PM PDT 24 10969867 ps
T7 /workspace/coverage/default/1.prim_async_alert.2115445682 Apr 16 01:05:44 PM PDT 24 Apr 16 01:05:46 PM PDT 24 11267648 ps
T12 /workspace/coverage/default/0.prim_async_alert.1918825377 Apr 16 01:05:43 PM PDT 24 Apr 16 01:05:45 PM PDT 24 11427597 ps
T18 /workspace/coverage/default/14.prim_async_alert.1613240060 Apr 16 01:05:44 PM PDT 24 Apr 16 01:05:45 PM PDT 24 11165847 ps
T19 /workspace/coverage/default/11.prim_async_alert.738884677 Apr 16 01:05:49 PM PDT 24 Apr 16 01:05:50 PM PDT 24 11569032 ps
T40 /workspace/coverage/default/18.prim_async_alert.2220815139 Apr 16 01:05:44 PM PDT 24 Apr 16 01:05:46 PM PDT 24 11783110 ps
T14 /workspace/coverage/default/5.prim_async_alert.1664378433 Apr 16 01:05:50 PM PDT 24 Apr 16 01:05:51 PM PDT 24 11179289 ps
T8 /workspace/coverage/default/17.prim_async_alert.2638979046 Apr 16 01:05:46 PM PDT 24 Apr 16 01:05:47 PM PDT 24 11488627 ps
T13 /workspace/coverage/default/3.prim_async_alert.891108752 Apr 16 01:05:42 PM PDT 24 Apr 16 01:05:43 PM PDT 24 10838261 ps
T41 /workspace/coverage/default/8.prim_async_alert.2301729885 Apr 16 01:05:42 PM PDT 24 Apr 16 01:05:43 PM PDT 24 10629013 ps
T20 /workspace/coverage/default/2.prim_async_alert.3910763093 Apr 16 01:05:43 PM PDT 24 Apr 16 01:05:45 PM PDT 24 10945171 ps
T42 /workspace/coverage/default/16.prim_async_alert.2977540695 Apr 16 01:05:44 PM PDT 24 Apr 16 01:05:45 PM PDT 24 10989948 ps
T21 /workspace/coverage/default/7.prim_async_alert.640062789 Apr 16 01:05:42 PM PDT 24 Apr 16 01:05:43 PM PDT 24 11189236 ps
T22 /workspace/coverage/default/6.prim_async_alert.1438808603 Apr 16 01:05:50 PM PDT 24 Apr 16 01:05:51 PM PDT 24 11524879 ps
T43 /workspace/coverage/default/15.prim_async_alert.2935697647 Apr 16 01:05:47 PM PDT 24 Apr 16 01:05:48 PM PDT 24 10772693 ps
T10 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2898324907 Apr 16 01:06:20 PM PDT 24 Apr 16 01:06:22 PM PDT 24 30743012 ps
T34 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1194911043 Apr 16 01:06:24 PM PDT 24 Apr 16 01:06:26 PM PDT 24 31012082 ps
T23 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3598478482 Apr 16 01:06:17 PM PDT 24 Apr 16 01:06:19 PM PDT 24 28904898 ps
T4 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.954091445 Apr 16 01:06:19 PM PDT 24 Apr 16 01:06:21 PM PDT 24 31567952 ps
T35 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2689092491 Apr 16 01:06:29 PM PDT 24 Apr 16 01:06:30 PM PDT 24 29846311 ps
T36 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3487581743 Apr 16 01:06:22 PM PDT 24 Apr 16 01:06:24 PM PDT 24 30937719 ps
T37 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1402520297 Apr 16 01:06:20 PM PDT 24 Apr 16 01:06:22 PM PDT 24 29010018 ps
T11 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2268043565 Apr 16 01:06:17 PM PDT 24 Apr 16 01:06:18 PM PDT 24 31046975 ps
T38 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2776293689 Apr 16 01:06:16 PM PDT 24 Apr 16 01:06:18 PM PDT 24 28660446 ps
T39 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2685069369 Apr 16 01:06:16 PM PDT 24 Apr 16 01:06:17 PM PDT 24 29694123 ps
T5 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.26134510 Apr 16 01:06:18 PM PDT 24 Apr 16 01:06:19 PM PDT 24 30160838 ps
T44 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3708724348 Apr 16 01:06:20 PM PDT 24 Apr 16 01:06:22 PM PDT 24 29970223 ps
T45 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3031342126 Apr 16 01:06:23 PM PDT 24 Apr 16 01:06:24 PM PDT 24 29117263 ps
T46 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3546607518 Apr 16 01:06:20 PM PDT 24 Apr 16 01:06:22 PM PDT 24 32124466 ps
T6 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1683124442 Apr 16 01:06:18 PM PDT 24 Apr 16 01:06:20 PM PDT 24 28677446 ps
T47 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4236921978 Apr 16 01:06:24 PM PDT 24 Apr 16 01:06:26 PM PDT 24 30714084 ps
T48 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3618073020 Apr 16 01:06:21 PM PDT 24 Apr 16 01:06:23 PM PDT 24 29498732 ps
T49 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2492032016 Apr 16 01:06:20 PM PDT 24 Apr 16 01:06:21 PM PDT 24 30677246 ps
T50 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3046617194 Apr 16 01:06:27 PM PDT 24 Apr 16 01:06:29 PM PDT 24 28452401 ps
T51 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.416693375 Apr 16 01:06:24 PM PDT 24 Apr 16 01:06:26 PM PDT 24 30167742 ps
T24 /workspace/coverage/sync_alert/9.prim_sync_alert.3387732203 Apr 16 01:06:21 PM PDT 24 Apr 16 01:06:23 PM PDT 24 9778557 ps
T25 /workspace/coverage/sync_alert/17.prim_sync_alert.3904969618 Apr 16 01:06:23 PM PDT 24 Apr 16 01:06:24 PM PDT 24 9663135 ps
T15 /workspace/coverage/sync_alert/12.prim_sync_alert.4274390714 Apr 16 01:06:29 PM PDT 24 Apr 16 01:06:30 PM PDT 24 9381044 ps
T26 /workspace/coverage/sync_alert/16.prim_sync_alert.612038422 Apr 16 01:06:21 PM PDT 24 Apr 16 01:06:23 PM PDT 24 9075566 ps
T27 /workspace/coverage/sync_alert/14.prim_sync_alert.3870711162 Apr 16 01:06:24 PM PDT 24 Apr 16 01:06:26 PM PDT 24 8235857 ps
T33 /workspace/coverage/sync_alert/18.prim_sync_alert.3973438137 Apr 16 01:06:24 PM PDT 24 Apr 16 01:06:26 PM PDT 24 9742289 ps
T28 /workspace/coverage/sync_alert/0.prim_sync_alert.118309752 Apr 16 01:06:17 PM PDT 24 Apr 16 01:06:18 PM PDT 24 8786056 ps
T29 /workspace/coverage/sync_alert/2.prim_sync_alert.1431580721 Apr 16 01:06:18 PM PDT 24 Apr 16 01:06:19 PM PDT 24 9472580 ps
T30 /workspace/coverage/sync_alert/5.prim_sync_alert.859922121 Apr 16 01:06:19 PM PDT 24 Apr 16 01:06:21 PM PDT 24 8404563 ps
T31 /workspace/coverage/sync_alert/1.prim_sync_alert.2421106493 Apr 16 01:06:20 PM PDT 24 Apr 16 01:06:21 PM PDT 24 8721501 ps
T52 /workspace/coverage/sync_alert/6.prim_sync_alert.3644492739 Apr 16 01:06:22 PM PDT 24 Apr 16 01:06:24 PM PDT 24 8653132 ps
T53 /workspace/coverage/sync_alert/8.prim_sync_alert.4203078553 Apr 16 01:06:22 PM PDT 24 Apr 16 01:06:24 PM PDT 24 8464419 ps
T54 /workspace/coverage/sync_alert/4.prim_sync_alert.3906225384 Apr 16 01:06:30 PM PDT 24 Apr 16 01:06:31 PM PDT 24 8809134 ps
T55 /workspace/coverage/sync_alert/15.prim_sync_alert.427713261 Apr 16 01:06:25 PM PDT 24 Apr 16 01:06:27 PM PDT 24 9373515 ps
T56 /workspace/coverage/sync_alert/3.prim_sync_alert.4016517963 Apr 16 01:06:25 PM PDT 24 Apr 16 01:06:27 PM PDT 24 9795477 ps
T32 /workspace/coverage/sync_alert/19.prim_sync_alert.1455082471 Apr 16 01:06:25 PM PDT 24 Apr 16 01:06:27 PM PDT 24 8690475 ps
T57 /workspace/coverage/sync_alert/13.prim_sync_alert.3407128668 Apr 16 01:06:25 PM PDT 24 Apr 16 01:06:27 PM PDT 24 9964695 ps
T58 /workspace/coverage/sync_alert/11.prim_sync_alert.503379367 Apr 16 01:06:18 PM PDT 24 Apr 16 01:06:20 PM PDT 24 8568692 ps
T59 /workspace/coverage/sync_alert/10.prim_sync_alert.2996078823 Apr 16 01:06:22 PM PDT 24 Apr 16 01:06:24 PM PDT 24 8695867 ps
T60 /workspace/coverage/sync_alert/7.prim_sync_alert.1272060407 Apr 16 01:06:15 PM PDT 24 Apr 16 01:06:16 PM PDT 24 9784581 ps
T61 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2273152826 Apr 16 01:20:35 PM PDT 24 Apr 16 01:20:36 PM PDT 24 27747359 ps
T62 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3875914755 Apr 16 01:20:22 PM PDT 24 Apr 16 01:20:23 PM PDT 24 24786200 ps
T63 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.603432179 Apr 16 01:20:03 PM PDT 24 Apr 16 01:20:04 PM PDT 24 29582375 ps
T64 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4271246012 Apr 16 01:20:36 PM PDT 24 Apr 16 01:20:37 PM PDT 24 25458255 ps
T65 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1125723669 Apr 16 01:20:22 PM PDT 24 Apr 16 01:20:23 PM PDT 24 27141650 ps
T66 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1075470387 Apr 16 01:20:09 PM PDT 24 Apr 16 01:20:10 PM PDT 24 29075965 ps
T67 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.761326452 Apr 16 01:20:37 PM PDT 24 Apr 16 01:20:38 PM PDT 24 28794604 ps
T68 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2809999336 Apr 16 01:20:11 PM PDT 24 Apr 16 01:20:12 PM PDT 24 27958530 ps
T69 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2571299286 Apr 16 01:20:18 PM PDT 24 Apr 16 01:20:19 PM PDT 24 29147376 ps
T70 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4145774542 Apr 16 01:20:37 PM PDT 24 Apr 16 01:20:38 PM PDT 24 27359631 ps
T71 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1266682021 Apr 16 01:20:38 PM PDT 24 Apr 16 01:20:39 PM PDT 24 28047740 ps
T72 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3734912820 Apr 16 01:20:39 PM PDT 24 Apr 16 01:20:40 PM PDT 24 28566066 ps
T73 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.584180363 Apr 16 01:20:37 PM PDT 24 Apr 16 01:20:38 PM PDT 24 27249689 ps
T74 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.309570259 Apr 16 01:20:13 PM PDT 24 Apr 16 01:20:14 PM PDT 24 26773097 ps
T75 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2633978299 Apr 16 01:20:26 PM PDT 24 Apr 16 01:20:27 PM PDT 24 25769223 ps
T76 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3345199076 Apr 16 01:20:37 PM PDT 24 Apr 16 01:20:38 PM PDT 24 26900536 ps
T77 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1223687458 Apr 16 01:20:17 PM PDT 24 Apr 16 01:20:18 PM PDT 24 27790527 ps
T78 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.529796398 Apr 16 01:20:12 PM PDT 24 Apr 16 01:20:13 PM PDT 24 25788834 ps
T79 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2324794108 Apr 16 01:20:12 PM PDT 24 Apr 16 01:20:13 PM PDT 24 27604793 ps
T80 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1795197134 Apr 16 01:20:38 PM PDT 24 Apr 16 01:20:39 PM PDT 24 28809104 ps

Test location /workspace/coverage/default/10.prim_async_alert.1725193432
Short name T1
Test name
Test status
Simulation time 12088600 ps
CPU time 0.39 seconds
Started Apr 16 01:05:43 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 145776 kb
Host smart-13d71462-91e6-4047-a222-6c46f5e6b585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725193432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1725193432
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.612038422
Short name T26
Test name
Test status
Simulation time 9075566 ps
CPU time 0.37 seconds
Started Apr 16 01:06:21 PM PDT 24
Finished Apr 16 01:06:23 PM PDT 24
Peak memory 145072 kb
Host smart-4aa7bc6a-0b8d-47c7-9db5-7b44f90ea96b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=612038422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.612038422
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.954091445
Short name T4
Test name
Test status
Simulation time 31567952 ps
CPU time 0.41 seconds
Started Apr 16 01:06:19 PM PDT 24
Finished Apr 16 01:06:21 PM PDT 24
Peak memory 145924 kb
Host smart-9cbaf0ea-ea86-4e70-b10c-d3a155995863
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=954091445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.954091445
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.26134510
Short name T5
Test name
Test status
Simulation time 30160838 ps
CPU time 0.38 seconds
Started Apr 16 01:06:18 PM PDT 24
Finished Apr 16 01:06:19 PM PDT 24
Peak memory 145832 kb
Host smart-42c8a8fc-c2c6-48f6-9942-ddfdc4615076
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=26134510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.26134510
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1918825377
Short name T12
Test name
Test status
Simulation time 11427597 ps
CPU time 0.39 seconds
Started Apr 16 01:05:43 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 145704 kb
Host smart-3d86d588-76e8-40ed-8cf6-219680e2e0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918825377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1918825377
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2115445682
Short name T7
Test name
Test status
Simulation time 11267648 ps
CPU time 0.4 seconds
Started Apr 16 01:05:44 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 145772 kb
Host smart-4c6ed848-227b-4f1a-976a-ce56f1571f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115445682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2115445682
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.738884677
Short name T19
Test name
Test status
Simulation time 11569032 ps
CPU time 0.39 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:05:50 PM PDT 24
Peak memory 145736 kb
Host smart-3b28cfd9-4ec2-4616-b181-5d55a0dc3e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738884677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.738884677
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1257339443
Short name T3
Test name
Test status
Simulation time 11533254 ps
CPU time 0.38 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:05:51 PM PDT 24
Peak memory 145752 kb
Host smart-fd737522-af19-49ed-944a-930657006511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257339443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1257339443
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2766256007
Short name T17
Test name
Test status
Simulation time 10969867 ps
CPU time 0.39 seconds
Started Apr 16 01:05:45 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 145796 kb
Host smart-a39fdc50-06d1-4a41-bdb0-6ac44865f040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766256007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2766256007
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1613240060
Short name T18
Test name
Test status
Simulation time 11165847 ps
CPU time 0.38 seconds
Started Apr 16 01:05:44 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 145808 kb
Host smart-ff9fbc06-09af-43d3-af8e-eddf59f38ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613240060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1613240060
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.2935697647
Short name T43
Test name
Test status
Simulation time 10772693 ps
CPU time 0.39 seconds
Started Apr 16 01:05:47 PM PDT 24
Finished Apr 16 01:05:48 PM PDT 24
Peak memory 145740 kb
Host smart-effd422a-400e-46cd-9b1a-1e32bb446b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935697647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2935697647
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2977540695
Short name T42
Test name
Test status
Simulation time 10989948 ps
CPU time 0.39 seconds
Started Apr 16 01:05:44 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 145768 kb
Host smart-aa6c76d6-3c6f-40f9-9480-e478fe4082d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977540695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2977540695
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2638979046
Short name T8
Test name
Test status
Simulation time 11488627 ps
CPU time 0.39 seconds
Started Apr 16 01:05:46 PM PDT 24
Finished Apr 16 01:05:47 PM PDT 24
Peak memory 145872 kb
Host smart-27cb4db7-c929-44fc-be1e-678fd268bdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638979046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2638979046
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2220815139
Short name T40
Test name
Test status
Simulation time 11783110 ps
CPU time 0.37 seconds
Started Apr 16 01:05:44 PM PDT 24
Finished Apr 16 01:05:46 PM PDT 24
Peak memory 145796 kb
Host smart-e7619ebb-0fc9-477f-a7fc-32ce6efbc496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220815139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2220815139
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2723549852
Short name T9
Test name
Test status
Simulation time 11813615 ps
CPU time 0.4 seconds
Started Apr 16 01:05:41 PM PDT 24
Finished Apr 16 01:05:42 PM PDT 24
Peak memory 145764 kb
Host smart-67973d1f-5a9c-4b8d-948c-a76e0ac9b3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723549852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2723549852
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3910763093
Short name T20
Test name
Test status
Simulation time 10945171 ps
CPU time 0.38 seconds
Started Apr 16 01:05:43 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 145800 kb
Host smart-68b64cc3-429d-4324-acc0-5c47080c9b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910763093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3910763093
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.891108752
Short name T13
Test name
Test status
Simulation time 10838261 ps
CPU time 0.37 seconds
Started Apr 16 01:05:42 PM PDT 24
Finished Apr 16 01:05:43 PM PDT 24
Peak memory 145740 kb
Host smart-71624308-231e-41fe-9243-14c2015d4733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891108752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.891108752
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1891553909
Short name T16
Test name
Test status
Simulation time 10962701 ps
CPU time 0.38 seconds
Started Apr 16 01:05:43 PM PDT 24
Finished Apr 16 01:05:45 PM PDT 24
Peak memory 145772 kb
Host smart-d87c4649-7463-487e-a724-19f6ef15af7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891553909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1891553909
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1664378433
Short name T14
Test name
Test status
Simulation time 11179289 ps
CPU time 0.37 seconds
Started Apr 16 01:05:50 PM PDT 24
Finished Apr 16 01:05:51 PM PDT 24
Peak memory 145760 kb
Host smart-5650b777-42aa-489e-a22e-eeda2d1ce60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664378433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1664378433
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1438808603
Short name T22
Test name
Test status
Simulation time 11524879 ps
CPU time 0.4 seconds
Started Apr 16 01:05:50 PM PDT 24
Finished Apr 16 01:05:51 PM PDT 24
Peak memory 145736 kb
Host smart-4eb5593c-7e16-493f-88ab-c6393bd6d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438808603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1438808603
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.640062789
Short name T21
Test name
Test status
Simulation time 11189236 ps
CPU time 0.39 seconds
Started Apr 16 01:05:42 PM PDT 24
Finished Apr 16 01:05:43 PM PDT 24
Peak memory 145800 kb
Host smart-568851ce-5a77-4fe8-b895-915435ffb5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640062789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.640062789
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2301729885
Short name T41
Test name
Test status
Simulation time 10629013 ps
CPU time 0.38 seconds
Started Apr 16 01:05:42 PM PDT 24
Finished Apr 16 01:05:43 PM PDT 24
Peak memory 145776 kb
Host smart-95349cf6-dfc1-4541-9302-18eea5e1e630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301729885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2301729885
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3866721183
Short name T2
Test name
Test status
Simulation time 11020398 ps
CPU time 0.4 seconds
Started Apr 16 01:05:41 PM PDT 24
Finished Apr 16 01:05:42 PM PDT 24
Peak memory 145796 kb
Host smart-3382e9c1-783e-4ab2-bfb2-023023b7bece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866721183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3866721183
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2776293689
Short name T38
Test name
Test status
Simulation time 28660446 ps
CPU time 0.4 seconds
Started Apr 16 01:06:16 PM PDT 24
Finished Apr 16 01:06:18 PM PDT 24
Peak memory 145780 kb
Host smart-021418b9-b546-4c3f-9a40-7f9157357416
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2776293689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2776293689
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1194911043
Short name T34
Test name
Test status
Simulation time 31012082 ps
CPU time 0.41 seconds
Started Apr 16 01:06:24 PM PDT 24
Finished Apr 16 01:06:26 PM PDT 24
Peak memory 145712 kb
Host smart-51f0db57-bb5f-4511-8a0a-c50d29cbfb1a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1194911043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1194911043
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3708724348
Short name T44
Test name
Test status
Simulation time 29970223 ps
CPU time 0.41 seconds
Started Apr 16 01:06:20 PM PDT 24
Finished Apr 16 01:06:22 PM PDT 24
Peak memory 145828 kb
Host smart-b2539425-42a2-42d7-93da-4f8d3978cf13
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3708724348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3708724348
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2898324907
Short name T10
Test name
Test status
Simulation time 30743012 ps
CPU time 0.41 seconds
Started Apr 16 01:06:20 PM PDT 24
Finished Apr 16 01:06:22 PM PDT 24
Peak memory 145828 kb
Host smart-17020c6e-fe99-46b2-a069-5e1c6aa1a632
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2898324907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2898324907
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3031342126
Short name T45
Test name
Test status
Simulation time 29117263 ps
CPU time 0.4 seconds
Started Apr 16 01:06:23 PM PDT 24
Finished Apr 16 01:06:24 PM PDT 24
Peak memory 145808 kb
Host smart-80cf99e2-b33e-4e6d-9a9d-cf1a119ed7a6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3031342126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3031342126
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1683124442
Short name T6
Test name
Test status
Simulation time 28677446 ps
CPU time 0.39 seconds
Started Apr 16 01:06:18 PM PDT 24
Finished Apr 16 01:06:20 PM PDT 24
Peak memory 145804 kb
Host smart-342f86b2-7b73-4dc2-acff-85c2dbc6bea8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1683124442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1683124442
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.416693375
Short name T51
Test name
Test status
Simulation time 30167742 ps
CPU time 0.41 seconds
Started Apr 16 01:06:24 PM PDT 24
Finished Apr 16 01:06:26 PM PDT 24
Peak memory 145776 kb
Host smart-f50bbc03-e816-4c91-a969-28ec669d61d4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=416693375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.416693375
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2689092491
Short name T35
Test name
Test status
Simulation time 29846311 ps
CPU time 0.44 seconds
Started Apr 16 01:06:29 PM PDT 24
Finished Apr 16 01:06:30 PM PDT 24
Peak memory 145800 kb
Host smart-b85a50b7-f671-4643-80c2-dad359771e58
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2689092491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2689092491
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2268043565
Short name T11
Test name
Test status
Simulation time 31046975 ps
CPU time 0.38 seconds
Started Apr 16 01:06:17 PM PDT 24
Finished Apr 16 01:06:18 PM PDT 24
Peak memory 145796 kb
Host smart-b2a7175f-821f-4604-9b55-c5656852cfe5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2268043565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2268043565
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3046617194
Short name T50
Test name
Test status
Simulation time 28452401 ps
CPU time 0.4 seconds
Started Apr 16 01:06:27 PM PDT 24
Finished Apr 16 01:06:29 PM PDT 24
Peak memory 145680 kb
Host smart-be65a70e-9bb0-4443-983e-690df2601f07
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3046617194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3046617194
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3546607518
Short name T46
Test name
Test status
Simulation time 32124466 ps
CPU time 0.4 seconds
Started Apr 16 01:06:20 PM PDT 24
Finished Apr 16 01:06:22 PM PDT 24
Peak memory 145796 kb
Host smart-9916ec8b-4748-4b17-b229-26fb25959671
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3546607518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3546607518
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3618073020
Short name T48
Test name
Test status
Simulation time 29498732 ps
CPU time 0.43 seconds
Started Apr 16 01:06:21 PM PDT 24
Finished Apr 16 01:06:23 PM PDT 24
Peak memory 145712 kb
Host smart-5757e22f-8feb-4b55-9fc2-432784e89909
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3618073020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3618073020
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1402520297
Short name T37
Test name
Test status
Simulation time 29010018 ps
CPU time 0.44 seconds
Started Apr 16 01:06:20 PM PDT 24
Finished Apr 16 01:06:22 PM PDT 24
Peak memory 145816 kb
Host smart-5047b425-93ba-4deb-91b8-33db019bd1c8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1402520297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1402520297
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3487581743
Short name T36
Test name
Test status
Simulation time 30937719 ps
CPU time 0.43 seconds
Started Apr 16 01:06:22 PM PDT 24
Finished Apr 16 01:06:24 PM PDT 24
Peak memory 145800 kb
Host smart-3d564910-1b3a-4ac2-9353-57203f77377c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3487581743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3487581743
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2685069369
Short name T39
Test name
Test status
Simulation time 29694123 ps
CPU time 0.4 seconds
Started Apr 16 01:06:16 PM PDT 24
Finished Apr 16 01:06:17 PM PDT 24
Peak memory 145828 kb
Host smart-73af082d-8aa2-4cd0-9685-f21816d02a08
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2685069369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2685069369
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4236921978
Short name T47
Test name
Test status
Simulation time 30714084 ps
CPU time 0.41 seconds
Started Apr 16 01:06:24 PM PDT 24
Finished Apr 16 01:06:26 PM PDT 24
Peak memory 145724 kb
Host smart-42324e33-1bf7-47b2-8ac3-43118654fac8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4236921978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.4236921978
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3598478482
Short name T23
Test name
Test status
Simulation time 28904898 ps
CPU time 0.39 seconds
Started Apr 16 01:06:17 PM PDT 24
Finished Apr 16 01:06:19 PM PDT 24
Peak memory 145804 kb
Host smart-a7564c2a-da79-45cc-85ca-ee4da735389c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3598478482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3598478482
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2492032016
Short name T49
Test name
Test status
Simulation time 30677246 ps
CPU time 0.42 seconds
Started Apr 16 01:06:20 PM PDT 24
Finished Apr 16 01:06:21 PM PDT 24
Peak memory 145756 kb
Host smart-2a5a114e-7929-4c75-982c-84200671e906
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2492032016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2492032016
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.118309752
Short name T28
Test name
Test status
Simulation time 8786056 ps
CPU time 0.44 seconds
Started Apr 16 01:06:17 PM PDT 24
Finished Apr 16 01:06:18 PM PDT 24
Peak memory 145044 kb
Host smart-84c2f85e-ca2a-41e4-8e51-02570e13dc58
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=118309752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.118309752
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2421106493
Short name T31
Test name
Test status
Simulation time 8721501 ps
CPU time 0.38 seconds
Started Apr 16 01:06:20 PM PDT 24
Finished Apr 16 01:06:21 PM PDT 24
Peak memory 145040 kb
Host smart-0534881f-143b-4ebb-a04f-6eca549c1ec7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2421106493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2421106493
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2996078823
Short name T59
Test name
Test status
Simulation time 8695867 ps
CPU time 0.38 seconds
Started Apr 16 01:06:22 PM PDT 24
Finished Apr 16 01:06:24 PM PDT 24
Peak memory 145024 kb
Host smart-900b2b19-c1ed-496d-a351-dbdd41f9f516
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2996078823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2996078823
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.503379367
Short name T58
Test name
Test status
Simulation time 8568692 ps
CPU time 0.38 seconds
Started Apr 16 01:06:18 PM PDT 24
Finished Apr 16 01:06:20 PM PDT 24
Peak memory 145048 kb
Host smart-eb123196-9409-4538-b4d4-08690ea066e9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=503379367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.503379367
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.4274390714
Short name T15
Test name
Test status
Simulation time 9381044 ps
CPU time 0.41 seconds
Started Apr 16 01:06:29 PM PDT 24
Finished Apr 16 01:06:30 PM PDT 24
Peak memory 145084 kb
Host smart-4d29d1de-a089-4f5d-81ba-f72a6bf099c8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4274390714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.4274390714
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3407128668
Short name T57
Test name
Test status
Simulation time 9964695 ps
CPU time 0.39 seconds
Started Apr 16 01:06:25 PM PDT 24
Finished Apr 16 01:06:27 PM PDT 24
Peak memory 145996 kb
Host smart-01768df6-87f8-4a13-a811-3219604fe7e6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3407128668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3407128668
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3870711162
Short name T27
Test name
Test status
Simulation time 8235857 ps
CPU time 0.44 seconds
Started Apr 16 01:06:24 PM PDT 24
Finished Apr 16 01:06:26 PM PDT 24
Peak memory 145040 kb
Host smart-9000558e-bf1a-48cf-a5bb-f9348425055f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3870711162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3870711162
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.427713261
Short name T55
Test name
Test status
Simulation time 9373515 ps
CPU time 0.39 seconds
Started Apr 16 01:06:25 PM PDT 24
Finished Apr 16 01:06:27 PM PDT 24
Peak memory 145084 kb
Host smart-f369eea9-febc-4397-a717-4ca03000bff4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=427713261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.427713261
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3904969618
Short name T25
Test name
Test status
Simulation time 9663135 ps
CPU time 0.38 seconds
Started Apr 16 01:06:23 PM PDT 24
Finished Apr 16 01:06:24 PM PDT 24
Peak memory 145084 kb
Host smart-9e9e8829-c5be-4516-8dae-5a7828f6480b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3904969618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3904969618
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3973438137
Short name T33
Test name
Test status
Simulation time 9742289 ps
CPU time 0.4 seconds
Started Apr 16 01:06:24 PM PDT 24
Finished Apr 16 01:06:26 PM PDT 24
Peak memory 145020 kb
Host smart-2cc019bb-82fb-4f65-affa-22401cedd1b1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3973438137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3973438137
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1455082471
Short name T32
Test name
Test status
Simulation time 8690475 ps
CPU time 0.39 seconds
Started Apr 16 01:06:25 PM PDT 24
Finished Apr 16 01:06:27 PM PDT 24
Peak memory 144940 kb
Host smart-7794be80-94f8-4762-9582-e4eb238e5a2a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1455082471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1455082471
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1431580721
Short name T29
Test name
Test status
Simulation time 9472580 ps
CPU time 0.38 seconds
Started Apr 16 01:06:18 PM PDT 24
Finished Apr 16 01:06:19 PM PDT 24
Peak memory 145068 kb
Host smart-87502464-1e79-4c54-8022-7e2bc04f72f1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1431580721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1431580721
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.4016517963
Short name T56
Test name
Test status
Simulation time 9795477 ps
CPU time 0.39 seconds
Started Apr 16 01:06:25 PM PDT 24
Finished Apr 16 01:06:27 PM PDT 24
Peak memory 145740 kb
Host smart-da584ea2-41de-42f7-abc0-08f7fdf16832
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4016517963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.4016517963
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3906225384
Short name T54
Test name
Test status
Simulation time 8809134 ps
CPU time 0.47 seconds
Started Apr 16 01:06:30 PM PDT 24
Finished Apr 16 01:06:31 PM PDT 24
Peak memory 144908 kb
Host smart-5b698b85-3ad2-41d4-8ba7-a7ef6bbf8c01
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3906225384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3906225384
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.859922121
Short name T30
Test name
Test status
Simulation time 8404563 ps
CPU time 0.4 seconds
Started Apr 16 01:06:19 PM PDT 24
Finished Apr 16 01:06:21 PM PDT 24
Peak memory 145084 kb
Host smart-bdc070ca-b399-4e07-b3c5-16a9302bbfd4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=859922121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.859922121
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3644492739
Short name T52
Test name
Test status
Simulation time 8653132 ps
CPU time 0.39 seconds
Started Apr 16 01:06:22 PM PDT 24
Finished Apr 16 01:06:24 PM PDT 24
Peak memory 144984 kb
Host smart-b240605b-0aca-4dd7-ad85-842362ec30c4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3644492739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3644492739
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1272060407
Short name T60
Test name
Test status
Simulation time 9784581 ps
CPU time 0.37 seconds
Started Apr 16 01:06:15 PM PDT 24
Finished Apr 16 01:06:16 PM PDT 24
Peak memory 145072 kb
Host smart-3a4bdc8f-cd9b-46ad-869a-b4e6b0dc7998
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1272060407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1272060407
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.4203078553
Short name T53
Test name
Test status
Simulation time 8464419 ps
CPU time 0.39 seconds
Started Apr 16 01:06:22 PM PDT 24
Finished Apr 16 01:06:24 PM PDT 24
Peak memory 145084 kb
Host smart-e8c6ae12-2441-4b1d-8993-38c10f96bc1a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4203078553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.4203078553
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3387732203
Short name T24
Test name
Test status
Simulation time 9778557 ps
CPU time 0.38 seconds
Started Apr 16 01:06:21 PM PDT 24
Finished Apr 16 01:06:23 PM PDT 24
Peak memory 145040 kb
Host smart-185dbcbc-c16b-4a20-a8e4-dd531de3169f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3387732203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3387732203
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.603432179
Short name T63
Test name
Test status
Simulation time 29582375 ps
CPU time 0.39 seconds
Started Apr 16 01:20:03 PM PDT 24
Finished Apr 16 01:20:04 PM PDT 24
Peak memory 145048 kb
Host smart-fe96b65b-60b8-4c1a-8e75-4bcfd5f50c66
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=603432179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.603432179
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2809999336
Short name T68
Test name
Test status
Simulation time 27958530 ps
CPU time 0.39 seconds
Started Apr 16 01:20:11 PM PDT 24
Finished Apr 16 01:20:12 PM PDT 24
Peak memory 145000 kb
Host smart-05746492-cce5-4df8-a954-5459ec0a8eb4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2809999336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2809999336
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2633978299
Short name T75
Test name
Test status
Simulation time 25769223 ps
CPU time 0.37 seconds
Started Apr 16 01:20:26 PM PDT 24
Finished Apr 16 01:20:27 PM PDT 24
Peak memory 145064 kb
Host smart-4c7395d8-e70d-46c4-abb9-c683eed4e466
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2633978299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2633978299
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4271246012
Short name T64
Test name
Test status
Simulation time 25458255 ps
CPU time 0.38 seconds
Started Apr 16 01:20:36 PM PDT 24
Finished Apr 16 01:20:37 PM PDT 24
Peak memory 145064 kb
Host smart-b41ec4b4-60cf-49a0-9edd-e2edba06a92e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4271246012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4271246012
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1266682021
Short name T71
Test name
Test status
Simulation time 28047740 ps
CPU time 0.4 seconds
Started Apr 16 01:20:38 PM PDT 24
Finished Apr 16 01:20:39 PM PDT 24
Peak memory 145060 kb
Host smart-0ab0d402-daaf-40b5-9d87-04f41cc89b1c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1266682021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1266682021
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2273152826
Short name T61
Test name
Test status
Simulation time 27747359 ps
CPU time 0.38 seconds
Started Apr 16 01:20:35 PM PDT 24
Finished Apr 16 01:20:36 PM PDT 24
Peak memory 145076 kb
Host smart-8184f8ce-a490-49f1-8115-dd3ebf8d19c0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2273152826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2273152826
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1795197134
Short name T80
Test name
Test status
Simulation time 28809104 ps
CPU time 0.38 seconds
Started Apr 16 01:20:38 PM PDT 24
Finished Apr 16 01:20:39 PM PDT 24
Peak memory 145056 kb
Host smart-88740c6d-fa7d-4c8b-81be-889002c32c7e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1795197134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1795197134
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3345199076
Short name T76
Test name
Test status
Simulation time 26900536 ps
CPU time 0.39 seconds
Started Apr 16 01:20:37 PM PDT 24
Finished Apr 16 01:20:38 PM PDT 24
Peak memory 145080 kb
Host smart-a3016cf0-b5cf-477f-8782-579c9ed36fa6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3345199076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3345199076
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.584180363
Short name T73
Test name
Test status
Simulation time 27249689 ps
CPU time 0.38 seconds
Started Apr 16 01:20:37 PM PDT 24
Finished Apr 16 01:20:38 PM PDT 24
Peak memory 145016 kb
Host smart-7aa54a1a-a3e0-4928-8016-99e9c772102f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=584180363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.584180363
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3734912820
Short name T72
Test name
Test status
Simulation time 28566066 ps
CPU time 0.39 seconds
Started Apr 16 01:20:39 PM PDT 24
Finished Apr 16 01:20:40 PM PDT 24
Peak memory 144948 kb
Host smart-8666ef03-41e1-4194-8a93-42824a847a27
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3734912820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3734912820
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.761326452
Short name T67
Test name
Test status
Simulation time 28794604 ps
CPU time 0.38 seconds
Started Apr 16 01:20:37 PM PDT 24
Finished Apr 16 01:20:38 PM PDT 24
Peak memory 145040 kb
Host smart-9bce7024-c31e-4d3c-b82e-c8c167a85aa3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=761326452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.761326452
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4145774542
Short name T70
Test name
Test status
Simulation time 27359631 ps
CPU time 0.39 seconds
Started Apr 16 01:20:37 PM PDT 24
Finished Apr 16 01:20:38 PM PDT 24
Peak memory 145064 kb
Host smart-1be508ad-a53c-4fe4-983f-79233bd05a58
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4145774542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4145774542
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1075470387
Short name T66
Test name
Test status
Simulation time 29075965 ps
CPU time 0.4 seconds
Started Apr 16 01:20:09 PM PDT 24
Finished Apr 16 01:20:10 PM PDT 24
Peak memory 145012 kb
Host smart-b0f484f6-7684-480b-93ca-17b09e3ec145
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1075470387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1075470387
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2324794108
Short name T79
Test name
Test status
Simulation time 27604793 ps
CPU time 0.39 seconds
Started Apr 16 01:20:12 PM PDT 24
Finished Apr 16 01:20:13 PM PDT 24
Peak memory 145040 kb
Host smart-f653671d-9691-435c-93a1-6e47ece38042
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2324794108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2324794108
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.529796398
Short name T78
Test name
Test status
Simulation time 25788834 ps
CPU time 0.39 seconds
Started Apr 16 01:20:12 PM PDT 24
Finished Apr 16 01:20:13 PM PDT 24
Peak memory 145104 kb
Host smart-d4fe71c1-0f38-4577-a893-13bb0a07aac1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=529796398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.529796398
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.309570259
Short name T74
Test name
Test status
Simulation time 26773097 ps
CPU time 0.38 seconds
Started Apr 16 01:20:13 PM PDT 24
Finished Apr 16 01:20:14 PM PDT 24
Peak memory 145040 kb
Host smart-b75d7240-251f-4a5a-ad00-30ca635534b6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=309570259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.309570259
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1223687458
Short name T77
Test name
Test status
Simulation time 27790527 ps
CPU time 0.38 seconds
Started Apr 16 01:20:17 PM PDT 24
Finished Apr 16 01:20:18 PM PDT 24
Peak memory 145072 kb
Host smart-333b8ca9-c044-4ce3-9cfa-b2ea09f10f24
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1223687458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1223687458
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2571299286
Short name T69
Test name
Test status
Simulation time 29147376 ps
CPU time 0.39 seconds
Started Apr 16 01:20:18 PM PDT 24
Finished Apr 16 01:20:19 PM PDT 24
Peak memory 145012 kb
Host smart-2e01a258-2e91-48d4-a1aa-ee45b3bf0eec
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2571299286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2571299286
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1125723669
Short name T65
Test name
Test status
Simulation time 27141650 ps
CPU time 0.38 seconds
Started Apr 16 01:20:22 PM PDT 24
Finished Apr 16 01:20:23 PM PDT 24
Peak memory 145024 kb
Host smart-c68ce36d-d39e-4ae3-baef-19f89ff0e04f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1125723669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1125723669
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3875914755
Short name T62
Test name
Test status
Simulation time 24786200 ps
CPU time 0.38 seconds
Started Apr 16 01:20:22 PM PDT 24
Finished Apr 16 01:20:23 PM PDT 24
Peak memory 145060 kb
Host smart-40dfce28-ed89-4d01-92a2-300ef895d6c8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3875914755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3875914755
Directory /workspace/9.prim_sync_fatal_alert/latest
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