Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.02 89.02 100.00 100.00 95.83 95.83 96.43 96.43 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/15.prim_async_alert.3869281716
92.15 3.13 100.00 0.00 95.83 0.00 96.43 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/16.prim_sync_alert.1028263379
93.90 1.76 100.00 0.00 95.83 0.00 100.00 3.57 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3871045160
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/7.prim_async_alert.2977085547
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2664084735
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/13.prim_sync_alert.3371021081

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2089849192
/workspace/coverage/default/1.prim_async_alert.1428551308
/workspace/coverage/default/10.prim_async_alert.2687118539
/workspace/coverage/default/11.prim_async_alert.976297637
/workspace/coverage/default/12.prim_async_alert.1685965891
/workspace/coverage/default/13.prim_async_alert.3793181321
/workspace/coverage/default/14.prim_async_alert.1524096919
/workspace/coverage/default/16.prim_async_alert.1871336943
/workspace/coverage/default/17.prim_async_alert.2861844061
/workspace/coverage/default/18.prim_async_alert.175820388
/workspace/coverage/default/19.prim_async_alert.4064199703
/workspace/coverage/default/2.prim_async_alert.140427984
/workspace/coverage/default/3.prim_async_alert.269794300
/workspace/coverage/default/4.prim_async_alert.1294103003
/workspace/coverage/default/5.prim_async_alert.3796546597
/workspace/coverage/default/6.prim_async_alert.2809904407
/workspace/coverage/default/8.prim_async_alert.2180453816
/workspace/coverage/default/9.prim_async_alert.2469711795
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2652429956
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2513017488
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2073747603
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1947574612
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.185473042
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3388943130
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2359480143
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4051003260
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3554521307
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.467377009
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.709119534
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2980636629
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2313698449
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3468798082
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.946085293
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3343359470
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2144920016
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2122664078
/workspace/coverage/sync_alert/0.prim_sync_alert.434485646
/workspace/coverage/sync_alert/1.prim_sync_alert.836400769
/workspace/coverage/sync_alert/10.prim_sync_alert.1641613762
/workspace/coverage/sync_alert/11.prim_sync_alert.1676808055
/workspace/coverage/sync_alert/12.prim_sync_alert.2369431683
/workspace/coverage/sync_alert/14.prim_sync_alert.156362854
/workspace/coverage/sync_alert/15.prim_sync_alert.3513726448
/workspace/coverage/sync_alert/17.prim_sync_alert.3426514521
/workspace/coverage/sync_alert/18.prim_sync_alert.3061260966
/workspace/coverage/sync_alert/19.prim_sync_alert.2722731596
/workspace/coverage/sync_alert/2.prim_sync_alert.4086294646
/workspace/coverage/sync_alert/3.prim_sync_alert.378898787
/workspace/coverage/sync_alert/4.prim_sync_alert.980549996
/workspace/coverage/sync_alert/5.prim_sync_alert.1412077226
/workspace/coverage/sync_alert/6.prim_sync_alert.3216801936
/workspace/coverage/sync_alert/7.prim_sync_alert.377246410
/workspace/coverage/sync_alert/8.prim_sync_alert.142868837
/workspace/coverage/sync_alert/9.prim_sync_alert.3079667739
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4105758691
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2697298629
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2907058441
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.676203221
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1945559452
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1251134908
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.432375837
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2400067811
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2372899439
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3114226836
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.392920581
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3356673422
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1847197683
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1795387637
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1086090860
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4292625750
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3477768103
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1027608375
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2342746441
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1578515148



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/11.prim_async_alert.976297637 Apr 18 12:17:56 PM PDT 24 Apr 18 12:17:57 PM PDT 24 10919800 ps
T2 /workspace/coverage/default/2.prim_async_alert.140427984 Apr 18 12:22:44 PM PDT 24 Apr 18 12:22:45 PM PDT 24 10768177 ps
T3 /workspace/coverage/default/13.prim_async_alert.3793181321 Apr 18 12:22:13 PM PDT 24 Apr 18 12:22:14 PM PDT 24 10949466 ps
T10 /workspace/coverage/default/5.prim_async_alert.3796546597 Apr 18 12:22:59 PM PDT 24 Apr 18 12:23:00 PM PDT 24 11427475 ps
T7 /workspace/coverage/default/8.prim_async_alert.2180453816 Apr 18 12:17:53 PM PDT 24 Apr 18 12:17:54 PM PDT 24 10756693 ps
T8 /workspace/coverage/default/6.prim_async_alert.2809904407 Apr 18 12:23:07 PM PDT 24 Apr 18 12:23:08 PM PDT 24 11232536 ps
T9 /workspace/coverage/default/15.prim_async_alert.3869281716 Apr 18 12:17:54 PM PDT 24 Apr 18 12:17:55 PM PDT 24 11283946 ps
T20 /workspace/coverage/default/12.prim_async_alert.1685965891 Apr 18 12:17:53 PM PDT 24 Apr 18 12:17:54 PM PDT 24 11017188 ps
T21 /workspace/coverage/default/14.prim_async_alert.1524096919 Apr 18 12:19:26 PM PDT 24 Apr 18 12:19:27 PM PDT 24 10915757 ps
T12 /workspace/coverage/default/19.prim_async_alert.4064199703 Apr 18 12:23:37 PM PDT 24 Apr 18 12:23:38 PM PDT 24 11600814 ps
T22 /workspace/coverage/default/9.prim_async_alert.2469711795 Apr 18 12:23:00 PM PDT 24 Apr 18 12:23:01 PM PDT 24 11330970 ps
T23 /workspace/coverage/default/16.prim_async_alert.1871336943 Apr 18 12:22:33 PM PDT 24 Apr 18 12:22:35 PM PDT 24 11022441 ps
T19 /workspace/coverage/default/3.prim_async_alert.269794300 Apr 18 12:19:28 PM PDT 24 Apr 18 12:19:29 PM PDT 24 11079451 ps
T49 /workspace/coverage/default/1.prim_async_alert.1428551308 Apr 18 12:22:42 PM PDT 24 Apr 18 12:22:43 PM PDT 24 11815212 ps
T17 /workspace/coverage/default/18.prim_async_alert.175820388 Apr 18 12:21:48 PM PDT 24 Apr 18 12:21:49 PM PDT 24 11810815 ps
T13 /workspace/coverage/default/7.prim_async_alert.2977085547 Apr 18 12:17:56 PM PDT 24 Apr 18 12:17:58 PM PDT 24 11691460 ps
T50 /workspace/coverage/default/4.prim_async_alert.1294103003 Apr 18 12:18:49 PM PDT 24 Apr 18 12:18:49 PM PDT 24 10220670 ps
T24 /workspace/coverage/default/10.prim_async_alert.2687118539 Apr 18 12:17:54 PM PDT 24 Apr 18 12:17:55 PM PDT 24 10782581 ps
T51 /workspace/coverage/default/0.prim_async_alert.2089849192 Apr 18 12:20:51 PM PDT 24 Apr 18 12:20:52 PM PDT 24 11043566 ps
T52 /workspace/coverage/default/17.prim_async_alert.2861844061 Apr 18 12:18:04 PM PDT 24 Apr 18 12:18:06 PM PDT 24 11035865 ps
T14 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1947574612 Apr 18 01:12:36 PM PDT 24 Apr 18 01:12:38 PM PDT 24 30286584 ps
T40 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2144920016 Apr 18 01:12:35 PM PDT 24 Apr 18 01:12:37 PM PDT 24 29608777 ps
T41 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2359480143 Apr 18 01:12:36 PM PDT 24 Apr 18 01:12:37 PM PDT 24 30760396 ps
T42 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4051003260 Apr 18 01:12:36 PM PDT 24 Apr 18 01:12:37 PM PDT 24 29315461 ps
T43 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3871045160 Apr 18 01:12:39 PM PDT 24 Apr 18 01:12:40 PM PDT 24 30117622 ps
T44 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2980636629 Apr 18 01:12:35 PM PDT 24 Apr 18 01:12:36 PM PDT 24 31908683 ps
T45 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2073747603 Apr 18 01:12:36 PM PDT 24 Apr 18 01:12:38 PM PDT 24 31041804 ps
T46 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2122664078 Apr 18 01:12:37 PM PDT 24 Apr 18 01:12:39 PM PDT 24 28663081 ps
T47 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3343359470 Apr 18 01:12:36 PM PDT 24 Apr 18 01:12:38 PM PDT 24 32221642 ps
T48 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3388943130 Apr 18 01:12:35 PM PDT 24 Apr 18 01:12:37 PM PDT 24 30855063 ps
T53 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.946085293 Apr 18 01:12:36 PM PDT 24 Apr 18 01:12:37 PM PDT 24 32619023 ps
T39 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2652429956 Apr 18 01:12:29 PM PDT 24 Apr 18 01:12:30 PM PDT 24 30218198 ps
T15 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.709119534 Apr 18 01:12:37 PM PDT 24 Apr 18 01:12:39 PM PDT 24 31552690 ps
T54 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3554521307 Apr 18 01:12:38 PM PDT 24 Apr 18 01:12:39 PM PDT 24 29221509 ps
T18 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.467377009 Apr 18 01:13:14 PM PDT 24 Apr 18 01:13:15 PM PDT 24 29106524 ps
T55 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2313698449 Apr 18 01:12:37 PM PDT 24 Apr 18 01:12:39 PM PDT 24 30751307 ps
T56 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.185473042 Apr 18 01:12:38 PM PDT 24 Apr 18 01:12:39 PM PDT 24 32616028 ps
T4 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2664084735 Apr 18 01:12:35 PM PDT 24 Apr 18 01:12:36 PM PDT 24 31513888 ps
T57 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2513017488 Apr 18 01:12:36 PM PDT 24 Apr 18 01:12:38 PM PDT 24 30769122 ps
T58 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3468798082 Apr 18 01:12:37 PM PDT 24 Apr 18 01:12:38 PM PDT 24 28895961 ps
T25 /workspace/coverage/sync_alert/6.prim_sync_alert.3216801936 Apr 18 01:12:42 PM PDT 24 Apr 18 01:12:43 PM PDT 24 9943241 ps
T26 /workspace/coverage/sync_alert/17.prim_sync_alert.3426514521 Apr 18 01:12:47 PM PDT 24 Apr 18 01:12:48 PM PDT 24 10553443 ps
T27 /workspace/coverage/sync_alert/14.prim_sync_alert.156362854 Apr 18 01:12:47 PM PDT 24 Apr 18 01:12:48 PM PDT 24 9482086 ps
T35 /workspace/coverage/sync_alert/4.prim_sync_alert.980549996 Apr 18 01:12:47 PM PDT 24 Apr 18 01:12:48 PM PDT 24 9627467 ps
T36 /workspace/coverage/sync_alert/5.prim_sync_alert.1412077226 Apr 18 01:12:41 PM PDT 24 Apr 18 01:12:42 PM PDT 24 9239968 ps
T37 /workspace/coverage/sync_alert/18.prim_sync_alert.3061260966 Apr 18 01:12:49 PM PDT 24 Apr 18 01:12:50 PM PDT 24 9294171 ps
T28 /workspace/coverage/sync_alert/7.prim_sync_alert.377246410 Apr 18 01:12:42 PM PDT 24 Apr 18 01:12:43 PM PDT 24 9471446 ps
T38 /workspace/coverage/sync_alert/3.prim_sync_alert.378898787 Apr 18 01:12:42 PM PDT 24 Apr 18 01:12:42 PM PDT 24 8605065 ps
T29 /workspace/coverage/sync_alert/0.prim_sync_alert.434485646 Apr 18 01:12:36 PM PDT 24 Apr 18 01:12:37 PM PDT 24 9251047 ps
T30 /workspace/coverage/sync_alert/16.prim_sync_alert.1028263379 Apr 18 01:12:47 PM PDT 24 Apr 18 01:12:48 PM PDT 24 9736902 ps
T59 /workspace/coverage/sync_alert/15.prim_sync_alert.3513726448 Apr 18 01:12:48 PM PDT 24 Apr 18 01:12:49 PM PDT 24 8914875 ps
T60 /workspace/coverage/sync_alert/11.prim_sync_alert.1676808055 Apr 18 01:12:41 PM PDT 24 Apr 18 01:12:42 PM PDT 24 10038660 ps
T61 /workspace/coverage/sync_alert/9.prim_sync_alert.3079667739 Apr 18 01:12:40 PM PDT 24 Apr 18 01:12:40 PM PDT 24 9344756 ps
T62 /workspace/coverage/sync_alert/1.prim_sync_alert.836400769 Apr 18 01:12:40 PM PDT 24 Apr 18 01:12:40 PM PDT 24 10294059 ps
T16 /workspace/coverage/sync_alert/10.prim_sync_alert.1641613762 Apr 18 01:12:39 PM PDT 24 Apr 18 01:12:40 PM PDT 24 9939206 ps
T31 /workspace/coverage/sync_alert/19.prim_sync_alert.2722731596 Apr 18 01:12:50 PM PDT 24 Apr 18 01:12:50 PM PDT 24 8084514 ps
T32 /workspace/coverage/sync_alert/8.prim_sync_alert.142868837 Apr 18 01:12:41 PM PDT 24 Apr 18 01:12:41 PM PDT 24 8441332 ps
T11 /workspace/coverage/sync_alert/13.prim_sync_alert.3371021081 Apr 18 01:12:43 PM PDT 24 Apr 18 01:12:44 PM PDT 24 10078646 ps
T33 /workspace/coverage/sync_alert/2.prim_sync_alert.4086294646 Apr 18 01:12:42 PM PDT 24 Apr 18 01:12:43 PM PDT 24 9033751 ps
T34 /workspace/coverage/sync_alert/12.prim_sync_alert.2369431683 Apr 18 01:12:41 PM PDT 24 Apr 18 01:12:42 PM PDT 24 9414633 ps
T63 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1847197683 Apr 18 01:12:48 PM PDT 24 Apr 18 01:12:49 PM PDT 24 27513940 ps
T5 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2342746441 Apr 18 01:12:53 PM PDT 24 Apr 18 01:12:54 PM PDT 24 26908079 ps
T64 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1795387637 Apr 18 01:12:50 PM PDT 24 Apr 18 01:12:51 PM PDT 24 26180434 ps
T65 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1027608375 Apr 18 01:12:53 PM PDT 24 Apr 18 01:12:54 PM PDT 24 25750870 ps
T66 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4292625750 Apr 18 01:12:52 PM PDT 24 Apr 18 01:12:53 PM PDT 24 28196561 ps
T67 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3477768103 Apr 18 01:12:54 PM PDT 24 Apr 18 01:12:55 PM PDT 24 28649831 ps
T68 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1086090860 Apr 18 01:12:53 PM PDT 24 Apr 18 01:12:54 PM PDT 24 28657450 ps
T69 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2697298629 Apr 18 01:12:50 PM PDT 24 Apr 18 01:12:51 PM PDT 24 29660199 ps
T70 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1578515148 Apr 18 01:12:52 PM PDT 24 Apr 18 01:12:53 PM PDT 24 27011796 ps
T6 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3114226836 Apr 18 01:13:00 PM PDT 24 Apr 18 01:13:01 PM PDT 24 26704011 ps
T71 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2372899439 Apr 18 01:13:00 PM PDT 24 Apr 18 01:13:01 PM PDT 24 26492735 ps
T72 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.392920581 Apr 18 01:13:01 PM PDT 24 Apr 18 01:13:02 PM PDT 24 28711764 ps
T73 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2907058441 Apr 18 01:12:53 PM PDT 24 Apr 18 01:12:54 PM PDT 24 26113517 ps
T74 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1251134908 Apr 18 01:13:00 PM PDT 24 Apr 18 01:13:01 PM PDT 24 25600442 ps
T75 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2400067811 Apr 18 01:13:00 PM PDT 24 Apr 18 01:13:01 PM PDT 24 29257506 ps
T76 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.676203221 Apr 18 01:13:00 PM PDT 24 Apr 18 01:13:01 PM PDT 24 27542155 ps
T77 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3356673422 Apr 18 01:13:01 PM PDT 24 Apr 18 01:13:02 PM PDT 24 26772139 ps
T78 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.432375837 Apr 18 01:13:02 PM PDT 24 Apr 18 01:13:03 PM PDT 24 28072455 ps
T79 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1945559452 Apr 18 01:13:00 PM PDT 24 Apr 18 01:13:01 PM PDT 24 28654426 ps
T80 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4105758691 Apr 18 01:12:50 PM PDT 24 Apr 18 01:12:51 PM PDT 24 27228446 ps

Test location /workspace/coverage/default/15.prim_async_alert.3869281716
Short name T9
Test name
Test status
Simulation time 11283946 ps
CPU time 0.48 seconds
Started Apr 18 12:17:54 PM PDT 24
Finished Apr 18 12:17:55 PM PDT 24
Peak memory 145048 kb
Host smart-17e4f7fa-d0bb-4974-9acf-0dbeda6a8898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869281716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3869281716
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1028263379
Short name T30
Test name
Test status
Simulation time 9736902 ps
CPU time 0.39 seconds
Started Apr 18 01:12:47 PM PDT 24
Finished Apr 18 01:12:48 PM PDT 24
Peak memory 145036 kb
Host smart-ce667562-3182-4574-a601-30c29a3bae6f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1028263379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1028263379
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3871045160
Short name T43
Test name
Test status
Simulation time 30117622 ps
CPU time 0.4 seconds
Started Apr 18 01:12:39 PM PDT 24
Finished Apr 18 01:12:40 PM PDT 24
Peak memory 145820 kb
Host smart-2e89b7c2-a563-46b9-b672-e5ff1c503e8b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3871045160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3871045160
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2977085547
Short name T13
Test name
Test status
Simulation time 11691460 ps
CPU time 0.41 seconds
Started Apr 18 12:17:56 PM PDT 24
Finished Apr 18 12:17:58 PM PDT 24
Peak memory 145192 kb
Host smart-40406333-d583-4a45-8527-8923833e0cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977085547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2977085547
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2664084735
Short name T4
Test name
Test status
Simulation time 31513888 ps
CPU time 0.4 seconds
Started Apr 18 01:12:35 PM PDT 24
Finished Apr 18 01:12:36 PM PDT 24
Peak memory 145796 kb
Host smart-e2562c38-cc1f-4982-9a13-890f1db492f5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2664084735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2664084735
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3371021081
Short name T11
Test name
Test status
Simulation time 10078646 ps
CPU time 0.38 seconds
Started Apr 18 01:12:43 PM PDT 24
Finished Apr 18 01:12:44 PM PDT 24
Peak memory 145008 kb
Host smart-e3acb5c4-b768-4f2d-906a-235cf877ba2b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3371021081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3371021081
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2089849192
Short name T51
Test name
Test status
Simulation time 11043566 ps
CPU time 0.43 seconds
Started Apr 18 12:20:51 PM PDT 24
Finished Apr 18 12:20:52 PM PDT 24
Peak memory 145612 kb
Host smart-f3caa3de-1c80-49fa-a6c8-00297760a852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089849192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2089849192
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1428551308
Short name T49
Test name
Test status
Simulation time 11815212 ps
CPU time 0.38 seconds
Started Apr 18 12:22:42 PM PDT 24
Finished Apr 18 12:22:43 PM PDT 24
Peak memory 145244 kb
Host smart-e65ddbe3-5af8-4a8b-8a0c-a43e557360e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428551308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1428551308
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2687118539
Short name T24
Test name
Test status
Simulation time 10782581 ps
CPU time 0.4 seconds
Started Apr 18 12:17:54 PM PDT 24
Finished Apr 18 12:17:55 PM PDT 24
Peak memory 145592 kb
Host smart-1bbfbd35-2736-4ffa-b048-522bd55d5cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687118539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2687118539
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.976297637
Short name T1
Test name
Test status
Simulation time 10919800 ps
CPU time 0.39 seconds
Started Apr 18 12:17:56 PM PDT 24
Finished Apr 18 12:17:57 PM PDT 24
Peak memory 146640 kb
Host smart-53265300-0e69-4113-ab48-d9458abc5a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976297637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.976297637
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1685965891
Short name T20
Test name
Test status
Simulation time 11017188 ps
CPU time 0.43 seconds
Started Apr 18 12:17:53 PM PDT 24
Finished Apr 18 12:17:54 PM PDT 24
Peak memory 143276 kb
Host smart-210bc6ce-0634-40ca-ba89-b34797966533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685965891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1685965891
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3793181321
Short name T3
Test name
Test status
Simulation time 10949466 ps
CPU time 0.4 seconds
Started Apr 18 12:22:13 PM PDT 24
Finished Apr 18 12:22:14 PM PDT 24
Peak memory 145648 kb
Host smart-912ef39d-4ac5-4f4a-825d-4551e3a0b24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793181321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3793181321
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1524096919
Short name T21
Test name
Test status
Simulation time 10915757 ps
CPU time 0.4 seconds
Started Apr 18 12:19:26 PM PDT 24
Finished Apr 18 12:19:27 PM PDT 24
Peak memory 145788 kb
Host smart-82ee8a1f-0be8-4798-a06f-66c20daf38c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524096919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1524096919
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1871336943
Short name T23
Test name
Test status
Simulation time 11022441 ps
CPU time 0.38 seconds
Started Apr 18 12:22:33 PM PDT 24
Finished Apr 18 12:22:35 PM PDT 24
Peak memory 145892 kb
Host smart-3e01b6bf-5b15-4452-960b-c07fbb29347a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871336943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1871336943
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2861844061
Short name T52
Test name
Test status
Simulation time 11035865 ps
CPU time 0.43 seconds
Started Apr 18 12:18:04 PM PDT 24
Finished Apr 18 12:18:06 PM PDT 24
Peak memory 145276 kb
Host smart-32a8d7d7-1c8a-4dbf-92b4-012053947165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861844061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2861844061
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.175820388
Short name T17
Test name
Test status
Simulation time 11810815 ps
CPU time 0.38 seconds
Started Apr 18 12:21:48 PM PDT 24
Finished Apr 18 12:21:49 PM PDT 24
Peak memory 145680 kb
Host smart-2a0d81c3-694a-4aaf-a78f-96a75898ba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175820388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.175820388
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.4064199703
Short name T12
Test name
Test status
Simulation time 11600814 ps
CPU time 0.39 seconds
Started Apr 18 12:23:37 PM PDT 24
Finished Apr 18 12:23:38 PM PDT 24
Peak memory 144732 kb
Host smart-58d1e6bb-f104-45a8-81f1-ae1a0b43e396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064199703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.4064199703
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.140427984
Short name T2
Test name
Test status
Simulation time 10768177 ps
CPU time 0.38 seconds
Started Apr 18 12:22:44 PM PDT 24
Finished Apr 18 12:22:45 PM PDT 24
Peak memory 145048 kb
Host smart-a43941f4-1866-4e1b-8ce6-0a5850a8e042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140427984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.140427984
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.269794300
Short name T19
Test name
Test status
Simulation time 11079451 ps
CPU time 0.43 seconds
Started Apr 18 12:19:28 PM PDT 24
Finished Apr 18 12:19:29 PM PDT 24
Peak memory 145656 kb
Host smart-8d72f858-c3c4-4b2c-9a53-441dcdb99c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269794300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.269794300
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1294103003
Short name T50
Test name
Test status
Simulation time 10220670 ps
CPU time 0.38 seconds
Started Apr 18 12:18:49 PM PDT 24
Finished Apr 18 12:18:49 PM PDT 24
Peak memory 145656 kb
Host smart-e4b00186-eca6-4acf-b131-41cf95d613d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294103003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1294103003
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3796546597
Short name T10
Test name
Test status
Simulation time 11427475 ps
CPU time 0.41 seconds
Started Apr 18 12:22:59 PM PDT 24
Finished Apr 18 12:23:00 PM PDT 24
Peak memory 145108 kb
Host smart-94febdde-a4e6-4403-bcdc-999b38e8088e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796546597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3796546597
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.2809904407
Short name T8
Test name
Test status
Simulation time 11232536 ps
CPU time 0.44 seconds
Started Apr 18 12:23:07 PM PDT 24
Finished Apr 18 12:23:08 PM PDT 24
Peak memory 143552 kb
Host smart-8e4b0728-2a52-4875-92cc-50425b6e4907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809904407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2809904407
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2180453816
Short name T7
Test name
Test status
Simulation time 10756693 ps
CPU time 0.43 seconds
Started Apr 18 12:17:53 PM PDT 24
Finished Apr 18 12:17:54 PM PDT 24
Peak memory 143552 kb
Host smart-f0df7826-2dee-43c5-95fb-aa262398b53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180453816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2180453816
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2469711795
Short name T22
Test name
Test status
Simulation time 11330970 ps
CPU time 0.38 seconds
Started Apr 18 12:23:00 PM PDT 24
Finished Apr 18 12:23:01 PM PDT 24
Peak memory 145296 kb
Host smart-1867a693-147d-40f0-aabb-5e99cbd5f73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469711795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2469711795
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2652429956
Short name T39
Test name
Test status
Simulation time 30218198 ps
CPU time 0.45 seconds
Started Apr 18 01:12:29 PM PDT 24
Finished Apr 18 01:12:30 PM PDT 24
Peak memory 145760 kb
Host smart-e8443a6c-4823-481c-acbf-4d10ae8aab41
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2652429956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2652429956
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2513017488
Short name T57
Test name
Test status
Simulation time 30769122 ps
CPU time 0.39 seconds
Started Apr 18 01:12:36 PM PDT 24
Finished Apr 18 01:12:38 PM PDT 24
Peak memory 145812 kb
Host smart-f1f90d79-1d04-4c08-8ac4-ae81025dabbf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2513017488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2513017488
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2073747603
Short name T45
Test name
Test status
Simulation time 31041804 ps
CPU time 0.4 seconds
Started Apr 18 01:12:36 PM PDT 24
Finished Apr 18 01:12:38 PM PDT 24
Peak memory 145728 kb
Host smart-468cd056-c7f2-487c-8f04-2a4452efdd88
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2073747603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2073747603
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1947574612
Short name T14
Test name
Test status
Simulation time 30286584 ps
CPU time 0.4 seconds
Started Apr 18 01:12:36 PM PDT 24
Finished Apr 18 01:12:38 PM PDT 24
Peak memory 145820 kb
Host smart-6d77bac1-93f4-40be-bda7-5b984d678088
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1947574612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1947574612
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.185473042
Short name T56
Test name
Test status
Simulation time 32616028 ps
CPU time 0.4 seconds
Started Apr 18 01:12:38 PM PDT 24
Finished Apr 18 01:12:39 PM PDT 24
Peak memory 145804 kb
Host smart-fcaaca8a-b034-48b9-8931-75f3724bbd8e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=185473042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.185473042
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3388943130
Short name T48
Test name
Test status
Simulation time 30855063 ps
CPU time 0.4 seconds
Started Apr 18 01:12:35 PM PDT 24
Finished Apr 18 01:12:37 PM PDT 24
Peak memory 145900 kb
Host smart-eb84b407-30a0-4489-a06a-38ac3c2602a0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3388943130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3388943130
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2359480143
Short name T41
Test name
Test status
Simulation time 30760396 ps
CPU time 0.41 seconds
Started Apr 18 01:12:36 PM PDT 24
Finished Apr 18 01:12:37 PM PDT 24
Peak memory 145800 kb
Host smart-b4724dc4-8cd1-4cc9-81ea-1e3e080107b2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2359480143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2359480143
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.4051003260
Short name T42
Test name
Test status
Simulation time 29315461 ps
CPU time 0.39 seconds
Started Apr 18 01:12:36 PM PDT 24
Finished Apr 18 01:12:37 PM PDT 24
Peak memory 145748 kb
Host smart-3acceaa0-753a-46ee-b27c-68fc05007030
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4051003260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.4051003260
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3554521307
Short name T54
Test name
Test status
Simulation time 29221509 ps
CPU time 0.38 seconds
Started Apr 18 01:12:38 PM PDT 24
Finished Apr 18 01:12:39 PM PDT 24
Peak memory 145828 kb
Host smart-2d8ef232-e22e-495d-a7c0-02ebaca5b422
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3554521307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3554521307
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.467377009
Short name T18
Test name
Test status
Simulation time 29106524 ps
CPU time 0.41 seconds
Started Apr 18 01:13:14 PM PDT 24
Finished Apr 18 01:13:15 PM PDT 24
Peak memory 145820 kb
Host smart-35de8da7-3e77-44ab-a089-d8bfa972a3b4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=467377009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.467377009
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.709119534
Short name T15
Test name
Test status
Simulation time 31552690 ps
CPU time 0.43 seconds
Started Apr 18 01:12:37 PM PDT 24
Finished Apr 18 01:12:39 PM PDT 24
Peak memory 145676 kb
Host smart-f5dd23c4-5654-48c4-a43c-60dac65dd1e0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=709119534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.709119534
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2980636629
Short name T44
Test name
Test status
Simulation time 31908683 ps
CPU time 0.38 seconds
Started Apr 18 01:12:35 PM PDT 24
Finished Apr 18 01:12:36 PM PDT 24
Peak memory 145824 kb
Host smart-0cb495c2-abbb-4c26-8abd-f111398b58b7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2980636629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2980636629
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2313698449
Short name T55
Test name
Test status
Simulation time 30751307 ps
CPU time 0.41 seconds
Started Apr 18 01:12:37 PM PDT 24
Finished Apr 18 01:12:39 PM PDT 24
Peak memory 145820 kb
Host smart-9675a1f0-a5c9-4c86-a0b5-11513c48fec9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2313698449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2313698449
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3468798082
Short name T58
Test name
Test status
Simulation time 28895961 ps
CPU time 0.4 seconds
Started Apr 18 01:12:37 PM PDT 24
Finished Apr 18 01:12:38 PM PDT 24
Peak memory 145712 kb
Host smart-007d0118-cc90-4703-8b52-9b3ddf628e46
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3468798082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3468798082
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.946085293
Short name T53
Test name
Test status
Simulation time 32619023 ps
CPU time 0.39 seconds
Started Apr 18 01:12:36 PM PDT 24
Finished Apr 18 01:12:37 PM PDT 24
Peak memory 145828 kb
Host smart-8d5ca013-bef8-4312-8840-990e2fa83949
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=946085293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.946085293
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3343359470
Short name T47
Test name
Test status
Simulation time 32221642 ps
CPU time 0.39 seconds
Started Apr 18 01:12:36 PM PDT 24
Finished Apr 18 01:12:38 PM PDT 24
Peak memory 145808 kb
Host smart-e30272b9-8bda-4312-8c2d-89a71cbcd988
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3343359470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3343359470
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2144920016
Short name T40
Test name
Test status
Simulation time 29608777 ps
CPU time 0.39 seconds
Started Apr 18 01:12:35 PM PDT 24
Finished Apr 18 01:12:37 PM PDT 24
Peak memory 145788 kb
Host smart-c7833dab-9f07-4c73-967b-52db76c58059
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2144920016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2144920016
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2122664078
Short name T46
Test name
Test status
Simulation time 28663081 ps
CPU time 0.4 seconds
Started Apr 18 01:12:37 PM PDT 24
Finished Apr 18 01:12:39 PM PDT 24
Peak memory 145808 kb
Host smart-c2c3e3d8-7479-4ca4-bc7f-7cf676ed4106
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2122664078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2122664078
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.434485646
Short name T29
Test name
Test status
Simulation time 9251047 ps
CPU time 0.38 seconds
Started Apr 18 01:12:36 PM PDT 24
Finished Apr 18 01:12:37 PM PDT 24
Peak memory 145004 kb
Host smart-8bf3e7cf-33c4-4a66-874c-2a5e100152be
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=434485646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.434485646
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.836400769
Short name T62
Test name
Test status
Simulation time 10294059 ps
CPU time 0.37 seconds
Started Apr 18 01:12:40 PM PDT 24
Finished Apr 18 01:12:40 PM PDT 24
Peak memory 145084 kb
Host smart-a523fbad-91bf-4ad6-87cd-81e8c6b944de
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=836400769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.836400769
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1641613762
Short name T16
Test name
Test status
Simulation time 9939206 ps
CPU time 0.37 seconds
Started Apr 18 01:12:39 PM PDT 24
Finished Apr 18 01:12:40 PM PDT 24
Peak memory 145080 kb
Host smart-78dcff0c-cc6b-4ac8-be0b-ce000b86764e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1641613762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1641613762
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1676808055
Short name T60
Test name
Test status
Simulation time 10038660 ps
CPU time 0.38 seconds
Started Apr 18 01:12:41 PM PDT 24
Finished Apr 18 01:12:42 PM PDT 24
Peak memory 145104 kb
Host smart-823d02a1-e72c-4281-9804-9b97c11ac00a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1676808055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1676808055
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2369431683
Short name T34
Test name
Test status
Simulation time 9414633 ps
CPU time 0.36 seconds
Started Apr 18 01:12:41 PM PDT 24
Finished Apr 18 01:12:42 PM PDT 24
Peak memory 145028 kb
Host smart-8bffa301-2924-4224-bf65-800acaa9ab1e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2369431683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2369431683
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.156362854
Short name T27
Test name
Test status
Simulation time 9482086 ps
CPU time 0.39 seconds
Started Apr 18 01:12:47 PM PDT 24
Finished Apr 18 01:12:48 PM PDT 24
Peak memory 144984 kb
Host smart-f1cb8e98-827c-4dfa-9613-57fb3e7fc353
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=156362854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.156362854
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3513726448
Short name T59
Test name
Test status
Simulation time 8914875 ps
CPU time 0.36 seconds
Started Apr 18 01:12:48 PM PDT 24
Finished Apr 18 01:12:49 PM PDT 24
Peak memory 145084 kb
Host smart-2c6f2c9a-92b7-423d-b8cf-788be42bee90
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3513726448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3513726448
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3426514521
Short name T26
Test name
Test status
Simulation time 10553443 ps
CPU time 0.42 seconds
Started Apr 18 01:12:47 PM PDT 24
Finished Apr 18 01:12:48 PM PDT 24
Peak memory 145080 kb
Host smart-1657e7da-858d-4b26-82c9-881c8363dc7e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3426514521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3426514521
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3061260966
Short name T37
Test name
Test status
Simulation time 9294171 ps
CPU time 0.37 seconds
Started Apr 18 01:12:49 PM PDT 24
Finished Apr 18 01:12:50 PM PDT 24
Peak memory 145088 kb
Host smart-36bef0be-f0fc-4eca-a860-7a5a2e660754
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3061260966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3061260966
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2722731596
Short name T31
Test name
Test status
Simulation time 8084514 ps
CPU time 0.38 seconds
Started Apr 18 01:12:50 PM PDT 24
Finished Apr 18 01:12:50 PM PDT 24
Peak memory 145088 kb
Host smart-ddb93f1a-8c5b-4125-94d1-ee54ab5d6994
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2722731596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2722731596
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.4086294646
Short name T33
Test name
Test status
Simulation time 9033751 ps
CPU time 0.38 seconds
Started Apr 18 01:12:42 PM PDT 24
Finished Apr 18 01:12:43 PM PDT 24
Peak memory 145080 kb
Host smart-babe26ba-3d91-4ed5-aabd-1293a6ca0439
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4086294646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.4086294646
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.378898787
Short name T38
Test name
Test status
Simulation time 8605065 ps
CPU time 0.38 seconds
Started Apr 18 01:12:42 PM PDT 24
Finished Apr 18 01:12:42 PM PDT 24
Peak memory 145056 kb
Host smart-c78083a3-1230-427f-aec8-a0eda3ead547
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=378898787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.378898787
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.980549996
Short name T35
Test name
Test status
Simulation time 9627467 ps
CPU time 0.37 seconds
Started Apr 18 01:12:47 PM PDT 24
Finished Apr 18 01:12:48 PM PDT 24
Peak memory 145028 kb
Host smart-e64aec4c-5d9f-4388-9917-67e4368efabe
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=980549996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.980549996
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1412077226
Short name T36
Test name
Test status
Simulation time 9239968 ps
CPU time 0.38 seconds
Started Apr 18 01:12:41 PM PDT 24
Finished Apr 18 01:12:42 PM PDT 24
Peak memory 145084 kb
Host smart-8ad5204d-6014-40b4-8ad9-264262d92397
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1412077226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1412077226
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3216801936
Short name T25
Test name
Test status
Simulation time 9943241 ps
CPU time 0.38 seconds
Started Apr 18 01:12:42 PM PDT 24
Finished Apr 18 01:12:43 PM PDT 24
Peak memory 145028 kb
Host smart-eb8ad04e-aa52-46a7-b1c6-a4594bb5ee26
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3216801936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3216801936
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.377246410
Short name T28
Test name
Test status
Simulation time 9471446 ps
CPU time 0.37 seconds
Started Apr 18 01:12:42 PM PDT 24
Finished Apr 18 01:12:43 PM PDT 24
Peak memory 145092 kb
Host smart-714e27fd-b6aa-4773-8007-00c2dc4c64b2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=377246410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.377246410
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.142868837
Short name T32
Test name
Test status
Simulation time 8441332 ps
CPU time 0.37 seconds
Started Apr 18 01:12:41 PM PDT 24
Finished Apr 18 01:12:41 PM PDT 24
Peak memory 145008 kb
Host smart-43291474-78fb-450e-978d-5780fa573205
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=142868837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.142868837
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3079667739
Short name T61
Test name
Test status
Simulation time 9344756 ps
CPU time 0.36 seconds
Started Apr 18 01:12:40 PM PDT 24
Finished Apr 18 01:12:40 PM PDT 24
Peak memory 145016 kb
Host smart-a5009af4-d52b-488f-9d94-16a76b33cb2f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3079667739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3079667739
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4105758691
Short name T80
Test name
Test status
Simulation time 27228446 ps
CPU time 0.41 seconds
Started Apr 18 01:12:50 PM PDT 24
Finished Apr 18 01:12:51 PM PDT 24
Peak memory 145060 kb
Host smart-13ed437d-ad8d-4a69-975e-874784cdcc34
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4105758691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4105758691
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2697298629
Short name T69
Test name
Test status
Simulation time 29660199 ps
CPU time 0.4 seconds
Started Apr 18 01:12:50 PM PDT 24
Finished Apr 18 01:12:51 PM PDT 24
Peak memory 145096 kb
Host smart-cd1d374a-7713-4995-8b43-ee8f32746ad8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2697298629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2697298629
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2907058441
Short name T73
Test name
Test status
Simulation time 26113517 ps
CPU time 0.39 seconds
Started Apr 18 01:12:53 PM PDT 24
Finished Apr 18 01:12:54 PM PDT 24
Peak memory 144928 kb
Host smart-bb9f1513-a958-44e3-8510-edf484926b2b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2907058441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2907058441
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.676203221
Short name T76
Test name
Test status
Simulation time 27542155 ps
CPU time 0.4 seconds
Started Apr 18 01:13:00 PM PDT 24
Finished Apr 18 01:13:01 PM PDT 24
Peak memory 145040 kb
Host smart-b7263442-7680-4a7e-ade5-a4eecb0c66b4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=676203221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.676203221
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1945559452
Short name T79
Test name
Test status
Simulation time 28654426 ps
CPU time 0.4 seconds
Started Apr 18 01:13:00 PM PDT 24
Finished Apr 18 01:13:01 PM PDT 24
Peak memory 145064 kb
Host smart-46f7b450-674a-4f2b-8c7d-567e22b38fe3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1945559452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1945559452
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1251134908
Short name T74
Test name
Test status
Simulation time 25600442 ps
CPU time 0.42 seconds
Started Apr 18 01:13:00 PM PDT 24
Finished Apr 18 01:13:01 PM PDT 24
Peak memory 145068 kb
Host smart-2c3d4fdb-ce27-4caf-b3fb-1b23e9ed40e4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1251134908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1251134908
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.432375837
Short name T78
Test name
Test status
Simulation time 28072455 ps
CPU time 0.41 seconds
Started Apr 18 01:13:02 PM PDT 24
Finished Apr 18 01:13:03 PM PDT 24
Peak memory 144972 kb
Host smart-a6070d25-a65c-46a4-9367-f8dbc515a9cf
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=432375837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.432375837
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2400067811
Short name T75
Test name
Test status
Simulation time 29257506 ps
CPU time 0.4 seconds
Started Apr 18 01:13:00 PM PDT 24
Finished Apr 18 01:13:01 PM PDT 24
Peak memory 144932 kb
Host smart-a918217d-2ae3-4f4b-b54e-01f9e2386786
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2400067811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2400067811
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2372899439
Short name T71
Test name
Test status
Simulation time 26492735 ps
CPU time 0.45 seconds
Started Apr 18 01:13:00 PM PDT 24
Finished Apr 18 01:13:01 PM PDT 24
Peak memory 145032 kb
Host smart-a87ee465-cb00-4d42-9ac4-455fe33b37a0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2372899439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2372899439
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3114226836
Short name T6
Test name
Test status
Simulation time 26704011 ps
CPU time 0.4 seconds
Started Apr 18 01:13:00 PM PDT 24
Finished Apr 18 01:13:01 PM PDT 24
Peak memory 145020 kb
Host smart-27c74168-5226-4511-b072-17a5b3cd5511
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3114226836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3114226836
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.392920581
Short name T72
Test name
Test status
Simulation time 28711764 ps
CPU time 0.44 seconds
Started Apr 18 01:13:01 PM PDT 24
Finished Apr 18 01:13:02 PM PDT 24
Peak memory 145004 kb
Host smart-9bd175a4-4f28-43fb-b2b3-8bb6a11cf421
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=392920581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.392920581
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3356673422
Short name T77
Test name
Test status
Simulation time 26772139 ps
CPU time 0.41 seconds
Started Apr 18 01:13:01 PM PDT 24
Finished Apr 18 01:13:02 PM PDT 24
Peak memory 144996 kb
Host smart-a31ae447-d09e-4bb3-a990-6e545c604aec
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3356673422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3356673422
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1847197683
Short name T63
Test name
Test status
Simulation time 27513940 ps
CPU time 0.38 seconds
Started Apr 18 01:12:48 PM PDT 24
Finished Apr 18 01:12:49 PM PDT 24
Peak memory 145064 kb
Host smart-263c2336-2a4e-418f-853b-6f6ef2892dda
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1847197683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1847197683
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1795387637
Short name T64
Test name
Test status
Simulation time 26180434 ps
CPU time 0.41 seconds
Started Apr 18 01:12:50 PM PDT 24
Finished Apr 18 01:12:51 PM PDT 24
Peak memory 145060 kb
Host smart-738236dc-1728-43bd-ac35-74f7ed9b61f6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1795387637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1795387637
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1086090860
Short name T68
Test name
Test status
Simulation time 28657450 ps
CPU time 0.38 seconds
Started Apr 18 01:12:53 PM PDT 24
Finished Apr 18 01:12:54 PM PDT 24
Peak memory 144976 kb
Host smart-809d15cc-2215-4a7e-8755-31d7fad102e7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1086090860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1086090860
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4292625750
Short name T66
Test name
Test status
Simulation time 28196561 ps
CPU time 0.38 seconds
Started Apr 18 01:12:52 PM PDT 24
Finished Apr 18 01:12:53 PM PDT 24
Peak memory 145080 kb
Host smart-a7df7348-05a7-4e0a-877e-ffec9e9323a7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4292625750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.4292625750
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3477768103
Short name T67
Test name
Test status
Simulation time 28649831 ps
CPU time 0.38 seconds
Started Apr 18 01:12:54 PM PDT 24
Finished Apr 18 01:12:55 PM PDT 24
Peak memory 145020 kb
Host smart-4a6a3687-2a43-4030-ae7c-ba1f4ff5f507
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3477768103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3477768103
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1027608375
Short name T65
Test name
Test status
Simulation time 25750870 ps
CPU time 0.39 seconds
Started Apr 18 01:12:53 PM PDT 24
Finished Apr 18 01:12:54 PM PDT 24
Peak memory 145112 kb
Host smart-98cee5fd-b47c-41e2-8704-2a37e8fde32e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1027608375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1027608375
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2342746441
Short name T5
Test name
Test status
Simulation time 26908079 ps
CPU time 0.4 seconds
Started Apr 18 01:12:53 PM PDT 24
Finished Apr 18 01:12:54 PM PDT 24
Peak memory 145032 kb
Host smart-34282c9d-7bba-4b85-aeaf-1933aeda13f5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2342746441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2342746441
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1578515148
Short name T70
Test name
Test status
Simulation time 27011796 ps
CPU time 0.41 seconds
Started Apr 18 01:12:52 PM PDT 24
Finished Apr 18 01:12:53 PM PDT 24
Peak memory 145028 kb
Host smart-86e72d46-8695-43c1-a056-da8d6650a678
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1578515148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1578515148
Directory /workspace/9.prim_sync_fatal_alert/latest
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