| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.63 | 88.63 | 100.00 | 100.00 | 95.83 | 95.83 | 100.00 | 100.00 | 75.00 | 75.00 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/12.prim_async_alert.1433661581 |
| 91.76 | 3.13 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/19.prim_sync_alert.1778774545 |
| 93.52 | 1.76 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 85.71 | 3.57 | 95.83 | 0.00 | 83.72 | 6.98 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2085644642 |
| 94.50 | 0.98 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 2.33 | /workspace/coverage/default/11.prim_async_alert.1032657454 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/5.prim_sync_alert.2954903144 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3300658826 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.1922395520 |
| /workspace/coverage/default/1.prim_async_alert.56125921 |
| /workspace/coverage/default/10.prim_async_alert.1999681508 |
| /workspace/coverage/default/13.prim_async_alert.2356438148 |
| /workspace/coverage/default/14.prim_async_alert.1930327284 |
| /workspace/coverage/default/15.prim_async_alert.3049489506 |
| /workspace/coverage/default/16.prim_async_alert.260423039 |
| /workspace/coverage/default/17.prim_async_alert.427399214 |
| /workspace/coverage/default/18.prim_async_alert.1526102577 |
| /workspace/coverage/default/19.prim_async_alert.1929602648 |
| /workspace/coverage/default/2.prim_async_alert.792957335 |
| /workspace/coverage/default/3.prim_async_alert.875355928 |
| /workspace/coverage/default/4.prim_async_alert.3779210858 |
| /workspace/coverage/default/5.prim_async_alert.1482381411 |
| /workspace/coverage/default/6.prim_async_alert.2433627668 |
| /workspace/coverage/default/7.prim_async_alert.1865888451 |
| /workspace/coverage/default/8.prim_async_alert.2603762014 |
| /workspace/coverage/default/9.prim_async_alert.4180365834 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3506000405 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2431269502 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.701223721 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.336287151 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.10973830 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.675245666 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.801362821 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2927901746 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.164234681 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1057386276 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2797420357 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2850589246 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3736223727 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.647344203 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2871101117 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2292099938 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2818797034 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3393269351 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.1268711997 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.1621165561 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.1091120094 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1474901470 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.2176879389 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1979483163 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.2532391631 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.4199908779 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.3469170305 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.1023340545 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.2691422944 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2116642494 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.4270933576 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.2899977432 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.514660302 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.304313006 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.110144746 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1927922949 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2319185089 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2621079978 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3675447876 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.803754844 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3160613381 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4211131003 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.110027558 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1755651473 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1572598945 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4228490791 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2709536224 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3651251503 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1346880098 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3013308083 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2749309759 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2955961814 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1838905640 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2457285970 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1126892172 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/4.prim_async_alert.3779210858 | Apr 21 12:37:30 PM PDT 24 | Apr 21 12:37:30 PM PDT 24 | 12440180 ps | ||
| T2 | /workspace/coverage/default/9.prim_async_alert.4180365834 | Apr 21 12:37:52 PM PDT 24 | Apr 21 12:37:53 PM PDT 24 | 11282921 ps | ||
| T3 | /workspace/coverage/default/12.prim_async_alert.1433661581 | Apr 21 12:37:46 PM PDT 24 | Apr 21 12:37:47 PM PDT 24 | 11566828 ps | ||
| T7 | /workspace/coverage/default/16.prim_async_alert.260423039 | Apr 21 12:37:46 PM PDT 24 | Apr 21 12:37:47 PM PDT 24 | 11103337 ps | ||
| T8 | /workspace/coverage/default/15.prim_async_alert.3049489506 | Apr 21 12:38:00 PM PDT 24 | Apr 21 12:38:01 PM PDT 24 | 10505673 ps | ||
| T6 | /workspace/coverage/default/2.prim_async_alert.792957335 | Apr 21 12:37:37 PM PDT 24 | Apr 21 12:37:38 PM PDT 24 | 11326165 ps | ||
| T13 | /workspace/coverage/default/19.prim_async_alert.1929602648 | Apr 21 12:37:56 PM PDT 24 | Apr 21 12:37:57 PM PDT 24 | 11084441 ps | ||
| T14 | /workspace/coverage/default/11.prim_async_alert.1032657454 | Apr 21 12:37:34 PM PDT 24 | Apr 21 12:37:34 PM PDT 24 | 10744757 ps | ||
| T15 | /workspace/coverage/default/3.prim_async_alert.875355928 | Apr 21 12:37:58 PM PDT 24 | Apr 21 12:37:58 PM PDT 24 | 11188937 ps | ||
| T16 | /workspace/coverage/default/6.prim_async_alert.2433627668 | Apr 21 12:37:32 PM PDT 24 | Apr 21 12:37:33 PM PDT 24 | 10603120 ps | ||
| T10 | /workspace/coverage/default/17.prim_async_alert.427399214 | Apr 21 12:37:29 PM PDT 24 | Apr 21 12:37:29 PM PDT 24 | 12356411 ps | ||
| T17 | /workspace/coverage/default/18.prim_async_alert.1526102577 | Apr 21 12:37:53 PM PDT 24 | Apr 21 12:37:54 PM PDT 24 | 11352154 ps | ||
| T18 | /workspace/coverage/default/13.prim_async_alert.2356438148 | Apr 21 12:37:35 PM PDT 24 | Apr 21 12:37:36 PM PDT 24 | 10490375 ps | ||
| T45 | /workspace/coverage/default/5.prim_async_alert.1482381411 | Apr 21 12:37:49 PM PDT 24 | Apr 21 12:37:50 PM PDT 24 | 11049018 ps | ||
| T19 | /workspace/coverage/default/14.prim_async_alert.1930327284 | Apr 21 12:37:59 PM PDT 24 | Apr 21 12:38:00 PM PDT 24 | 11998768 ps | ||
| T20 | /workspace/coverage/default/8.prim_async_alert.2603762014 | Apr 21 12:37:35 PM PDT 24 | Apr 21 12:37:36 PM PDT 24 | 11181762 ps | ||
| T11 | /workspace/coverage/default/0.prim_async_alert.1922395520 | Apr 21 12:37:29 PM PDT 24 | Apr 21 12:37:29 PM PDT 24 | 11484641 ps | ||
| T21 | /workspace/coverage/default/1.prim_async_alert.56125921 | Apr 21 12:37:53 PM PDT 24 | Apr 21 12:37:54 PM PDT 24 | 11361811 ps | ||
| T46 | /workspace/coverage/default/10.prim_async_alert.1999681508 | Apr 21 12:37:52 PM PDT 24 | Apr 21 12:37:53 PM PDT 24 | 11233558 ps | ||
| T47 | /workspace/coverage/default/7.prim_async_alert.1865888451 | Apr 21 12:37:40 PM PDT 24 | Apr 21 12:37:41 PM PDT 24 | 11451153 ps | ||
| T36 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.701223721 | Apr 21 12:37:53 PM PDT 24 | Apr 21 12:37:54 PM PDT 24 | 31388083 ps | ||
| T35 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3393269351 | Apr 21 12:38:02 PM PDT 24 | Apr 21 12:38:03 PM PDT 24 | 31561419 ps | ||
| T37 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.675245666 | Apr 21 12:37:58 PM PDT 24 | Apr 21 12:37:59 PM PDT 24 | 31040327 ps | ||
| T38 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2871101117 | Apr 21 12:38:05 PM PDT 24 | Apr 21 12:38:06 PM PDT 24 | 31665554 ps | ||
| T39 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3736223727 | Apr 21 12:37:53 PM PDT 24 | Apr 21 12:37:54 PM PDT 24 | 31323455 ps | ||
| T40 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2085644642 | Apr 21 12:37:38 PM PDT 24 | Apr 21 12:37:39 PM PDT 24 | 30208469 ps | ||
| T41 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.647344203 | Apr 21 12:38:06 PM PDT 24 | Apr 21 12:38:07 PM PDT 24 | 30417093 ps | ||
| T42 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2797420357 | Apr 21 12:37:59 PM PDT 24 | Apr 21 12:38:00 PM PDT 24 | 29272052 ps | ||
| T43 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2927901746 | Apr 21 12:38:09 PM PDT 24 | Apr 21 12:38:10 PM PDT 24 | 30239541 ps | ||
| T44 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.336287151 | Apr 21 12:38:13 PM PDT 24 | Apr 21 12:38:15 PM PDT 24 | 26718401 ps | ||
| T48 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.801362821 | Apr 21 12:38:10 PM PDT 24 | Apr 21 12:38:11 PM PDT 24 | 30346127 ps | ||
| T49 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.164234681 | Apr 21 12:38:00 PM PDT 24 | Apr 21 12:38:01 PM PDT 24 | 28536697 ps | ||
| T50 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.10973830 | Apr 21 12:38:01 PM PDT 24 | Apr 21 12:38:02 PM PDT 24 | 29615452 ps | ||
| T51 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2431269502 | Apr 21 12:37:52 PM PDT 24 | Apr 21 12:37:53 PM PDT 24 | 32385993 ps | ||
| T52 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2818797034 | Apr 21 12:38:09 PM PDT 24 | Apr 21 12:38:09 PM PDT 24 | 31136039 ps | ||
| T53 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2850589246 | Apr 21 12:37:59 PM PDT 24 | Apr 21 12:38:00 PM PDT 24 | 30090337 ps | ||
| T54 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3506000405 | Apr 21 12:37:55 PM PDT 24 | Apr 21 12:37:56 PM PDT 24 | 30071350 ps | ||
| T55 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2292099938 | Apr 21 12:38:02 PM PDT 24 | Apr 21 12:38:03 PM PDT 24 | 32164163 ps | ||
| T56 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1057386276 | Apr 21 12:37:59 PM PDT 24 | Apr 21 12:37:59 PM PDT 24 | 30863108 ps | ||
| T22 | /workspace/coverage/sync_alert/3.prim_sync_alert.4270933576 | Apr 21 12:20:00 PM PDT 24 | Apr 21 12:20:01 PM PDT 24 | 8606346 ps | ||
| T23 | /workspace/coverage/sync_alert/16.prim_sync_alert.3469170305 | Apr 21 12:17:47 PM PDT 24 | Apr 21 12:17:48 PM PDT 24 | 8803590 ps | ||
| T24 | /workspace/coverage/sync_alert/0.prim_sync_alert.1268711997 | Apr 21 12:20:01 PM PDT 24 | Apr 21 12:20:02 PM PDT 24 | 8535360 ps | ||
| T25 | /workspace/coverage/sync_alert/2.prim_sync_alert.2116642494 | Apr 21 12:19:58 PM PDT 24 | Apr 21 12:19:59 PM PDT 24 | 9504461 ps | ||
| T26 | /workspace/coverage/sync_alert/14.prim_sync_alert.2532391631 | Apr 21 12:19:44 PM PDT 24 | Apr 21 12:19:45 PM PDT 24 | 9648371 ps | ||
| T12 | /workspace/coverage/sync_alert/19.prim_sync_alert.1778774545 | Apr 21 12:20:08 PM PDT 24 | Apr 21 12:20:09 PM PDT 24 | 9915633 ps | ||
| T31 | /workspace/coverage/sync_alert/18.prim_sync_alert.2691422944 | Apr 21 12:22:35 PM PDT 24 | Apr 21 12:22:37 PM PDT 24 | 9057682 ps | ||
| T32 | /workspace/coverage/sync_alert/13.prim_sync_alert.1979483163 | Apr 21 12:19:42 PM PDT 24 | Apr 21 12:19:43 PM PDT 24 | 10548319 ps | ||
| T33 | /workspace/coverage/sync_alert/1.prim_sync_alert.1621165561 | Apr 21 12:22:33 PM PDT 24 | Apr 21 12:22:34 PM PDT 24 | 10022861 ps | ||
| T27 | /workspace/coverage/sync_alert/15.prim_sync_alert.4199908779 | Apr 21 12:22:49 PM PDT 24 | Apr 21 12:22:50 PM PDT 24 | 8180757 ps | ||
| T28 | /workspace/coverage/sync_alert/17.prim_sync_alert.1023340545 | Apr 21 12:23:37 PM PDT 24 | Apr 21 12:23:38 PM PDT 24 | 8854313 ps | ||
| T29 | /workspace/coverage/sync_alert/9.prim_sync_alert.1927922949 | Apr 21 12:22:33 PM PDT 24 | Apr 21 12:22:34 PM PDT 24 | 9545194 ps | ||
| T30 | /workspace/coverage/sync_alert/8.prim_sync_alert.110144746 | Apr 21 12:22:34 PM PDT 24 | Apr 21 12:22:35 PM PDT 24 | 9768841 ps | ||
| T57 | /workspace/coverage/sync_alert/10.prim_sync_alert.1091120094 | Apr 21 12:21:12 PM PDT 24 | Apr 21 12:21:13 PM PDT 24 | 9245572 ps | ||
| T34 | /workspace/coverage/sync_alert/4.prim_sync_alert.2899977432 | Apr 21 12:22:33 PM PDT 24 | Apr 21 12:22:34 PM PDT 24 | 9180197 ps | ||
| T58 | /workspace/coverage/sync_alert/6.prim_sync_alert.514660302 | Apr 21 12:22:49 PM PDT 24 | Apr 21 12:22:50 PM PDT 24 | 8884331 ps | ||
| T59 | /workspace/coverage/sync_alert/11.prim_sync_alert.1474901470 | Apr 21 12:22:33 PM PDT 24 | Apr 21 12:22:34 PM PDT 24 | 8850797 ps | ||
| T60 | /workspace/coverage/sync_alert/7.prim_sync_alert.304313006 | Apr 21 12:22:33 PM PDT 24 | Apr 21 12:22:34 PM PDT 24 | 9698916 ps | ||
| T61 | /workspace/coverage/sync_alert/12.prim_sync_alert.2176879389 | Apr 21 12:22:48 PM PDT 24 | Apr 21 12:22:50 PM PDT 24 | 9802659 ps | ||
| T9 | /workspace/coverage/sync_alert/5.prim_sync_alert.2954903144 | Apr 21 12:19:30 PM PDT 24 | Apr 21 12:19:31 PM PDT 24 | 9285531 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4228490791 | Apr 21 12:22:49 PM PDT 24 | Apr 21 12:22:51 PM PDT 24 | 29664707 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1346880098 | Apr 21 12:23:36 PM PDT 24 | Apr 21 12:23:37 PM PDT 24 | 27891618 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3651251503 | Apr 21 12:17:53 PM PDT 24 | Apr 21 12:17:54 PM PDT 24 | 27318472 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1126892172 | Apr 21 12:21:11 PM PDT 24 | Apr 21 12:21:12 PM PDT 24 | 28864400 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1572598945 | Apr 21 12:22:34 PM PDT 24 | Apr 21 12:22:35 PM PDT 24 | 28799904 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.110027558 | Apr 21 12:20:30 PM PDT 24 | Apr 21 12:20:31 PM PDT 24 | 27591287 ps | ||
| T4 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3300658826 | Apr 21 12:18:51 PM PDT 24 | Apr 21 12:18:51 PM PDT 24 | 28182533 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2955961814 | Apr 21 12:22:41 PM PDT 24 | Apr 21 12:22:43 PM PDT 24 | 27621859 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1755651473 | Apr 21 12:22:33 PM PDT 24 | Apr 21 12:22:34 PM PDT 24 | 28065234 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2709536224 | Apr 21 12:22:49 PM PDT 24 | Apr 21 12:22:51 PM PDT 24 | 28014137 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1838905640 | Apr 21 12:19:24 PM PDT 24 | Apr 21 12:19:24 PM PDT 24 | 27060939 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2621079978 | Apr 21 12:19:17 PM PDT 24 | Apr 21 12:19:18 PM PDT 24 | 27368407 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2319185089 | Apr 21 12:22:35 PM PDT 24 | Apr 21 12:22:37 PM PDT 24 | 27548389 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3013308083 | Apr 21 12:22:35 PM PDT 24 | Apr 21 12:22:37 PM PDT 24 | 26937448 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3675447876 | Apr 21 12:20:30 PM PDT 24 | Apr 21 12:20:31 PM PDT 24 | 27710463 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3160613381 | Apr 21 12:19:14 PM PDT 24 | Apr 21 12:19:15 PM PDT 24 | 26729680 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.803754844 | Apr 21 12:23:47 PM PDT 24 | Apr 21 12:23:48 PM PDT 24 | 29938446 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2457285970 | Apr 21 12:22:34 PM PDT 24 | Apr 21 12:22:36 PM PDT 24 | 26447516 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4211131003 | Apr 21 12:19:14 PM PDT 24 | Apr 21 12:19:15 PM PDT 24 | 26963437 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2749309759 | Apr 21 12:21:52 PM PDT 24 | Apr 21 12:21:53 PM PDT 24 | 26693085 ps |
| Test location | /workspace/coverage/default/12.prim_async_alert.1433661581 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11566828 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:37:46 PM PDT 24 |
| Finished | Apr 21 12:37:47 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-0dd6c92a-7238-493c-8c92-f73d115a45ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1433661581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1433661581 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.1778774545 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 9915633 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:20:08 PM PDT 24 |
| Finished | Apr 21 12:20:09 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-430704d9-3d60-4f08-b4e6-8ecc66c50b4a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1778774545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1778774545 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2085644642 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 30208469 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:37:38 PM PDT 24 |
| Finished | Apr 21 12:37:39 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-e9d1c224-5338-42d0-a52a-b3316d15bea3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2085644642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2085644642 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.1032657454 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10744757 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:37:34 PM PDT 24 |
| Finished | Apr 21 12:37:34 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-0d89d596-17b0-403d-8264-f4e6381be574 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1032657454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1032657454 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.2954903144 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9285531 ps |
| CPU time | 0.41 seconds |
| Started | Apr 21 12:19:30 PM PDT 24 |
| Finished | Apr 21 12:19:31 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-56337565-ed36-459d-abc0-90d132f8e9b2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2954903144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2954903144 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3300658826 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28182533 ps |
| CPU time | 0.43 seconds |
| Started | Apr 21 12:18:51 PM PDT 24 |
| Finished | Apr 21 12:18:51 PM PDT 24 |
| Peak memory | 144780 kb |
| Host | smart-93853f5b-cf1d-4998-8401-1772696e2816 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3300658826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3300658826 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.1922395520 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11484641 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:37:29 PM PDT 24 |
| Finished | Apr 21 12:37:29 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-11e0bb6f-33aa-4e3d-9d5b-b4231c35f27e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1922395520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1922395520 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.56125921 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11361811 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:37:53 PM PDT 24 |
| Finished | Apr 21 12:37:54 PM PDT 24 |
| Peak memory | 145728 kb |
| Host | smart-ccec3b69-3495-4927-85d6-54a5f80531e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56125921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.56125921 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.1999681508 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11233558 ps |
| CPU time | 0.37 seconds |
| Started | Apr 21 12:37:52 PM PDT 24 |
| Finished | Apr 21 12:37:53 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-4f3111b0-633e-4d3c-8213-ee9b51cf67de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999681508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1999681508 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.2356438148 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10490375 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:37:35 PM PDT 24 |
| Finished | Apr 21 12:37:36 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-92fae6fe-10d6-4306-8d2a-86848188da93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356438148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2356438148 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1930327284 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11998768 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:37:59 PM PDT 24 |
| Finished | Apr 21 12:38:00 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-096e9312-151d-4ca3-a200-4e43b64dcc74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1930327284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1930327284 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3049489506 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10505673 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:38:00 PM PDT 24 |
| Finished | Apr 21 12:38:01 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-7fd11833-5f25-40e3-8923-70a4b260ddc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3049489506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3049489506 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.260423039 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11103337 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:37:46 PM PDT 24 |
| Finished | Apr 21 12:37:47 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-3cf0af57-12b2-4725-b6f1-f990163f1f12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=260423039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.260423039 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.427399214 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12356411 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:37:29 PM PDT 24 |
| Finished | Apr 21 12:37:29 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-a86a5bd8-83b0-4566-90a6-ac20cd3021ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=427399214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.427399214 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.1526102577 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11352154 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:37:53 PM PDT 24 |
| Finished | Apr 21 12:37:54 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-e6474a65-aa60-4d5f-9a6d-45285214c5dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1526102577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1526102577 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.1929602648 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11084441 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:37:56 PM PDT 24 |
| Finished | Apr 21 12:37:57 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-aa9b0d4b-0e11-4b66-96b9-fd504b19ab1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1929602648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1929602648 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.792957335 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11326165 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:37:37 PM PDT 24 |
| Finished | Apr 21 12:37:38 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-c5c54996-2c26-4757-8f72-84218cf3e6fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792957335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.792957335 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.875355928 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11188937 ps |
| CPU time | 0.37 seconds |
| Started | Apr 21 12:37:58 PM PDT 24 |
| Finished | Apr 21 12:37:58 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-b304d7f7-e1ad-487a-bce5-356667376a24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875355928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.875355928 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.3779210858 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12440180 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:37:30 PM PDT 24 |
| Finished | Apr 21 12:37:30 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-a0dabd61-4feb-4ec2-a478-8232cefc7eec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779210858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3779210858 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1482381411 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11049018 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:37:49 PM PDT 24 |
| Finished | Apr 21 12:37:50 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-419656d1-efcb-45f9-9052-9d12202da391 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1482381411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1482381411 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2433627668 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10603120 ps |
| CPU time | 0.37 seconds |
| Started | Apr 21 12:37:32 PM PDT 24 |
| Finished | Apr 21 12:37:33 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-74402dd3-fdf0-4b76-a2fb-46a97ab1b071 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2433627668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2433627668 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.1865888451 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11451153 ps |
| CPU time | 0.42 seconds |
| Started | Apr 21 12:37:40 PM PDT 24 |
| Finished | Apr 21 12:37:41 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-f867639e-93a4-4b4e-b3c7-6cd7d2483d7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1865888451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1865888451 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2603762014 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11181762 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:37:35 PM PDT 24 |
| Finished | Apr 21 12:37:36 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-867839b6-4407-4d81-b1cf-f7f9cebb39d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2603762014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2603762014 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.4180365834 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11282921 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:37:52 PM PDT 24 |
| Finished | Apr 21 12:37:53 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-5f78db13-3473-4795-8c69-de960f48698c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180365834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.4180365834 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3506000405 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30071350 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:37:55 PM PDT 24 |
| Finished | Apr 21 12:37:56 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-6a948726-e46a-49d5-a4ea-b281d17a2266 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3506000405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3506000405 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2431269502 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 32385993 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:37:52 PM PDT 24 |
| Finished | Apr 21 12:37:53 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-0ac5ac34-5878-4a18-a891-aebeb9a62a44 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2431269502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2431269502 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.701223721 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 31388083 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:37:53 PM PDT 24 |
| Finished | Apr 21 12:37:54 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-ff2c7260-92c9-43e2-922b-a24e5d9f63d4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=701223721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.701223721 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.336287151 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 26718401 ps |
| CPU time | 0.45 seconds |
| Started | Apr 21 12:38:13 PM PDT 24 |
| Finished | Apr 21 12:38:15 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-1a45fc21-6987-4184-b309-f49aa067f0f7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=336287151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.336287151 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.10973830 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 29615452 ps |
| CPU time | 0.42 seconds |
| Started | Apr 21 12:38:01 PM PDT 24 |
| Finished | Apr 21 12:38:02 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-16ab6901-e8c2-430c-aef9-33fd78c66344 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=10973830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.10973830 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.675245666 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 31040327 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:37:58 PM PDT 24 |
| Finished | Apr 21 12:37:59 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-da544bb4-1ef1-4e38-bc81-34562b4092a8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=675245666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.675245666 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.801362821 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30346127 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:38:10 PM PDT 24 |
| Finished | Apr 21 12:38:11 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-21ef827e-40e6-419a-835b-9cd9c6805047 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=801362821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.801362821 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2927901746 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30239541 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:38:09 PM PDT 24 |
| Finished | Apr 21 12:38:10 PM PDT 24 |
| Peak memory | 145700 kb |
| Host | smart-030287d3-bfd0-4c43-8270-d01ce8fcc586 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2927901746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2927901746 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.164234681 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 28536697 ps |
| CPU time | 0.41 seconds |
| Started | Apr 21 12:38:00 PM PDT 24 |
| Finished | Apr 21 12:38:01 PM PDT 24 |
| Peak memory | 145692 kb |
| Host | smart-819a419c-def6-4f6c-b66c-4f26d4f7084f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=164234681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.164234681 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1057386276 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 30863108 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:37:59 PM PDT 24 |
| Finished | Apr 21 12:37:59 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-59b31918-61d0-4631-953d-adebfae9b637 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1057386276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1057386276 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2797420357 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29272052 ps |
| CPU time | 0.42 seconds |
| Started | Apr 21 12:37:59 PM PDT 24 |
| Finished | Apr 21 12:38:00 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-7dcbc50c-f0c5-48ef-a783-09552ca8d3ee |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2797420357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2797420357 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2850589246 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30090337 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:37:59 PM PDT 24 |
| Finished | Apr 21 12:38:00 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-22a65d1e-747d-4de9-9822-d72db69dc3e7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2850589246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2850589246 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3736223727 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 31323455 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:37:53 PM PDT 24 |
| Finished | Apr 21 12:37:54 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-a5d8e1c4-637f-4aef-be70-da76d5d0ce28 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3736223727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3736223727 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.647344203 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30417093 ps |
| CPU time | 0.42 seconds |
| Started | Apr 21 12:38:06 PM PDT 24 |
| Finished | Apr 21 12:38:07 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-65dbd601-63cc-4556-b083-a60c96dd6d62 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=647344203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.647344203 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2871101117 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 31665554 ps |
| CPU time | 0.41 seconds |
| Started | Apr 21 12:38:05 PM PDT 24 |
| Finished | Apr 21 12:38:06 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-0a9ad2d1-6d8b-47c1-ae70-fada81e13456 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2871101117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2871101117 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2292099938 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 32164163 ps |
| CPU time | 0.41 seconds |
| Started | Apr 21 12:38:02 PM PDT 24 |
| Finished | Apr 21 12:38:03 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-e05ef685-2795-4a77-9b1a-babb2689df8a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2292099938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2292099938 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2818797034 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 31136039 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:38:09 PM PDT 24 |
| Finished | Apr 21 12:38:09 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-a1e40027-54e1-4bf1-b36b-9f7b5f29a80f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2818797034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2818797034 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3393269351 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 31561419 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:38:02 PM PDT 24 |
| Finished | Apr 21 12:38:03 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-39ed27f7-74ab-4c20-b8d1-b693161a414b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3393269351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3393269351 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.1268711997 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8535360 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:20:01 PM PDT 24 |
| Finished | Apr 21 12:20:02 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-2f8e3ab0-294b-4232-8d0f-ad8b33ea51a6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1268711997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1268711997 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.1621165561 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10022861 ps |
| CPU time | 0.43 seconds |
| Started | Apr 21 12:22:33 PM PDT 24 |
| Finished | Apr 21 12:22:34 PM PDT 24 |
| Peak memory | 142356 kb |
| Host | smart-69aa8d11-99df-4b59-9e80-f631124d3578 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1621165561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1621165561 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.1091120094 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9245572 ps |
| CPU time | 0.42 seconds |
| Started | Apr 21 12:21:12 PM PDT 24 |
| Finished | Apr 21 12:21:13 PM PDT 24 |
| Peak memory | 144748 kb |
| Host | smart-c272293e-80ce-43fd-875d-7cf4dc9d6e13 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1091120094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1091120094 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1474901470 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8850797 ps |
| CPU time | 0.37 seconds |
| Started | Apr 21 12:22:33 PM PDT 24 |
| Finished | Apr 21 12:22:34 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-bd791bfa-b7c9-4ae8-bbea-17162193e72b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1474901470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1474901470 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.2176879389 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9802659 ps |
| CPU time | 0.44 seconds |
| Started | Apr 21 12:22:48 PM PDT 24 |
| Finished | Apr 21 12:22:50 PM PDT 24 |
| Peak memory | 143976 kb |
| Host | smart-3a4f1b78-577a-4757-b513-f858429714eb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2176879389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2176879389 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1979483163 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10548319 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:19:42 PM PDT 24 |
| Finished | Apr 21 12:19:43 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-825e4675-9cc0-437c-87dd-def3e0531273 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1979483163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1979483163 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.2532391631 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9648371 ps |
| CPU time | 0.41 seconds |
| Started | Apr 21 12:19:44 PM PDT 24 |
| Finished | Apr 21 12:19:45 PM PDT 24 |
| Peak memory | 144788 kb |
| Host | smart-eb7ca0b8-692b-4e72-aa87-14d70656d317 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2532391631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2532391631 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.4199908779 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8180757 ps |
| CPU time | 0.38 seconds |
| Started | Apr 21 12:22:49 PM PDT 24 |
| Finished | Apr 21 12:22:50 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-a8a0f23b-5c4b-4e3e-a5e1-779a566cf8e7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4199908779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.4199908779 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.3469170305 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8803590 ps |
| CPU time | 0.43 seconds |
| Started | Apr 21 12:17:47 PM PDT 24 |
| Finished | Apr 21 12:17:48 PM PDT 24 |
| Peak memory | 145336 kb |
| Host | smart-316a5bf6-4f55-49df-89ae-b3e666ccc0ee |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3469170305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3469170305 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.1023340545 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8854313 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:23:37 PM PDT 24 |
| Finished | Apr 21 12:23:38 PM PDT 24 |
| Peak memory | 144708 kb |
| Host | smart-1182e750-d4c5-4bde-a5a2-59c351040037 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1023340545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1023340545 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.2691422944 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9057682 ps |
| CPU time | 0.44 seconds |
| Started | Apr 21 12:22:35 PM PDT 24 |
| Finished | Apr 21 12:22:37 PM PDT 24 |
| Peak memory | 142948 kb |
| Host | smart-13c40131-51fd-4d61-8f4c-3f9c4c3b6c0f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2691422944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2691422944 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2116642494 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9504461 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:19:58 PM PDT 24 |
| Finished | Apr 21 12:19:59 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-7b4a3a46-4c45-43b9-9394-a4f57e0cd32e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2116642494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2116642494 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.4270933576 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8606346 ps |
| CPU time | 0.41 seconds |
| Started | Apr 21 12:20:00 PM PDT 24 |
| Finished | Apr 21 12:20:01 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-4c95dc74-3b03-4c34-adfd-68251f4209f7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4270933576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.4270933576 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.2899977432 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9180197 ps |
| CPU time | 0.43 seconds |
| Started | Apr 21 12:22:33 PM PDT 24 |
| Finished | Apr 21 12:22:34 PM PDT 24 |
| Peak memory | 142888 kb |
| Host | smart-30ff4e27-01eb-4046-adb7-6b6388c6fea9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2899977432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2899977432 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.514660302 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8884331 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:22:49 PM PDT 24 |
| Finished | Apr 21 12:22:50 PM PDT 24 |
| Peak memory | 144460 kb |
| Host | smart-56fe84b0-9369-4f9d-87e3-6148fa75b36c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=514660302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.514660302 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.304313006 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9698916 ps |
| CPU time | 0.43 seconds |
| Started | Apr 21 12:22:33 PM PDT 24 |
| Finished | Apr 21 12:22:34 PM PDT 24 |
| Peak memory | 142808 kb |
| Host | smart-6afb1e8f-9469-4a3b-86c7-697eb7ade52f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=304313006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.304313006 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.110144746 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9768841 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:22:34 PM PDT 24 |
| Finished | Apr 21 12:22:35 PM PDT 24 |
| Peak memory | 144736 kb |
| Host | smart-5b07835e-761f-4c6a-a920-5d82919d7cea |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=110144746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.110144746 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1927922949 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9545194 ps |
| CPU time | 0.44 seconds |
| Started | Apr 21 12:22:33 PM PDT 24 |
| Finished | Apr 21 12:22:34 PM PDT 24 |
| Peak memory | 143060 kb |
| Host | smart-dab87afd-f202-4a39-a96f-3a6d1c0331b0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1927922949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1927922949 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2319185089 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27548389 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:22:35 PM PDT 24 |
| Finished | Apr 21 12:22:37 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-a667c94b-e4df-4fbf-bd45-d8b9b6d26772 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2319185089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2319185089 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2621079978 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27368407 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:19:17 PM PDT 24 |
| Finished | Apr 21 12:19:18 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-0111d510-af93-4970-b406-a67ce753cab3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2621079978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2621079978 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3675447876 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27710463 ps |
| CPU time | 0.52 seconds |
| Started | Apr 21 12:20:30 PM PDT 24 |
| Finished | Apr 21 12:20:31 PM PDT 24 |
| Peak memory | 143476 kb |
| Host | smart-c7b11af6-510c-4950-9250-7b0a8276c154 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3675447876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3675447876 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.803754844 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 29938446 ps |
| CPU time | 0.47 seconds |
| Started | Apr 21 12:23:47 PM PDT 24 |
| Finished | Apr 21 12:23:48 PM PDT 24 |
| Peak memory | 143688 kb |
| Host | smart-8c84289b-7ee8-443e-aefa-bbeb16f40ff3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=803754844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.803754844 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3160613381 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26729680 ps |
| CPU time | 0.41 seconds |
| Started | Apr 21 12:19:14 PM PDT 24 |
| Finished | Apr 21 12:19:15 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-1280ba2a-1a2c-46c6-9f23-2952360030b9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3160613381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3160613381 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4211131003 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26963437 ps |
| CPU time | 0.4 seconds |
| Started | Apr 21 12:19:14 PM PDT 24 |
| Finished | Apr 21 12:19:15 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-64f774f5-7343-49e1-b601-fccf30c6838b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4211131003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.4211131003 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.110027558 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27591287 ps |
| CPU time | 0.46 seconds |
| Started | Apr 21 12:20:30 PM PDT 24 |
| Finished | Apr 21 12:20:31 PM PDT 24 |
| Peak memory | 143296 kb |
| Host | smart-3859f098-940e-4c6d-9e08-3f7fdd562a0c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=110027558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.110027558 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1755651473 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28065234 ps |
| CPU time | 0.46 seconds |
| Started | Apr 21 12:22:33 PM PDT 24 |
| Finished | Apr 21 12:22:34 PM PDT 24 |
| Peak memory | 142836 kb |
| Host | smart-65be9227-d02f-4957-8abb-381a9642bcd4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1755651473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1755651473 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1572598945 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 28799904 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:22:34 PM PDT 24 |
| Finished | Apr 21 12:22:35 PM PDT 24 |
| Peak memory | 144736 kb |
| Host | smart-906fd739-62da-4cdf-ba86-e1b97ad872ba |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1572598945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1572598945 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4228490791 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 29664707 ps |
| CPU time | 0.44 seconds |
| Started | Apr 21 12:22:49 PM PDT 24 |
| Finished | Apr 21 12:22:51 PM PDT 24 |
| Peak memory | 142984 kb |
| Host | smart-5661c70b-8c5b-4939-81d3-b2b3ee1f2101 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4228490791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.4228490791 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2709536224 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28014137 ps |
| CPU time | 0.43 seconds |
| Started | Apr 21 12:22:49 PM PDT 24 |
| Finished | Apr 21 12:22:51 PM PDT 24 |
| Peak memory | 143008 kb |
| Host | smart-ce07db7d-7eef-40d3-9312-70e532e5a68c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2709536224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2709536224 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3651251503 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27318472 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:17:53 PM PDT 24 |
| Finished | Apr 21 12:17:54 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-a166e3fe-ac47-4fd5-92fc-ac0ca51848cc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3651251503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3651251503 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1346880098 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27891618 ps |
| CPU time | 0.47 seconds |
| Started | Apr 21 12:23:36 PM PDT 24 |
| Finished | Apr 21 12:23:37 PM PDT 24 |
| Peak memory | 143856 kb |
| Host | smart-45724aef-e574-4236-b262-5549789928c4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1346880098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1346880098 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3013308083 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26937448 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:22:35 PM PDT 24 |
| Finished | Apr 21 12:22:37 PM PDT 24 |
| Peak memory | 144644 kb |
| Host | smart-bb898cfd-3069-4177-8c31-2f2d53eb24b4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3013308083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3013308083 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2749309759 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 26693085 ps |
| CPU time | 0.41 seconds |
| Started | Apr 21 12:21:52 PM PDT 24 |
| Finished | Apr 21 12:21:53 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-f287c288-7894-4e16-90f9-22ec7b8cc7c3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2749309759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2749309759 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2955961814 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 27621859 ps |
| CPU time | 0.39 seconds |
| Started | Apr 21 12:22:41 PM PDT 24 |
| Finished | Apr 21 12:22:43 PM PDT 24 |
| Peak memory | 144856 kb |
| Host | smart-8e65bb0d-5cb4-4d0b-b240-bff942b04740 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2955961814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2955961814 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1838905640 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27060939 ps |
| CPU time | 0.41 seconds |
| Started | Apr 21 12:19:24 PM PDT 24 |
| Finished | Apr 21 12:19:24 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-e620c06b-8a36-4f7b-95ff-c47e1af29fbb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1838905640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1838905640 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2457285970 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 26447516 ps |
| CPU time | 0.45 seconds |
| Started | Apr 21 12:22:34 PM PDT 24 |
| Finished | Apr 21 12:22:36 PM PDT 24 |
| Peak memory | 144768 kb |
| Host | smart-a37ef787-1223-4915-8ac5-404a591f6856 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2457285970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2457285970 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1126892172 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28864400 ps |
| CPU time | 0.41 seconds |
| Started | Apr 21 12:21:11 PM PDT 24 |
| Finished | Apr 21 12:21:12 PM PDT 24 |
| Peak memory | 144736 kb |
| Host | smart-51c14257-b24a-4229-b7f0-df44d1c26567 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1126892172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1126892172 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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