Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/14.prim_async_alert.4219232189
91.80 3.13 100.00 0.00 93.75 0.00 100.00 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/4.prim_sync_alert.259294218
94.15 2.35 100.00 0.00 93.75 0.00 100.00 0.00 89.29 7.14 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.449484148
94.85 0.69 100.00 0.00 97.92 4.17 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1399791186
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1106688244

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2088953868
/workspace/coverage/default/1.prim_async_alert.223769510
/workspace/coverage/default/10.prim_async_alert.3668349217
/workspace/coverage/default/11.prim_async_alert.1804157545
/workspace/coverage/default/12.prim_async_alert.195930969
/workspace/coverage/default/13.prim_async_alert.1779684073
/workspace/coverage/default/15.prim_async_alert.2416405453
/workspace/coverage/default/16.prim_async_alert.2731122803
/workspace/coverage/default/17.prim_async_alert.3372946426
/workspace/coverage/default/18.prim_async_alert.3261882425
/workspace/coverage/default/19.prim_async_alert.2941523631
/workspace/coverage/default/2.prim_async_alert.2758774281
/workspace/coverage/default/3.prim_async_alert.1821777538
/workspace/coverage/default/4.prim_async_alert.3250418525
/workspace/coverage/default/5.prim_async_alert.3377305810
/workspace/coverage/default/6.prim_async_alert.3289950919
/workspace/coverage/default/7.prim_async_alert.2858354565
/workspace/coverage/default/8.prim_async_alert.3002922682
/workspace/coverage/default/9.prim_async_alert.2473781184
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3708056753
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.800651152
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.926366233
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1974578403
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.665421705
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3009981960
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1690113133
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1680227222
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2691031380
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1805301176
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.514035838
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3437264004
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2043043107
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3709032715
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2362020239
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3004995287
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2910890545
/workspace/coverage/sync_alert/0.prim_sync_alert.3091354510
/workspace/coverage/sync_alert/1.prim_sync_alert.1862169811
/workspace/coverage/sync_alert/10.prim_sync_alert.1382887660
/workspace/coverage/sync_alert/11.prim_sync_alert.1562120395
/workspace/coverage/sync_alert/12.prim_sync_alert.3050129353
/workspace/coverage/sync_alert/13.prim_sync_alert.911434077
/workspace/coverage/sync_alert/14.prim_sync_alert.268478287
/workspace/coverage/sync_alert/15.prim_sync_alert.638854422
/workspace/coverage/sync_alert/16.prim_sync_alert.2732552656
/workspace/coverage/sync_alert/17.prim_sync_alert.2967877259
/workspace/coverage/sync_alert/18.prim_sync_alert.2225895333
/workspace/coverage/sync_alert/19.prim_sync_alert.1597190814
/workspace/coverage/sync_alert/2.prim_sync_alert.1689672978
/workspace/coverage/sync_alert/3.prim_sync_alert.554299767
/workspace/coverage/sync_alert/5.prim_sync_alert.1848501293
/workspace/coverage/sync_alert/6.prim_sync_alert.3860963955
/workspace/coverage/sync_alert/7.prim_sync_alert.1661139643
/workspace/coverage/sync_alert/8.prim_sync_alert.2254867265
/workspace/coverage/sync_alert/9.prim_sync_alert.3866086512
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2929912540
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.506593831
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.891828706
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3780730288
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2989950217
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2922324080
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.970221443
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3414949494
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1655250893
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1487954813
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4032130472
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1450775398
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1056381977
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.976053040
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.165673757
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2153445286
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2062298456
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3666017237
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3461005760



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/11.prim_async_alert.1804157545 Apr 23 01:36:25 PM PDT 24 Apr 23 01:36:26 PM PDT 24 10918522 ps
T2 /workspace/coverage/default/4.prim_async_alert.3250418525 Apr 23 01:36:24 PM PDT 24 Apr 23 01:36:25 PM PDT 24 11931056 ps
T3 /workspace/coverage/default/16.prim_async_alert.2731122803 Apr 23 01:36:24 PM PDT 24 Apr 23 01:36:25 PM PDT 24 11502446 ps
T7 /workspace/coverage/default/7.prim_async_alert.2858354565 Apr 23 01:36:25 PM PDT 24 Apr 23 01:36:26 PM PDT 24 11151369 ps
T9 /workspace/coverage/default/17.prim_async_alert.3372946426 Apr 23 01:36:25 PM PDT 24 Apr 23 01:36:26 PM PDT 24 11141940 ps
T8 /workspace/coverage/default/0.prim_async_alert.2088953868 Apr 23 01:36:24 PM PDT 24 Apr 23 01:36:25 PM PDT 24 11885026 ps
T18 /workspace/coverage/default/10.prim_async_alert.3668349217 Apr 23 01:36:24 PM PDT 24 Apr 23 01:36:26 PM PDT 24 11612646 ps
T11 /workspace/coverage/default/2.prim_async_alert.2758774281 Apr 23 01:36:25 PM PDT 24 Apr 23 01:36:26 PM PDT 24 12180328 ps
T19 /workspace/coverage/default/9.prim_async_alert.2473781184 Apr 23 01:36:25 PM PDT 24 Apr 23 01:36:27 PM PDT 24 10901574 ps
T12 /workspace/coverage/default/14.prim_async_alert.4219232189 Apr 23 01:36:25 PM PDT 24 Apr 23 01:36:26 PM PDT 24 12886451 ps
T16 /workspace/coverage/default/6.prim_async_alert.3289950919 Apr 23 01:36:25 PM PDT 24 Apr 23 01:36:26 PM PDT 24 11769669 ps
T20 /workspace/coverage/default/3.prim_async_alert.1821777538 Apr 23 01:36:26 PM PDT 24 Apr 23 01:36:27 PM PDT 24 10774434 ps
T46 /workspace/coverage/default/15.prim_async_alert.2416405453 Apr 23 01:36:24 PM PDT 24 Apr 23 01:36:25 PM PDT 24 11438778 ps
T21 /workspace/coverage/default/18.prim_async_alert.3261882425 Apr 23 01:36:24 PM PDT 24 Apr 23 01:36:26 PM PDT 24 10797507 ps
T47 /workspace/coverage/default/8.prim_async_alert.3002922682 Apr 23 01:36:27 PM PDT 24 Apr 23 01:36:28 PM PDT 24 11149553 ps
T22 /workspace/coverage/default/5.prim_async_alert.3377305810 Apr 23 01:36:24 PM PDT 24 Apr 23 01:36:25 PM PDT 24 11868435 ps
T17 /workspace/coverage/default/13.prim_async_alert.1779684073 Apr 23 01:36:25 PM PDT 24 Apr 23 01:36:26 PM PDT 24 12198512 ps
T48 /workspace/coverage/default/12.prim_async_alert.195930969 Apr 23 01:36:24 PM PDT 24 Apr 23 01:36:26 PM PDT 24 11067826 ps
T23 /workspace/coverage/default/1.prim_async_alert.223769510 Apr 23 01:36:23 PM PDT 24 Apr 23 01:36:24 PM PDT 24 11077086 ps
T49 /workspace/coverage/default/19.prim_async_alert.2941523631 Apr 23 01:36:30 PM PDT 24 Apr 23 01:36:31 PM PDT 24 11762582 ps
T24 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2362020239 Apr 23 01:36:33 PM PDT 24 Apr 23 01:36:34 PM PDT 24 29549853 ps
T41 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.926366233 Apr 23 01:36:33 PM PDT 24 Apr 23 01:36:34 PM PDT 24 29131192 ps
T25 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3004995287 Apr 23 01:36:29 PM PDT 24 Apr 23 01:36:29 PM PDT 24 30076540 ps
T4 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1399791186 Apr 23 01:36:35 PM PDT 24 Apr 23 01:36:36 PM PDT 24 29927593 ps
T42 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2910890545 Apr 23 01:36:31 PM PDT 24 Apr 23 01:36:32 PM PDT 24 29047476 ps
T40 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1974578403 Apr 23 01:36:33 PM PDT 24 Apr 23 01:36:33 PM PDT 24 31578129 ps
T43 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3437264004 Apr 23 01:36:28 PM PDT 24 Apr 23 01:36:29 PM PDT 24 30641800 ps
T13 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.449484148 Apr 23 01:36:30 PM PDT 24 Apr 23 01:36:30 PM PDT 24 30821794 ps
T44 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3708056753 Apr 23 01:36:30 PM PDT 24 Apr 23 01:36:31 PM PDT 24 30514589 ps
T45 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3009981960 Apr 23 01:36:30 PM PDT 24 Apr 23 01:36:31 PM PDT 24 29713365 ps
T50 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2043043107 Apr 23 01:36:31 PM PDT 24 Apr 23 01:36:32 PM PDT 24 28783282 ps
T51 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.665421705 Apr 23 01:36:27 PM PDT 24 Apr 23 01:36:28 PM PDT 24 28819297 ps
T52 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3709032715 Apr 23 01:36:29 PM PDT 24 Apr 23 01:36:30 PM PDT 24 30069500 ps
T53 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1690113133 Apr 23 01:36:30 PM PDT 24 Apr 23 01:36:31 PM PDT 24 30673132 ps
T54 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.800651152 Apr 23 01:36:31 PM PDT 24 Apr 23 01:36:31 PM PDT 24 29905102 ps
T55 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2691031380 Apr 23 01:36:34 PM PDT 24 Apr 23 01:36:35 PM PDT 24 30293627 ps
T56 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.514035838 Apr 23 01:36:30 PM PDT 24 Apr 23 01:36:30 PM PDT 24 31492683 ps
T5 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1805301176 Apr 23 01:36:39 PM PDT 24 Apr 23 01:36:40 PM PDT 24 30692679 ps
T57 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1680227222 Apr 23 01:36:34 PM PDT 24 Apr 23 01:36:35 PM PDT 24 27679660 ps
T26 /workspace/coverage/sync_alert/4.prim_sync_alert.259294218 Apr 23 01:36:34 PM PDT 24 Apr 23 01:36:35 PM PDT 24 8502195 ps
T36 /workspace/coverage/sync_alert/14.prim_sync_alert.268478287 Apr 23 01:36:39 PM PDT 24 Apr 23 01:36:40 PM PDT 24 8857196 ps
T27 /workspace/coverage/sync_alert/17.prim_sync_alert.2967877259 Apr 23 01:36:39 PM PDT 24 Apr 23 01:36:40 PM PDT 24 9504311 ps
T37 /workspace/coverage/sync_alert/6.prim_sync_alert.3860963955 Apr 23 01:36:37 PM PDT 24 Apr 23 01:36:38 PM PDT 24 9959100 ps
T28 /workspace/coverage/sync_alert/3.prim_sync_alert.554299767 Apr 23 01:36:33 PM PDT 24 Apr 23 01:36:34 PM PDT 24 9086855 ps
T14 /workspace/coverage/sync_alert/9.prim_sync_alert.3866086512 Apr 23 01:36:39 PM PDT 24 Apr 23 01:36:40 PM PDT 24 9999349 ps
T38 /workspace/coverage/sync_alert/2.prim_sync_alert.1689672978 Apr 23 01:36:36 PM PDT 24 Apr 23 01:36:37 PM PDT 24 8339497 ps
T39 /workspace/coverage/sync_alert/7.prim_sync_alert.1661139643 Apr 23 01:36:34 PM PDT 24 Apr 23 01:36:35 PM PDT 24 8974583 ps
T29 /workspace/coverage/sync_alert/16.prim_sync_alert.2732552656 Apr 23 01:36:35 PM PDT 24 Apr 23 01:36:37 PM PDT 24 8914352 ps
T30 /workspace/coverage/sync_alert/5.prim_sync_alert.1848501293 Apr 23 01:36:41 PM PDT 24 Apr 23 01:36:42 PM PDT 24 9780353 ps
T31 /workspace/coverage/sync_alert/19.prim_sync_alert.1597190814 Apr 23 01:36:40 PM PDT 24 Apr 23 01:36:41 PM PDT 24 9412690 ps
T32 /workspace/coverage/sync_alert/12.prim_sync_alert.3050129353 Apr 23 01:36:36 PM PDT 24 Apr 23 01:36:37 PM PDT 24 9481507 ps
T33 /workspace/coverage/sync_alert/10.prim_sync_alert.1382887660 Apr 23 01:36:36 PM PDT 24 Apr 23 01:36:38 PM PDT 24 9264376 ps
T58 /workspace/coverage/sync_alert/0.prim_sync_alert.3091354510 Apr 23 01:36:35 PM PDT 24 Apr 23 01:36:36 PM PDT 24 9904123 ps
T59 /workspace/coverage/sync_alert/8.prim_sync_alert.2254867265 Apr 23 01:36:34 PM PDT 24 Apr 23 01:36:35 PM PDT 24 9304368 ps
T60 /workspace/coverage/sync_alert/1.prim_sync_alert.1862169811 Apr 23 01:36:34 PM PDT 24 Apr 23 01:36:35 PM PDT 24 9174710 ps
T61 /workspace/coverage/sync_alert/15.prim_sync_alert.638854422 Apr 23 01:36:36 PM PDT 24 Apr 23 01:36:37 PM PDT 24 10462762 ps
T15 /workspace/coverage/sync_alert/11.prim_sync_alert.1562120395 Apr 23 01:36:35 PM PDT 24 Apr 23 01:36:36 PM PDT 24 9956806 ps
T34 /workspace/coverage/sync_alert/18.prim_sync_alert.2225895333 Apr 23 01:36:41 PM PDT 24 Apr 23 01:36:42 PM PDT 24 8834788 ps
T62 /workspace/coverage/sync_alert/13.prim_sync_alert.911434077 Apr 23 01:36:34 PM PDT 24 Apr 23 01:36:35 PM PDT 24 8994205 ps
T35 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.891828706 Apr 23 01:36:39 PM PDT 24 Apr 23 01:36:40 PM PDT 24 26942596 ps
T63 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2922324080 Apr 23 01:36:43 PM PDT 24 Apr 23 01:36:44 PM PDT 24 27662066 ps
T64 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1056381977 Apr 23 01:36:39 PM PDT 24 Apr 23 01:36:41 PM PDT 24 25721204 ps
T65 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.976053040 Apr 23 01:36:41 PM PDT 24 Apr 23 01:36:42 PM PDT 24 27902868 ps
T66 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3666017237 Apr 23 01:36:41 PM PDT 24 Apr 23 01:36:42 PM PDT 24 28258720 ps
T67 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.165673757 Apr 23 01:36:36 PM PDT 24 Apr 23 01:36:37 PM PDT 24 27614557 ps
T68 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.506593831 Apr 23 01:36:39 PM PDT 24 Apr 23 01:36:40 PM PDT 24 26028380 ps
T69 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.970221443 Apr 23 01:36:40 PM PDT 24 Apr 23 01:36:41 PM PDT 24 26115303 ps
T70 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2062298456 Apr 23 01:36:41 PM PDT 24 Apr 23 01:36:42 PM PDT 24 29241734 ps
T71 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1487954813 Apr 23 01:36:39 PM PDT 24 Apr 23 01:36:41 PM PDT 24 27011293 ps
T10 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1106688244 Apr 23 01:36:39 PM PDT 24 Apr 23 01:36:41 PM PDT 24 26703749 ps
T6 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3414949494 Apr 23 01:36:42 PM PDT 24 Apr 23 01:36:43 PM PDT 24 27326917 ps
T72 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1450775398 Apr 23 01:36:37 PM PDT 24 Apr 23 01:36:38 PM PDT 24 26514830 ps
T73 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2929912540 Apr 23 01:36:41 PM PDT 24 Apr 23 01:36:42 PM PDT 24 25776305 ps
T74 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4032130472 Apr 23 01:36:39 PM PDT 24 Apr 23 01:36:39 PM PDT 24 28532438 ps
T75 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3780730288 Apr 23 01:36:37 PM PDT 24 Apr 23 01:36:38 PM PDT 24 26269852 ps
T76 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1655250893 Apr 23 01:36:38 PM PDT 24 Apr 23 01:36:39 PM PDT 24 26966285 ps
T77 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3461005760 Apr 23 01:36:38 PM PDT 24 Apr 23 01:36:39 PM PDT 24 27378854 ps
T78 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2153445286 Apr 23 01:36:41 PM PDT 24 Apr 23 01:36:42 PM PDT 24 25290735 ps
T79 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2989950217 Apr 23 01:36:42 PM PDT 24 Apr 23 01:36:43 PM PDT 24 27269530 ps

Test location /workspace/coverage/default/14.prim_async_alert.4219232189
Short name T12
Test name
Test status
Simulation time 12886451 ps
CPU time 0.4 seconds
Started Apr 23 01:36:25 PM PDT 24
Finished Apr 23 01:36:26 PM PDT 24
Peak memory 145684 kb
Host smart-693ce89d-4f6b-4ef4-a33d-a636e4438a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219232189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.4219232189
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.259294218
Short name T26
Test name
Test status
Simulation time 8502195 ps
CPU time 0.39 seconds
Started Apr 23 01:36:34 PM PDT 24
Finished Apr 23 01:36:35 PM PDT 24
Peak memory 145024 kb
Host smart-11e9cc94-c036-4698-9a00-66ccedddc06a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=259294218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.259294218
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.449484148
Short name T13
Test name
Test status
Simulation time 30821794 ps
CPU time 0.4 seconds
Started Apr 23 01:36:30 PM PDT 24
Finished Apr 23 01:36:30 PM PDT 24
Peak memory 145816 kb
Host smart-4705df6c-4c32-461c-93e1-946490f8be51
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=449484148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.449484148
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1399791186
Short name T4
Test name
Test status
Simulation time 29927593 ps
CPU time 0.43 seconds
Started Apr 23 01:36:35 PM PDT 24
Finished Apr 23 01:36:36 PM PDT 24
Peak memory 145804 kb
Host smart-f1f8c6fd-6ddd-4f7f-ab75-a44c46dc185b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1399791186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1399791186
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1106688244
Short name T10
Test name
Test status
Simulation time 26703749 ps
CPU time 0.39 seconds
Started Apr 23 01:36:39 PM PDT 24
Finished Apr 23 01:36:41 PM PDT 24
Peak memory 144896 kb
Host smart-8eada38f-55e6-4fa1-a97d-93f83e4a2f06
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1106688244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1106688244
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2088953868
Short name T8
Test name
Test status
Simulation time 11885026 ps
CPU time 0.4 seconds
Started Apr 23 01:36:24 PM PDT 24
Finished Apr 23 01:36:25 PM PDT 24
Peak memory 145784 kb
Host smart-ac707394-5392-4687-86c3-0643c4682969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088953868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2088953868
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.223769510
Short name T23
Test name
Test status
Simulation time 11077086 ps
CPU time 0.39 seconds
Started Apr 23 01:36:23 PM PDT 24
Finished Apr 23 01:36:24 PM PDT 24
Peak memory 145764 kb
Host smart-eb580eae-50bf-4f0f-aebc-4392b8f6394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223769510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.223769510
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3668349217
Short name T18
Test name
Test status
Simulation time 11612646 ps
CPU time 0.42 seconds
Started Apr 23 01:36:24 PM PDT 24
Finished Apr 23 01:36:26 PM PDT 24
Peak memory 145644 kb
Host smart-0fc68053-42fc-4c8c-b075-0541aa12f78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668349217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3668349217
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1804157545
Short name T1
Test name
Test status
Simulation time 10918522 ps
CPU time 0.41 seconds
Started Apr 23 01:36:25 PM PDT 24
Finished Apr 23 01:36:26 PM PDT 24
Peak memory 145692 kb
Host smart-9b6a9a8f-4169-4c08-a245-3d83d5c3e0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804157545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1804157545
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.195930969
Short name T48
Test name
Test status
Simulation time 11067826 ps
CPU time 0.39 seconds
Started Apr 23 01:36:24 PM PDT 24
Finished Apr 23 01:36:26 PM PDT 24
Peak memory 145772 kb
Host smart-eb6680cd-2fe3-4238-be03-0c13f514c05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195930969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.195930969
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1779684073
Short name T17
Test name
Test status
Simulation time 12198512 ps
CPU time 0.39 seconds
Started Apr 23 01:36:25 PM PDT 24
Finished Apr 23 01:36:26 PM PDT 24
Peak memory 145792 kb
Host smart-3f5cf80d-bb71-41b9-8536-cab145cca9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779684073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1779684073
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.2416405453
Short name T46
Test name
Test status
Simulation time 11438778 ps
CPU time 0.38 seconds
Started Apr 23 01:36:24 PM PDT 24
Finished Apr 23 01:36:25 PM PDT 24
Peak memory 145740 kb
Host smart-f8dfa3f2-517d-4cc2-9570-c1a84ab8b47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416405453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2416405453
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2731122803
Short name T3
Test name
Test status
Simulation time 11502446 ps
CPU time 0.4 seconds
Started Apr 23 01:36:24 PM PDT 24
Finished Apr 23 01:36:25 PM PDT 24
Peak memory 145700 kb
Host smart-e575b472-92b8-4dab-8393-56dc405a0c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731122803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2731122803
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3372946426
Short name T9
Test name
Test status
Simulation time 11141940 ps
CPU time 0.44 seconds
Started Apr 23 01:36:25 PM PDT 24
Finished Apr 23 01:36:26 PM PDT 24
Peak memory 145708 kb
Host smart-c0e0b5a5-ffbd-4c7a-b43f-aa6a14c70970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372946426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3372946426
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3261882425
Short name T21
Test name
Test status
Simulation time 10797507 ps
CPU time 0.38 seconds
Started Apr 23 01:36:24 PM PDT 24
Finished Apr 23 01:36:26 PM PDT 24
Peak memory 145792 kb
Host smart-75610b7c-72b4-48cb-8db5-5adac005179d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261882425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3261882425
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2941523631
Short name T49
Test name
Test status
Simulation time 11762582 ps
CPU time 0.39 seconds
Started Apr 23 01:36:30 PM PDT 24
Finished Apr 23 01:36:31 PM PDT 24
Peak memory 145764 kb
Host smart-aa1bb0e1-3141-4096-9a14-7777d9432e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941523631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2941523631
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2758774281
Short name T11
Test name
Test status
Simulation time 12180328 ps
CPU time 0.46 seconds
Started Apr 23 01:36:25 PM PDT 24
Finished Apr 23 01:36:26 PM PDT 24
Peak memory 145744 kb
Host smart-7d117f5b-3256-432a-b369-36a6dfa850d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758774281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2758774281
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1821777538
Short name T20
Test name
Test status
Simulation time 10774434 ps
CPU time 0.39 seconds
Started Apr 23 01:36:26 PM PDT 24
Finished Apr 23 01:36:27 PM PDT 24
Peak memory 145668 kb
Host smart-ce45a3c9-8183-4718-9741-161acf5b8cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821777538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1821777538
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3250418525
Short name T2
Test name
Test status
Simulation time 11931056 ps
CPU time 0.45 seconds
Started Apr 23 01:36:24 PM PDT 24
Finished Apr 23 01:36:25 PM PDT 24
Peak memory 145768 kb
Host smart-c107580f-2232-4b8f-89e0-db996ebcd174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250418525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3250418525
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3377305810
Short name T22
Test name
Test status
Simulation time 11868435 ps
CPU time 0.44 seconds
Started Apr 23 01:36:24 PM PDT 24
Finished Apr 23 01:36:25 PM PDT 24
Peak memory 145696 kb
Host smart-446b0138-13a7-4c38-be29-33a0235e6e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377305810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3377305810
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3289950919
Short name T16
Test name
Test status
Simulation time 11769669 ps
CPU time 0.4 seconds
Started Apr 23 01:36:25 PM PDT 24
Finished Apr 23 01:36:26 PM PDT 24
Peak memory 145704 kb
Host smart-be5f727d-0429-4c05-af57-710678c26d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289950919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3289950919
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2858354565
Short name T7
Test name
Test status
Simulation time 11151369 ps
CPU time 0.39 seconds
Started Apr 23 01:36:25 PM PDT 24
Finished Apr 23 01:36:26 PM PDT 24
Peak memory 145800 kb
Host smart-98bc276e-8f95-4aa0-9ca6-8c185aed4294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858354565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2858354565
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3002922682
Short name T47
Test name
Test status
Simulation time 11149553 ps
CPU time 0.42 seconds
Started Apr 23 01:36:27 PM PDT 24
Finished Apr 23 01:36:28 PM PDT 24
Peak memory 145704 kb
Host smart-b984a894-acd8-4118-afee-6853ee06bd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002922682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3002922682
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2473781184
Short name T19
Test name
Test status
Simulation time 10901574 ps
CPU time 0.42 seconds
Started Apr 23 01:36:25 PM PDT 24
Finished Apr 23 01:36:27 PM PDT 24
Peak memory 145772 kb
Host smart-4cd4535e-8b36-455b-be8b-7bfdf24066f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473781184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2473781184
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3708056753
Short name T44
Test name
Test status
Simulation time 30514589 ps
CPU time 0.44 seconds
Started Apr 23 01:36:30 PM PDT 24
Finished Apr 23 01:36:31 PM PDT 24
Peak memory 145800 kb
Host smart-24d4c4fd-bbce-42b1-9740-27e5a7b41513
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3708056753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3708056753
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.800651152
Short name T54
Test name
Test status
Simulation time 29905102 ps
CPU time 0.41 seconds
Started Apr 23 01:36:31 PM PDT 24
Finished Apr 23 01:36:31 PM PDT 24
Peak memory 145804 kb
Host smart-617cb427-5101-419c-8dcc-b237314477d5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=800651152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.800651152
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.926366233
Short name T41
Test name
Test status
Simulation time 29131192 ps
CPU time 0.42 seconds
Started Apr 23 01:36:33 PM PDT 24
Finished Apr 23 01:36:34 PM PDT 24
Peak memory 145720 kb
Host smart-e391a41f-e958-4428-b30a-fa4b245f453b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=926366233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.926366233
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1974578403
Short name T40
Test name
Test status
Simulation time 31578129 ps
CPU time 0.4 seconds
Started Apr 23 01:36:33 PM PDT 24
Finished Apr 23 01:36:33 PM PDT 24
Peak memory 145712 kb
Host smart-0bf1c8d6-f95e-42c4-9f4a-0826228a494d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1974578403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1974578403
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.665421705
Short name T51
Test name
Test status
Simulation time 28819297 ps
CPU time 0.38 seconds
Started Apr 23 01:36:27 PM PDT 24
Finished Apr 23 01:36:28 PM PDT 24
Peak memory 145672 kb
Host smart-3d6fe94c-3fd4-4dfb-8715-3568b78fe7f4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=665421705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.665421705
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3009981960
Short name T45
Test name
Test status
Simulation time 29713365 ps
CPU time 0.41 seconds
Started Apr 23 01:36:30 PM PDT 24
Finished Apr 23 01:36:31 PM PDT 24
Peak memory 145824 kb
Host smart-c301ae61-7edd-4c38-aaf9-25fa22c66879
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3009981960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3009981960
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1690113133
Short name T53
Test name
Test status
Simulation time 30673132 ps
CPU time 0.46 seconds
Started Apr 23 01:36:30 PM PDT 24
Finished Apr 23 01:36:31 PM PDT 24
Peak memory 145800 kb
Host smart-1868f6b0-5cfb-4b92-88bd-e6e103e738b5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1690113133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1690113133
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1680227222
Short name T57
Test name
Test status
Simulation time 27679660 ps
CPU time 0.4 seconds
Started Apr 23 01:36:34 PM PDT 24
Finished Apr 23 01:36:35 PM PDT 24
Peak memory 145724 kb
Host smart-1ff7efe4-60e0-4c6d-8e6b-d6aaa00acf5a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1680227222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1680227222
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2691031380
Short name T55
Test name
Test status
Simulation time 30293627 ps
CPU time 0.4 seconds
Started Apr 23 01:36:34 PM PDT 24
Finished Apr 23 01:36:35 PM PDT 24
Peak memory 145720 kb
Host smart-92f9a83a-ce17-4d9d-850f-8a5619c550b3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2691031380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2691031380
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1805301176
Short name T5
Test name
Test status
Simulation time 30692679 ps
CPU time 0.43 seconds
Started Apr 23 01:36:39 PM PDT 24
Finished Apr 23 01:36:40 PM PDT 24
Peak memory 145700 kb
Host smart-8ae4d760-95e9-4f53-b354-88b83ff7dcbe
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1805301176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1805301176
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.514035838
Short name T56
Test name
Test status
Simulation time 31492683 ps
CPU time 0.41 seconds
Started Apr 23 01:36:30 PM PDT 24
Finished Apr 23 01:36:30 PM PDT 24
Peak memory 145724 kb
Host smart-1eac9f6b-e662-43ca-ab12-447e4628d7ba
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=514035838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.514035838
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3437264004
Short name T43
Test name
Test status
Simulation time 30641800 ps
CPU time 0.41 seconds
Started Apr 23 01:36:28 PM PDT 24
Finished Apr 23 01:36:29 PM PDT 24
Peak memory 145812 kb
Host smart-a7e58e66-9292-468c-8741-041390f07a48
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3437264004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3437264004
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2043043107
Short name T50
Test name
Test status
Simulation time 28783282 ps
CPU time 0.47 seconds
Started Apr 23 01:36:31 PM PDT 24
Finished Apr 23 01:36:32 PM PDT 24
Peak memory 145696 kb
Host smart-a3e94d84-73c9-4b62-a5e9-c4425028732d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2043043107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2043043107
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3709032715
Short name T52
Test name
Test status
Simulation time 30069500 ps
CPU time 0.41 seconds
Started Apr 23 01:36:29 PM PDT 24
Finished Apr 23 01:36:30 PM PDT 24
Peak memory 145696 kb
Host smart-f913eeeb-e140-4f26-8c7d-ffa71ab42759
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3709032715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3709032715
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2362020239
Short name T24
Test name
Test status
Simulation time 29549853 ps
CPU time 0.42 seconds
Started Apr 23 01:36:33 PM PDT 24
Finished Apr 23 01:36:34 PM PDT 24
Peak memory 145720 kb
Host smart-4baa560c-c0f1-4dd7-89c8-b2cd1ae8fee7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2362020239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2362020239
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3004995287
Short name T25
Test name
Test status
Simulation time 30076540 ps
CPU time 0.39 seconds
Started Apr 23 01:36:29 PM PDT 24
Finished Apr 23 01:36:29 PM PDT 24
Peak memory 145808 kb
Host smart-a1b1dac6-8daf-4a0e-b643-8b8c404835e8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3004995287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3004995287
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2910890545
Short name T42
Test name
Test status
Simulation time 29047476 ps
CPU time 0.41 seconds
Started Apr 23 01:36:31 PM PDT 24
Finished Apr 23 01:36:32 PM PDT 24
Peak memory 145804 kb
Host smart-b5ef0f77-9b49-4517-b066-7a69708cd7b8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2910890545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2910890545
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3091354510
Short name T58
Test name
Test status
Simulation time 9904123 ps
CPU time 0.38 seconds
Started Apr 23 01:36:35 PM PDT 24
Finished Apr 23 01:36:36 PM PDT 24
Peak memory 145040 kb
Host smart-0686994e-91aa-4934-babc-39f7649e6fb6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3091354510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3091354510
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1862169811
Short name T60
Test name
Test status
Simulation time 9174710 ps
CPU time 0.39 seconds
Started Apr 23 01:36:34 PM PDT 24
Finished Apr 23 01:36:35 PM PDT 24
Peak memory 144984 kb
Host smart-0fe789de-eed8-42d9-bc55-bf018e08b6c3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1862169811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1862169811
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1382887660
Short name T33
Test name
Test status
Simulation time 9264376 ps
CPU time 0.38 seconds
Started Apr 23 01:36:36 PM PDT 24
Finished Apr 23 01:36:38 PM PDT 24
Peak memory 144984 kb
Host smart-568a390e-9cd9-445d-9353-5acd3b4e0b1b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1382887660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1382887660
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1562120395
Short name T15
Test name
Test status
Simulation time 9956806 ps
CPU time 0.4 seconds
Started Apr 23 01:36:35 PM PDT 24
Finished Apr 23 01:36:36 PM PDT 24
Peak memory 144988 kb
Host smart-d89538d1-94db-47d6-8de5-de42fead6c13
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1562120395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1562120395
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3050129353
Short name T32
Test name
Test status
Simulation time 9481507 ps
CPU time 0.38 seconds
Started Apr 23 01:36:36 PM PDT 24
Finished Apr 23 01:36:37 PM PDT 24
Peak memory 144956 kb
Host smart-d0e447c2-78fa-47a1-803a-b7f18d51b55d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3050129353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3050129353
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.911434077
Short name T62
Test name
Test status
Simulation time 8994205 ps
CPU time 0.38 seconds
Started Apr 23 01:36:34 PM PDT 24
Finished Apr 23 01:36:35 PM PDT 24
Peak memory 144988 kb
Host smart-193d0e83-2e8d-4159-b439-4a0c2ebb425b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=911434077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.911434077
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.268478287
Short name T36
Test name
Test status
Simulation time 8857196 ps
CPU time 0.37 seconds
Started Apr 23 01:36:39 PM PDT 24
Finished Apr 23 01:36:40 PM PDT 24
Peak memory 145068 kb
Host smart-8002833c-2f1d-4843-9455-ecc088a03e5b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=268478287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.268478287
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.638854422
Short name T61
Test name
Test status
Simulation time 10462762 ps
CPU time 0.43 seconds
Started Apr 23 01:36:36 PM PDT 24
Finished Apr 23 01:36:37 PM PDT 24
Peak memory 145000 kb
Host smart-64ce5a63-e9b5-4acf-802b-f9325373e21c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=638854422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.638854422
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2732552656
Short name T29
Test name
Test status
Simulation time 8914352 ps
CPU time 0.4 seconds
Started Apr 23 01:36:35 PM PDT 24
Finished Apr 23 01:36:37 PM PDT 24
Peak memory 145024 kb
Host smart-2c42603f-de21-49d5-938d-ca4c18e291aa
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2732552656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2732552656
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2967877259
Short name T27
Test name
Test status
Simulation time 9504311 ps
CPU time 0.4 seconds
Started Apr 23 01:36:39 PM PDT 24
Finished Apr 23 01:36:40 PM PDT 24
Peak memory 144964 kb
Host smart-080d5c31-e37f-40c9-be93-783fb76be411
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2967877259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2967877259
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2225895333
Short name T34
Test name
Test status
Simulation time 8834788 ps
CPU time 0.38 seconds
Started Apr 23 01:36:41 PM PDT 24
Finished Apr 23 01:36:42 PM PDT 24
Peak memory 144992 kb
Host smart-f43e12a9-4c18-4d11-b50a-68e20a06f425
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2225895333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2225895333
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1597190814
Short name T31
Test name
Test status
Simulation time 9412690 ps
CPU time 0.39 seconds
Started Apr 23 01:36:40 PM PDT 24
Finished Apr 23 01:36:41 PM PDT 24
Peak memory 144972 kb
Host smart-f2b5eb95-5006-4fe8-bbfc-54997048e3ec
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1597190814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1597190814
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1689672978
Short name T38
Test name
Test status
Simulation time 8339497 ps
CPU time 0.37 seconds
Started Apr 23 01:36:36 PM PDT 24
Finished Apr 23 01:36:37 PM PDT 24
Peak memory 145068 kb
Host smart-89ebcdf7-fcdc-4e39-8567-f811287d2f8d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1689672978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1689672978
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.554299767
Short name T28
Test name
Test status
Simulation time 9086855 ps
CPU time 0.38 seconds
Started Apr 23 01:36:33 PM PDT 24
Finished Apr 23 01:36:34 PM PDT 24
Peak memory 144996 kb
Host smart-5b33edd6-e517-41eb-ac1a-dd4bac11dfb6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=554299767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.554299767
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1848501293
Short name T30
Test name
Test status
Simulation time 9780353 ps
CPU time 0.39 seconds
Started Apr 23 01:36:41 PM PDT 24
Finished Apr 23 01:36:42 PM PDT 24
Peak memory 144956 kb
Host smart-a429d451-7f84-402c-8962-75579dddac38
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1848501293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1848501293
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3860963955
Short name T37
Test name
Test status
Simulation time 9959100 ps
CPU time 0.4 seconds
Started Apr 23 01:36:37 PM PDT 24
Finished Apr 23 01:36:38 PM PDT 24
Peak memory 144984 kb
Host smart-f2c399f7-0c85-424c-9178-13ca1d9132d7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3860963955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3860963955
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1661139643
Short name T39
Test name
Test status
Simulation time 8974583 ps
CPU time 0.4 seconds
Started Apr 23 01:36:34 PM PDT 24
Finished Apr 23 01:36:35 PM PDT 24
Peak memory 145052 kb
Host smart-4b7169a8-4354-4a40-b70f-94b529504bc5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1661139643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1661139643
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2254867265
Short name T59
Test name
Test status
Simulation time 9304368 ps
CPU time 0.37 seconds
Started Apr 23 01:36:34 PM PDT 24
Finished Apr 23 01:36:35 PM PDT 24
Peak memory 144988 kb
Host smart-9f4e84e3-7a2e-40a4-b39e-1bd115f1d6aa
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2254867265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2254867265
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3866086512
Short name T14
Test name
Test status
Simulation time 9999349 ps
CPU time 0.39 seconds
Started Apr 23 01:36:39 PM PDT 24
Finished Apr 23 01:36:40 PM PDT 24
Peak memory 144964 kb
Host smart-08b7016b-40d5-4963-8b0e-5f705fd7e523
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3866086512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3866086512
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2929912540
Short name T73
Test name
Test status
Simulation time 25776305 ps
CPU time 0.4 seconds
Started Apr 23 01:36:41 PM PDT 24
Finished Apr 23 01:36:42 PM PDT 24
Peak memory 145084 kb
Host smart-7e9be536-682b-4877-8355-d950b7264eb0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2929912540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2929912540
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.506593831
Short name T68
Test name
Test status
Simulation time 26028380 ps
CPU time 0.41 seconds
Started Apr 23 01:36:39 PM PDT 24
Finished Apr 23 01:36:40 PM PDT 24
Peak memory 144968 kb
Host smart-20ad5189-2e34-4457-871b-530a8c555d2f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=506593831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.506593831
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.891828706
Short name T35
Test name
Test status
Simulation time 26942596 ps
CPU time 0.39 seconds
Started Apr 23 01:36:39 PM PDT 24
Finished Apr 23 01:36:40 PM PDT 24
Peak memory 144940 kb
Host smart-a4b8e19f-4255-4616-8eb8-6e68bb40a2b2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=891828706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.891828706
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3780730288
Short name T75
Test name
Test status
Simulation time 26269852 ps
CPU time 0.41 seconds
Started Apr 23 01:36:37 PM PDT 24
Finished Apr 23 01:36:38 PM PDT 24
Peak memory 144988 kb
Host smart-36b1cecc-d09d-40ce-b3e8-6455e7927dff
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3780730288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3780730288
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2989950217
Short name T79
Test name
Test status
Simulation time 27269530 ps
CPU time 0.38 seconds
Started Apr 23 01:36:42 PM PDT 24
Finished Apr 23 01:36:43 PM PDT 24
Peak memory 145068 kb
Host smart-338ff9b7-60cd-4e45-9b29-2363dc2d4ee6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2989950217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2989950217
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2922324080
Short name T63
Test name
Test status
Simulation time 27662066 ps
CPU time 0.4 seconds
Started Apr 23 01:36:43 PM PDT 24
Finished Apr 23 01:36:44 PM PDT 24
Peak memory 144992 kb
Host smart-d1100c9b-2c1a-4d8d-8387-5a255864650f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2922324080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2922324080
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.970221443
Short name T69
Test name
Test status
Simulation time 26115303 ps
CPU time 0.4 seconds
Started Apr 23 01:36:40 PM PDT 24
Finished Apr 23 01:36:41 PM PDT 24
Peak memory 145040 kb
Host smart-61f0bf09-1b09-465a-a100-fc5e150b6b67
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=970221443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.970221443
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3414949494
Short name T6
Test name
Test status
Simulation time 27326917 ps
CPU time 0.4 seconds
Started Apr 23 01:36:42 PM PDT 24
Finished Apr 23 01:36:43 PM PDT 24
Peak memory 144964 kb
Host smart-dfb58f3b-d47e-4353-9b30-0999ecd82ff1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3414949494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3414949494
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1655250893
Short name T76
Test name
Test status
Simulation time 26966285 ps
CPU time 0.4 seconds
Started Apr 23 01:36:38 PM PDT 24
Finished Apr 23 01:36:39 PM PDT 24
Peak memory 144972 kb
Host smart-b98ef0b3-9459-496a-8a8f-7e721da87e56
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1655250893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1655250893
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1487954813
Short name T71
Test name
Test status
Simulation time 27011293 ps
CPU time 0.42 seconds
Started Apr 23 01:36:39 PM PDT 24
Finished Apr 23 01:36:41 PM PDT 24
Peak memory 145060 kb
Host smart-45ff7d80-4d64-44b8-afe2-6b2de8254b3d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1487954813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1487954813
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4032130472
Short name T74
Test name
Test status
Simulation time 28532438 ps
CPU time 0.39 seconds
Started Apr 23 01:36:39 PM PDT 24
Finished Apr 23 01:36:39 PM PDT 24
Peak memory 144896 kb
Host smart-16cc8114-b3ee-4ea7-88c6-ca87bd7b0b83
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4032130472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4032130472
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1450775398
Short name T72
Test name
Test status
Simulation time 26514830 ps
CPU time 0.43 seconds
Started Apr 23 01:36:37 PM PDT 24
Finished Apr 23 01:36:38 PM PDT 24
Peak memory 144964 kb
Host smart-30f92f6a-4dc6-49a1-ac0b-59fa331f641d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1450775398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1450775398
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1056381977
Short name T64
Test name
Test status
Simulation time 25721204 ps
CPU time 0.4 seconds
Started Apr 23 01:36:39 PM PDT 24
Finished Apr 23 01:36:41 PM PDT 24
Peak memory 145064 kb
Host smart-7b285895-9ed4-41d1-8f01-ccb339ee591e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1056381977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1056381977
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.976053040
Short name T65
Test name
Test status
Simulation time 27902868 ps
CPU time 0.4 seconds
Started Apr 23 01:36:41 PM PDT 24
Finished Apr 23 01:36:42 PM PDT 24
Peak memory 144984 kb
Host smart-98d98156-134a-4276-92ce-49c26b193032
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=976053040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.976053040
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.165673757
Short name T67
Test name
Test status
Simulation time 27614557 ps
CPU time 0.39 seconds
Started Apr 23 01:36:36 PM PDT 24
Finished Apr 23 01:36:37 PM PDT 24
Peak memory 144968 kb
Host smart-13208a81-0011-4a0c-b264-27a1fa3e24dd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=165673757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.165673757
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2153445286
Short name T78
Test name
Test status
Simulation time 25290735 ps
CPU time 0.41 seconds
Started Apr 23 01:36:41 PM PDT 24
Finished Apr 23 01:36:42 PM PDT 24
Peak memory 145064 kb
Host smart-497d4984-e44f-4f14-8d1d-aa4459f84dfc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2153445286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2153445286
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2062298456
Short name T70
Test name
Test status
Simulation time 29241734 ps
CPU time 0.4 seconds
Started Apr 23 01:36:41 PM PDT 24
Finished Apr 23 01:36:42 PM PDT 24
Peak memory 145008 kb
Host smart-e931495b-6c32-40fb-aeb5-695e07ae2c60
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2062298456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2062298456
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3666017237
Short name T66
Test name
Test status
Simulation time 28258720 ps
CPU time 0.4 seconds
Started Apr 23 01:36:41 PM PDT 24
Finished Apr 23 01:36:42 PM PDT 24
Peak memory 144964 kb
Host smart-76e87980-d6c8-49d2-8b01-918c4d205481
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3666017237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3666017237
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3461005760
Short name T77
Test name
Test status
Simulation time 27378854 ps
CPU time 0.38 seconds
Started Apr 23 01:36:38 PM PDT 24
Finished Apr 23 01:36:39 PM PDT 24
Peak memory 144956 kb
Host smart-3be54754-2358-4300-8752-cc86437888b5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3461005760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3461005760
Directory /workspace/9.prim_sync_fatal_alert/latest
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