Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.53 88.53 100.00 100.00 91.67 91.67 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/13.prim_async_alert.3145936188
91.76 3.23 100.00 0.00 95.83 4.17 100.00 0.00 82.14 3.57 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/7.prim_sync_alert.2014961089
93.52 1.76 100.00 0.00 95.83 0.00 100.00 0.00 85.71 3.57 95.83 0.00 83.72 6.98 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4034985079
94.50 0.98 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 2.33 /workspace/coverage/default/1.prim_async_alert.2077779126
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3105312359
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.462311394

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2762806198
/workspace/coverage/default/10.prim_async_alert.3440100659
/workspace/coverage/default/11.prim_async_alert.589685663
/workspace/coverage/default/12.prim_async_alert.2324749292
/workspace/coverage/default/14.prim_async_alert.2289473633
/workspace/coverage/default/15.prim_async_alert.1052667598
/workspace/coverage/default/16.prim_async_alert.3622168038
/workspace/coverage/default/17.prim_async_alert.3476021285
/workspace/coverage/default/18.prim_async_alert.3055484717
/workspace/coverage/default/19.prim_async_alert.1440725559
/workspace/coverage/default/2.prim_async_alert.384538880
/workspace/coverage/default/3.prim_async_alert.2596701442
/workspace/coverage/default/4.prim_async_alert.673369635
/workspace/coverage/default/5.prim_async_alert.421166399
/workspace/coverage/default/6.prim_async_alert.3124838918
/workspace/coverage/default/7.prim_async_alert.3719005567
/workspace/coverage/default/8.prim_async_alert.1386420363
/workspace/coverage/default/9.prim_async_alert.2556291405
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4286334648
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.245003081
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2093748453
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2274205588
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3289157589
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3052210954
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.28991010
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3784582727
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2282141713
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3167444283
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4047449223
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3396683010
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2309466123
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1239919622
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2040174574
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1677985132
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2128609036
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1798703714
/workspace/coverage/sync_alert/0.prim_sync_alert.1977095314
/workspace/coverage/sync_alert/1.prim_sync_alert.3389750659
/workspace/coverage/sync_alert/10.prim_sync_alert.2304717736
/workspace/coverage/sync_alert/11.prim_sync_alert.4043322293
/workspace/coverage/sync_alert/12.prim_sync_alert.3866561184
/workspace/coverage/sync_alert/13.prim_sync_alert.382933746
/workspace/coverage/sync_alert/14.prim_sync_alert.2904088962
/workspace/coverage/sync_alert/15.prim_sync_alert.3023227117
/workspace/coverage/sync_alert/16.prim_sync_alert.3122616116
/workspace/coverage/sync_alert/17.prim_sync_alert.936869382
/workspace/coverage/sync_alert/18.prim_sync_alert.3107952864
/workspace/coverage/sync_alert/19.prim_sync_alert.2604251549
/workspace/coverage/sync_alert/2.prim_sync_alert.1575833703
/workspace/coverage/sync_alert/3.prim_sync_alert.2317634006
/workspace/coverage/sync_alert/4.prim_sync_alert.2928439131
/workspace/coverage/sync_alert/5.prim_sync_alert.565993084
/workspace/coverage/sync_alert/6.prim_sync_alert.2539876395
/workspace/coverage/sync_alert/8.prim_sync_alert.2216956834
/workspace/coverage/sync_alert/9.prim_sync_alert.3661892792
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4245724509
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1864452240
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.730070826
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2876368764
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1437175581
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2210635170
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1442017614
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1641748283
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2852009095
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2799367430
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3116345632
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4162059014
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3921313009
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2932714596
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2088198216
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2095453228
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3823893717
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.991814655
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.987562416



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/15.prim_async_alert.1052667598 Apr 25 12:39:46 PM PDT 24 Apr 25 12:39:48 PM PDT 24 11202885 ps
T2 /workspace/coverage/default/14.prim_async_alert.2289473633 Apr 25 12:39:42 PM PDT 24 Apr 25 12:39:44 PM PDT 24 11466782 ps
T3 /workspace/coverage/default/5.prim_async_alert.421166399 Apr 25 12:39:40 PM PDT 24 Apr 25 12:39:42 PM PDT 24 11079699 ps
T5 /workspace/coverage/default/18.prim_async_alert.3055484717 Apr 25 12:39:45 PM PDT 24 Apr 25 12:39:47 PM PDT 24 11523209 ps
T10 /workspace/coverage/default/13.prim_async_alert.3145936188 Apr 25 12:39:39 PM PDT 24 Apr 25 12:39:41 PM PDT 24 12125662 ps
T12 /workspace/coverage/default/1.prim_async_alert.2077779126 Apr 25 12:39:48 PM PDT 24 Apr 25 12:39:51 PM PDT 24 10454985 ps
T14 /workspace/coverage/default/8.prim_async_alert.1386420363 Apr 25 12:39:40 PM PDT 24 Apr 25 12:39:42 PM PDT 24 11092716 ps
T8 /workspace/coverage/default/10.prim_async_alert.3440100659 Apr 25 12:39:50 PM PDT 24 Apr 25 12:39:53 PM PDT 24 11418123 ps
T13 /workspace/coverage/default/11.prim_async_alert.589685663 Apr 25 12:39:39 PM PDT 24 Apr 25 12:39:40 PM PDT 24 11542965 ps
T6 /workspace/coverage/default/4.prim_async_alert.673369635 Apr 25 12:39:41 PM PDT 24 Apr 25 12:39:43 PM PDT 24 11470447 ps
T11 /workspace/coverage/default/2.prim_async_alert.384538880 Apr 25 12:39:52 PM PDT 24 Apr 25 12:39:55 PM PDT 24 12267177 ps
T7 /workspace/coverage/default/17.prim_async_alert.3476021285 Apr 25 12:39:47 PM PDT 24 Apr 25 12:39:50 PM PDT 24 11980282 ps
T15 /workspace/coverage/default/9.prim_async_alert.2556291405 Apr 25 12:39:47 PM PDT 24 Apr 25 12:39:50 PM PDT 24 11891731 ps
T16 /workspace/coverage/default/16.prim_async_alert.3622168038 Apr 25 12:39:48 PM PDT 24 Apr 25 12:39:51 PM PDT 24 11632529 ps
T17 /workspace/coverage/default/3.prim_async_alert.2596701442 Apr 25 12:39:39 PM PDT 24 Apr 25 12:39:41 PM PDT 24 11197675 ps
T44 /workspace/coverage/default/7.prim_async_alert.3719005567 Apr 25 12:39:46 PM PDT 24 Apr 25 12:39:49 PM PDT 24 11641337 ps
T45 /workspace/coverage/default/6.prim_async_alert.3124838918 Apr 25 12:39:47 PM PDT 24 Apr 25 12:39:49 PM PDT 24 12191160 ps
T46 /workspace/coverage/default/19.prim_async_alert.1440725559 Apr 25 12:39:43 PM PDT 24 Apr 25 12:39:44 PM PDT 24 11210409 ps
T47 /workspace/coverage/default/0.prim_async_alert.2762806198 Apr 25 12:39:42 PM PDT 24 Apr 25 12:39:44 PM PDT 24 11377072 ps
T18 /workspace/coverage/default/12.prim_async_alert.2324749292 Apr 25 12:39:42 PM PDT 24 Apr 25 12:39:44 PM PDT 24 12389129 ps
T38 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.28991010 Apr 25 12:38:37 PM PDT 24 Apr 25 12:38:39 PM PDT 24 31438621 ps
T4 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3105312359 Apr 25 12:38:35 PM PDT 24 Apr 25 12:38:36 PM PDT 24 30343196 ps
T39 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4034985079 Apr 25 12:38:31 PM PDT 24 Apr 25 12:38:33 PM PDT 24 30315589 ps
T19 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2040174574 Apr 25 12:38:57 PM PDT 24 Apr 25 12:38:59 PM PDT 24 29544915 ps
T40 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3396683010 Apr 25 12:38:31 PM PDT 24 Apr 25 12:38:33 PM PDT 24 30547268 ps
T20 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3167444283 Apr 25 12:38:33 PM PDT 24 Apr 25 12:38:34 PM PDT 24 30164141 ps
T41 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.245003081 Apr 25 12:38:32 PM PDT 24 Apr 25 12:38:33 PM PDT 24 29339711 ps
T42 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1239919622 Apr 25 12:38:34 PM PDT 24 Apr 25 12:38:35 PM PDT 24 32446935 ps
T21 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2282141713 Apr 25 12:38:35 PM PDT 24 Apr 25 12:38:36 PM PDT 24 31032078 ps
T43 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2274205588 Apr 25 12:38:29 PM PDT 24 Apr 25 12:38:32 PM PDT 24 30373434 ps
T48 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2128609036 Apr 25 12:38:26 PM PDT 24 Apr 25 12:38:28 PM PDT 24 30755258 ps
T49 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3784582727 Apr 25 12:38:35 PM PDT 24 Apr 25 12:38:36 PM PDT 24 30413938 ps
T50 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4286334648 Apr 25 12:38:28 PM PDT 24 Apr 25 12:38:29 PM PDT 24 28498694 ps
T51 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3289157589 Apr 25 12:38:46 PM PDT 24 Apr 25 12:38:48 PM PDT 24 29903710 ps
T52 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1798703714 Apr 25 12:38:36 PM PDT 24 Apr 25 12:38:37 PM PDT 24 29069592 ps
T53 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2093748453 Apr 25 12:38:27 PM PDT 24 Apr 25 12:38:29 PM PDT 24 29449197 ps
T54 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1677985132 Apr 25 12:38:31 PM PDT 24 Apr 25 12:38:33 PM PDT 24 29860780 ps
T55 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4047449223 Apr 25 12:38:42 PM PDT 24 Apr 25 12:38:43 PM PDT 24 28946485 ps
T56 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2309466123 Apr 25 12:38:30 PM PDT 24 Apr 25 12:38:33 PM PDT 24 27673048 ps
T57 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3052210954 Apr 25 12:38:52 PM PDT 24 Apr 25 12:38:54 PM PDT 24 30746818 ps
T22 /workspace/coverage/sync_alert/19.prim_sync_alert.2604251549 Apr 25 12:39:45 PM PDT 24 Apr 25 12:39:47 PM PDT 24 9540358 ps
T23 /workspace/coverage/sync_alert/11.prim_sync_alert.4043322293 Apr 25 12:39:56 PM PDT 24 Apr 25 12:39:58 PM PDT 24 8993433 ps
T32 /workspace/coverage/sync_alert/7.prim_sync_alert.2014961089 Apr 25 12:39:41 PM PDT 24 Apr 25 12:39:43 PM PDT 24 8484972 ps
T33 /workspace/coverage/sync_alert/5.prim_sync_alert.565993084 Apr 25 12:39:45 PM PDT 24 Apr 25 12:39:46 PM PDT 24 9328966 ps
T34 /workspace/coverage/sync_alert/13.prim_sync_alert.382933746 Apr 25 12:39:46 PM PDT 24 Apr 25 12:39:49 PM PDT 24 9041844 ps
T35 /workspace/coverage/sync_alert/6.prim_sync_alert.2539876395 Apr 25 12:39:41 PM PDT 24 Apr 25 12:39:43 PM PDT 24 9839089 ps
T24 /workspace/coverage/sync_alert/2.prim_sync_alert.1575833703 Apr 25 12:39:39 PM PDT 24 Apr 25 12:39:41 PM PDT 24 9566799 ps
T36 /workspace/coverage/sync_alert/8.prim_sync_alert.2216956834 Apr 25 12:39:50 PM PDT 24 Apr 25 12:39:53 PM PDT 24 9037047 ps
T37 /workspace/coverage/sync_alert/3.prim_sync_alert.2317634006 Apr 25 12:39:41 PM PDT 24 Apr 25 12:39:43 PM PDT 24 9657379 ps
T25 /workspace/coverage/sync_alert/1.prim_sync_alert.3389750659 Apr 25 12:39:49 PM PDT 24 Apr 25 12:39:52 PM PDT 24 10232957 ps
T58 /workspace/coverage/sync_alert/4.prim_sync_alert.2928439131 Apr 25 12:39:46 PM PDT 24 Apr 25 12:39:47 PM PDT 24 10741214 ps
T59 /workspace/coverage/sync_alert/10.prim_sync_alert.2304717736 Apr 25 12:39:46 PM PDT 24 Apr 25 12:39:48 PM PDT 24 8585631 ps
T26 /workspace/coverage/sync_alert/12.prim_sync_alert.3866561184 Apr 25 12:39:46 PM PDT 24 Apr 25 12:39:48 PM PDT 24 8691526 ps
T60 /workspace/coverage/sync_alert/9.prim_sync_alert.3661892792 Apr 25 12:39:46 PM PDT 24 Apr 25 12:39:48 PM PDT 24 8758696 ps
T27 /workspace/coverage/sync_alert/17.prim_sync_alert.936869382 Apr 25 12:40:09 PM PDT 24 Apr 25 12:40:11 PM PDT 24 9157340 ps
T61 /workspace/coverage/sync_alert/15.prim_sync_alert.3023227117 Apr 25 12:39:51 PM PDT 24 Apr 25 12:39:54 PM PDT 24 10148018 ps
T28 /workspace/coverage/sync_alert/16.prim_sync_alert.3122616116 Apr 25 12:39:54 PM PDT 24 Apr 25 12:39:57 PM PDT 24 9097232 ps
T62 /workspace/coverage/sync_alert/14.prim_sync_alert.2904088962 Apr 25 12:39:48 PM PDT 24 Apr 25 12:39:51 PM PDT 24 9273725 ps
T29 /workspace/coverage/sync_alert/18.prim_sync_alert.3107952864 Apr 25 12:39:50 PM PDT 24 Apr 25 12:39:53 PM PDT 24 9543949 ps
T63 /workspace/coverage/sync_alert/0.prim_sync_alert.1977095314 Apr 25 12:39:47 PM PDT 24 Apr 25 12:39:49 PM PDT 24 8982248 ps
T30 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2210635170 Apr 25 12:39:50 PM PDT 24 Apr 25 12:39:53 PM PDT 24 25611951 ps
T31 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3116345632 Apr 25 12:39:47 PM PDT 24 Apr 25 12:39:50 PM PDT 24 27046349 ps
T64 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4162059014 Apr 25 12:39:51 PM PDT 24 Apr 25 12:39:54 PM PDT 24 26906862 ps
T65 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3823893717 Apr 25 12:39:47 PM PDT 24 Apr 25 12:39:49 PM PDT 24 27496986 ps
T66 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.987562416 Apr 25 12:39:50 PM PDT 24 Apr 25 12:39:53 PM PDT 24 27772584 ps
T67 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2088198216 Apr 25 12:39:58 PM PDT 24 Apr 25 12:40:00 PM PDT 24 28695185 ps
T68 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2095453228 Apr 25 12:39:55 PM PDT 24 Apr 25 12:39:57 PM PDT 24 28167357 ps
T69 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1437175581 Apr 25 12:40:06 PM PDT 24 Apr 25 12:40:08 PM PDT 24 29272553 ps
T70 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4245724509 Apr 25 12:39:51 PM PDT 24 Apr 25 12:39:54 PM PDT 24 29421330 ps
T71 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2852009095 Apr 25 12:39:49 PM PDT 24 Apr 25 12:39:52 PM PDT 24 26762094 ps
T72 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.730070826 Apr 25 12:39:51 PM PDT 24 Apr 25 12:39:54 PM PDT 24 27849954 ps
T73 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2932714596 Apr 25 12:39:46 PM PDT 24 Apr 25 12:39:49 PM PDT 24 26819154 ps
T74 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2799367430 Apr 25 12:39:58 PM PDT 24 Apr 25 12:39:59 PM PDT 24 27870470 ps
T75 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1864452240 Apr 25 12:39:51 PM PDT 24 Apr 25 12:39:54 PM PDT 24 28450206 ps
T76 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3921313009 Apr 25 12:40:40 PM PDT 24 Apr 25 12:40:42 PM PDT 24 27880575 ps
T77 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2876368764 Apr 25 12:39:50 PM PDT 24 Apr 25 12:39:53 PM PDT 24 24383799 ps
T9 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.462311394 Apr 25 12:39:49 PM PDT 24 Apr 25 12:39:52 PM PDT 24 27555148 ps
T78 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.991814655 Apr 25 12:39:50 PM PDT 24 Apr 25 12:39:53 PM PDT 24 26972636 ps
T79 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1442017614 Apr 25 12:39:48 PM PDT 24 Apr 25 12:39:50 PM PDT 24 25196808 ps
T80 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1641748283 Apr 25 12:39:52 PM PDT 24 Apr 25 12:39:55 PM PDT 24 27408306 ps

Test location /workspace/coverage/default/13.prim_async_alert.3145936188
Short name T10
Test name
Test status
Simulation time 12125662 ps
CPU time 0.41 seconds
Started Apr 25 12:39:39 PM PDT 24
Finished Apr 25 12:39:41 PM PDT 24
Peak memory 145788 kb
Host smart-b5005493-6a69-4829-88f9-28e89ddacceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145936188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3145936188
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2014961089
Short name T32
Test name
Test status
Simulation time 8484972 ps
CPU time 0.38 seconds
Started Apr 25 12:39:41 PM PDT 24
Finished Apr 25 12:39:43 PM PDT 24
Peak memory 145496 kb
Host smart-e04f76ac-ee6e-4e7c-a68b-82369c7d2bc8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2014961089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2014961089
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4034985079
Short name T39
Test name
Test status
Simulation time 30315589 ps
CPU time 0.4 seconds
Started Apr 25 12:38:31 PM PDT 24
Finished Apr 25 12:38:33 PM PDT 24
Peak memory 145628 kb
Host smart-445973e5-0925-4d04-ab76-7dac38f10164
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4034985079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4034985079
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2077779126
Short name T12
Test name
Test status
Simulation time 10454985 ps
CPU time 0.38 seconds
Started Apr 25 12:39:48 PM PDT 24
Finished Apr 25 12:39:51 PM PDT 24
Peak memory 145732 kb
Host smart-68754f5c-3d6b-4d7d-b259-417fc3150cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077779126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2077779126
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3105312359
Short name T4
Test name
Test status
Simulation time 30343196 ps
CPU time 0.41 seconds
Started Apr 25 12:38:35 PM PDT 24
Finished Apr 25 12:38:36 PM PDT 24
Peak memory 145816 kb
Host smart-9a5c2665-e705-4b57-beb5-77605e1c9285
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3105312359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3105312359
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.462311394
Short name T9
Test name
Test status
Simulation time 27555148 ps
CPU time 0.4 seconds
Started Apr 25 12:39:49 PM PDT 24
Finished Apr 25 12:39:52 PM PDT 24
Peak memory 145572 kb
Host smart-177480a0-9f31-4df6-9d0a-acc9078df94f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=462311394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.462311394
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2762806198
Short name T47
Test name
Test status
Simulation time 11377072 ps
CPU time 0.39 seconds
Started Apr 25 12:39:42 PM PDT 24
Finished Apr 25 12:39:44 PM PDT 24
Peak memory 145708 kb
Host smart-05dff7aa-c7f9-45e5-9a3b-6f26d25f11b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762806198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2762806198
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3440100659
Short name T8
Test name
Test status
Simulation time 11418123 ps
CPU time 0.39 seconds
Started Apr 25 12:39:50 PM PDT 24
Finished Apr 25 12:39:53 PM PDT 24
Peak memory 145740 kb
Host smart-5103004d-3246-46ab-b943-7d3180a22085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440100659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3440100659
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.589685663
Short name T13
Test name
Test status
Simulation time 11542965 ps
CPU time 0.39 seconds
Started Apr 25 12:39:39 PM PDT 24
Finished Apr 25 12:39:40 PM PDT 24
Peak memory 145796 kb
Host smart-9ecb2a5b-3e9e-47ac-8002-9920e3e0a4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589685663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.589685663
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2324749292
Short name T18
Test name
Test status
Simulation time 12389129 ps
CPU time 0.4 seconds
Started Apr 25 12:39:42 PM PDT 24
Finished Apr 25 12:39:44 PM PDT 24
Peak memory 145812 kb
Host smart-dad30268-a8b3-425d-b069-05a2bca95e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324749292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2324749292
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2289473633
Short name T2
Test name
Test status
Simulation time 11466782 ps
CPU time 0.39 seconds
Started Apr 25 12:39:42 PM PDT 24
Finished Apr 25 12:39:44 PM PDT 24
Peak memory 145812 kb
Host smart-f9acd921-9819-4862-8ff7-7dba6624f7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289473633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2289473633
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1052667598
Short name T1
Test name
Test status
Simulation time 11202885 ps
CPU time 0.4 seconds
Started Apr 25 12:39:46 PM PDT 24
Finished Apr 25 12:39:48 PM PDT 24
Peak memory 145628 kb
Host smart-de4cb55f-5ad4-4db3-94db-63bd745cd231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052667598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1052667598
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3622168038
Short name T16
Test name
Test status
Simulation time 11632529 ps
CPU time 0.39 seconds
Started Apr 25 12:39:48 PM PDT 24
Finished Apr 25 12:39:51 PM PDT 24
Peak memory 145756 kb
Host smart-964ceb16-1140-422a-967d-9010049d8b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622168038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3622168038
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3476021285
Short name T7
Test name
Test status
Simulation time 11980282 ps
CPU time 0.38 seconds
Started Apr 25 12:39:47 PM PDT 24
Finished Apr 25 12:39:50 PM PDT 24
Peak memory 145740 kb
Host smart-8448b88a-195a-4b00-bac7-8bf34ae6e0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476021285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3476021285
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3055484717
Short name T5
Test name
Test status
Simulation time 11523209 ps
CPU time 0.39 seconds
Started Apr 25 12:39:45 PM PDT 24
Finished Apr 25 12:39:47 PM PDT 24
Peak memory 145688 kb
Host smart-c837755e-f9a0-47b8-9002-f7e79f3f6d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055484717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3055484717
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1440725559
Short name T46
Test name
Test status
Simulation time 11210409 ps
CPU time 0.38 seconds
Started Apr 25 12:39:43 PM PDT 24
Finished Apr 25 12:39:44 PM PDT 24
Peak memory 145796 kb
Host smart-da6a0229-d128-401d-8cd1-c5bf47a19302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440725559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1440725559
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.384538880
Short name T11
Test name
Test status
Simulation time 12267177 ps
CPU time 0.44 seconds
Started Apr 25 12:39:52 PM PDT 24
Finished Apr 25 12:39:55 PM PDT 24
Peak memory 145700 kb
Host smart-0eda7a4a-c0c4-430a-995a-ec07660f718f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384538880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.384538880
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2596701442
Short name T17
Test name
Test status
Simulation time 11197675 ps
CPU time 0.38 seconds
Started Apr 25 12:39:39 PM PDT 24
Finished Apr 25 12:39:41 PM PDT 24
Peak memory 145684 kb
Host smart-e842bc59-6cca-490f-a7c9-a7fee5043e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596701442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2596701442
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.673369635
Short name T6
Test name
Test status
Simulation time 11470447 ps
CPU time 0.43 seconds
Started Apr 25 12:39:41 PM PDT 24
Finished Apr 25 12:39:43 PM PDT 24
Peak memory 145792 kb
Host smart-181a6cc4-ef8c-4385-8893-370f169297b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673369635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.673369635
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.421166399
Short name T3
Test name
Test status
Simulation time 11079699 ps
CPU time 0.41 seconds
Started Apr 25 12:39:40 PM PDT 24
Finished Apr 25 12:39:42 PM PDT 24
Peak memory 145748 kb
Host smart-18468c6b-d8ba-4e93-9f10-667009266062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421166399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.421166399
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3124838918
Short name T45
Test name
Test status
Simulation time 12191160 ps
CPU time 0.38 seconds
Started Apr 25 12:39:47 PM PDT 24
Finished Apr 25 12:39:49 PM PDT 24
Peak memory 145804 kb
Host smart-b29c7ff8-f959-4ae4-bfe2-b2dfd2fef01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124838918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3124838918
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3719005567
Short name T44
Test name
Test status
Simulation time 11641337 ps
CPU time 0.38 seconds
Started Apr 25 12:39:46 PM PDT 24
Finished Apr 25 12:39:49 PM PDT 24
Peak memory 145712 kb
Host smart-98cce29d-19b7-497d-a87a-26130bff1719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719005567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3719005567
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1386420363
Short name T14
Test name
Test status
Simulation time 11092716 ps
CPU time 0.4 seconds
Started Apr 25 12:39:40 PM PDT 24
Finished Apr 25 12:39:42 PM PDT 24
Peak memory 145644 kb
Host smart-61a28866-61cd-414a-89ab-d05a5f33b7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386420363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1386420363
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2556291405
Short name T15
Test name
Test status
Simulation time 11891731 ps
CPU time 0.43 seconds
Started Apr 25 12:39:47 PM PDT 24
Finished Apr 25 12:39:50 PM PDT 24
Peak memory 145804 kb
Host smart-62cd2566-3bc9-4c16-a38e-fbc39d44f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556291405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2556291405
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4286334648
Short name T50
Test name
Test status
Simulation time 28498694 ps
CPU time 0.46 seconds
Started Apr 25 12:38:28 PM PDT 24
Finished Apr 25 12:38:29 PM PDT 24
Peak memory 145704 kb
Host smart-9939d283-e1b3-4cbe-b8af-f0149768ae22
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4286334648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.4286334648
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.245003081
Short name T41
Test name
Test status
Simulation time 29339711 ps
CPU time 0.39 seconds
Started Apr 25 12:38:32 PM PDT 24
Finished Apr 25 12:38:33 PM PDT 24
Peak memory 145708 kb
Host smart-3a3b867e-d49f-4c6e-b73b-29cba63e9952
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=245003081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.245003081
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2093748453
Short name T53
Test name
Test status
Simulation time 29449197 ps
CPU time 0.4 seconds
Started Apr 25 12:38:27 PM PDT 24
Finished Apr 25 12:38:29 PM PDT 24
Peak memory 145704 kb
Host smart-9fd5fafb-3c14-481a-ad7c-164a442b2362
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2093748453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2093748453
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2274205588
Short name T43
Test name
Test status
Simulation time 30373434 ps
CPU time 0.39 seconds
Started Apr 25 12:38:29 PM PDT 24
Finished Apr 25 12:38:32 PM PDT 24
Peak memory 145824 kb
Host smart-a3af8d2c-a47e-425e-9280-0e23b00c89fa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2274205588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2274205588
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3289157589
Short name T51
Test name
Test status
Simulation time 29903710 ps
CPU time 0.4 seconds
Started Apr 25 12:38:46 PM PDT 24
Finished Apr 25 12:38:48 PM PDT 24
Peak memory 145712 kb
Host smart-e2725cd6-ec6b-4fd3-94cd-db4fb9604438
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3289157589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3289157589
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3052210954
Short name T57
Test name
Test status
Simulation time 30746818 ps
CPU time 0.4 seconds
Started Apr 25 12:38:52 PM PDT 24
Finished Apr 25 12:38:54 PM PDT 24
Peak memory 145712 kb
Host smart-95a191b2-0080-40cd-9514-98824b984330
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3052210954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3052210954
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.28991010
Short name T38
Test name
Test status
Simulation time 31438621 ps
CPU time 0.4 seconds
Started Apr 25 12:38:37 PM PDT 24
Finished Apr 25 12:38:39 PM PDT 24
Peak memory 145732 kb
Host smart-574d4c45-ef49-488b-a0ca-8e702b8340dd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=28991010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.28991010
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3784582727
Short name T49
Test name
Test status
Simulation time 30413938 ps
CPU time 0.41 seconds
Started Apr 25 12:38:35 PM PDT 24
Finished Apr 25 12:38:36 PM PDT 24
Peak memory 145820 kb
Host smart-4d89496e-706a-4e80-9259-64cb24bb9bf9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3784582727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3784582727
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2282141713
Short name T21
Test name
Test status
Simulation time 31032078 ps
CPU time 0.41 seconds
Started Apr 25 12:38:35 PM PDT 24
Finished Apr 25 12:38:36 PM PDT 24
Peak memory 145816 kb
Host smart-54001a2a-0387-4acb-a493-bd20cdbeacf7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2282141713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2282141713
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3167444283
Short name T20
Test name
Test status
Simulation time 30164141 ps
CPU time 0.41 seconds
Started Apr 25 12:38:33 PM PDT 24
Finished Apr 25 12:38:34 PM PDT 24
Peak memory 145748 kb
Host smart-ba6a6f46-a532-42e6-8739-00679c9e3eed
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3167444283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3167444283
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4047449223
Short name T55
Test name
Test status
Simulation time 28946485 ps
CPU time 0.38 seconds
Started Apr 25 12:38:42 PM PDT 24
Finished Apr 25 12:38:43 PM PDT 24
Peak memory 145824 kb
Host smart-af132c2f-19e4-45f7-90ca-8e5bcc8e8d1f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4047449223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4047449223
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3396683010
Short name T40
Test name
Test status
Simulation time 30547268 ps
CPU time 0.4 seconds
Started Apr 25 12:38:31 PM PDT 24
Finished Apr 25 12:38:33 PM PDT 24
Peak memory 145712 kb
Host smart-c16e205c-708d-4391-b123-b0facd292d88
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3396683010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3396683010
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2309466123
Short name T56
Test name
Test status
Simulation time 27673048 ps
CPU time 0.4 seconds
Started Apr 25 12:38:30 PM PDT 24
Finished Apr 25 12:38:33 PM PDT 24
Peak memory 145716 kb
Host smart-8a7e6a56-4788-4a80-b059-4383e90ac3b8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2309466123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2309466123
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1239919622
Short name T42
Test name
Test status
Simulation time 32446935 ps
CPU time 0.4 seconds
Started Apr 25 12:38:34 PM PDT 24
Finished Apr 25 12:38:35 PM PDT 24
Peak memory 145696 kb
Host smart-ba76e4d8-59c4-4999-8c51-db195fe33d72
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1239919622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1239919622
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2040174574
Short name T19
Test name
Test status
Simulation time 29544915 ps
CPU time 0.39 seconds
Started Apr 25 12:38:57 PM PDT 24
Finished Apr 25 12:38:59 PM PDT 24
Peak memory 145708 kb
Host smart-5396dfed-a13d-421d-8038-d00036065ed2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2040174574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2040174574
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1677985132
Short name T54
Test name
Test status
Simulation time 29860780 ps
CPU time 0.4 seconds
Started Apr 25 12:38:31 PM PDT 24
Finished Apr 25 12:38:33 PM PDT 24
Peak memory 145696 kb
Host smart-4a56c786-b8cf-4948-93c4-b0a4fa0d7b90
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1677985132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1677985132
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2128609036
Short name T48
Test name
Test status
Simulation time 30755258 ps
CPU time 0.41 seconds
Started Apr 25 12:38:26 PM PDT 24
Finished Apr 25 12:38:28 PM PDT 24
Peak memory 145716 kb
Host smart-9accec1c-9933-496c-96b6-92e8f286ef3e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2128609036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2128609036
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1798703714
Short name T52
Test name
Test status
Simulation time 29069592 ps
CPU time 0.4 seconds
Started Apr 25 12:38:36 PM PDT 24
Finished Apr 25 12:38:37 PM PDT 24
Peak memory 145816 kb
Host smart-e8b023b7-cf18-4ddb-8df6-b33c93a6f224
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1798703714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1798703714
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1977095314
Short name T63
Test name
Test status
Simulation time 8982248 ps
CPU time 0.38 seconds
Started Apr 25 12:39:47 PM PDT 24
Finished Apr 25 12:39:49 PM PDT 24
Peak memory 145536 kb
Host smart-077308b7-38ad-4530-9ee7-4b041a825fd3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1977095314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1977095314
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3389750659
Short name T25
Test name
Test status
Simulation time 10232957 ps
CPU time 0.41 seconds
Started Apr 25 12:39:49 PM PDT 24
Finished Apr 25 12:39:52 PM PDT 24
Peak memory 145504 kb
Host smart-0a83338b-5ee4-44b2-8d07-8904fa170c08
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3389750659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3389750659
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2304717736
Short name T59
Test name
Test status
Simulation time 8585631 ps
CPU time 0.38 seconds
Started Apr 25 12:39:46 PM PDT 24
Finished Apr 25 12:39:48 PM PDT 24
Peak memory 145556 kb
Host smart-c4db58c9-1055-41b5-ad8a-5b78d07d0f0a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2304717736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2304717736
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.4043322293
Short name T23
Test name
Test status
Simulation time 8993433 ps
CPU time 0.37 seconds
Started Apr 25 12:39:56 PM PDT 24
Finished Apr 25 12:39:58 PM PDT 24
Peak memory 145564 kb
Host smart-3592c4f9-15ee-4c79-ad4f-7f15b4a7feb0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4043322293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.4043322293
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3866561184
Short name T26
Test name
Test status
Simulation time 8691526 ps
CPU time 0.39 seconds
Started Apr 25 12:39:46 PM PDT 24
Finished Apr 25 12:39:48 PM PDT 24
Peak memory 145476 kb
Host smart-d5cf91d5-03dc-48a8-803c-8ba306dd75df
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3866561184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3866561184
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.382933746
Short name T34
Test name
Test status
Simulation time 9041844 ps
CPU time 0.42 seconds
Started Apr 25 12:39:46 PM PDT 24
Finished Apr 25 12:39:49 PM PDT 24
Peak memory 145496 kb
Host smart-7a8607d9-13de-4ddd-99e9-530d59963583
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=382933746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.382933746
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2904088962
Short name T62
Test name
Test status
Simulation time 9273725 ps
CPU time 0.41 seconds
Started Apr 25 12:39:48 PM PDT 24
Finished Apr 25 12:39:51 PM PDT 24
Peak memory 145472 kb
Host smart-76da1446-aaf0-4e4a-9aae-5c14c76b8c9d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2904088962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2904088962
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3023227117
Short name T61
Test name
Test status
Simulation time 10148018 ps
CPU time 0.39 seconds
Started Apr 25 12:39:51 PM PDT 24
Finished Apr 25 12:39:54 PM PDT 24
Peak memory 145496 kb
Host smart-97a1a8e4-e115-4a7a-8782-2f17747b4464
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3023227117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3023227117
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3122616116
Short name T28
Test name
Test status
Simulation time 9097232 ps
CPU time 0.38 seconds
Started Apr 25 12:39:54 PM PDT 24
Finished Apr 25 12:39:57 PM PDT 24
Peak memory 145464 kb
Host smart-b570373f-b2d2-4672-9a51-e1e7e87d3778
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3122616116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3122616116
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.936869382
Short name T27
Test name
Test status
Simulation time 9157340 ps
CPU time 0.38 seconds
Started Apr 25 12:40:09 PM PDT 24
Finished Apr 25 12:40:11 PM PDT 24
Peak memory 145456 kb
Host smart-7243606e-a983-499b-bec2-c247af8f75e5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=936869382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.936869382
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3107952864
Short name T29
Test name
Test status
Simulation time 9543949 ps
CPU time 0.38 seconds
Started Apr 25 12:39:50 PM PDT 24
Finished Apr 25 12:39:53 PM PDT 24
Peak memory 145500 kb
Host smart-c0871d64-03e5-44ba-a9bc-a56ac8e2cd60
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3107952864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3107952864
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2604251549
Short name T22
Test name
Test status
Simulation time 9540358 ps
CPU time 0.39 seconds
Started Apr 25 12:39:45 PM PDT 24
Finished Apr 25 12:39:47 PM PDT 24
Peak memory 145456 kb
Host smart-34084ecc-110a-40ad-b5f3-bfe7400660d2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2604251549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2604251549
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1575833703
Short name T24
Test name
Test status
Simulation time 9566799 ps
CPU time 0.4 seconds
Started Apr 25 12:39:39 PM PDT 24
Finished Apr 25 12:39:41 PM PDT 24
Peak memory 145600 kb
Host smart-22075817-e5cd-4985-86a2-7f61f76945b6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1575833703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1575833703
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2317634006
Short name T37
Test name
Test status
Simulation time 9657379 ps
CPU time 0.38 seconds
Started Apr 25 12:39:41 PM PDT 24
Finished Apr 25 12:39:43 PM PDT 24
Peak memory 145572 kb
Host smart-037eaa56-de9f-452e-a9d4-d40aaa87b7d4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2317634006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2317634006
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2928439131
Short name T58
Test name
Test status
Simulation time 10741214 ps
CPU time 0.39 seconds
Started Apr 25 12:39:46 PM PDT 24
Finished Apr 25 12:39:47 PM PDT 24
Peak memory 145576 kb
Host smart-75355abd-5d66-4fa6-b125-dfc974846c8d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2928439131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2928439131
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.565993084
Short name T33
Test name
Test status
Simulation time 9328966 ps
CPU time 0.4 seconds
Started Apr 25 12:39:45 PM PDT 24
Finished Apr 25 12:39:46 PM PDT 24
Peak memory 145520 kb
Host smart-6f958cd0-041d-4819-91ac-e2313d96c086
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=565993084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.565993084
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2539876395
Short name T35
Test name
Test status
Simulation time 9839089 ps
CPU time 0.4 seconds
Started Apr 25 12:39:41 PM PDT 24
Finished Apr 25 12:39:43 PM PDT 24
Peak memory 145588 kb
Host smart-cfefa58d-822a-4fa7-8e0d-e677764874be
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2539876395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2539876395
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2216956834
Short name T36
Test name
Test status
Simulation time 9037047 ps
CPU time 0.39 seconds
Started Apr 25 12:39:50 PM PDT 24
Finished Apr 25 12:39:53 PM PDT 24
Peak memory 145596 kb
Host smart-b01649f2-e21a-4dbc-81b7-8b3b7a332979
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2216956834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2216956834
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3661892792
Short name T60
Test name
Test status
Simulation time 8758696 ps
CPU time 0.39 seconds
Started Apr 25 12:39:46 PM PDT 24
Finished Apr 25 12:39:48 PM PDT 24
Peak memory 145464 kb
Host smart-3415438b-577a-4708-a635-29cb9f1c22be
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3661892792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3661892792
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4245724509
Short name T70
Test name
Test status
Simulation time 29421330 ps
CPU time 0.38 seconds
Started Apr 25 12:39:51 PM PDT 24
Finished Apr 25 12:39:54 PM PDT 24
Peak memory 145452 kb
Host smart-a4ef8e95-e005-4062-b6fd-4c6beb9e3a27
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4245724509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4245724509
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1864452240
Short name T75
Test name
Test status
Simulation time 28450206 ps
CPU time 0.42 seconds
Started Apr 25 12:39:51 PM PDT 24
Finished Apr 25 12:39:54 PM PDT 24
Peak memory 145476 kb
Host smart-d53c61c8-5751-4868-997f-13cd942fd4f3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1864452240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1864452240
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.730070826
Short name T72
Test name
Test status
Simulation time 27849954 ps
CPU time 0.4 seconds
Started Apr 25 12:39:51 PM PDT 24
Finished Apr 25 12:39:54 PM PDT 24
Peak memory 145476 kb
Host smart-1d6a7e05-d881-43b1-bb7c-b98564b5b61f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=730070826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.730070826
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2876368764
Short name T77
Test name
Test status
Simulation time 24383799 ps
CPU time 0.42 seconds
Started Apr 25 12:39:50 PM PDT 24
Finished Apr 25 12:39:53 PM PDT 24
Peak memory 145464 kb
Host smart-42b50217-a79e-403b-8169-bb4244999b82
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2876368764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2876368764
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1437175581
Short name T69
Test name
Test status
Simulation time 29272553 ps
CPU time 0.39 seconds
Started Apr 25 12:40:06 PM PDT 24
Finished Apr 25 12:40:08 PM PDT 24
Peak memory 145568 kb
Host smart-2817090d-35ca-4149-a130-d732f529cc54
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1437175581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1437175581
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2210635170
Short name T30
Test name
Test status
Simulation time 25611951 ps
CPU time 0.41 seconds
Started Apr 25 12:39:50 PM PDT 24
Finished Apr 25 12:39:53 PM PDT 24
Peak memory 145568 kb
Host smart-d6dd41d1-9dad-4299-8452-a9ac35f3892a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2210635170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2210635170
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1442017614
Short name T79
Test name
Test status
Simulation time 25196808 ps
CPU time 0.4 seconds
Started Apr 25 12:39:48 PM PDT 24
Finished Apr 25 12:39:50 PM PDT 24
Peak memory 145436 kb
Host smart-1d85c871-00fd-4da9-8d3c-7e51eb3c0407
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1442017614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1442017614
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1641748283
Short name T80
Test name
Test status
Simulation time 27408306 ps
CPU time 0.4 seconds
Started Apr 25 12:39:52 PM PDT 24
Finished Apr 25 12:39:55 PM PDT 24
Peak memory 145472 kb
Host smart-4ec9a6c7-6432-41b0-9399-b1c71d3e0690
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1641748283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1641748283
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2852009095
Short name T71
Test name
Test status
Simulation time 26762094 ps
CPU time 0.39 seconds
Started Apr 25 12:39:49 PM PDT 24
Finished Apr 25 12:39:52 PM PDT 24
Peak memory 145588 kb
Host smart-0171237c-9017-4573-8f50-4d5ea9baef6e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2852009095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2852009095
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2799367430
Short name T74
Test name
Test status
Simulation time 27870470 ps
CPU time 0.38 seconds
Started Apr 25 12:39:58 PM PDT 24
Finished Apr 25 12:39:59 PM PDT 24
Peak memory 145568 kb
Host smart-f592bdc4-5ad6-4dad-801a-db47489b4ffe
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2799367430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2799367430
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3116345632
Short name T31
Test name
Test status
Simulation time 27046349 ps
CPU time 0.41 seconds
Started Apr 25 12:39:47 PM PDT 24
Finished Apr 25 12:39:50 PM PDT 24
Peak memory 145552 kb
Host smart-97a07a9d-b32a-4520-8624-48e668678ea9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3116345632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3116345632
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4162059014
Short name T64
Test name
Test status
Simulation time 26906862 ps
CPU time 0.39 seconds
Started Apr 25 12:39:51 PM PDT 24
Finished Apr 25 12:39:54 PM PDT 24
Peak memory 145472 kb
Host smart-c1bc4557-4535-4164-a23b-3582ab425064
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4162059014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4162059014
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3921313009
Short name T76
Test name
Test status
Simulation time 27880575 ps
CPU time 0.38 seconds
Started Apr 25 12:40:40 PM PDT 24
Finished Apr 25 12:40:42 PM PDT 24
Peak memory 145568 kb
Host smart-97176803-20aa-4ab3-92fb-5a3a92ec7418
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3921313009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3921313009
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2932714596
Short name T73
Test name
Test status
Simulation time 26819154 ps
CPU time 0.43 seconds
Started Apr 25 12:39:46 PM PDT 24
Finished Apr 25 12:39:49 PM PDT 24
Peak memory 145564 kb
Host smart-9cc470ac-f759-4bf3-9666-8ca09f611cba
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2932714596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2932714596
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2088198216
Short name T67
Test name
Test status
Simulation time 28695185 ps
CPU time 0.39 seconds
Started Apr 25 12:39:58 PM PDT 24
Finished Apr 25 12:40:00 PM PDT 24
Peak memory 145536 kb
Host smart-207bb693-f51d-43c9-b4fa-22314adc74ac
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2088198216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2088198216
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2095453228
Short name T68
Test name
Test status
Simulation time 28167357 ps
CPU time 0.42 seconds
Started Apr 25 12:39:55 PM PDT 24
Finished Apr 25 12:39:57 PM PDT 24
Peak memory 145588 kb
Host smart-4154e271-2d5c-4517-ba7f-ea46b1e5edb1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2095453228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2095453228
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3823893717
Short name T65
Test name
Test status
Simulation time 27496986 ps
CPU time 0.4 seconds
Started Apr 25 12:39:47 PM PDT 24
Finished Apr 25 12:39:49 PM PDT 24
Peak memory 145476 kb
Host smart-81f1619c-bca7-434a-ba87-d22767b7f73f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3823893717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3823893717
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.991814655
Short name T78
Test name
Test status
Simulation time 26972636 ps
CPU time 0.41 seconds
Started Apr 25 12:39:50 PM PDT 24
Finished Apr 25 12:39:53 PM PDT 24
Peak memory 145492 kb
Host smart-7f0760ac-ab3d-4756-b93b-2ba4c42da790
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=991814655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.991814655
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.987562416
Short name T66
Test name
Test status
Simulation time 27772584 ps
CPU time 0.4 seconds
Started Apr 25 12:39:50 PM PDT 24
Finished Apr 25 12:39:53 PM PDT 24
Peak memory 145464 kb
Host smart-ff939819-933f-47b5-bc52-ad7d974046bb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=987562416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.987562416
Directory /workspace/9.prim_sync_fatal_alert/latest
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