Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.02 89.02 100.00 100.00 95.83 95.83 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/16.prim_async_alert.2557764626
91.55 2.53 100.00 0.00 95.83 0.00 100.00 0.00 78.57 3.57 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/0.prim_sync_alert.1738689697
93.90 2.35 100.00 0.00 95.83 0.00 100.00 0.00 85.71 7.14 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2312438675
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/3.prim_async_alert.3578627676
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1359296459
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/17.prim_sync_alert.202405476

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.767347157
/workspace/coverage/default/1.prim_async_alert.2625858447
/workspace/coverage/default/10.prim_async_alert.1344330297
/workspace/coverage/default/11.prim_async_alert.3199919063
/workspace/coverage/default/12.prim_async_alert.3956625123
/workspace/coverage/default/13.prim_async_alert.333047178
/workspace/coverage/default/14.prim_async_alert.3471458262
/workspace/coverage/default/15.prim_async_alert.720059334
/workspace/coverage/default/17.prim_async_alert.1128405249
/workspace/coverage/default/18.prim_async_alert.2564291873
/workspace/coverage/default/19.prim_async_alert.2045101921
/workspace/coverage/default/2.prim_async_alert.1821636855
/workspace/coverage/default/4.prim_async_alert.64584834
/workspace/coverage/default/5.prim_async_alert.881398683
/workspace/coverage/default/6.prim_async_alert.3950463528
/workspace/coverage/default/7.prim_async_alert.1547328033
/workspace/coverage/default/8.prim_async_alert.1636715524
/workspace/coverage/default/9.prim_async_alert.2288651826
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3237576577
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1935886435
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.265324269
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1544834507
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4164645937
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1034184815
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1582084677
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2408108064
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.12346618
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2729207536
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3099985765
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3258895331
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.966938669
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.194313230
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.661913680
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4022713073
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2063364903
/workspace/coverage/sync_alert/1.prim_sync_alert.4286631455
/workspace/coverage/sync_alert/10.prim_sync_alert.2207926393
/workspace/coverage/sync_alert/11.prim_sync_alert.1084872909
/workspace/coverage/sync_alert/12.prim_sync_alert.3939568823
/workspace/coverage/sync_alert/13.prim_sync_alert.2719208353
/workspace/coverage/sync_alert/14.prim_sync_alert.330920097
/workspace/coverage/sync_alert/15.prim_sync_alert.3799193430
/workspace/coverage/sync_alert/16.prim_sync_alert.325338180
/workspace/coverage/sync_alert/18.prim_sync_alert.1460231220
/workspace/coverage/sync_alert/19.prim_sync_alert.1611618740
/workspace/coverage/sync_alert/2.prim_sync_alert.1940077322
/workspace/coverage/sync_alert/3.prim_sync_alert.4020685649
/workspace/coverage/sync_alert/4.prim_sync_alert.929296230
/workspace/coverage/sync_alert/5.prim_sync_alert.1907243335
/workspace/coverage/sync_alert/6.prim_sync_alert.2546983067
/workspace/coverage/sync_alert/7.prim_sync_alert.3616173567
/workspace/coverage/sync_alert/8.prim_sync_alert.2565859958
/workspace/coverage/sync_alert/9.prim_sync_alert.644492989
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2544498443
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2553409460
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3645616447
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2249801272
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4182379910
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1675777265
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2918526218
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1070513152
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3074526254
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2133291193
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.781978461
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4184072112
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4095550023
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1073280524
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.372533777
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2087308472
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2299342155
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.104391624
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1722824499
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2978068677



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/12.prim_async_alert.3956625123 Apr 28 12:23:30 PM PDT 24 Apr 28 12:23:31 PM PDT 24 11364832 ps
T2 /workspace/coverage/default/1.prim_async_alert.2625858447 Apr 28 12:22:50 PM PDT 24 Apr 28 12:23:02 PM PDT 24 11628164 ps
T3 /workspace/coverage/default/18.prim_async_alert.2564291873 Apr 28 12:17:58 PM PDT 24 Apr 28 12:17:59 PM PDT 24 11196843 ps
T12 /workspace/coverage/default/3.prim_async_alert.3578627676 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:13 PM PDT 24 12076657 ps
T13 /workspace/coverage/default/17.prim_async_alert.1128405249 Apr 28 12:17:59 PM PDT 24 Apr 28 12:18:00 PM PDT 24 12455418 ps
T7 /workspace/coverage/default/10.prim_async_alert.1344330297 Apr 28 12:23:37 PM PDT 24 Apr 28 12:23:38 PM PDT 24 10561292 ps
T20 /workspace/coverage/default/11.prim_async_alert.3199919063 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:13 PM PDT 24 10656979 ps
T18 /workspace/coverage/default/6.prim_async_alert.3950463528 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:15 PM PDT 24 10859444 ps
T8 /workspace/coverage/default/16.prim_async_alert.2557764626 Apr 28 12:17:43 PM PDT 24 Apr 28 12:17:44 PM PDT 24 12001143 ps
T19 /workspace/coverage/default/2.prim_async_alert.1821636855 Apr 28 12:22:42 PM PDT 24 Apr 28 12:22:49 PM PDT 24 12118160 ps
T9 /workspace/coverage/default/7.prim_async_alert.1547328033 Apr 28 12:23:33 PM PDT 24 Apr 28 12:23:34 PM PDT 24 10952950 ps
T16 /workspace/coverage/default/9.prim_async_alert.2288651826 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:15 PM PDT 24 11087663 ps
T21 /workspace/coverage/default/0.prim_async_alert.767347157 Apr 28 12:22:21 PM PDT 24 Apr 28 12:22:23 PM PDT 24 10712749 ps
T45 /workspace/coverage/default/15.prim_async_alert.720059334 Apr 28 12:21:26 PM PDT 24 Apr 28 12:21:27 PM PDT 24 12498904 ps
T46 /workspace/coverage/default/19.prim_async_alert.2045101921 Apr 28 12:18:14 PM PDT 24 Apr 28 12:18:15 PM PDT 24 11379701 ps
T22 /workspace/coverage/default/5.prim_async_alert.881398683 Apr 28 12:22:05 PM PDT 24 Apr 28 12:22:08 PM PDT 24 10818022 ps
T47 /workspace/coverage/default/13.prim_async_alert.333047178 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:15 PM PDT 24 11361551 ps
T48 /workspace/coverage/default/14.prim_async_alert.3471458262 Apr 28 12:22:46 PM PDT 24 Apr 28 12:22:55 PM PDT 24 11725969 ps
T23 /workspace/coverage/default/8.prim_async_alert.1636715524 Apr 28 12:18:34 PM PDT 24 Apr 28 12:18:35 PM PDT 24 10484595 ps
T49 /workspace/coverage/default/4.prim_async_alert.64584834 Apr 28 12:22:36 PM PDT 24 Apr 28 12:22:42 PM PDT 24 11769540 ps
T39 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.194313230 Apr 28 12:22:07 PM PDT 24 Apr 28 12:22:10 PM PDT 24 28698251 ps
T17 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1544834507 Apr 28 12:19:06 PM PDT 24 Apr 28 12:19:06 PM PDT 24 30688751 ps
T40 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.265324269 Apr 28 12:18:57 PM PDT 24 Apr 28 12:18:58 PM PDT 24 29916228 ps
T14 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2063364903 Apr 28 12:21:06 PM PDT 24 Apr 28 12:21:07 PM PDT 24 29558864 ps
T41 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2408108064 Apr 28 12:22:47 PM PDT 24 Apr 28 12:22:58 PM PDT 24 31108373 ps
T42 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1935886435 Apr 28 12:21:06 PM PDT 24 Apr 28 12:21:07 PM PDT 24 28808053 ps
T43 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.966938669 Apr 28 12:19:43 PM PDT 24 Apr 28 12:19:44 PM PDT 24 30348811 ps
T44 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3237576577 Apr 28 12:22:44 PM PDT 24 Apr 28 12:22:52 PM PDT 24 29635842 ps
T37 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2312438675 Apr 28 12:18:47 PM PDT 24 Apr 28 12:18:48 PM PDT 24 30767098 ps
T4 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2729207536 Apr 28 12:18:59 PM PDT 24 Apr 28 12:18:59 PM PDT 24 30632719 ps
T50 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1034184815 Apr 28 12:18:41 PM PDT 24 Apr 28 12:18:42 PM PDT 24 30399992 ps
T51 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3258895331 Apr 28 12:22:48 PM PDT 24 Apr 28 12:22:59 PM PDT 24 31801425 ps
T52 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1582084677 Apr 28 12:22:48 PM PDT 24 Apr 28 12:22:58 PM PDT 24 29789261 ps
T15 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4022713073 Apr 28 12:17:09 PM PDT 24 Apr 28 12:17:09 PM PDT 24 30902277 ps
T53 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3099985765 Apr 28 12:22:48 PM PDT 24 Apr 28 12:22:59 PM PDT 24 28931927 ps
T5 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1359296459 Apr 28 12:22:44 PM PDT 24 Apr 28 12:22:52 PM PDT 24 29389391 ps
T6 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4164645937 Apr 28 12:22:46 PM PDT 24 Apr 28 12:22:56 PM PDT 24 30404049 ps
T38 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.661913680 Apr 28 12:17:06 PM PDT 24 Apr 28 12:17:07 PM PDT 24 29180282 ps
T54 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.12346618 Apr 28 12:22:05 PM PDT 24 Apr 28 12:22:08 PM PDT 24 29018774 ps
T33 /workspace/coverage/sync_alert/11.prim_sync_alert.1084872909 Apr 28 12:22:21 PM PDT 24 Apr 28 12:22:23 PM PDT 24 9864153 ps
T34 /workspace/coverage/sync_alert/15.prim_sync_alert.3799193430 Apr 28 12:22:36 PM PDT 24 Apr 28 12:22:42 PM PDT 24 8570243 ps
T24 /workspace/coverage/sync_alert/6.prim_sync_alert.2546983067 Apr 28 12:17:46 PM PDT 24 Apr 28 12:17:47 PM PDT 24 8875909 ps
T25 /workspace/coverage/sync_alert/0.prim_sync_alert.1738689697 Apr 28 12:22:05 PM PDT 24 Apr 28 12:22:08 PM PDT 24 10352841 ps
T26 /workspace/coverage/sync_alert/3.prim_sync_alert.4020685649 Apr 28 12:19:34 PM PDT 24 Apr 28 12:19:35 PM PDT 24 9109388 ps
T27 /workspace/coverage/sync_alert/18.prim_sync_alert.1460231220 Apr 28 12:21:14 PM PDT 24 Apr 28 12:21:15 PM PDT 24 9013119 ps
T35 /workspace/coverage/sync_alert/1.prim_sync_alert.4286631455 Apr 28 12:19:33 PM PDT 24 Apr 28 12:19:35 PM PDT 24 8747412 ps
T28 /workspace/coverage/sync_alert/14.prim_sync_alert.330920097 Apr 28 12:22:42 PM PDT 24 Apr 28 12:22:48 PM PDT 24 8880969 ps
T29 /workspace/coverage/sync_alert/13.prim_sync_alert.2719208353 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:13 PM PDT 24 9626259 ps
T36 /workspace/coverage/sync_alert/5.prim_sync_alert.1907243335 Apr 28 12:19:28 PM PDT 24 Apr 28 12:19:29 PM PDT 24 8052796 ps
T55 /workspace/coverage/sync_alert/2.prim_sync_alert.1940077322 Apr 28 12:19:35 PM PDT 24 Apr 28 12:19:36 PM PDT 24 8432597 ps
T30 /workspace/coverage/sync_alert/7.prim_sync_alert.3616173567 Apr 28 12:19:46 PM PDT 24 Apr 28 12:19:48 PM PDT 24 8526058 ps
T56 /workspace/coverage/sync_alert/4.prim_sync_alert.929296230 Apr 28 12:22:20 PM PDT 24 Apr 28 12:22:22 PM PDT 24 9018673 ps
T57 /workspace/coverage/sync_alert/19.prim_sync_alert.1611618740 Apr 28 12:21:52 PM PDT 24 Apr 28 12:21:55 PM PDT 24 9607031 ps
T10 /workspace/coverage/sync_alert/17.prim_sync_alert.202405476 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:15 PM PDT 24 9368455 ps
T58 /workspace/coverage/sync_alert/16.prim_sync_alert.325338180 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:15 PM PDT 24 10106164 ps
T31 /workspace/coverage/sync_alert/12.prim_sync_alert.3939568823 Apr 28 12:22:03 PM PDT 24 Apr 28 12:22:07 PM PDT 24 9855969 ps
T32 /workspace/coverage/sync_alert/10.prim_sync_alert.2207926393 Apr 28 12:18:04 PM PDT 24 Apr 28 12:18:05 PM PDT 24 9438256 ps
T59 /workspace/coverage/sync_alert/9.prim_sync_alert.644492989 Apr 28 12:19:45 PM PDT 24 Apr 28 12:19:47 PM PDT 24 9124559 ps
T60 /workspace/coverage/sync_alert/8.prim_sync_alert.2565859958 Apr 28 12:19:40 PM PDT 24 Apr 28 12:19:41 PM PDT 24 9385543 ps
T61 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4182379910 Apr 28 12:22:09 PM PDT 24 Apr 28 12:22:11 PM PDT 24 28854066 ps
T62 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.104391624 Apr 28 12:22:42 PM PDT 24 Apr 28 12:22:48 PM PDT 24 29412370 ps
T63 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3645616447 Apr 28 12:22:12 PM PDT 24 Apr 28 12:22:15 PM PDT 24 25966886 ps
T64 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2553409460 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:14 PM PDT 24 26806675 ps
T65 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1675777265 Apr 28 12:22:38 PM PDT 24 Apr 28 12:22:44 PM PDT 24 27001857 ps
T66 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2133291193 Apr 28 12:22:50 PM PDT 24 Apr 28 12:23:02 PM PDT 24 28320876 ps
T67 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4095550023 Apr 28 12:22:07 PM PDT 24 Apr 28 12:22:10 PM PDT 24 27035711 ps
T68 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.372533777 Apr 28 12:18:01 PM PDT 24 Apr 28 12:18:02 PM PDT 24 28443523 ps
T69 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2087308472 Apr 28 12:22:36 PM PDT 24 Apr 28 12:22:42 PM PDT 24 26990515 ps
T70 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2918526218 Apr 28 12:22:38 PM PDT 24 Apr 28 12:22:44 PM PDT 24 27063494 ps
T11 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1722824499 Apr 28 12:18:01 PM PDT 24 Apr 28 12:18:02 PM PDT 24 28796476 ps
T71 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2978068677 Apr 28 12:17:36 PM PDT 24 Apr 28 12:17:37 PM PDT 24 25139307 ps
T72 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2249801272 Apr 28 12:18:51 PM PDT 24 Apr 28 12:18:51 PM PDT 24 29570265 ps
T73 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1070513152 Apr 28 12:20:19 PM PDT 24 Apr 28 12:20:19 PM PDT 24 28016990 ps
T74 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4184072112 Apr 28 12:22:49 PM PDT 24 Apr 28 12:23:01 PM PDT 24 27897287 ps
T75 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2544498443 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:14 PM PDT 24 29519241 ps
T76 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2299342155 Apr 28 12:18:09 PM PDT 24 Apr 28 12:18:10 PM PDT 24 28088390 ps
T77 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1073280524 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:14 PM PDT 24 26730094 ps
T78 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3074526254 Apr 28 12:22:48 PM PDT 24 Apr 28 12:22:59 PM PDT 24 26392205 ps
T79 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.781978461 Apr 28 12:22:34 PM PDT 24 Apr 28 12:22:37 PM PDT 24 26756573 ps

Test location /workspace/coverage/default/16.prim_async_alert.2557764626
Short name T8
Test name
Test status
Simulation time 12001143 ps
CPU time 0.39 seconds
Started Apr 28 12:17:43 PM PDT 24
Finished Apr 28 12:17:44 PM PDT 24
Peak memory 145752 kb
Host smart-cd7685c4-5a14-4423-aaed-5b51f160c375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557764626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2557764626
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1738689697
Short name T25
Test name
Test status
Simulation time 10352841 ps
CPU time 0.37 seconds
Started Apr 28 12:22:05 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 144604 kb
Host smart-2f9a97c8-c1c1-461e-b690-8c9514868cd7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1738689697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1738689697
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2312438675
Short name T37
Test name
Test status
Simulation time 30767098 ps
CPU time 0.41 seconds
Started Apr 28 12:18:47 PM PDT 24
Finished Apr 28 12:18:48 PM PDT 24
Peak memory 145648 kb
Host smart-2ae32e58-c001-4c3d-805f-347b425f2c91
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2312438675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2312438675
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3578627676
Short name T12
Test name
Test status
Simulation time 12076657 ps
CPU time 0.41 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:13 PM PDT 24
Peak memory 144548 kb
Host smart-b6d5dd0c-298e-4443-83fe-c7abe757b4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578627676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3578627676
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1359296459
Short name T5
Test name
Test status
Simulation time 29389391 ps
CPU time 0.37 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:52 PM PDT 24
Peak memory 145632 kb
Host smart-93332a42-2093-4385-82f8-f961c84485db
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1359296459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1359296459
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.202405476
Short name T10
Test name
Test status
Simulation time 9368455 ps
CPU time 0.38 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:15 PM PDT 24
Peak memory 146296 kb
Host smart-779db0c0-278d-4fab-8a5a-9155f31b47dd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=202405476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.202405476
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.767347157
Short name T21
Test name
Test status
Simulation time 10712749 ps
CPU time 0.38 seconds
Started Apr 28 12:22:21 PM PDT 24
Finished Apr 28 12:22:23 PM PDT 24
Peak memory 145580 kb
Host smart-4272ff8e-f26a-4a8f-a708-c2114524a7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767347157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.767347157
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2625858447
Short name T2
Test name
Test status
Simulation time 11628164 ps
CPU time 0.4 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 145572 kb
Host smart-7d28b78e-f772-454d-ad3e-5966a91257af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625858447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2625858447
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1344330297
Short name T7
Test name
Test status
Simulation time 10561292 ps
CPU time 0.37 seconds
Started Apr 28 12:23:37 PM PDT 24
Finished Apr 28 12:23:38 PM PDT 24
Peak memory 145640 kb
Host smart-52017566-067a-4335-a5c2-1853a4248489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344330297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1344330297
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3199919063
Short name T20
Test name
Test status
Simulation time 10656979 ps
CPU time 0.39 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:13 PM PDT 24
Peak memory 145344 kb
Host smart-e380242b-d4a1-4bab-8209-174254a454c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199919063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3199919063
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.3956625123
Short name T1
Test name
Test status
Simulation time 11364832 ps
CPU time 0.38 seconds
Started Apr 28 12:23:30 PM PDT 24
Finished Apr 28 12:23:31 PM PDT 24
Peak memory 145608 kb
Host smart-cfc034f4-a671-4456-8885-26a82f989026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956625123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3956625123
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.333047178
Short name T47
Test name
Test status
Simulation time 11361551 ps
CPU time 0.4 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:15 PM PDT 24
Peak memory 145396 kb
Host smart-94d1bc85-6355-4fd8-bd7d-c1c1917c75fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333047178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.333047178
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3471458262
Short name T48
Test name
Test status
Simulation time 11725969 ps
CPU time 0.38 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:22:55 PM PDT 24
Peak memory 145756 kb
Host smart-94067b21-d60b-4d12-b084-b1e378e62400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471458262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3471458262
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.720059334
Short name T45
Test name
Test status
Simulation time 12498904 ps
CPU time 0.4 seconds
Started Apr 28 12:21:26 PM PDT 24
Finished Apr 28 12:21:27 PM PDT 24
Peak memory 145608 kb
Host smart-8d9874ba-9fe2-457b-8726-fe77b7a17acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720059334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.720059334
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1128405249
Short name T13
Test name
Test status
Simulation time 12455418 ps
CPU time 0.38 seconds
Started Apr 28 12:17:59 PM PDT 24
Finished Apr 28 12:18:00 PM PDT 24
Peak memory 145628 kb
Host smart-9ef941cb-f9ad-4b8f-b92c-df8885e81892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128405249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1128405249
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2564291873
Short name T3
Test name
Test status
Simulation time 11196843 ps
CPU time 0.43 seconds
Started Apr 28 12:17:58 PM PDT 24
Finished Apr 28 12:17:59 PM PDT 24
Peak memory 145604 kb
Host smart-b3002714-deea-4d1d-9fc9-07800e7dd058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564291873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2564291873
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2045101921
Short name T46
Test name
Test status
Simulation time 11379701 ps
CPU time 0.39 seconds
Started Apr 28 12:18:14 PM PDT 24
Finished Apr 28 12:18:15 PM PDT 24
Peak memory 145752 kb
Host smart-e61be015-9f92-47a6-ba04-318ab500cf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045101921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2045101921
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.1821636855
Short name T19
Test name
Test status
Simulation time 12118160 ps
CPU time 0.4 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:49 PM PDT 24
Peak memory 145280 kb
Host smart-11f74352-3675-40d2-8f5e-4f03220aa957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821636855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1821636855
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.64584834
Short name T49
Test name
Test status
Simulation time 11769540 ps
CPU time 0.39 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:42 PM PDT 24
Peak memory 145576 kb
Host smart-48d2d7f8-e787-4523-a1a6-dfe079da16b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64584834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.64584834
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.881398683
Short name T22
Test name
Test status
Simulation time 10818022 ps
CPU time 0.43 seconds
Started Apr 28 12:22:05 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 145200 kb
Host smart-a8a2b4a5-6d84-434b-af06-dc811223c593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881398683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.881398683
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3950463528
Short name T18
Test name
Test status
Simulation time 10859444 ps
CPU time 0.39 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:15 PM PDT 24
Peak memory 145392 kb
Host smart-6c5c442c-642d-4112-943c-fa69696ceb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950463528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3950463528
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1547328033
Short name T9
Test name
Test status
Simulation time 10952950 ps
CPU time 0.38 seconds
Started Apr 28 12:23:33 PM PDT 24
Finished Apr 28 12:23:34 PM PDT 24
Peak memory 145600 kb
Host smart-d3f31e86-c7ce-4820-b1c1-35c3740c36a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547328033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1547328033
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1636715524
Short name T23
Test name
Test status
Simulation time 10484595 ps
CPU time 0.45 seconds
Started Apr 28 12:18:34 PM PDT 24
Finished Apr 28 12:18:35 PM PDT 24
Peak memory 145628 kb
Host smart-7884aa08-49a0-472b-bab7-e6ec166a5afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636715524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1636715524
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2288651826
Short name T16
Test name
Test status
Simulation time 11087663 ps
CPU time 0.38 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:15 PM PDT 24
Peak memory 145364 kb
Host smart-e0cd2c9f-21f1-402e-851e-772f945b2b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288651826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2288651826
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3237576577
Short name T44
Test name
Test status
Simulation time 29635842 ps
CPU time 0.39 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:52 PM PDT 24
Peak memory 145332 kb
Host smart-56f2d7cf-0979-411f-917f-122911cfea27
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3237576577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3237576577
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1935886435
Short name T42
Test name
Test status
Simulation time 28808053 ps
CPU time 0.39 seconds
Started Apr 28 12:21:06 PM PDT 24
Finished Apr 28 12:21:07 PM PDT 24
Peak memory 145684 kb
Host smart-dc23fd98-29f2-49ab-8cb6-5fa39dedf8fc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1935886435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1935886435
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.265324269
Short name T40
Test name
Test status
Simulation time 29916228 ps
CPU time 0.41 seconds
Started Apr 28 12:18:57 PM PDT 24
Finished Apr 28 12:18:58 PM PDT 24
Peak memory 145668 kb
Host smart-2e535357-c29c-47e5-96de-c3f6c158f3b2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=265324269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.265324269
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1544834507
Short name T17
Test name
Test status
Simulation time 30688751 ps
CPU time 0.44 seconds
Started Apr 28 12:19:06 PM PDT 24
Finished Apr 28 12:19:06 PM PDT 24
Peak memory 145684 kb
Host smart-98adb72f-6ed0-4f01-b95f-b34d930af733
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1544834507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1544834507
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4164645937
Short name T6
Test name
Test status
Simulation time 30404049 ps
CPU time 0.45 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:22:56 PM PDT 24
Peak memory 144340 kb
Host smart-c13d2d50-5fcb-44e2-80c9-6ef802df938c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4164645937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.4164645937
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1034184815
Short name T50
Test name
Test status
Simulation time 30399992 ps
CPU time 0.4 seconds
Started Apr 28 12:18:41 PM PDT 24
Finished Apr 28 12:18:42 PM PDT 24
Peak memory 145632 kb
Host smart-5e52a7c4-27fa-4fe4-a8c2-4fb473b21059
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1034184815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1034184815
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1582084677
Short name T52
Test name
Test status
Simulation time 29789261 ps
CPU time 0.38 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:58 PM PDT 24
Peak memory 145612 kb
Host smart-0e5891d5-9ac7-40f1-a83d-d5b427ce93e6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1582084677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1582084677
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2408108064
Short name T41
Test name
Test status
Simulation time 31108373 ps
CPU time 0.39 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:58 PM PDT 24
Peak memory 145600 kb
Host smart-0fd53c3f-d08b-4076-b5fa-6e9f06d03503
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2408108064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2408108064
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.12346618
Short name T54
Test name
Test status
Simulation time 29018774 ps
CPU time 0.39 seconds
Started Apr 28 12:22:05 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 144812 kb
Host smart-f073de03-22d7-498b-bf1d-df121c70cec1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=12346618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.12346618
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2729207536
Short name T4
Test name
Test status
Simulation time 30632719 ps
CPU time 0.4 seconds
Started Apr 28 12:18:59 PM PDT 24
Finished Apr 28 12:18:59 PM PDT 24
Peak memory 145672 kb
Host smart-16190a05-5d47-4cc0-a8c8-39a8a8f26f82
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2729207536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2729207536
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3099985765
Short name T53
Test name
Test status
Simulation time 28931927 ps
CPU time 0.39 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 145308 kb
Host smart-725c17aa-4171-420e-b651-475c12243cb4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3099985765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3099985765
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3258895331
Short name T51
Test name
Test status
Simulation time 31801425 ps
CPU time 0.39 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 145320 kb
Host smart-5294088a-9931-4c26-8189-417e5e821ca7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3258895331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3258895331
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.966938669
Short name T43
Test name
Test status
Simulation time 30348811 ps
CPU time 0.4 seconds
Started Apr 28 12:19:43 PM PDT 24
Finished Apr 28 12:19:44 PM PDT 24
Peak memory 145640 kb
Host smart-b2488a07-1089-4646-9058-2017a8a22eb3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=966938669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.966938669
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.194313230
Short name T39
Test name
Test status
Simulation time 28698251 ps
CPU time 0.46 seconds
Started Apr 28 12:22:07 PM PDT 24
Finished Apr 28 12:22:10 PM PDT 24
Peak memory 143988 kb
Host smart-f4298cea-1767-417f-85b1-e11a0264e95a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=194313230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.194313230
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.661913680
Short name T38
Test name
Test status
Simulation time 29180282 ps
CPU time 0.46 seconds
Started Apr 28 12:17:06 PM PDT 24
Finished Apr 28 12:17:07 PM PDT 24
Peak memory 144584 kb
Host smart-dc24ccf4-b20a-4d93-b4c5-561b986e417a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=661913680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.661913680
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.4022713073
Short name T15
Test name
Test status
Simulation time 30902277 ps
CPU time 0.39 seconds
Started Apr 28 12:17:09 PM PDT 24
Finished Apr 28 12:17:09 PM PDT 24
Peak memory 145688 kb
Host smart-58e2786e-c39b-4074-ad12-18190ed5dfda
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4022713073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.4022713073
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2063364903
Short name T14
Test name
Test status
Simulation time 29558864 ps
CPU time 0.39 seconds
Started Apr 28 12:21:06 PM PDT 24
Finished Apr 28 12:21:07 PM PDT 24
Peak memory 145676 kb
Host smart-c7b07d68-6f98-4a46-904e-4634ce24ced3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2063364903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2063364903
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.4286631455
Short name T35
Test name
Test status
Simulation time 8747412 ps
CPU time 0.43 seconds
Started Apr 28 12:19:33 PM PDT 24
Finished Apr 28 12:19:35 PM PDT 24
Peak memory 145440 kb
Host smart-9ca396c4-537d-4c9f-b18a-ed8f71016e76
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4286631455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.4286631455
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2207926393
Short name T32
Test name
Test status
Simulation time 9438256 ps
CPU time 0.38 seconds
Started Apr 28 12:18:04 PM PDT 24
Finished Apr 28 12:18:05 PM PDT 24
Peak memory 145444 kb
Host smart-9734e5a8-b235-49b3-8419-ade31cb10f77
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2207926393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2207926393
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1084872909
Short name T33
Test name
Test status
Simulation time 9864153 ps
CPU time 0.38 seconds
Started Apr 28 12:22:21 PM PDT 24
Finished Apr 28 12:22:23 PM PDT 24
Peak memory 145360 kb
Host smart-dc564761-f9eb-4b4d-bcf8-3a8c42a32a0e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1084872909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1084872909
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3939568823
Short name T31
Test name
Test status
Simulation time 9855969 ps
CPU time 0.37 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:22:07 PM PDT 24
Peak memory 145092 kb
Host smart-cf80b2cd-3fae-46e4-b4ad-59aaf445a79e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3939568823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3939568823
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2719208353
Short name T29
Test name
Test status
Simulation time 9626259 ps
CPU time 0.41 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:13 PM PDT 24
Peak memory 145880 kb
Host smart-114da851-8c11-409c-bcc2-8b0766697ffd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2719208353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2719208353
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.330920097
Short name T28
Test name
Test status
Simulation time 8880969 ps
CPU time 0.39 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:48 PM PDT 24
Peak memory 144716 kb
Host smart-47ed6a03-b653-4ade-a587-b743c341ca19
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=330920097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.330920097
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3799193430
Short name T34
Test name
Test status
Simulation time 8570243 ps
CPU time 0.38 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:42 PM PDT 24
Peak memory 145396 kb
Host smart-9de85dfc-a4a5-4c2a-be7d-2eb47fced9fd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3799193430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3799193430
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.325338180
Short name T58
Test name
Test status
Simulation time 10106164 ps
CPU time 0.37 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:15 PM PDT 24
Peak memory 145712 kb
Host smart-74374644-7c7a-4ec3-81c6-7b91b196b9d1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=325338180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.325338180
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1460231220
Short name T27
Test name
Test status
Simulation time 9013119 ps
CPU time 0.38 seconds
Started Apr 28 12:21:14 PM PDT 24
Finished Apr 28 12:21:15 PM PDT 24
Peak memory 145408 kb
Host smart-83bb3ef0-7a92-4a19-93ee-1cc4440235b8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1460231220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1460231220
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1611618740
Short name T57
Test name
Test status
Simulation time 9607031 ps
CPU time 0.41 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:21:55 PM PDT 24
Peak memory 143792 kb
Host smart-01eb671c-b418-447a-b2b1-ee3b23050f0e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1611618740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1611618740
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1940077322
Short name T55
Test name
Test status
Simulation time 8432597 ps
CPU time 0.37 seconds
Started Apr 28 12:19:35 PM PDT 24
Finished Apr 28 12:19:36 PM PDT 24
Peak memory 145460 kb
Host smart-dd969e60-2852-4b5c-a40a-f8c1063f87b1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1940077322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1940077322
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.4020685649
Short name T26
Test name
Test status
Simulation time 9109388 ps
CPU time 0.38 seconds
Started Apr 28 12:19:34 PM PDT 24
Finished Apr 28 12:19:35 PM PDT 24
Peak memory 145460 kb
Host smart-113a435d-00e9-463f-9114-fc8ed23eb090
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4020685649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.4020685649
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.929296230
Short name T56
Test name
Test status
Simulation time 9018673 ps
CPU time 0.38 seconds
Started Apr 28 12:22:20 PM PDT 24
Finished Apr 28 12:22:22 PM PDT 24
Peak memory 145184 kb
Host smart-4b4f4fbd-0c7b-4a90-9616-c603f29f2bff
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=929296230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.929296230
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1907243335
Short name T36
Test name
Test status
Simulation time 8052796 ps
CPU time 0.45 seconds
Started Apr 28 12:19:28 PM PDT 24
Finished Apr 28 12:19:29 PM PDT 24
Peak memory 145460 kb
Host smart-665466a4-2498-4601-8fed-d5bfd5a4f1be
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1907243335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1907243335
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2546983067
Short name T24
Test name
Test status
Simulation time 8875909 ps
CPU time 0.38 seconds
Started Apr 28 12:17:46 PM PDT 24
Finished Apr 28 12:17:47 PM PDT 24
Peak memory 145380 kb
Host smart-da6f4bdb-44aa-49db-a343-4bfdf2a6c3bf
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2546983067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2546983067
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3616173567
Short name T30
Test name
Test status
Simulation time 8526058 ps
CPU time 0.38 seconds
Started Apr 28 12:19:46 PM PDT 24
Finished Apr 28 12:19:48 PM PDT 24
Peak memory 145428 kb
Host smart-600dc776-2695-4aea-8cd4-0311ad300bd0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3616173567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3616173567
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2565859958
Short name T60
Test name
Test status
Simulation time 9385543 ps
CPU time 0.38 seconds
Started Apr 28 12:19:40 PM PDT 24
Finished Apr 28 12:19:41 PM PDT 24
Peak memory 145448 kb
Host smart-2842830e-8d6f-4480-be55-5a69dd714e25
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2565859958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2565859958
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.644492989
Short name T59
Test name
Test status
Simulation time 9124559 ps
CPU time 0.36 seconds
Started Apr 28 12:19:45 PM PDT 24
Finished Apr 28 12:19:47 PM PDT 24
Peak memory 145448 kb
Host smart-36c95cb2-a4ee-45b5-9adb-48b4abcae6f8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=644492989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.644492989
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2544498443
Short name T75
Test name
Test status
Simulation time 29519241 ps
CPU time 0.41 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:14 PM PDT 24
Peak memory 145212 kb
Host smart-976c2c5a-11a3-40e5-bf97-70863755f371
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2544498443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2544498443
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2553409460
Short name T64
Test name
Test status
Simulation time 26806675 ps
CPU time 0.38 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:14 PM PDT 24
Peak memory 145220 kb
Host smart-a772181e-19bf-45ae-9331-cfc071f6acd0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2553409460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2553409460
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3645616447
Short name T63
Test name
Test status
Simulation time 25966886 ps
CPU time 0.39 seconds
Started Apr 28 12:22:12 PM PDT 24
Finished Apr 28 12:22:15 PM PDT 24
Peak memory 145420 kb
Host smart-3850cd5d-7a7a-481b-aff1-963f66d573f2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3645616447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3645616447
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2249801272
Short name T72
Test name
Test status
Simulation time 29570265 ps
CPU time 0.41 seconds
Started Apr 28 12:18:51 PM PDT 24
Finished Apr 28 12:18:51 PM PDT 24
Peak memory 145428 kb
Host smart-2941e7a6-7e91-467c-90d8-d53fc42349da
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2249801272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2249801272
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4182379910
Short name T61
Test name
Test status
Simulation time 28854066 ps
CPU time 0.39 seconds
Started Apr 28 12:22:09 PM PDT 24
Finished Apr 28 12:22:11 PM PDT 24
Peak memory 145132 kb
Host smart-b3990c60-36e9-414c-9834-26a5076618c5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4182379910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4182379910
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1675777265
Short name T65
Test name
Test status
Simulation time 27001857 ps
CPU time 0.47 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:44 PM PDT 24
Peak memory 143688 kb
Host smart-d40ebd18-8a87-4c5d-b929-05b496f21ecc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1675777265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1675777265
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2918526218
Short name T70
Test name
Test status
Simulation time 27063494 ps
CPU time 0.5 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:44 PM PDT 24
Peak memory 144220 kb
Host smart-5a083489-0da8-4c20-889c-d73b29ae9040
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2918526218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2918526218
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1070513152
Short name T73
Test name
Test status
Simulation time 28016990 ps
CPU time 0.41 seconds
Started Apr 28 12:20:19 PM PDT 24
Finished Apr 28 12:20:19 PM PDT 24
Peak memory 145472 kb
Host smart-7b996b09-eec0-4f2e-913c-1cf562b92b0a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1070513152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1070513152
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3074526254
Short name T78
Test name
Test status
Simulation time 26392205 ps
CPU time 0.41 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 145388 kb
Host smart-56e6edbb-dbc4-43a6-9d00-9c20bed48193
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3074526254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3074526254
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2133291193
Short name T66
Test name
Test status
Simulation time 28320876 ps
CPU time 0.39 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 145400 kb
Host smart-8e59630a-4dcf-4ea8-b643-48ff771def1d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2133291193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2133291193
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.781978461
Short name T79
Test name
Test status
Simulation time 26756573 ps
CPU time 0.46 seconds
Started Apr 28 12:22:34 PM PDT 24
Finished Apr 28 12:22:37 PM PDT 24
Peak memory 143640 kb
Host smart-8f49bd3b-5ce7-4b66-b6d8-2488d3d7149a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=781978461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.781978461
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4184072112
Short name T74
Test name
Test status
Simulation time 27897287 ps
CPU time 0.42 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:01 PM PDT 24
Peak memory 145152 kb
Host smart-3ad18114-c662-41e5-89e2-6e7774f5cfb2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4184072112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4184072112
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4095550023
Short name T67
Test name
Test status
Simulation time 27035711 ps
CPU time 0.39 seconds
Started Apr 28 12:22:07 PM PDT 24
Finished Apr 28 12:22:10 PM PDT 24
Peak memory 145412 kb
Host smart-5d3fcc6d-ec99-477b-8481-57b6b050dc2c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4095550023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.4095550023
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1073280524
Short name T77
Test name
Test status
Simulation time 26730094 ps
CPU time 0.41 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:14 PM PDT 24
Peak memory 145012 kb
Host smart-57421830-69c5-4e0b-acc6-372b45e9ae98
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1073280524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1073280524
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.372533777
Short name T68
Test name
Test status
Simulation time 28443523 ps
CPU time 0.4 seconds
Started Apr 28 12:18:01 PM PDT 24
Finished Apr 28 12:18:02 PM PDT 24
Peak memory 145424 kb
Host smart-cc847da8-0978-4586-8121-41f582767e5f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=372533777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.372533777
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2087308472
Short name T69
Test name
Test status
Simulation time 26990515 ps
CPU time 0.39 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:42 PM PDT 24
Peak memory 145396 kb
Host smart-7a60e3bf-e350-45e5-a691-344847cb8ae3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2087308472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2087308472
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2299342155
Short name T76
Test name
Test status
Simulation time 28088390 ps
CPU time 0.4 seconds
Started Apr 28 12:18:09 PM PDT 24
Finished Apr 28 12:18:10 PM PDT 24
Peak memory 145456 kb
Host smart-b984e682-b3ea-40ea-9427-dd4bb345d45e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2299342155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2299342155
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.104391624
Short name T62
Test name
Test status
Simulation time 29412370 ps
CPU time 0.41 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:48 PM PDT 24
Peak memory 145124 kb
Host smart-8507997e-e08d-487a-b9e9-d643894189b9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=104391624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.104391624
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1722824499
Short name T11
Test name
Test status
Simulation time 28796476 ps
CPU time 0.4 seconds
Started Apr 28 12:18:01 PM PDT 24
Finished Apr 28 12:18:02 PM PDT 24
Peak memory 145424 kb
Host smart-c01d9b78-3b2d-4d80-b288-6535c0f20e8a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1722824499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1722824499
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2978068677
Short name T71
Test name
Test status
Simulation time 25139307 ps
CPU time 0.39 seconds
Started Apr 28 12:17:36 PM PDT 24
Finished Apr 28 12:17:37 PM PDT 24
Peak memory 145212 kb
Host smart-1880a05f-f259-4d97-a043-e4296ba3bd95
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2978068677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2978068677
Directory /workspace/9.prim_sync_fatal_alert/latest
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