| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.42 | 88.42 | 100.00 | 100.00 | 95.83 | 95.83 | 96.43 | 96.43 | 75.00 | 75.00 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/18.prim_async_alert.3176311666 |
| 91.55 | 3.13 | 100.00 | 0.00 | 95.83 | 0.00 | 96.43 | 0.00 | 82.14 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/0.prim_sync_alert.3124485199 |
| 93.90 | 2.35 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 3.57 | 85.71 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.716124927 |
| 94.50 | 0.60 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/11.prim_async_alert.92350710 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3698010851 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/11.prim_sync_alert.857354637 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.3244686518 |
| /workspace/coverage/default/1.prim_async_alert.568545027 |
| /workspace/coverage/default/10.prim_async_alert.777450019 |
| /workspace/coverage/default/12.prim_async_alert.1198444689 |
| /workspace/coverage/default/13.prim_async_alert.4012851939 |
| /workspace/coverage/default/14.prim_async_alert.2993957519 |
| /workspace/coverage/default/15.prim_async_alert.1619694758 |
| /workspace/coverage/default/16.prim_async_alert.2243336818 |
| /workspace/coverage/default/17.prim_async_alert.4293962220 |
| /workspace/coverage/default/19.prim_async_alert.3459491031 |
| /workspace/coverage/default/2.prim_async_alert.2090113852 |
| /workspace/coverage/default/3.prim_async_alert.3030640246 |
| /workspace/coverage/default/4.prim_async_alert.1304310472 |
| /workspace/coverage/default/5.prim_async_alert.96800852 |
| /workspace/coverage/default/6.prim_async_alert.1366268589 |
| /workspace/coverage/default/7.prim_async_alert.3542499730 |
| /workspace/coverage/default/8.prim_async_alert.2005451610 |
| /workspace/coverage/default/9.prim_async_alert.719107579 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1478262400 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3019959855 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3735788949 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.376782755 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3251964840 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1030924575 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.482173941 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2020189534 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3962171324 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.309400064 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1886179349 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3555429037 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.852452311 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.727300246 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1012483984 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1695214879 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1084945390 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2657060839 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.1091131419 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.2379063816 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.1994099923 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.940158107 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.337156465 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.3952457343 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.3557793183 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.2092705105 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.4008171491 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.829093753 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.1177341149 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.2418291978 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.355881298 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.224006201 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.3856862226 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.3225307372 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.1286729135 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1343452248 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1922706908 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2382066720 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2638873160 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1282838403 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1220206603 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.800395225 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1455478177 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2289129917 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2257066788 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4272691127 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3732533721 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.383249838 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3825830543 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3829491399 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4041225571 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3225567387 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1013558531 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.340881477 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2055279634 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.133856383 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/2.prim_async_alert.2090113852 | Apr 30 12:17:10 PM PDT 24 | Apr 30 12:17:12 PM PDT 24 | 11984204 ps | ||
| T2 | /workspace/coverage/default/12.prim_async_alert.1198444689 | Apr 30 12:22:46 PM PDT 24 | Apr 30 12:22:48 PM PDT 24 | 11079229 ps | ||
| T3 | /workspace/coverage/default/6.prim_async_alert.1366268589 | Apr 30 12:17:07 PM PDT 24 | Apr 30 12:17:08 PM PDT 24 | 11684338 ps | ||
| T7 | /workspace/coverage/default/18.prim_async_alert.3176311666 | Apr 30 12:22:48 PM PDT 24 | Apr 30 12:22:50 PM PDT 24 | 10827846 ps | ||
| T9 | /workspace/coverage/default/11.prim_async_alert.92350710 | Apr 30 12:22:47 PM PDT 24 | Apr 30 12:22:49 PM PDT 24 | 11123453 ps | ||
| T16 | /workspace/coverage/default/8.prim_async_alert.2005451610 | Apr 30 12:16:58 PM PDT 24 | Apr 30 12:16:59 PM PDT 24 | 10589075 ps | ||
| T8 | /workspace/coverage/default/16.prim_async_alert.2243336818 | Apr 30 12:23:01 PM PDT 24 | Apr 30 12:23:04 PM PDT 24 | 10984832 ps | ||
| T17 | /workspace/coverage/default/7.prim_async_alert.3542499730 | Apr 30 12:17:11 PM PDT 24 | Apr 30 12:17:12 PM PDT 24 | 11477232 ps | ||
| T15 | /workspace/coverage/default/9.prim_async_alert.719107579 | Apr 30 12:17:07 PM PDT 24 | Apr 30 12:17:08 PM PDT 24 | 10736994 ps | ||
| T18 | /workspace/coverage/default/17.prim_async_alert.4293962220 | Apr 30 12:22:04 PM PDT 24 | Apr 30 12:22:06 PM PDT 24 | 10688105 ps | ||
| T11 | /workspace/coverage/default/13.prim_async_alert.4012851939 | Apr 30 12:22:03 PM PDT 24 | Apr 30 12:22:05 PM PDT 24 | 12085269 ps | ||
| T39 | /workspace/coverage/default/4.prim_async_alert.1304310472 | Apr 30 12:17:07 PM PDT 24 | Apr 30 12:17:08 PM PDT 24 | 10853285 ps | ||
| T12 | /workspace/coverage/default/5.prim_async_alert.96800852 | Apr 30 12:17:03 PM PDT 24 | Apr 30 12:17:04 PM PDT 24 | 12431372 ps | ||
| T19 | /workspace/coverage/default/14.prim_async_alert.2993957519 | Apr 30 12:22:48 PM PDT 24 | Apr 30 12:22:50 PM PDT 24 | 10349914 ps | ||
| T48 | /workspace/coverage/default/3.prim_async_alert.3030640246 | Apr 30 12:17:03 PM PDT 24 | Apr 30 12:17:04 PM PDT 24 | 11529291 ps | ||
| T20 | /workspace/coverage/default/0.prim_async_alert.3244686518 | Apr 30 12:17:11 PM PDT 24 | Apr 30 12:17:12 PM PDT 24 | 12040763 ps | ||
| T49 | /workspace/coverage/default/15.prim_async_alert.1619694758 | Apr 30 12:22:46 PM PDT 24 | Apr 30 12:22:48 PM PDT 24 | 10655385 ps | ||
| T50 | /workspace/coverage/default/10.prim_async_alert.777450019 | Apr 30 12:21:21 PM PDT 24 | Apr 30 12:21:22 PM PDT 24 | 11975038 ps | ||
| T21 | /workspace/coverage/default/1.prim_async_alert.568545027 | Apr 30 12:17:03 PM PDT 24 | Apr 30 12:17:04 PM PDT 24 | 10426840 ps | ||
| T51 | /workspace/coverage/default/19.prim_async_alert.3459491031 | Apr 30 12:22:48 PM PDT 24 | Apr 30 12:22:50 PM PDT 24 | 12598721 ps | ||
| T41 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1030924575 | Apr 30 12:22:02 PM PDT 24 | Apr 30 12:22:04 PM PDT 24 | 30557512 ps | ||
| T22 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1695214879 | Apr 30 12:18:20 PM PDT 24 | Apr 30 12:18:20 PM PDT 24 | 28561161 ps | ||
| T13 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.716124927 | Apr 30 12:18:17 PM PDT 24 | Apr 30 12:18:19 PM PDT 24 | 30578504 ps | ||
| T42 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1012483984 | Apr 30 12:20:07 PM PDT 24 | Apr 30 12:20:08 PM PDT 24 | 30941403 ps | ||
| T43 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1084945390 | Apr 30 12:20:56 PM PDT 24 | Apr 30 12:20:57 PM PDT 24 | 30372792 ps | ||
| T44 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1478262400 | Apr 30 12:22:20 PM PDT 24 | Apr 30 12:22:21 PM PDT 24 | 30576173 ps | ||
| T45 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2657060839 | Apr 30 12:18:20 PM PDT 24 | Apr 30 12:18:21 PM PDT 24 | 29061443 ps | ||
| T46 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2020189534 | Apr 30 12:19:58 PM PDT 24 | Apr 30 12:19:59 PM PDT 24 | 31369852 ps | ||
| T4 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3698010851 | Apr 30 12:19:09 PM PDT 24 | Apr 30 12:19:10 PM PDT 24 | 29883420 ps | ||
| T47 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1886179349 | Apr 30 12:20:00 PM PDT 24 | Apr 30 12:20:01 PM PDT 24 | 29521020 ps | ||
| T40 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.727300246 | Apr 30 12:22:13 PM PDT 24 | Apr 30 12:22:15 PM PDT 24 | 27307683 ps | ||
| T52 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3962171324 | Apr 30 12:20:30 PM PDT 24 | Apr 30 12:20:31 PM PDT 24 | 33239279 ps | ||
| T53 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.376782755 | Apr 30 12:19:23 PM PDT 24 | Apr 30 12:19:24 PM PDT 24 | 31116902 ps | ||
| T54 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.309400064 | Apr 30 12:22:02 PM PDT 24 | Apr 30 12:22:03 PM PDT 24 | 28533719 ps | ||
| T14 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.852452311 | Apr 30 12:18:59 PM PDT 24 | Apr 30 12:19:00 PM PDT 24 | 28807190 ps | ||
| T55 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3251964840 | Apr 30 12:20:57 PM PDT 24 | Apr 30 12:20:58 PM PDT 24 | 29556687 ps | ||
| T56 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3019959855 | Apr 30 12:18:19 PM PDT 24 | Apr 30 12:18:20 PM PDT 24 | 28750133 ps | ||
| T57 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3555429037 | Apr 30 12:22:46 PM PDT 24 | Apr 30 12:22:48 PM PDT 24 | 31545017 ps | ||
| T58 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3735788949 | Apr 30 12:20:43 PM PDT 24 | Apr 30 12:20:44 PM PDT 24 | 31630436 ps | ||
| T59 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.482173941 | Apr 30 12:22:11 PM PDT 24 | Apr 30 12:22:13 PM PDT 24 | 30422986 ps | ||
| T32 | /workspace/coverage/sync_alert/19.prim_sync_alert.829093753 | Apr 30 12:17:37 PM PDT 24 | Apr 30 12:17:37 PM PDT 24 | 8991025 ps | ||
| T33 | /workspace/coverage/sync_alert/1.prim_sync_alert.1091131419 | Apr 30 12:23:01 PM PDT 24 | Apr 30 12:23:02 PM PDT 24 | 9529960 ps | ||
| T23 | /workspace/coverage/sync_alert/12.prim_sync_alert.1994099923 | Apr 30 12:18:36 PM PDT 24 | Apr 30 12:18:37 PM PDT 24 | 9295034 ps | ||
| T24 | /workspace/coverage/sync_alert/5.prim_sync_alert.224006201 | Apr 30 12:22:16 PM PDT 24 | Apr 30 12:22:18 PM PDT 24 | 9716905 ps | ||
| T34 | /workspace/coverage/sync_alert/15.prim_sync_alert.3952457343 | Apr 30 12:22:03 PM PDT 24 | Apr 30 12:22:05 PM PDT 24 | 8677763 ps | ||
| T35 | /workspace/coverage/sync_alert/0.prim_sync_alert.3124485199 | Apr 30 12:19:18 PM PDT 24 | Apr 30 12:19:19 PM PDT 24 | 9847953 ps | ||
| T36 | /workspace/coverage/sync_alert/14.prim_sync_alert.337156465 | Apr 30 12:22:15 PM PDT 24 | Apr 30 12:22:17 PM PDT 24 | 8913662 ps | ||
| T37 | /workspace/coverage/sync_alert/3.prim_sync_alert.2418291978 | Apr 30 12:20:10 PM PDT 24 | Apr 30 12:20:11 PM PDT 24 | 10778629 ps | ||
| T25 | /workspace/coverage/sync_alert/6.prim_sync_alert.3856862226 | Apr 30 12:22:13 PM PDT 24 | Apr 30 12:22:15 PM PDT 24 | 9311074 ps | ||
| T38 | /workspace/coverage/sync_alert/8.prim_sync_alert.1286729135 | Apr 30 12:17:37 PM PDT 24 | Apr 30 12:17:37 PM PDT 24 | 9509087 ps | ||
| T26 | /workspace/coverage/sync_alert/13.prim_sync_alert.940158107 | Apr 30 12:21:57 PM PDT 24 | Apr 30 12:21:58 PM PDT 24 | 8979427 ps | ||
| T27 | /workspace/coverage/sync_alert/4.prim_sync_alert.355881298 | Apr 30 12:22:13 PM PDT 24 | Apr 30 12:22:15 PM PDT 24 | 8449542 ps | ||
| T28 | /workspace/coverage/sync_alert/18.prim_sync_alert.4008171491 | Apr 30 12:22:03 PM PDT 24 | Apr 30 12:22:05 PM PDT 24 | 9758954 ps | ||
| T60 | /workspace/coverage/sync_alert/16.prim_sync_alert.3557793183 | Apr 30 12:18:58 PM PDT 24 | Apr 30 12:18:58 PM PDT 24 | 9330268 ps | ||
| T61 | /workspace/coverage/sync_alert/17.prim_sync_alert.2092705105 | Apr 30 12:22:21 PM PDT 24 | Apr 30 12:22:22 PM PDT 24 | 9924411 ps | ||
| T29 | /workspace/coverage/sync_alert/7.prim_sync_alert.3225307372 | Apr 30 12:22:14 PM PDT 24 | Apr 30 12:22:17 PM PDT 24 | 9261595 ps | ||
| T62 | /workspace/coverage/sync_alert/2.prim_sync_alert.1177341149 | Apr 30 12:20:44 PM PDT 24 | Apr 30 12:20:45 PM PDT 24 | 8743202 ps | ||
| T10 | /workspace/coverage/sync_alert/11.prim_sync_alert.857354637 | Apr 30 12:19:29 PM PDT 24 | Apr 30 12:19:30 PM PDT 24 | 8851158 ps | ||
| T63 | /workspace/coverage/sync_alert/10.prim_sync_alert.2379063816 | Apr 30 12:21:57 PM PDT 24 | Apr 30 12:21:58 PM PDT 24 | 9163843 ps | ||
| T30 | /workspace/coverage/sync_alert/9.prim_sync_alert.1343452248 | Apr 30 12:22:13 PM PDT 24 | Apr 30 12:22:15 PM PDT 24 | 9646077 ps | ||
| T31 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4272691127 | Apr 30 12:22:48 PM PDT 24 | Apr 30 12:22:50 PM PDT 24 | 27981182 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.383249838 | Apr 30 12:22:58 PM PDT 24 | Apr 30 12:23:00 PM PDT 24 | 26102236 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1282838403 | Apr 30 12:22:03 PM PDT 24 | Apr 30 12:22:05 PM PDT 24 | 24416498 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.800395225 | Apr 30 12:22:02 PM PDT 24 | Apr 30 12:22:03 PM PDT 24 | 26676778 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.340881477 | Apr 30 12:22:02 PM PDT 24 | Apr 30 12:22:03 PM PDT 24 | 27557394 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2382066720 | Apr 30 12:17:57 PM PDT 24 | Apr 30 12:17:58 PM PDT 24 | 26642134 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3829491399 | Apr 30 12:22:10 PM PDT 24 | Apr 30 12:22:11 PM PDT 24 | 28730975 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2257066788 | Apr 30 12:22:04 PM PDT 24 | Apr 30 12:22:06 PM PDT 24 | 29035817 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3732533721 | Apr 30 12:22:47 PM PDT 24 | Apr 30 12:22:49 PM PDT 24 | 29451810 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4041225571 | Apr 30 12:22:11 PM PDT 24 | Apr 30 12:22:13 PM PDT 24 | 28340770 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2289129917 | Apr 30 12:22:06 PM PDT 24 | Apr 30 12:22:08 PM PDT 24 | 27158029 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1922706908 | Apr 30 12:20:25 PM PDT 24 | Apr 30 12:20:26 PM PDT 24 | 28618512 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1220206603 | Apr 30 12:22:58 PM PDT 24 | Apr 30 12:23:00 PM PDT 24 | 27220200 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1013558531 | Apr 30 12:22:28 PM PDT 24 | Apr 30 12:22:29 PM PDT 24 | 27632173 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3825830543 | Apr 30 12:22:13 PM PDT 24 | Apr 30 12:22:16 PM PDT 24 | 28324748 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1455478177 | Apr 30 12:22:46 PM PDT 24 | Apr 30 12:22:48 PM PDT 24 | 26563538 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.133856383 | Apr 30 12:22:58 PM PDT 24 | Apr 30 12:23:00 PM PDT 24 | 28785985 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2638873160 | Apr 30 12:22:03 PM PDT 24 | Apr 30 12:22:05 PM PDT 24 | 26174327 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3225567387 | Apr 30 12:22:03 PM PDT 24 | Apr 30 12:22:05 PM PDT 24 | 29455705 ps | ||
| T80 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2055279634 | Apr 30 12:22:03 PM PDT 24 | Apr 30 12:22:05 PM PDT 24 | 27529380 ps |
| Test location | /workspace/coverage/default/18.prim_async_alert.3176311666 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10827846 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 12:22:48 PM PDT 24 |
| Finished | Apr 30 12:22:50 PM PDT 24 |
| Peak memory | 145308 kb |
| Host | smart-5fcf042a-3d16-432e-9221-9a9c0010807d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176311666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3176311666 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.3124485199 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9847953 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 12:19:18 PM PDT 24 |
| Finished | Apr 30 12:19:19 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-c464ed81-d304-496d-99df-26452d03586c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3124485199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3124485199 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.716124927 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 30578504 ps |
| CPU time | 0.45 seconds |
| Started | Apr 30 12:18:17 PM PDT 24 |
| Finished | Apr 30 12:18:19 PM PDT 24 |
| Peak memory | 143700 kb |
| Host | smart-204b0510-3d46-4b5d-8dd9-a538758ad83a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=716124927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.716124927 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.92350710 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11123453 ps |
| CPU time | 0.37 seconds |
| Started | Apr 30 12:22:47 PM PDT 24 |
| Finished | Apr 30 12:22:49 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-ae01fb93-0753-41b8-b042-dfd53a92bc70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92350710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.92350710 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3698010851 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 29883420 ps |
| CPU time | 0.42 seconds |
| Started | Apr 30 12:19:09 PM PDT 24 |
| Finished | Apr 30 12:19:10 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-e808201e-219f-4178-9f19-159e53232ab2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3698010851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3698010851 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.857354637 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8851158 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:19:29 PM PDT 24 |
| Finished | Apr 30 12:19:30 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-492145df-2949-4e81-8076-17efc10f8752 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=857354637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.857354637 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.3244686518 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12040763 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 12:17:11 PM PDT 24 |
| Finished | Apr 30 12:17:12 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-59352f7f-42fe-452a-9b11-155b8a50593c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244686518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3244686518 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.568545027 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10426840 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:17:03 PM PDT 24 |
| Finished | Apr 30 12:17:04 PM PDT 24 |
| Peak memory | 145852 kb |
| Host | smart-de021b42-993d-4451-a30a-11ce05f3d269 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=568545027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.568545027 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.777450019 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11975038 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:21:21 PM PDT 24 |
| Finished | Apr 30 12:21:22 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-6fb3f34a-e5c0-48ee-8ad2-bc08c56350d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777450019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.777450019 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.1198444689 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11079229 ps |
| CPU time | 0.42 seconds |
| Started | Apr 30 12:22:46 PM PDT 24 |
| Finished | Apr 30 12:22:48 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-d4f5710b-b3f2-45e2-ade0-86646bb33b3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1198444689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1198444689 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.4012851939 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12085269 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:03 PM PDT 24 |
| Finished | Apr 30 12:22:05 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-6bdd6b44-6599-4d66-9445-fce29ec4ac86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4012851939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.4012851939 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.2993957519 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10349914 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:48 PM PDT 24 |
| Finished | Apr 30 12:22:50 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-ab7e7091-d91a-4093-90cd-39295dd3ac8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2993957519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2993957519 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1619694758 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10655385 ps |
| CPU time | 0.42 seconds |
| Started | Apr 30 12:22:46 PM PDT 24 |
| Finished | Apr 30 12:22:48 PM PDT 24 |
| Peak memory | 144276 kb |
| Host | smart-c4ad1b2d-5598-4058-a0e9-9f660e372777 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619694758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1619694758 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.2243336818 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10984832 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:23:01 PM PDT 24 |
| Finished | Apr 30 12:23:04 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-a72f2f7a-642f-45ff-bcef-a59c1d02fce9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2243336818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2243336818 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.4293962220 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10688105 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:22:04 PM PDT 24 |
| Finished | Apr 30 12:22:06 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-84f30f77-76d6-4a2a-8ce9-5acca2e2a662 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4293962220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4293962220 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3459491031 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 12598721 ps |
| CPU time | 0.45 seconds |
| Started | Apr 30 12:22:48 PM PDT 24 |
| Finished | Apr 30 12:22:50 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-f869a091-b4d3-4f7a-abdc-347b708be866 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3459491031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3459491031 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.2090113852 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11984204 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 12:17:10 PM PDT 24 |
| Finished | Apr 30 12:17:12 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-5c18f3d6-3c4a-49d1-addb-124273dbc995 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2090113852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2090113852 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.3030640246 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11529291 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 12:17:03 PM PDT 24 |
| Finished | Apr 30 12:17:04 PM PDT 24 |
| Peak memory | 145848 kb |
| Host | smart-f6616c2c-f0e0-4204-ad47-b3775a234003 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3030640246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3030640246 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.1304310472 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10853285 ps |
| CPU time | 0.44 seconds |
| Started | Apr 30 12:17:07 PM PDT 24 |
| Finished | Apr 30 12:17:08 PM PDT 24 |
| Peak memory | 143220 kb |
| Host | smart-be87fb07-6579-42f5-b25a-85880a3c455e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304310472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1304310472 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.96800852 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12431372 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:17:03 PM PDT 24 |
| Finished | Apr 30 12:17:04 PM PDT 24 |
| Peak memory | 145896 kb |
| Host | smart-31034fb1-d968-49ec-bfde-78d73c1ac489 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96800852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.96800852 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.1366268589 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11684338 ps |
| CPU time | 0.5 seconds |
| Started | Apr 30 12:17:07 PM PDT 24 |
| Finished | Apr 30 12:17:08 PM PDT 24 |
| Peak memory | 143436 kb |
| Host | smart-c81b53f7-1260-482a-bb2c-807e5d80726a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1366268589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1366268589 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.3542499730 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11477232 ps |
| CPU time | 0.37 seconds |
| Started | Apr 30 12:17:11 PM PDT 24 |
| Finished | Apr 30 12:17:12 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-ce4d16de-9e95-4b44-b916-1e44bf5e5723 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542499730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3542499730 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2005451610 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10589075 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:16:58 PM PDT 24 |
| Finished | Apr 30 12:16:59 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-058c87a0-892b-411f-b2a3-0252043d478f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005451610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2005451610 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.719107579 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10736994 ps |
| CPU time | 0.46 seconds |
| Started | Apr 30 12:17:07 PM PDT 24 |
| Finished | Apr 30 12:17:08 PM PDT 24 |
| Peak memory | 143780 kb |
| Host | smart-42020f9c-d5ed-4025-950b-b20117a7bd77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=719107579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.719107579 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1478262400 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30576173 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:20 PM PDT 24 |
| Finished | Apr 30 12:22:21 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-db5ee592-61aa-45d9-b365-c89706311755 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1478262400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1478262400 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3019959855 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 28750133 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:18:19 PM PDT 24 |
| Finished | Apr 30 12:18:20 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-2af051f8-bf4e-4f16-bd98-60a22f1fb42b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3019959855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3019959855 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3735788949 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 31630436 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:20:43 PM PDT 24 |
| Finished | Apr 30 12:20:44 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-80293c6f-36cf-47e3-8057-964eaa40031a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3735788949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3735788949 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.376782755 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 31116902 ps |
| CPU time | 0.43 seconds |
| Started | Apr 30 12:19:23 PM PDT 24 |
| Finished | Apr 30 12:19:24 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-c1fc620f-2098-408f-8101-7fa324f7ca07 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=376782755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.376782755 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3251964840 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29556687 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:20:57 PM PDT 24 |
| Finished | Apr 30 12:20:58 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-be70897d-4662-4cfb-bcae-261f703a3ce6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3251964840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3251964840 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1030924575 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30557512 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:02 PM PDT 24 |
| Finished | Apr 30 12:22:04 PM PDT 24 |
| Peak memory | 145400 kb |
| Host | smart-9c98dbde-dc9a-4ecd-881c-502bb8b08ecf |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1030924575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1030924575 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.482173941 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 30422986 ps |
| CPU time | 0.43 seconds |
| Started | Apr 30 12:22:11 PM PDT 24 |
| Finished | Apr 30 12:22:13 PM PDT 24 |
| Peak memory | 143816 kb |
| Host | smart-537c9cc4-4d18-488c-9781-5037550cc64b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=482173941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.482173941 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2020189534 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 31369852 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 12:19:58 PM PDT 24 |
| Finished | Apr 30 12:19:59 PM PDT 24 |
| Peak memory | 145852 kb |
| Host | smart-3a7aa634-d281-4af1-acc9-0c77d5a8d9e2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2020189534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2020189534 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3962171324 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 33239279 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:20:30 PM PDT 24 |
| Finished | Apr 30 12:20:31 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-f3d81bb3-c834-4041-8799-6dde0fb26d15 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3962171324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3962171324 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.309400064 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 28533719 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:22:02 PM PDT 24 |
| Finished | Apr 30 12:22:03 PM PDT 24 |
| Peak memory | 144368 kb |
| Host | smart-b7c4d712-596f-44ff-8eec-2b66fecc4453 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=309400064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.309400064 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1886179349 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 29521020 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 12:20:00 PM PDT 24 |
| Finished | Apr 30 12:20:01 PM PDT 24 |
| Peak memory | 145728 kb |
| Host | smart-d6938887-e874-44c0-9bb9-521213698f47 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1886179349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1886179349 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3555429037 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 31545017 ps |
| CPU time | 0.43 seconds |
| Started | Apr 30 12:22:46 PM PDT 24 |
| Finished | Apr 30 12:22:48 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-0d50f4f3-ee8e-4051-93ee-751add07e1e7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3555429037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3555429037 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.852452311 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 28807190 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:18:59 PM PDT 24 |
| Finished | Apr 30 12:19:00 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-b198ce10-b463-47f4-89f9-52ee61690b90 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=852452311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.852452311 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.727300246 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 27307683 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:13 PM PDT 24 |
| Finished | Apr 30 12:22:15 PM PDT 24 |
| Peak memory | 145360 kb |
| Host | smart-3ee135c3-bf50-4e98-bb31-2008bc9ed36c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=727300246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.727300246 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1012483984 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30941403 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 12:20:07 PM PDT 24 |
| Finished | Apr 30 12:20:08 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-87f832ad-dd2e-4c35-aca9-90fc51d079a4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1012483984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1012483984 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1695214879 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 28561161 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 12:18:20 PM PDT 24 |
| Finished | Apr 30 12:18:20 PM PDT 24 |
| Peak memory | 145376 kb |
| Host | smart-a12993a3-7bb8-441c-8132-c2b94cde524e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1695214879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1695214879 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1084945390 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30372792 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 12:20:56 PM PDT 24 |
| Finished | Apr 30 12:20:57 PM PDT 24 |
| Peak memory | 144596 kb |
| Host | smart-22b9bdd4-aa5a-4bc8-bc38-4a55b72cde08 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1084945390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1084945390 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2657060839 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29061443 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:18:20 PM PDT 24 |
| Finished | Apr 30 12:18:21 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-185cd0c4-04f0-4323-9f54-539720e79f05 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2657060839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2657060839 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.1091131419 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9529960 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 12:23:01 PM PDT 24 |
| Finished | Apr 30 12:23:02 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-97e95349-45b6-4cf4-a3ff-ab508c31403a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1091131419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1091131419 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.2379063816 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 9163843 ps |
| CPU time | 0.42 seconds |
| Started | Apr 30 12:21:57 PM PDT 24 |
| Finished | Apr 30 12:21:58 PM PDT 24 |
| Peak memory | 143400 kb |
| Host | smart-c5713aae-b9ae-4e27-ae42-51a81246019e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2379063816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2379063816 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.1994099923 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9295034 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 12:18:36 PM PDT 24 |
| Finished | Apr 30 12:18:37 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-bce29aa0-52c2-41d0-9368-ae83287f8165 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1994099923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1994099923 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.940158107 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8979427 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:21:57 PM PDT 24 |
| Finished | Apr 30 12:21:58 PM PDT 24 |
| Peak memory | 143460 kb |
| Host | smart-03997012-8984-4980-bc22-6719c8e2f812 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=940158107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.940158107 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.337156465 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8913662 ps |
| CPU time | 0.37 seconds |
| Started | Apr 30 12:22:15 PM PDT 24 |
| Finished | Apr 30 12:22:17 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-4d9ba5da-2fde-4e1c-8ed2-270db9894a42 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=337156465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.337156465 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3952457343 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8677763 ps |
| CPU time | 0.37 seconds |
| Started | Apr 30 12:22:03 PM PDT 24 |
| Finished | Apr 30 12:22:05 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-337aa3c0-3339-495d-9f9b-6395abc79a7b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3952457343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3952457343 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.3557793183 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9330268 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 12:18:58 PM PDT 24 |
| Finished | Apr 30 12:18:58 PM PDT 24 |
| Peak memory | 145396 kb |
| Host | smart-93061b64-7727-45bd-9579-68af56948051 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3557793183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3557793183 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.2092705105 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9924411 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:21 PM PDT 24 |
| Finished | Apr 30 12:22:22 PM PDT 24 |
| Peak memory | 145340 kb |
| Host | smart-4881fae1-5b4f-476a-b90e-2cd118701198 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2092705105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2092705105 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.4008171491 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9758954 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 12:22:03 PM PDT 24 |
| Finished | Apr 30 12:22:05 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-5a829aa4-40d3-4404-a98c-38be0d2533a8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4008171491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.4008171491 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.829093753 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8991025 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:17:37 PM PDT 24 |
| Finished | Apr 30 12:17:37 PM PDT 24 |
| Peak memory | 145508 kb |
| Host | smart-8f9cdded-6888-4158-8c85-6d408a920fc4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=829093753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.829093753 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.1177341149 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 8743202 ps |
| CPU time | 0.42 seconds |
| Started | Apr 30 12:20:44 PM PDT 24 |
| Finished | Apr 30 12:20:45 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-f01d1038-f571-4205-9448-5079646c0aa0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1177341149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1177341149 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.2418291978 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10778629 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 12:20:10 PM PDT 24 |
| Finished | Apr 30 12:20:11 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-81541cfe-70e2-4d70-9901-d6edf4c33013 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2418291978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2418291978 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.355881298 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8449542 ps |
| CPU time | 0.44 seconds |
| Started | Apr 30 12:22:13 PM PDT 24 |
| Finished | Apr 30 12:22:15 PM PDT 24 |
| Peak memory | 143560 kb |
| Host | smart-337fd28a-40fd-4a46-8965-e282f5a41d74 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=355881298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.355881298 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.224006201 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9716905 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 12:22:16 PM PDT 24 |
| Finished | Apr 30 12:22:18 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-f31981ed-35a0-4e6e-a9a6-393155f15b62 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=224006201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.224006201 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.3856862226 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9311074 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:13 PM PDT 24 |
| Finished | Apr 30 12:22:15 PM PDT 24 |
| Peak memory | 143572 kb |
| Host | smart-c17e0069-bf84-414a-84f1-0c7fb8175ece |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3856862226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3856862226 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.3225307372 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9261595 ps |
| CPU time | 0.35 seconds |
| Started | Apr 30 12:22:14 PM PDT 24 |
| Finished | Apr 30 12:22:17 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-2e3ef12f-e4c8-4c61-addc-3193934bf03c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3225307372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3225307372 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1286729135 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9509087 ps |
| CPU time | 0.37 seconds |
| Started | Apr 30 12:17:37 PM PDT 24 |
| Finished | Apr 30 12:17:37 PM PDT 24 |
| Peak memory | 145512 kb |
| Host | smart-40763fb4-ec45-4135-9680-349b9ea254d6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1286729135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1286729135 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1343452248 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9646077 ps |
| CPU time | 0.36 seconds |
| Started | Apr 30 12:22:13 PM PDT 24 |
| Finished | Apr 30 12:22:15 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-55335c56-41a7-4559-a188-aa5fa04989b7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1343452248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1343452248 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1922706908 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28618512 ps |
| CPU time | 0.42 seconds |
| Started | Apr 30 12:20:25 PM PDT 24 |
| Finished | Apr 30 12:20:26 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-ff5f7b21-4b65-4650-9d55-f3854e37de5d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1922706908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1922706908 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2382066720 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26642134 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 12:17:57 PM PDT 24 |
| Finished | Apr 30 12:17:58 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-a5e4764e-4f9f-4022-90ed-4ac069dc7a72 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2382066720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2382066720 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2638873160 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26174327 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 12:22:03 PM PDT 24 |
| Finished | Apr 30 12:22:05 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-602e3f19-cb73-4052-b8a8-9d5f7d075918 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2638873160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2638873160 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1282838403 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 24416498 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:03 PM PDT 24 |
| Finished | Apr 30 12:22:05 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-68a32eae-f9ca-421e-bc71-3081f01d7838 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1282838403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1282838403 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1220206603 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27220200 ps |
| CPU time | 0.38 seconds |
| Started | Apr 30 12:22:58 PM PDT 24 |
| Finished | Apr 30 12:23:00 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-93b83cf8-b291-4b51-b40c-3c3c29cd803f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1220206603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1220206603 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.800395225 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 26676778 ps |
| CPU time | 0.48 seconds |
| Started | Apr 30 12:22:02 PM PDT 24 |
| Finished | Apr 30 12:22:03 PM PDT 24 |
| Peak memory | 144452 kb |
| Host | smart-fc118302-bc7f-4e91-8eeb-a71aabaf7227 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=800395225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.800395225 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1455478177 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 26563538 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:46 PM PDT 24 |
| Finished | Apr 30 12:22:48 PM PDT 24 |
| Peak memory | 145840 kb |
| Host | smart-6581d48c-e870-4116-ba4e-18e9eb8c7712 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1455478177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1455478177 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2289129917 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27158029 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:06 PM PDT 24 |
| Finished | Apr 30 12:22:08 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-efa0cf5f-dc9f-445c-b4b1-3f8201ecf277 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2289129917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2289129917 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2257066788 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 29035817 ps |
| CPU time | 0.5 seconds |
| Started | Apr 30 12:22:04 PM PDT 24 |
| Finished | Apr 30 12:22:06 PM PDT 24 |
| Peak memory | 143992 kb |
| Host | smart-0950df34-7d21-4723-bb11-62b5c3c7ae15 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2257066788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2257066788 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.4272691127 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 27981182 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:22:48 PM PDT 24 |
| Finished | Apr 30 12:22:50 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-7b49f9bf-99a7-42b5-8a01-e019f65facde |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4272691127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.4272691127 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3732533721 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 29451810 ps |
| CPU time | 0.44 seconds |
| Started | Apr 30 12:22:47 PM PDT 24 |
| Finished | Apr 30 12:22:49 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-809a4e50-1485-4760-9fa6-cb0ce6713167 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3732533721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3732533721 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.383249838 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26102236 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:58 PM PDT 24 |
| Finished | Apr 30 12:23:00 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-4670c4c8-248c-43d2-9efa-7c13a31acd50 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=383249838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.383249838 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3825830543 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 28324748 ps |
| CPU time | 0.42 seconds |
| Started | Apr 30 12:22:13 PM PDT 24 |
| Finished | Apr 30 12:22:16 PM PDT 24 |
| Peak memory | 144140 kb |
| Host | smart-129f52c2-5de1-4f6a-bb97-543d4e358f4d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3825830543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3825830543 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3829491399 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28730975 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:10 PM PDT 24 |
| Finished | Apr 30 12:22:11 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-28646d93-9ee4-432b-a9f9-f091eb5634f7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3829491399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3829491399 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4041225571 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28340770 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:22:11 PM PDT 24 |
| Finished | Apr 30 12:22:13 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-e2ded88f-5e7c-43b6-bc85-2abfae3d5065 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4041225571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.4041225571 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3225567387 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 29455705 ps |
| CPU time | 0.44 seconds |
| Started | Apr 30 12:22:03 PM PDT 24 |
| Finished | Apr 30 12:22:05 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-56c109a1-dd99-437c-9b1c-4c584dabbdfd |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3225567387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3225567387 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1013558531 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27632173 ps |
| CPU time | 0.4 seconds |
| Started | Apr 30 12:22:28 PM PDT 24 |
| Finished | Apr 30 12:22:29 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-71eec42e-598a-4235-975d-88386e594a5d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1013558531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1013558531 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.340881477 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27557394 ps |
| CPU time | 0.42 seconds |
| Started | Apr 30 12:22:02 PM PDT 24 |
| Finished | Apr 30 12:22:03 PM PDT 24 |
| Peak memory | 144624 kb |
| Host | smart-2cb164a3-03f3-4d12-9786-efd5821983fd |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=340881477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.340881477 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2055279634 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 27529380 ps |
| CPU time | 0.41 seconds |
| Started | Apr 30 12:22:03 PM PDT 24 |
| Finished | Apr 30 12:22:05 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-aba1215f-5e7d-49ab-93a7-6af5f927f0f9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2055279634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2055279634 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.133856383 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 28785985 ps |
| CPU time | 0.39 seconds |
| Started | Apr 30 12:22:58 PM PDT 24 |
| Finished | Apr 30 12:23:00 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-0b55d552-bc35-4902-92ad-a9ec78aeea9e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=133856383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.133856383 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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