Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	100.00	100.00	89.29	95.83	86.05

Total tests in report: 79

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
88.67	88.67	100.00	100.00	93.75	93.75	96.43	96.43	78.57	78.57	95.83	95.83	67.44	67.44	/workspace/coverage/default/8.prim_async_alert.2467838883
91.55	2.88	100.00	0.00	95.83	2.08	96.43	0.00	82.14	3.57	95.83	0.00	79.07	11.63	/workspace/coverage/sync_alert/13.prim_sync_alert.991816112
93.90	2.35	100.00	0.00	95.83	0.00	100.00	3.57	85.71	3.57	95.83	0.00	86.05	6.98	/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2102245636
94.50	0.60	100.00	0.00	95.83	0.00	100.00	0.00	89.29	3.57	95.83	0.00	86.05	0.00	/workspace/coverage/default/12.prim_async_alert.494079061
94.85	0.35	100.00	0.00	97.92	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspace/coverage/default/18.prim_async_alert.3657296523
95.19	0.35	100.00	0.00	100.00	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1709240358

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.793383268
/workspace/coverage/default/1.prim_async_alert.3324937280
/workspace/coverage/default/10.prim_async_alert.1797527786
/workspace/coverage/default/11.prim_async_alert.1135732985
/workspace/coverage/default/13.prim_async_alert.1295323948
/workspace/coverage/default/14.prim_async_alert.4186459479
/workspace/coverage/default/15.prim_async_alert.879153537
/workspace/coverage/default/16.prim_async_alert.2907582462
/workspace/coverage/default/17.prim_async_alert.4147564369
/workspace/coverage/default/19.prim_async_alert.1368261410
/workspace/coverage/default/2.prim_async_alert.4148955358
/workspace/coverage/default/3.prim_async_alert.151983561
/workspace/coverage/default/4.prim_async_alert.235678988
/workspace/coverage/default/5.prim_async_alert.2512499032
/workspace/coverage/default/6.prim_async_alert.1528854906
/workspace/coverage/default/7.prim_async_alert.1611288369
/workspace/coverage/default/9.prim_async_alert.2767446988
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2583684266
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2748242914
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4085962818
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3384838229
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3180208208
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1214224371
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2932916796
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2683768359
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2975974769
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2434960681
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1396397514
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2499241608
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3988787750
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1903664682
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2256952637
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4101488091
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2202507477
/workspace/coverage/sync_alert/0.prim_sync_alert.1062782896
/workspace/coverage/sync_alert/1.prim_sync_alert.1381606156
/workspace/coverage/sync_alert/10.prim_sync_alert.3433709512
/workspace/coverage/sync_alert/11.prim_sync_alert.1129474696
/workspace/coverage/sync_alert/12.prim_sync_alert.155865357
/workspace/coverage/sync_alert/14.prim_sync_alert.3115845041
/workspace/coverage/sync_alert/15.prim_sync_alert.597876271
/workspace/coverage/sync_alert/16.prim_sync_alert.753531063
/workspace/coverage/sync_alert/17.prim_sync_alert.2988839916
/workspace/coverage/sync_alert/18.prim_sync_alert.4065704818
/workspace/coverage/sync_alert/19.prim_sync_alert.1779300733
/workspace/coverage/sync_alert/2.prim_sync_alert.2346204632
/workspace/coverage/sync_alert/3.prim_sync_alert.1137034938
/workspace/coverage/sync_alert/4.prim_sync_alert.4217132165
/workspace/coverage/sync_alert/5.prim_sync_alert.2805621064
/workspace/coverage/sync_alert/6.prim_sync_alert.1165497073
/workspace/coverage/sync_alert/7.prim_sync_alert.4047577933
/workspace/coverage/sync_alert/8.prim_sync_alert.739195604
/workspace/coverage/sync_alert/9.prim_sync_alert.2036551744
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.381327496
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3660047179
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1343387773
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3769314117
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4239461337
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.404544076
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3549184844
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.775965731
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.340030827
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.675049397
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2911391955
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1945212070
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2061934976
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3690041997
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3764096709
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3029257003
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4062853783
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1310856097
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1308846517
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2557083129

Total test records in report: 79

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/18.prim_async_alert.3657296523	May 02 12:38:02 PM PDT 24	May 02 12:38:04 PM PDT 24	11474925 ps
T2	/workspace/coverage/default/19.prim_async_alert.1368261410	May 02 12:38:05 PM PDT 24	May 02 12:38:07 PM PDT 24	10680352 ps
T3	/workspace/coverage/default/3.prim_async_alert.151983561	May 02 12:38:09 PM PDT 24	May 02 12:38:12 PM PDT 24	11706017 ps
T14	/workspace/coverage/default/2.prim_async_alert.4148955358	May 02 12:37:58 PM PDT 24	May 02 12:37:59 PM PDT 24	11137487 ps
T6	/workspace/coverage/default/8.prim_async_alert.2467838883	May 02 12:38:12 PM PDT 24	May 02 12:38:19 PM PDT 24	11937265 ps
T18	/workspace/coverage/default/7.prim_async_alert.1611288369	May 02 12:37:52 PM PDT 24	May 02 12:37:53 PM PDT 24	10447527 ps
T16	/workspace/coverage/default/1.prim_async_alert.3324937280	May 02 12:38:13 PM PDT 24	May 02 12:38:16 PM PDT 24	10627163 ps
T19	/workspace/coverage/default/11.prim_async_alert.1135732985	May 02 12:37:57 PM PDT 24	May 02 12:37:59 PM PDT 24	10802063 ps
T11	/workspace/coverage/default/4.prim_async_alert.235678988	May 02 12:37:47 PM PDT 24	May 02 12:37:48 PM PDT 24	11383122 ps
T20	/workspace/coverage/default/9.prim_async_alert.2767446988	May 02 12:37:57 PM PDT 24	May 02 12:37:58 PM PDT 24	10426412 ps
T21	/workspace/coverage/default/13.prim_async_alert.1295323948	May 02 12:37:55 PM PDT 24	May 02 12:37:57 PM PDT 24	11831438 ps
T17	/workspace/coverage/default/15.prim_async_alert.879153537	May 02 12:38:00 PM PDT 24	May 02 12:38:01 PM PDT 24	10998603 ps
T12	/workspace/coverage/default/5.prim_async_alert.2512499032	May 02 12:38:27 PM PDT 24	May 02 12:38:28 PM PDT 24	13131856 ps
T13	/workspace/coverage/default/14.prim_async_alert.4186459479	May 02 12:37:59 PM PDT 24	May 02 12:38:01 PM PDT 24	12221575 ps
T22	/workspace/coverage/default/16.prim_async_alert.2907582462	May 02 12:38:03 PM PDT 24	May 02 12:38:04 PM PDT 24	11494097 ps
T47	/workspace/coverage/default/17.prim_async_alert.4147564369	May 02 12:38:00 PM PDT 24	May 02 12:38:01 PM PDT 24	11013230 ps
T15	/workspace/coverage/default/12.prim_async_alert.494079061	May 02 12:38:01 PM PDT 24	May 02 12:38:02 PM PDT 24	10996203 ps
T48	/workspace/coverage/default/10.prim_async_alert.1797527786	May 02 12:38:01 PM PDT 24	May 02 12:38:03 PM PDT 24	12008544 ps
T7	/workspace/coverage/default/6.prim_async_alert.1528854906	May 02 12:38:05 PM PDT 24	May 02 12:38:07 PM PDT 24	11005472 ps
T49	/workspace/coverage/default/0.prim_async_alert.793383268	May 02 12:37:53 PM PDT 24	May 02 12:37:54 PM PDT 24	10700059 ps
T37	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1903664682	May 02 12:38:48 PM PDT 24	May 02 12:38:49 PM PDT 24	30565180 ps
T38	/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2202507477	May 02 12:38:49 PM PDT 24	May 02 12:38:52 PM PDT 24	31286306 ps
T39	/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2102245636	May 02 12:38:56 PM PDT 24	May 02 12:38:58 PM PDT 24	29381399 ps
T40	/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2932916796	May 02 12:38:48 PM PDT 24	May 02 12:38:49 PM PDT 24	29431166 ps
T41	/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2434960681	May 02 12:38:46 PM PDT 24	May 02 12:38:47 PM PDT 24	27953011 ps
T42	/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3384838229	May 02 12:38:59 PM PDT 24	May 02 12:39:01 PM PDT 24	29055172 ps
T43	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3988787750	May 02 12:39:07 PM PDT 24	May 02 12:39:08 PM PDT 24	30175201 ps
T44	/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2975974769	May 02 12:38:52 PM PDT 24	May 02 12:38:54 PM PDT 24	29428287 ps
T45	/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4085962818	May 02 12:38:50 PM PDT 24	May 02 12:38:52 PM PDT 24	30507118 ps
T46	/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4101488091	May 02 12:38:52 PM PDT 24	May 02 12:38:55 PM PDT 24	28759126 ps
T50	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2583684266	May 02 12:38:59 PM PDT 24	May 02 12:39:00 PM PDT 24	29424751 ps
T51	/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1214224371	May 02 12:38:53 PM PDT 24	May 02 12:38:56 PM PDT 24	31358218 ps
T52	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1396397514	May 02 12:38:52 PM PDT 24	May 02 12:38:54 PM PDT 24	29343637 ps
T53	/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2499241608	May 02 12:38:51 PM PDT 24	May 02 12:38:53 PM PDT 24	29731255 ps
T54	/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2256952637	May 02 12:38:49 PM PDT 24	May 02 12:38:50 PM PDT 24	30690828 ps
T55	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2748242914	May 02 12:38:41 PM PDT 24	May 02 12:38:42 PM PDT 24	29722544 ps
T56	/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2683768359	May 02 12:38:39 PM PDT 24	May 02 12:38:40 PM PDT 24	30075960 ps
T4	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1709240358	May 02 12:38:52 PM PDT 24	May 02 12:38:55 PM PDT 24	30673345 ps
T57	/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3180208208	May 02 12:38:55 PM PDT 24	May 02 12:38:58 PM PDT 24	28831399 ps
T23	/workspace/coverage/sync_alert/10.prim_sync_alert.3433709512	May 02 12:38:49 PM PDT 24	May 02 12:38:50 PM PDT 24	9654828 ps
T32	/workspace/coverage/sync_alert/15.prim_sync_alert.597876271	May 02 12:39:00 PM PDT 24	May 02 12:39:02 PM PDT 24	9917241 ps
T24	/workspace/coverage/sync_alert/16.prim_sync_alert.753531063	May 02 12:38:46 PM PDT 24	May 02 12:38:47 PM PDT 24	8706339 ps
T33	/workspace/coverage/sync_alert/6.prim_sync_alert.1165497073	May 02 12:38:49 PM PDT 24	May 02 12:38:51 PM PDT 24	9466907 ps
T25	/workspace/coverage/sync_alert/4.prim_sync_alert.4217132165	May 02 12:38:36 PM PDT 24	May 02 12:38:38 PM PDT 24	10613923 ps
T34	/workspace/coverage/sync_alert/2.prim_sync_alert.2346204632	May 02 12:38:49 PM PDT 24	May 02 12:38:50 PM PDT 24	10240873 ps
T35	/workspace/coverage/sync_alert/7.prim_sync_alert.4047577933	May 02 12:38:35 PM PDT 24	May 02 12:38:37 PM PDT 24	9433660 ps
T26	/workspace/coverage/sync_alert/3.prim_sync_alert.1137034938	May 02 12:38:43 PM PDT 24	May 02 12:38:44 PM PDT 24	8287454 ps
T8	/workspace/coverage/sync_alert/13.prim_sync_alert.991816112	May 02 12:39:03 PM PDT 24	May 02 12:39:04 PM PDT 24	8758996 ps
T36	/workspace/coverage/sync_alert/9.prim_sync_alert.2036551744	May 02 12:38:58 PM PDT 24	May 02 12:38:59 PM PDT 24	8277751 ps
T58	/workspace/coverage/sync_alert/14.prim_sync_alert.3115845041	May 02 12:38:51 PM PDT 24	May 02 12:38:54 PM PDT 24	9601376 ps
T27	/workspace/coverage/sync_alert/19.prim_sync_alert.1779300733	May 02 12:38:51 PM PDT 24	May 02 12:38:54 PM PDT 24	9252404 ps
T28	/workspace/coverage/sync_alert/8.prim_sync_alert.739195604	May 02 12:38:50 PM PDT 24	May 02 12:38:52 PM PDT 24	9372464 ps
T59	/workspace/coverage/sync_alert/18.prim_sync_alert.4065704818	May 02 12:38:55 PM PDT 24	May 02 12:38:57 PM PDT 24	9129063 ps
T29	/workspace/coverage/sync_alert/5.prim_sync_alert.2805621064	May 02 12:38:56 PM PDT 24	May 02 12:38:58 PM PDT 24	10570555 ps
T60	/workspace/coverage/sync_alert/0.prim_sync_alert.1062782896	May 02 12:38:50 PM PDT 24	May 02 12:38:52 PM PDT 24	9357782 ps
T61	/workspace/coverage/sync_alert/11.prim_sync_alert.1129474696	May 02 12:39:10 PM PDT 24	May 02 12:39:12 PM PDT 24	8460837 ps
T62	/workspace/coverage/sync_alert/17.prim_sync_alert.2988839916	May 02 12:38:57 PM PDT 24	May 02 12:38:59 PM PDT 24	8786253 ps
T63	/workspace/coverage/sync_alert/1.prim_sync_alert.1381606156	May 02 12:38:50 PM PDT 24	May 02 12:38:52 PM PDT 24	9131274 ps
T64	/workspace/coverage/sync_alert/12.prim_sync_alert.155865357	May 02 12:38:47 PM PDT 24	May 02 12:38:55 PM PDT 24	10816344 ps
T65	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1343387773	May 02 12:39:03 PM PDT 24	May 02 12:39:04 PM PDT 24	29334853 ps
T30	/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.381327496	May 02 12:38:59 PM PDT 24	May 02 12:39:01 PM PDT 24	27436047 ps
T66	/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1308846517	May 02 12:39:05 PM PDT 24	May 02 12:39:06 PM PDT 24	26109375 ps
T67	/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.340030827	May 02 12:38:52 PM PDT 24	May 02 12:38:55 PM PDT 24	26155000 ps
T9	/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2911391955	May 02 12:38:53 PM PDT 24	May 02 12:38:56 PM PDT 24	29137577 ps
T31	/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.775965731	May 02 12:38:52 PM PDT 24	May 02 12:38:55 PM PDT 24	27087937 ps
T68	/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1945212070	May 02 12:38:50 PM PDT 24	May 02 12:38:52 PM PDT 24	28571459 ps
T69	/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3764096709	May 02 12:39:00 PM PDT 24	May 02 12:39:02 PM PDT 24	24998423 ps
T70	/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2061934976	May 02 12:39:00 PM PDT 24	May 02 12:39:01 PM PDT 24	30399413 ps
T71	/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.675049397	May 02 12:38:53 PM PDT 24	May 02 12:38:56 PM PDT 24	26945506 ps
T5	/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3549184844	May 02 12:39:05 PM PDT 24	May 02 12:39:07 PM PDT 24	24870586 ps
T72	/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.404544076	May 02 12:39:00 PM PDT 24	May 02 12:39:01 PM PDT 24	27712415 ps
T73	/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2557083129	May 02 12:38:53 PM PDT 24	May 02 12:38:55 PM PDT 24	28412678 ps
T74	/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3690041997	May 02 12:38:54 PM PDT 24	May 02 12:38:57 PM PDT 24	27186836 ps
T75	/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4239461337	May 02 12:39:00 PM PDT 24	May 02 12:39:02 PM PDT 24	29434741 ps
T76	/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4062853783	May 02 12:38:44 PM PDT 24	May 02 12:38:45 PM PDT 24	27601694 ps
T77	/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1310856097	May 02 12:38:47 PM PDT 24	May 02 12:38:48 PM PDT 24	26863068 ps
T10	/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3660047179	May 02 12:39:01 PM PDT 24	May 02 12:39:03 PM PDT 24	29192422 ps
T78	/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3769314117	May 02 12:38:59 PM PDT 24	May 02 12:39:01 PM PDT 24	26382367 ps
T79	/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3029257003	May 02 12:38:58 PM PDT 24	May 02 12:38:59 PM PDT 24	30107075 ps

Test location	/workspace/coverage/default/8.prim_async_alert.2467838883
Short name	T6
Test name
Test status
Simulation time	11937265 ps
CPU time	0.38 seconds
Started	May 02 12:38:12 PM PDT 24
Finished	May 02 12:38:19 PM PDT 24
Peak memory	145528 kb
Host	smart-dbb83511-e2f0-474f-a8c3-27612660774b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2467838883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2467838883
Directory	/workspace/8.prim_async_alert/latest

Test location	/workspace/coverage/sync_alert/13.prim_sync_alert.991816112
Short name	T8
Test name
Test status
Simulation time	8758996 ps
CPU time	0.38 seconds
Started	May 02 12:39:03 PM PDT 24
Finished	May 02 12:39:04 PM PDT 24
Peak memory	145164 kb
Host	smart-52bfe9aa-04b3-4c73-b9bf-e6deb83eb6c5
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=991816112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.991816112
Directory	/workspace/13.prim_sync_alert/latest

Test location	/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2102245636
Short name	T39
Test name
Test status
Simulation time	29381399 ps
CPU time	0.4 seconds
Started	May 02 12:38:56 PM PDT 24
Finished	May 02 12:38:58 PM PDT 24
Peak memory	145552 kb
Host	smart-70017921-1685-4576-89a1-3408aee6066a
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2102245636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2102245636
Directory	/workspace/12.prim_async_fatal_alert/latest

Test location	/workspace/coverage/default/12.prim_async_alert.494079061
Short name	T15
Test name
Test status
Simulation time	10996203 ps
CPU time	0.39 seconds
Started	May 02 12:38:01 PM PDT 24
Finished	May 02 12:38:02 PM PDT 24
Peak memory	145544 kb
Host	smart-f3d48d8c-59d6-48af-801a-ef8ef96febe9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494079061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.494079061
Directory	/workspace/12.prim_async_alert/latest

Test location	/workspace/coverage/default/18.prim_async_alert.3657296523
Short name	T1
Test name
Test status
Simulation time	11474925 ps
CPU time	0.39 seconds
Started	May 02 12:38:02 PM PDT 24
Finished	May 02 12:38:04 PM PDT 24
Peak memory	145548 kb
Host	smart-aafa73e9-8b9f-4d21-9883-d93f47472420
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3657296523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3657296523
Directory	/workspace/18.prim_async_alert/latest

Test location	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1709240358
Short name	T4
Test name
Test status
Simulation time	30673345 ps
CPU time	0.41 seconds
Started	May 02 12:38:52 PM PDT 24
Finished	May 02 12:38:55 PM PDT 24
Peak memory	145528 kb
Host	smart-4fe1facd-3c54-4f04-ab96-b61f5a722cd0
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1709240358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1709240358
Directory	/workspace/6.prim_async_fatal_alert/latest

Test location	/workspace/coverage/default/0.prim_async_alert.793383268
Short name	T49
Test name
Test status
Simulation time	10700059 ps
CPU time	0.39 seconds
Started	May 02 12:37:53 PM PDT 24
Finished	May 02 12:37:54 PM PDT 24
Peak memory	145500 kb
Host	smart-b8816b65-d450-42b9-bf0a-69ef964e69f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=793383268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.793383268
Directory	/workspace/0.prim_async_alert/latest

Test location	/workspace/coverage/default/1.prim_async_alert.3324937280
Short name	T16
Test name
Test status
Simulation time	10627163 ps
CPU time	0.45 seconds
Started	May 02 12:38:13 PM PDT 24
Finished	May 02 12:38:16 PM PDT 24
Peak memory	145272 kb
Host	smart-359c51cb-d94a-4c70-a12f-0f4a593196e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3324937280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3324937280
Directory	/workspace/1.prim_async_alert/latest

Test location	/workspace/coverage/default/10.prim_async_alert.1797527786
Short name	T48
Test name
Test status
Simulation time	12008544 ps
CPU time	0.39 seconds
Started	May 02 12:38:01 PM PDT 24
Finished	May 02 12:38:03 PM PDT 24
Peak memory	145568 kb
Host	smart-294186fd-5aa8-4258-8896-254ed87799d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797527786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1797527786
Directory	/workspace/10.prim_async_alert/latest

Test location	/workspace/coverage/default/11.prim_async_alert.1135732985
Short name	T19
Test name
Test status
Simulation time	10802063 ps
CPU time	0.37 seconds
Started	May 02 12:37:57 PM PDT 24
Finished	May 02 12:37:59 PM PDT 24
Peak memory	145500 kb
Host	smart-d9dfe92b-469c-4ec4-94f4-23c022deb16e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1135732985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1135732985
Directory	/workspace/11.prim_async_alert/latest

Test location	/workspace/coverage/default/13.prim_async_alert.1295323948
Short name	T21
Test name
Test status
Simulation time	11831438 ps
CPU time	0.4 seconds
Started	May 02 12:37:55 PM PDT 24
Finished	May 02 12:37:57 PM PDT 24
Peak memory	145876 kb
Host	smart-0100dc14-a006-47d4-8f7f-839389fa5a7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1295323948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1295323948
Directory	/workspace/13.prim_async_alert/latest

Test location	/workspace/coverage/default/14.prim_async_alert.4186459479
Short name	T13
Test name
Test status
Simulation time	12221575 ps
CPU time	0.39 seconds
Started	May 02 12:37:59 PM PDT 24
Finished	May 02 12:38:01 PM PDT 24
Peak memory	145548 kb
Host	smart-71ccd1ed-f2a6-41f3-9a8e-d470f91a9c9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186459479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.4186459479
Directory	/workspace/14.prim_async_alert/latest

Test location	/workspace/coverage/default/15.prim_async_alert.879153537
Short name	T17
Test name
Test status
Simulation time	10998603 ps
CPU time	0.38 seconds
Started	May 02 12:38:00 PM PDT 24
Finished	May 02 12:38:01 PM PDT 24
Peak memory	145572 kb
Host	smart-7fe72c7d-3fc7-4b97-a52a-d856011fccf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879153537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.879153537
Directory	/workspace/15.prim_async_alert/latest

Test location	/workspace/coverage/default/16.prim_async_alert.2907582462
Short name	T22
Test name
Test status
Simulation time	11494097 ps
CPU time	0.38 seconds
Started	May 02 12:38:03 PM PDT 24
Finished	May 02 12:38:04 PM PDT 24
Peak memory	145500 kb
Host	smart-86e59a76-b208-4ff1-a311-aaa94be50493
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907582462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2907582462
Directory	/workspace/16.prim_async_alert/latest

Test location	/workspace/coverage/default/17.prim_async_alert.4147564369
Short name	T47
Test name
Test status
Simulation time	11013230 ps
CPU time	0.39 seconds
Started	May 02 12:38:00 PM PDT 24
Finished	May 02 12:38:01 PM PDT 24
Peak memory	145532 kb
Host	smart-8590f5a9-b5d1-431e-8b4b-de377533f485
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147564369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4147564369
Directory	/workspace/17.prim_async_alert/latest

Test location	/workspace/coverage/default/19.prim_async_alert.1368261410
Short name	T2
Test name
Test status
Simulation time	10680352 ps
CPU time	0.41 seconds
Started	May 02 12:38:05 PM PDT 24
Finished	May 02 12:38:07 PM PDT 24
Peak memory	145536 kb
Host	smart-5547cd6e-0fff-4828-97f3-50f4e3781704
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1368261410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1368261410
Directory	/workspace/19.prim_async_alert/latest

Test location	/workspace/coverage/default/2.prim_async_alert.4148955358
Short name	T14
Test name
Test status
Simulation time	11137487 ps
CPU time	0.39 seconds
Started	May 02 12:37:58 PM PDT 24
Finished	May 02 12:37:59 PM PDT 24
Peak memory	145852 kb
Host	smart-142e52a8-e741-4aba-9268-65c528a27f8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4148955358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.4148955358
Directory	/workspace/2.prim_async_alert/latest

Test location	/workspace/coverage/default/3.prim_async_alert.151983561
Short name	T3
Test name
Test status
Simulation time	11706017 ps
CPU time	0.38 seconds
Started	May 02 12:38:09 PM PDT 24
Finished	May 02 12:38:12 PM PDT 24
Peak memory	145556 kb
Host	smart-3886fdf4-d8be-4845-a6e1-1746bb746e04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=151983561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.151983561
Directory	/workspace/3.prim_async_alert/latest

Test location	/workspace/coverage/default/4.prim_async_alert.235678988
Short name	T11
Test name
Test status
Simulation time	11383122 ps
CPU time	0.41 seconds
Started	May 02 12:37:47 PM PDT 24
Finished	May 02 12:37:48 PM PDT 24
Peak memory	145492 kb
Host	smart-f8d88b01-2902-443c-a7ec-dade52a22643
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235678988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.235678988
Directory	/workspace/4.prim_async_alert/latest

Test location	/workspace/coverage/default/5.prim_async_alert.2512499032
Short name	T12
Test name
Test status
Simulation time	13131856 ps
CPU time	0.38 seconds
Started	May 02 12:38:27 PM PDT 24
Finished	May 02 12:38:28 PM PDT 24
Peak memory	145424 kb
Host	smart-d3fc7457-0e22-4160-9492-32821201d294
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512499032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2512499032
Directory	/workspace/5.prim_async_alert/latest

Test location	/workspace/coverage/default/6.prim_async_alert.1528854906
Short name	T7
Test name
Test status
Simulation time	11005472 ps
CPU time	0.44 seconds
Started	May 02 12:38:05 PM PDT 24
Finished	May 02 12:38:07 PM PDT 24
Peak memory	145252 kb
Host	smart-41337222-ad4b-4469-9924-22eddadfa526
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528854906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1528854906
Directory	/workspace/6.prim_async_alert/latest

Test location	/workspace/coverage/default/7.prim_async_alert.1611288369
Short name	T18
Test name
Test status
Simulation time	10447527 ps
CPU time	0.38 seconds
Started	May 02 12:37:52 PM PDT 24
Finished	May 02 12:37:53 PM PDT 24
Peak memory	145552 kb
Host	smart-a47c14e0-265b-44ce-bcbd-d93514f0e0d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611288369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1611288369
Directory	/workspace/7.prim_async_alert/latest

Test location	/workspace/coverage/default/9.prim_async_alert.2767446988
Short name	T20
Test name
Test status
Simulation time	10426412 ps
CPU time	0.38 seconds
Started	May 02 12:37:57 PM PDT 24
Finished	May 02 12:37:58 PM PDT 24
Peak memory	145488 kb
Host	smart-7072040e-5995-459a-9bd3-1ea3e4879564
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2767446988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2767446988
Directory	/workspace/9.prim_async_alert/latest

Test location	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2583684266
Short name	T50
Test name
Test status
Simulation time	29424751 ps
CPU time	0.4 seconds
Started	May 02 12:38:59 PM PDT 24
Finished	May 02 12:39:00 PM PDT 24
Peak memory	145524 kb
Host	smart-c78b047d-2b2b-4831-b122-75d3ee4f50ad
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2583684266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2583684266
Directory	/workspace/0.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2748242914
Short name	T55
Test name
Test status
Simulation time	29722544 ps
CPU time	0.41 seconds
Started	May 02 12:38:41 PM PDT 24
Finished	May 02 12:38:42 PM PDT 24
Peak memory	145532 kb
Host	smart-9120bc62-e707-4876-aefa-c7ada2242016
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2748242914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2748242914
Directory	/workspace/1.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.4085962818
Short name	T45
Test name
Test status
Simulation time	30507118 ps
CPU time	0.4 seconds
Started	May 02 12:38:50 PM PDT 24
Finished	May 02 12:38:52 PM PDT 24
Peak memory	145536 kb
Host	smart-1ddb8f59-a6ae-4e38-afe9-40be5ca9bb65
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4085962818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.4085962818
Directory	/workspace/10.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3384838229
Short name	T42
Test name
Test status
Simulation time	29055172 ps
CPU time	0.42 seconds
Started	May 02 12:38:59 PM PDT 24
Finished	May 02 12:39:01 PM PDT 24
Peak memory	145520 kb
Host	smart-577d7bcf-1629-419c-9e36-81b2277c81d3
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3384838229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3384838229
Directory	/workspace/11.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3180208208
Short name	T57
Test name
Test status
Simulation time	28831399 ps
CPU time	0.4 seconds
Started	May 02 12:38:55 PM PDT 24
Finished	May 02 12:38:58 PM PDT 24
Peak memory	145640 kb
Host	smart-57214baa-82db-40b7-b544-a73a4beebbf0
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3180208208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3180208208
Directory	/workspace/13.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1214224371
Short name	T51
Test name
Test status
Simulation time	31358218 ps
CPU time	0.4 seconds
Started	May 02 12:38:53 PM PDT 24
Finished	May 02 12:38:56 PM PDT 24
Peak memory	145532 kb
Host	smart-5e34d1ca-1860-4f79-aad0-41bf563c4917
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1214224371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1214224371
Directory	/workspace/14.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2932916796
Short name	T40
Test name
Test status
Simulation time	29431166 ps
CPU time	0.41 seconds
Started	May 02 12:38:48 PM PDT 24
Finished	May 02 12:38:49 PM PDT 24
Peak memory	145576 kb
Host	smart-bbf9c30b-6f07-45a2-a74d-ea54aa5dae32
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2932916796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2932916796
Directory	/workspace/15.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2683768359
Short name	T56
Test name
Test status
Simulation time	30075960 ps
CPU time	0.41 seconds
Started	May 02 12:38:39 PM PDT 24
Finished	May 02 12:38:40 PM PDT 24
Peak memory	145484 kb
Host	smart-de95c086-62da-4291-a929-49a7f292db94
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2683768359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2683768359
Directory	/workspace/16.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2975974769
Short name	T44
Test name
Test status
Simulation time	29428287 ps
CPU time	0.4 seconds
Started	May 02 12:38:52 PM PDT 24
Finished	May 02 12:38:54 PM PDT 24
Peak memory	145512 kb
Host	smart-6d2b3e63-1924-4b18-bd6f-077cbfa8bcd8
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2975974769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2975974769
Directory	/workspace/17.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2434960681
Short name	T41
Test name
Test status
Simulation time	27953011 ps
CPU time	0.4 seconds
Started	May 02 12:38:46 PM PDT 24
Finished	May 02 12:38:47 PM PDT 24
Peak memory	145568 kb
Host	smart-e1f73d9f-d6c1-4b3b-9d6a-dfc753a3f87b
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2434960681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2434960681
Directory	/workspace/18.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1396397514
Short name	T52
Test name
Test status
Simulation time	29343637 ps
CPU time	0.4 seconds
Started	May 02 12:38:52 PM PDT 24
Finished	May 02 12:38:54 PM PDT 24
Peak memory	145580 kb
Host	smart-bf2b720b-3671-41bf-b40d-bad6978e032f
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1396397514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1396397514
Directory	/workspace/19.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2499241608
Short name	T53
Test name
Test status
Simulation time	29731255 ps
CPU time	0.39 seconds
Started	May 02 12:38:51 PM PDT 24
Finished	May 02 12:38:53 PM PDT 24
Peak memory	145508 kb
Host	smart-937230b8-a040-43b3-a9a9-85ca51b13a28
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2499241608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2499241608
Directory	/workspace/2.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3988787750
Short name	T43
Test name
Test status
Simulation time	30175201 ps
CPU time	0.4 seconds
Started	May 02 12:39:07 PM PDT 24
Finished	May 02 12:39:08 PM PDT 24
Peak memory	145568 kb
Host	smart-fadba567-0741-413a-821d-13b67ea6878d
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3988787750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3988787750
Directory	/workspace/3.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1903664682
Short name	T37
Test name
Test status
Simulation time	30565180 ps
CPU time	0.41 seconds
Started	May 02 12:38:48 PM PDT 24
Finished	May 02 12:38:49 PM PDT 24
Peak memory	145524 kb
Host	smart-595364ad-4c69-44fd-8772-af565eeec3d2
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1903664682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1903664682
Directory	/workspace/5.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2256952637
Short name	T54
Test name
Test status
Simulation time	30690828 ps
CPU time	0.42 seconds
Started	May 02 12:38:49 PM PDT 24
Finished	May 02 12:38:50 PM PDT 24
Peak memory	145552 kb
Host	smart-efbb7221-243f-4e2e-a634-c17fd65a6097
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2256952637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2256952637
Directory	/workspace/7.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4101488091
Short name	T46
Test name
Test status
Simulation time	28759126 ps
CPU time	0.41 seconds
Started	May 02 12:38:52 PM PDT 24
Finished	May 02 12:38:55 PM PDT 24
Peak memory	145560 kb
Host	smart-f805b171-85de-4a29-8892-dd4338b16245
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4101488091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.4101488091
Directory	/workspace/8.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2202507477
Short name	T38
Test name
Test status
Simulation time	31286306 ps
CPU time	0.4 seconds
Started	May 02 12:38:49 PM PDT 24
Finished	May 02 12:38:52 PM PDT 24
Peak memory	145552 kb
Host	smart-5596870f-f2a2-4e26-890e-b519c94c35de
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2202507477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2202507477
Directory	/workspace/9.prim_async_fatal_alert/latest

Test location	/workspace/coverage/sync_alert/0.prim_sync_alert.1062782896
Short name	T60
Test name
Test status
Simulation time	9357782 ps
CPU time	0.39 seconds
Started	May 02 12:38:50 PM PDT 24
Finished	May 02 12:38:52 PM PDT 24
Peak memory	145312 kb
Host	smart-c8c8b58e-4649-4290-bc2e-fa8b8be261a3
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1062782896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1062782896
Directory	/workspace/0.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/1.prim_sync_alert.1381606156
Short name	T63
Test name
Test status
Simulation time	9131274 ps
CPU time	0.38 seconds
Started	May 02 12:38:50 PM PDT 24
Finished	May 02 12:38:52 PM PDT 24
Peak memory	145216 kb
Host	smart-6d76dafe-8f27-4155-a890-77dd9bb31a4c
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1381606156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1381606156
Directory	/workspace/1.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/10.prim_sync_alert.3433709512
Short name	T23
Test name
Test status
Simulation time	9654828 ps
CPU time	0.39 seconds
Started	May 02 12:38:49 PM PDT 24
Finished	May 02 12:38:50 PM PDT 24
Peak memory	145288 kb
Host	smart-ef5114be-3854-4a91-9e9c-3247cc33e147
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3433709512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3433709512
Directory	/workspace/10.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/11.prim_sync_alert.1129474696
Short name	T61
Test name
Test status
Simulation time	8460837 ps
CPU time	0.39 seconds
Started	May 02 12:39:10 PM PDT 24
Finished	May 02 12:39:12 PM PDT 24
Peak memory	145828 kb
Host	smart-30d6b0e5-f98f-4e6b-ac75-c1a8a9b56b48
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1129474696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1129474696
Directory	/workspace/11.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/12.prim_sync_alert.155865357
Short name	T64
Test name
Test status
Simulation time	10816344 ps
CPU time	0.38 seconds
Started	May 02 12:38:47 PM PDT 24
Finished	May 02 12:38:55 PM PDT 24
Peak memory	145288 kb
Host	smart-03c89528-57d0-4324-b92b-c211b7b11337
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=155865357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.155865357
Directory	/workspace/12.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/14.prim_sync_alert.3115845041
Short name	T58
Test name
Test status
Simulation time	9601376 ps
CPU time	0.39 seconds
Started	May 02 12:38:51 PM PDT 24
Finished	May 02 12:38:54 PM PDT 24
Peak memory	145264 kb
Host	smart-997e9774-0e6d-4eaa-8e38-5dbaeab8fe2c
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3115845041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3115845041
Directory	/workspace/14.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/15.prim_sync_alert.597876271
Short name	T32
Test name
Test status
Simulation time	9917241 ps
CPU time	0.41 seconds
Started	May 02 12:39:00 PM PDT 24
Finished	May 02 12:39:02 PM PDT 24
Peak memory	145200 kb
Host	smart-8da38d05-dbc2-4f80-a1b8-4a9041712c64
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=597876271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.597876271
Directory	/workspace/15.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/16.prim_sync_alert.753531063
Short name	T24
Test name
Test status
Simulation time	8706339 ps
CPU time	0.38 seconds
Started	May 02 12:38:46 PM PDT 24
Finished	May 02 12:38:47 PM PDT 24
Peak memory	145264 kb
Host	smart-dfca92f5-bb75-48f4-9cc6-ad5ea12e2386
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=753531063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.753531063
Directory	/workspace/16.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/17.prim_sync_alert.2988839916
Short name	T62
Test name
Test status
Simulation time	8786253 ps
CPU time	0.38 seconds
Started	May 02 12:38:57 PM PDT 24
Finished	May 02 12:38:59 PM PDT 24
Peak memory	145392 kb
Host	smart-07a26cea-575e-49cb-a20c-03644058d34d
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2988839916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2988839916
Directory	/workspace/17.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/18.prim_sync_alert.4065704818
Short name	T59
Test name
Test status
Simulation time	9129063 ps
CPU time	0.38 seconds
Started	May 02 12:38:55 PM PDT 24
Finished	May 02 12:38:57 PM PDT 24
Peak memory	145212 kb
Host	smart-cb03dc0a-7313-4d1b-891f-a4d05edabe1a
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4065704818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.4065704818
Directory	/workspace/18.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/19.prim_sync_alert.1779300733
Short name	T27
Test name
Test status
Simulation time	9252404 ps
CPU time	0.42 seconds
Started	May 02 12:38:51 PM PDT 24
Finished	May 02 12:38:54 PM PDT 24
Peak memory	145844 kb
Host	smart-b05f75ad-a7be-414a-9d62-10383e3e0da4
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1779300733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1779300733
Directory	/workspace/19.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/2.prim_sync_alert.2346204632
Short name	T34
Test name
Test status
Simulation time	10240873 ps
CPU time	0.37 seconds
Started	May 02 12:38:49 PM PDT 24
Finished	May 02 12:38:50 PM PDT 24
Peak memory	145268 kb
Host	smart-04181124-f48b-4327-b299-36098b03fb6d
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2346204632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2346204632
Directory	/workspace/2.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/3.prim_sync_alert.1137034938
Short name	T26
Test name
Test status
Simulation time	8287454 ps
CPU time	0.38 seconds
Started	May 02 12:38:43 PM PDT 24
Finished	May 02 12:38:44 PM PDT 24
Peak memory	145268 kb
Host	smart-9501d2e1-fb71-4be1-9a8b-da89d52fa2fa
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1137034938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1137034938
Directory	/workspace/3.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/4.prim_sync_alert.4217132165
Short name	T25
Test name
Test status
Simulation time	10613923 ps
CPU time	0.38 seconds
Started	May 02 12:38:36 PM PDT 24
Finished	May 02 12:38:38 PM PDT 24
Peak memory	145288 kb
Host	smart-4d5391cc-6084-4e86-bc99-3c65173cc1be
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4217132165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.4217132165
Directory	/workspace/4.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/5.prim_sync_alert.2805621064
Short name	T29
Test name
Test status
Simulation time	10570555 ps
CPU time	0.41 seconds
Started	May 02 12:38:56 PM PDT 24
Finished	May 02 12:38:58 PM PDT 24
Peak memory	145176 kb
Host	smart-23c6460e-e2bc-478a-8553-b6f607f389ac
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2805621064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2805621064
Directory	/workspace/5.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/6.prim_sync_alert.1165497073
Short name	T33
Test name
Test status
Simulation time	9466907 ps
CPU time	0.4 seconds
Started	May 02 12:38:49 PM PDT 24
Finished	May 02 12:38:51 PM PDT 24
Peak memory	145176 kb
Host	smart-2430fc2a-6b6d-4d22-8422-b04e33e00c1b
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1165497073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1165497073
Directory	/workspace/6.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/7.prim_sync_alert.4047577933
Short name	T35
Test name
Test status
Simulation time	9433660 ps
CPU time	0.39 seconds
Started	May 02 12:38:35 PM PDT 24
Finished	May 02 12:38:37 PM PDT 24
Peak memory	145296 kb
Host	smart-a2c0208b-060a-41c8-b8f8-9db605121a1d
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4047577933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.4047577933
Directory	/workspace/7.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/8.prim_sync_alert.739195604
Short name	T28
Test name
Test status
Simulation time	9372464 ps
CPU time	0.42 seconds
Started	May 02 12:38:50 PM PDT 24
Finished	May 02 12:38:52 PM PDT 24
Peak memory	145268 kb
Host	smart-2e289dc6-ea55-4ef2-948f-5ded86b91b17
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=739195604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.739195604
Directory	/workspace/8.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/9.prim_sync_alert.2036551744
Short name	T36
Test name
Test status
Simulation time	8277751 ps
CPU time	0.39 seconds
Started	May 02 12:38:58 PM PDT 24
Finished	May 02 12:38:59 PM PDT 24
Peak memory	145308 kb
Host	smart-0f9585cd-6de1-4c5c-a583-979b4ba0a317
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2036551744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2036551744
Directory	/workspace/9.prim_sync_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.381327496
Short name	T30
Test name
Test status
Simulation time	27436047 ps
CPU time	0.41 seconds
Started	May 02 12:38:59 PM PDT 24
Finished	May 02 12:39:01 PM PDT 24
Peak memory	145232 kb
Host	smart-d05b4de4-3ffb-49a3-bb5e-eedca958a0f6
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=381327496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.381327496
Directory	/workspace/0.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3660047179
Short name	T10
Test name
Test status
Simulation time	29192422 ps
CPU time	0.4 seconds
Started	May 02 12:39:01 PM PDT 24
Finished	May 02 12:39:03 PM PDT 24
Peak memory	145284 kb
Host	smart-05fd8357-ddfc-422a-b118-5fc7ed6cb568
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3660047179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3660047179
Directory	/workspace/1.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1343387773
Short name	T65
Test name
Test status
Simulation time	29334853 ps
CPU time	0.42 seconds
Started	May 02 12:39:03 PM PDT 24
Finished	May 02 12:39:04 PM PDT 24
Peak memory	145192 kb
Host	smart-3bdec66c-95e5-4214-ab90-b248e2f194fc
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1343387773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1343387773
Directory	/workspace/10.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3769314117
Short name	T78
Test name
Test status
Simulation time	26382367 ps
CPU time	0.42 seconds
Started	May 02 12:38:59 PM PDT 24
Finished	May 02 12:39:01 PM PDT 24
Peak memory	145244 kb
Host	smart-4553db8d-082d-41b3-83da-0482e5cc9301
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3769314117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3769314117
Directory	/workspace/11.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4239461337
Short name	T75
Test name
Test status
Simulation time	29434741 ps
CPU time	0.46 seconds
Started	May 02 12:39:00 PM PDT 24
Finished	May 02 12:39:02 PM PDT 24
Peak memory	145816 kb
Host	smart-0adf1f6f-d24d-4ff1-a472-94a801c5bb9c
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4239461337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4239461337
Directory	/workspace/12.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.404544076
Short name	T72
Test name
Test status
Simulation time	27712415 ps
CPU time	0.42 seconds
Started	May 02 12:39:00 PM PDT 24
Finished	May 02 12:39:01 PM PDT 24
Peak memory	145444 kb
Host	smart-1d2a2cce-c4f2-4cd6-af94-8c0415344f70
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=404544076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.404544076
Directory	/workspace/13.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3549184844
Short name	T5
Test name
Test status
Simulation time	24870586 ps
CPU time	0.38 seconds
Started	May 02 12:39:05 PM PDT 24
Finished	May 02 12:39:07 PM PDT 24
Peak memory	145292 kb
Host	smart-5eccb237-abe0-41ce-a9bb-90255f30d3c2
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3549184844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3549184844
Directory	/workspace/14.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.775965731
Short name	T31
Test name
Test status
Simulation time	27087937 ps
CPU time	0.41 seconds
Started	May 02 12:38:52 PM PDT 24
Finished	May 02 12:38:55 PM PDT 24
Peak memory	145280 kb
Host	smart-6bc98a5c-fe2b-47a0-a0b3-e7294aa4be80
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=775965731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.775965731
Directory	/workspace/15.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.340030827
Short name	T67
Test name
Test status
Simulation time	26155000 ps
CPU time	0.39 seconds
Started	May 02 12:38:52 PM PDT 24
Finished	May 02 12:38:55 PM PDT 24
Peak memory	145352 kb
Host	smart-28f576db-091c-47f3-a186-62c96651a72b
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=340030827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.340030827
Directory	/workspace/16.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.675049397
Short name	T71
Test name
Test status
Simulation time	26945506 ps
CPU time	0.4 seconds
Started	May 02 12:38:53 PM PDT 24
Finished	May 02 12:38:56 PM PDT 24
Peak memory	145296 kb
Host	smart-3343e24d-1656-4236-aa1f-1e48266ae9c9
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=675049397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.675049397
Directory	/workspace/17.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2911391955
Short name	T9
Test name
Test status
Simulation time	29137577 ps
CPU time	0.43 seconds
Started	May 02 12:38:53 PM PDT 24
Finished	May 02 12:38:56 PM PDT 24
Peak memory	145212 kb
Host	smart-8f92b8c9-2c90-4359-b803-18454b680f06
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2911391955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2911391955
Directory	/workspace/18.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1945212070
Short name	T68
Test name
Test status
Simulation time	28571459 ps
CPU time	0.4 seconds
Started	May 02 12:38:50 PM PDT 24
Finished	May 02 12:38:52 PM PDT 24
Peak memory	145188 kb
Host	smart-dfe3bbab-305f-4c14-bb7d-9e0ba1d1be14
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1945212070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1945212070
Directory	/workspace/19.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2061934976
Short name	T70
Test name
Test status
Simulation time	30399413 ps
CPU time	0.41 seconds
Started	May 02 12:39:00 PM PDT 24
Finished	May 02 12:39:01 PM PDT 24
Peak memory	145248 kb
Host	smart-0c31721a-ca54-4785-b953-ac97c3df27ce
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2061934976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2061934976
Directory	/workspace/2.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3690041997
Short name	T74
Test name
Test status
Simulation time	27186836 ps
CPU time	0.39 seconds
Started	May 02 12:38:54 PM PDT 24
Finished	May 02 12:38:57 PM PDT 24
Peak memory	145256 kb
Host	smart-e0466a01-3dd7-462f-818b-f09e72aabe38
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3690041997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3690041997
Directory	/workspace/3.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3764096709
Short name	T69
Test name
Test status
Simulation time	24998423 ps
CPU time	0.4 seconds
Started	May 02 12:39:00 PM PDT 24
Finished	May 02 12:39:02 PM PDT 24
Peak memory	145496 kb
Host	smart-7d700dde-4626-40e5-bbbc-95ee0291d4ad
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3764096709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3764096709
Directory	/workspace/4.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3029257003
Short name	T79
Test name
Test status
Simulation time	30107075 ps
CPU time	0.4 seconds
Started	May 02 12:38:58 PM PDT 24
Finished	May 02 12:38:59 PM PDT 24
Peak memory	145140 kb
Host	smart-d2e0e772-9c50-4472-a6fd-0aecc235b822
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3029257003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3029257003
Directory	/workspace/5.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4062853783
Short name	T76
Test name
Test status
Simulation time	27601694 ps
CPU time	0.38 seconds
Started	May 02 12:38:44 PM PDT 24
Finished	May 02 12:38:45 PM PDT 24
Peak memory	145188 kb
Host	smart-e7a8db5f-7816-4374-9ae7-e1696a7d9f76
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4062853783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.4062853783
Directory	/workspace/6.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1310856097
Short name	T77
Test name
Test status
Simulation time	26863068 ps
CPU time	0.39 seconds
Started	May 02 12:38:47 PM PDT 24
Finished	May 02 12:38:48 PM PDT 24
Peak memory	145168 kb
Host	smart-82fdf5fa-24ca-42d9-aedd-591dcfd2b9a1
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1310856097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1310856097
Directory	/workspace/7.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1308846517
Short name	T66
Test name
Test status
Simulation time	26109375 ps
CPU time	0.38 seconds
Started	May 02 12:39:05 PM PDT 24
Finished	May 02 12:39:06 PM PDT 24
Peak memory	145392 kb
Host	smart-11f750ab-779a-428b-a717-034f8d92a895
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1308846517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1308846517
Directory	/workspace/8.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2557083129
Short name	T73
Test name
Test status
Simulation time	28412678 ps
CPU time	0.42 seconds
Started	May 02 12:38:53 PM PDT 24
Finished	May 02 12:38:55 PM PDT 24
Peak memory	145312 kb
Host	smart-635cac97-3236-4457-ae01-252f2be23e51
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2557083129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2557083129
Directory	/workspace/9.prim_sync_fatal_alert/latest