Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.85	100.00	97.92	100.00	89.29	95.83	86.05

Total tests in report: 80

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
88.67	88.67	100.00	100.00	93.75	93.75	96.43	96.43	78.57	78.57	95.83	95.83	67.44	67.44	/workspace/coverage/default/19.prim_async_alert.2041574348
91.37	2.70	100.00	0.00	95.83	2.08	100.00	3.57	82.14	3.57	95.83	0.00	74.42	6.98	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2084609582
93.90	2.53	100.00	0.00	95.83	0.00	100.00	0.00	85.71	3.57	95.83	0.00	86.05	11.63	/workspace/coverage/sync_alert/16.prim_sync_alert.18212433
94.50	0.60	100.00	0.00	95.83	0.00	100.00	0.00	89.29	3.57	95.83	0.00	86.05	0.00	/workspace/coverage/default/15.prim_async_alert.3303349843
94.85	0.35	100.00	0.00	97.92	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2668882279

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.4175553190
/workspace/coverage/default/1.prim_async_alert.3382467120
/workspace/coverage/default/10.prim_async_alert.1764081135
/workspace/coverage/default/11.prim_async_alert.4180262536
/workspace/coverage/default/12.prim_async_alert.209178915
/workspace/coverage/default/13.prim_async_alert.2349312685
/workspace/coverage/default/14.prim_async_alert.470956669
/workspace/coverage/default/16.prim_async_alert.2114020911
/workspace/coverage/default/17.prim_async_alert.1624342111
/workspace/coverage/default/18.prim_async_alert.2424701068
/workspace/coverage/default/2.prim_async_alert.3857852943
/workspace/coverage/default/3.prim_async_alert.3000260743
/workspace/coverage/default/4.prim_async_alert.503210616
/workspace/coverage/default/5.prim_async_alert.3771023870
/workspace/coverage/default/6.prim_async_alert.950216054
/workspace/coverage/default/7.prim_async_alert.2491018957
/workspace/coverage/default/8.prim_async_alert.1480628468
/workspace/coverage/default/9.prim_async_alert.1612234233
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.261496863
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2857601623
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.473222076
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1592410203
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2210713717
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1523234830
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2642428930
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.143142164
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1920813289
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1365074152
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1096835455
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4064131535
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3109891349
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1245566415
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1262286258
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.78048052
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2128760316
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.946582865
/workspace/coverage/sync_alert/0.prim_sync_alert.1499248227
/workspace/coverage/sync_alert/1.prim_sync_alert.1647736234
/workspace/coverage/sync_alert/10.prim_sync_alert.2585627400
/workspace/coverage/sync_alert/11.prim_sync_alert.3039965241
/workspace/coverage/sync_alert/12.prim_sync_alert.1437768
/workspace/coverage/sync_alert/13.prim_sync_alert.312259461
/workspace/coverage/sync_alert/14.prim_sync_alert.1807372296
/workspace/coverage/sync_alert/15.prim_sync_alert.614554871
/workspace/coverage/sync_alert/17.prim_sync_alert.4106285802
/workspace/coverage/sync_alert/18.prim_sync_alert.1527635296
/workspace/coverage/sync_alert/19.prim_sync_alert.777658461
/workspace/coverage/sync_alert/2.prim_sync_alert.3518601749
/workspace/coverage/sync_alert/3.prim_sync_alert.1963619892
/workspace/coverage/sync_alert/4.prim_sync_alert.543190276
/workspace/coverage/sync_alert/5.prim_sync_alert.1014292698
/workspace/coverage/sync_alert/6.prim_sync_alert.2509008959
/workspace/coverage/sync_alert/7.prim_sync_alert.3005681318
/workspace/coverage/sync_alert/8.prim_sync_alert.1544825826
/workspace/coverage/sync_alert/9.prim_sync_alert.2282655910
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1484359406
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2064305374
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2277803243
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3722125143
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.652301405
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4053956809
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2561306859
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3803709019
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3124262122
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2471062804
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2729289917
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3836134984
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.821428507
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.527288210
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3940701101
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2138392037
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.445815626
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4116129814
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.329870007
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2484072985

Total test records in report: 80

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.prim_async_alert.3382467120	May 05 12:24:05 PM PDT 24	May 05 12:24:09 PM PDT 24	10707114 ps
T2	/workspace/coverage/default/16.prim_async_alert.2114020911	May 05 12:19:03 PM PDT 24	May 05 12:19:05 PM PDT 24	11018873 ps
T3	/workspace/coverage/default/7.prim_async_alert.2491018957	May 05 12:19:15 PM PDT 24	May 05 12:19:16 PM PDT 24	11116516 ps
T7	/workspace/coverage/default/13.prim_async_alert.2349312685	May 05 12:24:11 PM PDT 24	May 05 12:24:16 PM PDT 24	11546488 ps
T17	/workspace/coverage/default/10.prim_async_alert.1764081135	May 05 12:19:11 PM PDT 24	May 05 12:19:12 PM PDT 24	11426227 ps
T8	/workspace/coverage/default/14.prim_async_alert.470956669	May 05 12:22:30 PM PDT 24	May 05 12:22:31 PM PDT 24	11176896 ps
T10	/workspace/coverage/default/6.prim_async_alert.950216054	May 05 12:19:06 PM PDT 24	May 05 12:19:07 PM PDT 24	11687206 ps
T9	/workspace/coverage/default/19.prim_async_alert.2041574348	May 05 12:24:10 PM PDT 24	May 05 12:24:15 PM PDT 24	10872666 ps
T18	/workspace/coverage/default/17.prim_async_alert.1624342111	May 05 12:19:11 PM PDT 24	May 05 12:19:12 PM PDT 24	11006141 ps
T19	/workspace/coverage/default/9.prim_async_alert.1612234233	May 05 12:22:36 PM PDT 24	May 05 12:22:37 PM PDT 24	11038102 ps
T20	/workspace/coverage/default/8.prim_async_alert.1480628468	May 05 12:19:17 PM PDT 24	May 05 12:19:19 PM PDT 24	11871714 ps
T48	/workspace/coverage/default/2.prim_async_alert.3857852943	May 05 12:20:26 PM PDT 24	May 05 12:20:27 PM PDT 24	12404117 ps
T11	/workspace/coverage/default/15.prim_async_alert.3303349843	May 05 12:21:14 PM PDT 24	May 05 12:21:15 PM PDT 24	12054066 ps
T14	/workspace/coverage/default/12.prim_async_alert.209178915	May 05 12:19:18 PM PDT 24	May 05 12:19:20 PM PDT 24	11398676 ps
T49	/workspace/coverage/default/0.prim_async_alert.4175553190	May 05 12:19:17 PM PDT 24	May 05 12:19:18 PM PDT 24	11444317 ps
T50	/workspace/coverage/default/4.prim_async_alert.503210616	May 05 12:24:36 PM PDT 24	May 05 12:24:39 PM PDT 24	10980520 ps
T21	/workspace/coverage/default/18.prim_async_alert.2424701068	May 05 12:19:17 PM PDT 24	May 05 12:19:19 PM PDT 24	10719099 ps
T22	/workspace/coverage/default/11.prim_async_alert.4180262536	May 05 12:19:13 PM PDT 24	May 05 12:19:14 PM PDT 24	10910615 ps
T51	/workspace/coverage/default/5.prim_async_alert.3771023870	May 05 12:19:17 PM PDT 24	May 05 12:19:19 PM PDT 24	11818249 ps
T12	/workspace/coverage/default/3.prim_async_alert.3000260743	May 05 12:23:48 PM PDT 24	May 05 12:23:50 PM PDT 24	11370623 ps
T4	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2668882279	May 05 12:23:40 PM PDT 24	May 05 12:23:41 PM PDT 24	30462320 ps
T23	/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2128760316	May 05 12:19:17 PM PDT 24	May 05 12:19:19 PM PDT 24	27639885 ps
T42	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1262286258	May 05 12:23:41 PM PDT 24	May 05 12:23:43 PM PDT 24	28844926 ps
T15	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2084609582	May 05 12:19:26 PM PDT 24	May 05 12:19:27 PM PDT 24	29883307 ps
T43	/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2210713717	May 05 12:19:17 PM PDT 24	May 05 12:19:19 PM PDT 24	31441699 ps
T24	/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1523234830	May 05 12:23:40 PM PDT 24	May 05 12:23:42 PM PDT 24	30789169 ps
T44	/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.946582865	May 05 12:20:28 PM PDT 24	May 05 12:20:29 PM PDT 24	31107106 ps
T45	/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1592410203	May 05 12:23:40 PM PDT 24	May 05 12:23:41 PM PDT 24	30898222 ps
T46	/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1096835455	May 05 12:22:18 PM PDT 24	May 05 12:22:19 PM PDT 24	31643012 ps
T47	/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2642428930	May 05 12:19:18 PM PDT 24	May 05 12:19:20 PM PDT 24	29397779 ps
T16	/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1245566415	May 05 12:21:17 PM PDT 24	May 05 12:21:18 PM PDT 24	28484084 ps
T52	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.261496863	May 05 12:19:17 PM PDT 24	May 05 12:19:19 PM PDT 24	27696219 ps
T53	/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.473222076	May 05 12:19:17 PM PDT 24	May 05 12:19:19 PM PDT 24	28840213 ps
T54	/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.143142164	May 05 12:23:40 PM PDT 24	May 05 12:23:41 PM PDT 24	30766143 ps
T55	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2857601623	May 05 12:19:18 PM PDT 24	May 05 12:19:20 PM PDT 24	27290731 ps
T56	/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.78048052	May 05 12:19:17 PM PDT 24	May 05 12:19:18 PM PDT 24	31167204 ps
T57	/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1365074152	May 05 12:23:40 PM PDT 24	May 05 12:23:42 PM PDT 24	31937449 ps
T58	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3109891349	May 05 12:19:11 PM PDT 24	May 05 12:19:12 PM PDT 24	29102525 ps
T59	/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4064131535	May 05 12:19:13 PM PDT 24	May 05 12:19:14 PM PDT 24	29148341 ps
T60	/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1920813289	May 05 12:19:59 PM PDT 24	May 05 12:20:00 PM PDT 24	30738436 ps
T34	/workspace/coverage/sync_alert/7.prim_sync_alert.3005681318	May 05 12:22:17 PM PDT 24	May 05 12:22:18 PM PDT 24	8857056 ps
T25	/workspace/coverage/sync_alert/14.prim_sync_alert.1807372296	May 05 12:23:40 PM PDT 24	May 05 12:23:41 PM PDT 24	9246820 ps
T26	/workspace/coverage/sync_alert/10.prim_sync_alert.2585627400	May 05 12:19:18 PM PDT 24	May 05 12:19:20 PM PDT 24	9592770 ps
T35	/workspace/coverage/sync_alert/17.prim_sync_alert.4106285802	May 05 12:19:19 PM PDT 24	May 05 12:19:21 PM PDT 24	8436195 ps
T36	/workspace/coverage/sync_alert/16.prim_sync_alert.18212433	May 05 12:19:18 PM PDT 24	May 05 12:19:20 PM PDT 24	8264425 ps
T37	/workspace/coverage/sync_alert/6.prim_sync_alert.2509008959	May 05 12:23:40 PM PDT 24	May 05 12:23:41 PM PDT 24	9474075 ps
T27	/workspace/coverage/sync_alert/3.prim_sync_alert.1963619892	May 05 12:19:26 PM PDT 24	May 05 12:19:27 PM PDT 24	9261002 ps
T38	/workspace/coverage/sync_alert/4.prim_sync_alert.543190276	May 05 12:22:09 PM PDT 24	May 05 12:22:10 PM PDT 24	8985106 ps
T28	/workspace/coverage/sync_alert/15.prim_sync_alert.614554871	May 05 12:19:27 PM PDT 24	May 05 12:19:28 PM PDT 24	9570663 ps
T39	/workspace/coverage/sync_alert/12.prim_sync_alert.1437768	May 05 12:19:19 PM PDT 24	May 05 12:19:20 PM PDT 24	9656338 ps
T29	/workspace/coverage/sync_alert/18.prim_sync_alert.1527635296	May 05 12:23:42 PM PDT 24	May 05 12:23:43 PM PDT 24	8983943 ps
T30	/workspace/coverage/sync_alert/1.prim_sync_alert.1647736234	May 05 12:19:44 PM PDT 24	May 05 12:19:45 PM PDT 24	9628838 ps
T31	/workspace/coverage/sync_alert/5.prim_sync_alert.1014292698	May 05 12:19:41 PM PDT 24	May 05 12:19:42 PM PDT 24	9555044 ps
T32	/workspace/coverage/sync_alert/13.prim_sync_alert.312259461	May 05 12:19:26 PM PDT 24	May 05 12:19:28 PM PDT 24	8705977 ps
T40	/workspace/coverage/sync_alert/2.prim_sync_alert.3518601749	May 05 12:22:09 PM PDT 24	May 05 12:22:10 PM PDT 24	9070588 ps
T33	/workspace/coverage/sync_alert/11.prim_sync_alert.3039965241	May 05 12:19:17 PM PDT 24	May 05 12:19:19 PM PDT 24	8718731 ps
T61	/workspace/coverage/sync_alert/8.prim_sync_alert.1544825826	May 05 12:19:17 PM PDT 24	May 05 12:19:18 PM PDT 24	10107057 ps
T41	/workspace/coverage/sync_alert/9.prim_sync_alert.2282655910	May 05 12:19:17 PM PDT 24	May 05 12:19:18 PM PDT 24	9066456 ps
T62	/workspace/coverage/sync_alert/0.prim_sync_alert.1499248227	May 05 12:21:57 PM PDT 24	May 05 12:21:58 PM PDT 24	8718324 ps
T63	/workspace/coverage/sync_alert/19.prim_sync_alert.777658461	May 05 12:22:07 PM PDT 24	May 05 12:22:08 PM PDT 24	9456786 ps
T13	/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3722125143	May 05 12:19:27 PM PDT 24	May 05 12:19:28 PM PDT 24	27458547 ps
T64	/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3836134984	May 05 12:19:26 PM PDT 24	May 05 12:19:27 PM PDT 24	27262689 ps
T65	/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2561306859	May 05 12:19:19 PM PDT 24	May 05 12:19:21 PM PDT 24	27276419 ps
T66	/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3803709019	May 05 12:19:17 PM PDT 24	May 05 12:19:18 PM PDT 24	27983677 ps
T67	/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2064305374	May 05 12:19:17 PM PDT 24	May 05 12:19:19 PM PDT 24	26781455 ps
T68	/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.329870007	May 05 12:19:18 PM PDT 24	May 05 12:19:20 PM PDT 24	28092977 ps
T5	/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.652301405	May 05 12:19:17 PM PDT 24	May 05 12:19:19 PM PDT 24	28556055 ps
T69	/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2138392037	May 05 12:21:15 PM PDT 24	May 05 12:21:16 PM PDT 24	25220884 ps
T70	/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2484072985	May 05 12:19:19 PM PDT 24	May 05 12:19:20 PM PDT 24	26540066 ps
T71	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2277803243	May 05 12:24:01 PM PDT 24	May 05 12:24:03 PM PDT 24	28958789 ps
T72	/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1484359406	May 05 12:19:17 PM PDT 24	May 05 12:19:19 PM PDT 24	27789761 ps
T6	/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4053956809	May 05 12:19:18 PM PDT 24	May 05 12:19:20 PM PDT 24	27133558 ps
T73	/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.821428507	May 05 12:22:06 PM PDT 24	May 05 12:22:07 PM PDT 24	26026024 ps
T74	/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3124262122	May 05 12:23:40 PM PDT 24	May 05 12:23:41 PM PDT 24	28824853 ps
T75	/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3940701101	May 05 12:23:42 PM PDT 24	May 05 12:23:43 PM PDT 24	26346158 ps
T76	/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.527288210	May 05 12:22:07 PM PDT 24	May 05 12:22:09 PM PDT 24	28568698 ps
T77	/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4116129814	May 05 12:22:37 PM PDT 24	May 05 12:22:38 PM PDT 24	26880809 ps
T78	/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.445815626	May 05 12:23:42 PM PDT 24	May 05 12:23:43 PM PDT 24	27961654 ps
T79	/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2471062804	May 05 12:19:18 PM PDT 24	May 05 12:19:20 PM PDT 24	27388925 ps
T80	/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2729289917	May 05 12:20:03 PM PDT 24	May 05 12:20:05 PM PDT 24	26680819 ps

Test location	/workspace/coverage/default/19.prim_async_alert.2041574348
Short name	T9
Test name
Test status
Simulation time	10872666 ps
CPU time	0.38 seconds
Started	May 05 12:24:10 PM PDT 24
Finished	May 05 12:24:15 PM PDT 24
Peak memory	144480 kb
Host	smart-63c1a818-ba17-455b-b728-9d977f31e5a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041574348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2041574348
Directory	/workspace/19.prim_async_alert/latest

Test location	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2084609582
Short name	T15
Test name
Test status
Simulation time	29883307 ps
CPU time	0.39 seconds
Started	May 05 12:19:26 PM PDT 24
Finished	May 05 12:19:27 PM PDT 24
Peak memory	145664 kb
Host	smart-74074d21-c431-4fc4-80b5-b9135397d3cf
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2084609582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2084609582
Directory	/workspace/6.prim_async_fatal_alert/latest

Test location	/workspace/coverage/sync_alert/16.prim_sync_alert.18212433
Short name	T36
Test name
Test status
Simulation time	8264425 ps
CPU time	0.4 seconds
Started	May 05 12:19:18 PM PDT 24
Finished	May 05 12:19:20 PM PDT 24
Peak memory	144980 kb
Host	smart-5455ed03-8244-427c-9df7-3b412b32d3ad
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=18212433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.18212433
Directory	/workspace/16.prim_sync_alert/latest

Test location	/workspace/coverage/default/15.prim_async_alert.3303349843
Short name	T11
Test name
Test status
Simulation time	12054066 ps
CPU time	0.39 seconds
Started	May 05 12:21:14 PM PDT 24
Finished	May 05 12:21:15 PM PDT 24
Peak memory	145672 kb
Host	smart-571edc6d-9019-40d4-9318-e2dbfd6ebc24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3303349843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3303349843
Directory	/workspace/15.prim_async_alert/latest

Test location	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2668882279
Short name	T4
Test name
Test status
Simulation time	30462320 ps
CPU time	0.45 seconds
Started	May 05 12:23:40 PM PDT 24
Finished	May 05 12:23:41 PM PDT 24
Peak memory	142736 kb
Host	smart-9343f709-a959-4a7b-b589-534f580d7f95
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2668882279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2668882279
Directory	/workspace/19.prim_async_fatal_alert/latest

Test location	/workspace/coverage/default/0.prim_async_alert.4175553190
Short name	T49
Test name
Test status
Simulation time	11444317 ps
CPU time	0.42 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:18 PM PDT 24
Peak memory	143468 kb
Host	smart-d1954cf5-4f89-4d67-b1ff-2167d91f169b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175553190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.4175553190
Directory	/workspace/0.prim_async_alert/latest

Test location	/workspace/coverage/default/1.prim_async_alert.3382467120
Short name	T1
Test name
Test status
Simulation time	10707114 ps
CPU time	0.43 seconds
Started	May 05 12:24:05 PM PDT 24
Finished	May 05 12:24:09 PM PDT 24
Peak memory	144988 kb
Host	smart-2c903043-6150-4b0f-90e3-052ac13e5d45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3382467120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3382467120
Directory	/workspace/1.prim_async_alert/latest

Test location	/workspace/coverage/default/10.prim_async_alert.1764081135
Short name	T17
Test name
Test status
Simulation time	11426227 ps
CPU time	0.38 seconds
Started	May 05 12:19:11 PM PDT 24
Finished	May 05 12:19:12 PM PDT 24
Peak memory	145856 kb
Host	smart-3a667c57-9893-4d5f-ba39-b3201f35e2f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764081135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1764081135
Directory	/workspace/10.prim_async_alert/latest

Test location	/workspace/coverage/default/11.prim_async_alert.4180262536
Short name	T22
Test name
Test status
Simulation time	10910615 ps
CPU time	0.4 seconds
Started	May 05 12:19:13 PM PDT 24
Finished	May 05 12:19:14 PM PDT 24
Peak memory	145360 kb
Host	smart-d624eabd-4d68-4adc-a776-a0f043ca89db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180262536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4180262536
Directory	/workspace/11.prim_async_alert/latest

Test location	/workspace/coverage/default/12.prim_async_alert.209178915
Short name	T14
Test name
Test status
Simulation time	11398676 ps
CPU time	0.37 seconds
Started	May 05 12:19:18 PM PDT 24
Finished	May 05 12:19:20 PM PDT 24
Peak memory	145396 kb
Host	smart-d0128291-78c6-40ce-90f9-3933220bb739
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=209178915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.209178915
Directory	/workspace/12.prim_async_alert/latest

Test location	/workspace/coverage/default/13.prim_async_alert.2349312685
Short name	T7
Test name
Test status
Simulation time	11546488 ps
CPU time	0.37 seconds
Started	May 05 12:24:11 PM PDT 24
Finished	May 05 12:24:16 PM PDT 24
Peak memory	145296 kb
Host	smart-1de4d16f-e980-412d-a0b4-0e4672a9cc4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349312685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2349312685
Directory	/workspace/13.prim_async_alert/latest

Test location	/workspace/coverage/default/14.prim_async_alert.470956669
Short name	T8
Test name
Test status
Simulation time	11176896 ps
CPU time	0.42 seconds
Started	May 05 12:22:30 PM PDT 24
Finished	May 05 12:22:31 PM PDT 24
Peak memory	145652 kb
Host	smart-ebd376f1-46a7-439f-bcd4-0377b79d57f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470956669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.470956669
Directory	/workspace/14.prim_async_alert/latest

Test location	/workspace/coverage/default/16.prim_async_alert.2114020911
Short name	T2
Test name
Test status
Simulation time	11018873 ps
CPU time	0.45 seconds
Started	May 05 12:19:03 PM PDT 24
Finished	May 05 12:19:05 PM PDT 24
Peak memory	144000 kb
Host	smart-9f33fe96-e6c7-4488-b436-a078f8b8dbe1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114020911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2114020911
Directory	/workspace/16.prim_async_alert/latest

Test location	/workspace/coverage/default/17.prim_async_alert.1624342111
Short name	T18
Test name
Test status
Simulation time	11006141 ps
CPU time	0.39 seconds
Started	May 05 12:19:11 PM PDT 24
Finished	May 05 12:19:12 PM PDT 24
Peak memory	145560 kb
Host	smart-cc7bcb44-9fdb-4d08-bcd3-31897eb59ff5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1624342111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1624342111
Directory	/workspace/17.prim_async_alert/latest

Test location	/workspace/coverage/default/18.prim_async_alert.2424701068
Short name	T21
Test name
Test status
Simulation time	10719099 ps
CPU time	0.38 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:19 PM PDT 24
Peak memory	145624 kb
Host	smart-68a3dc7d-4757-4b8a-9148-4e5f792f828e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424701068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2424701068
Directory	/workspace/18.prim_async_alert/latest

Test location	/workspace/coverage/default/2.prim_async_alert.3857852943
Short name	T48
Test name
Test status
Simulation time	12404117 ps
CPU time	0.41 seconds
Started	May 05 12:20:26 PM PDT 24
Finished	May 05 12:20:27 PM PDT 24
Peak memory	145648 kb
Host	smart-605615e7-32e9-46b5-9038-844623a438ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857852943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3857852943
Directory	/workspace/2.prim_async_alert/latest

Test location	/workspace/coverage/default/3.prim_async_alert.3000260743
Short name	T12
Test name
Test status
Simulation time	11370623 ps
CPU time	0.41 seconds
Started	May 05 12:23:48 PM PDT 24
Finished	May 05 12:23:50 PM PDT 24
Peak memory	143876 kb
Host	smart-053aa240-c7c1-48fa-9e44-eab7d1b3b2b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3000260743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3000260743
Directory	/workspace/3.prim_async_alert/latest

Test location	/workspace/coverage/default/4.prim_async_alert.503210616
Short name	T50
Test name
Test status
Simulation time	10980520 ps
CPU time	0.4 seconds
Started	May 05 12:24:36 PM PDT 24
Finished	May 05 12:24:39 PM PDT 24
Peak memory	144096 kb
Host	smart-1def7a7e-26d3-413e-9fa4-2c250e72dc0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=503210616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.503210616
Directory	/workspace/4.prim_async_alert/latest

Test location	/workspace/coverage/default/5.prim_async_alert.3771023870
Short name	T51
Test name
Test status
Simulation time	11818249 ps
CPU time	0.38 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:19 PM PDT 24
Peak memory	145852 kb
Host	smart-6f92c147-66b3-46a0-be29-d1c6ec3a9ede
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771023870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3771023870
Directory	/workspace/5.prim_async_alert/latest

Test location	/workspace/coverage/default/6.prim_async_alert.950216054
Short name	T10
Test name
Test status
Simulation time	11687206 ps
CPU time	0.41 seconds
Started	May 05 12:19:06 PM PDT 24
Finished	May 05 12:19:07 PM PDT 24
Peak memory	145624 kb
Host	smart-672e0f25-c801-4089-8b72-c7e629ac22b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950216054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.950216054
Directory	/workspace/6.prim_async_alert/latest

Test location	/workspace/coverage/default/7.prim_async_alert.2491018957
Short name	T3
Test name
Test status
Simulation time	11116516 ps
CPU time	0.4 seconds
Started	May 05 12:19:15 PM PDT 24
Finished	May 05 12:19:16 PM PDT 24
Peak memory	145624 kb
Host	smart-666d3718-866c-4541-956c-4f165c0a6de4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491018957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2491018957
Directory	/workspace/7.prim_async_alert/latest

Test location	/workspace/coverage/default/8.prim_async_alert.1480628468
Short name	T20
Test name
Test status
Simulation time	11871714 ps
CPU time	0.37 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:19 PM PDT 24
Peak memory	145396 kb
Host	smart-4da04fce-cbc5-427b-9f00-aac4fdde2cb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1480628468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1480628468
Directory	/workspace/8.prim_async_alert/latest

Test location	/workspace/coverage/default/9.prim_async_alert.1612234233
Short name	T19
Test name
Test status
Simulation time	11038102 ps
CPU time	0.4 seconds
Started	May 05 12:22:36 PM PDT 24
Finished	May 05 12:22:37 PM PDT 24
Peak memory	145664 kb
Host	smart-223c7f02-9db0-4a6e-ba9a-0a6e2bba2bc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612234233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1612234233
Directory	/workspace/9.prim_async_alert/latest

Test location	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.261496863
Short name	T52
Test name
Test status
Simulation time	27696219 ps
CPU time	0.42 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:19 PM PDT 24
Peak memory	144664 kb
Host	smart-dc5708a9-65af-4623-8346-676dc58d6c91
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=261496863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.261496863
Directory	/workspace/0.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2857601623
Short name	T55
Test name
Test status
Simulation time	27290731 ps
CPU time	0.39 seconds
Started	May 05 12:19:18 PM PDT 24
Finished	May 05 12:19:20 PM PDT 24
Peak memory	145392 kb
Host	smart-8c1db1f1-88d0-45c5-95d8-c911748f1951
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2857601623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2857601623
Directory	/workspace/1.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.473222076
Short name	T53
Test name
Test status
Simulation time	28840213 ps
CPU time	0.4 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:19 PM PDT 24
Peak memory	145384 kb
Host	smart-78a6fa11-594f-4d41-b82a-91cdb0ec4bfa
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=473222076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.473222076
Directory	/workspace/10.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1592410203
Short name	T45
Test name
Test status
Simulation time	30898222 ps
CPU time	0.44 seconds
Started	May 05 12:23:40 PM PDT 24
Finished	May 05 12:23:41 PM PDT 24
Peak memory	142864 kb
Host	smart-91b5bd72-65b7-4b6b-acb2-39201994112c
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1592410203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1592410203
Directory	/workspace/11.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2210713717
Short name	T43
Test name
Test status
Simulation time	31441699 ps
CPU time	0.4 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:19 PM PDT 24
Peak memory	145376 kb
Host	smart-474b1d67-187c-4ee9-b30a-e1a57a87d6e3
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2210713717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2210713717
Directory	/workspace/12.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1523234830
Short name	T24
Test name
Test status
Simulation time	30789169 ps
CPU time	0.4 seconds
Started	May 05 12:23:40 PM PDT 24
Finished	May 05 12:23:42 PM PDT 24
Peak memory	145252 kb
Host	smart-976dc946-df04-49fa-95a0-83efd60e5944
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1523234830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1523234830
Directory	/workspace/13.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2642428930
Short name	T47
Test name
Test status
Simulation time	29397779 ps
CPU time	0.4 seconds
Started	May 05 12:19:18 PM PDT 24
Finished	May 05 12:19:20 PM PDT 24
Peak memory	145412 kb
Host	smart-0eb465e1-a084-45bf-b31c-e4c24dd3c6e4
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2642428930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2642428930
Directory	/workspace/14.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.143142164
Short name	T54
Test name
Test status
Simulation time	30766143 ps
CPU time	0.39 seconds
Started	May 05 12:23:40 PM PDT 24
Finished	May 05 12:23:41 PM PDT 24
Peak memory	145104 kb
Host	smart-6839cbd0-b711-47e9-95f0-19defbb3c235
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=143142164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.143142164
Directory	/workspace/15.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1920813289
Short name	T60
Test name
Test status
Simulation time	30738436 ps
CPU time	0.4 seconds
Started	May 05 12:19:59 PM PDT 24
Finished	May 05 12:20:00 PM PDT 24
Peak memory	145664 kb
Host	smart-222b4087-b3ed-46c0-ad6a-d505093cf5b9
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1920813289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1920813289
Directory	/workspace/16.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1365074152
Short name	T57
Test name
Test status
Simulation time	31937449 ps
CPU time	0.4 seconds
Started	May 05 12:23:40 PM PDT 24
Finished	May 05 12:23:42 PM PDT 24
Peak memory	145252 kb
Host	smart-c6f7c87a-3777-4786-8b74-7cd8819d56da
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1365074152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1365074152
Directory	/workspace/17.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1096835455
Short name	T46
Test name
Test status
Simulation time	31643012 ps
CPU time	0.41 seconds
Started	May 05 12:22:18 PM PDT 24
Finished	May 05 12:22:19 PM PDT 24
Peak memory	145668 kb
Host	smart-340edd46-6488-4612-8d37-ea63e540d16f
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1096835455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1096835455
Directory	/workspace/18.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4064131535
Short name	T59
Test name
Test status
Simulation time	29148341 ps
CPU time	0.44 seconds
Started	May 05 12:19:13 PM PDT 24
Finished	May 05 12:19:14 PM PDT 24
Peak memory	145360 kb
Host	smart-e51ea1b5-9d10-4892-a692-41838a7d7b7c
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4064131535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4064131535
Directory	/workspace/2.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3109891349
Short name	T58
Test name
Test status
Simulation time	29102525 ps
CPU time	0.4 seconds
Started	May 05 12:19:11 PM PDT 24
Finished	May 05 12:19:12 PM PDT 24
Peak memory	145576 kb
Host	smart-0c404a2a-5f6c-4746-83f7-c4489797782d
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3109891349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3109891349
Directory	/workspace/3.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1245566415
Short name	T16
Test name
Test status
Simulation time	28484084 ps
CPU time	0.4 seconds
Started	May 05 12:21:17 PM PDT 24
Finished	May 05 12:21:18 PM PDT 24
Peak memory	145668 kb
Host	smart-633d53bf-393b-47eb-9de2-f5bbbb9f0a22
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1245566415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1245566415
Directory	/workspace/4.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1262286258
Short name	T42
Test name
Test status
Simulation time	28844926 ps
CPU time	0.4 seconds
Started	May 05 12:23:41 PM PDT 24
Finished	May 05 12:23:43 PM PDT 24
Peak memory	145372 kb
Host	smart-2cd91241-5635-4b27-92f2-4fec110494d6
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1262286258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1262286258
Directory	/workspace/5.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.78048052
Short name	T56
Test name
Test status
Simulation time	31167204 ps
CPU time	0.45 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:18 PM PDT 24
Peak memory	143352 kb
Host	smart-45b59274-e2c7-4c6e-af0c-ef42f56ac218
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=78048052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.78048052
Directory	/workspace/7.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2128760316
Short name	T23
Test name
Test status
Simulation time	27639885 ps
CPU time	0.4 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:19 PM PDT 24
Peak memory	145212 kb
Host	smart-ef8a0689-137a-4921-982a-8042fceea8d5
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2128760316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2128760316
Directory	/workspace/8.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.946582865
Short name	T44
Test name
Test status
Simulation time	31107106 ps
CPU time	0.45 seconds
Started	May 05 12:20:28 PM PDT 24
Finished	May 05 12:20:29 PM PDT 24
Peak memory	145736 kb
Host	smart-c8f5fd01-83f0-485a-b2b1-81f72eb4bb37
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=946582865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.946582865
Directory	/workspace/9.prim_async_fatal_alert/latest

Test location	/workspace/coverage/sync_alert/0.prim_sync_alert.1499248227
Short name	T62
Test name
Test status
Simulation time	8718324 ps
CPU time	0.39 seconds
Started	May 05 12:21:57 PM PDT 24
Finished	May 05 12:21:58 PM PDT 24
Peak memory	145448 kb
Host	smart-d1e531da-a3e5-4530-a7aa-d15b473c7182
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1499248227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1499248227
Directory	/workspace/0.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/1.prim_sync_alert.1647736234
Short name	T30
Test name
Test status
Simulation time	9628838 ps
CPU time	0.38 seconds
Started	May 05 12:19:44 PM PDT 24
Finished	May 05 12:19:45 PM PDT 24
Peak memory	145456 kb
Host	smart-a096d2a8-c632-4806-b80f-8fba70b3b29d
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1647736234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1647736234
Directory	/workspace/1.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/10.prim_sync_alert.2585627400
Short name	T26
Test name
Test status
Simulation time	9592770 ps
CPU time	0.37 seconds
Started	May 05 12:19:18 PM PDT 24
Finished	May 05 12:19:20 PM PDT 24
Peak memory	145008 kb
Host	smart-a4db5285-048b-4113-8e6e-39bb7eac5565
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2585627400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2585627400
Directory	/workspace/10.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/11.prim_sync_alert.3039965241
Short name	T33
Test name
Test status
Simulation time	8718731 ps
CPU time	0.37 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:19 PM PDT 24
Peak memory	145004 kb
Host	smart-ea66e9a5-384b-4e8f-94b0-a27b68ffdb94
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3039965241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3039965241
Directory	/workspace/11.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/12.prim_sync_alert.1437768
Short name	T39
Test name
Test status
Simulation time	9656338 ps
CPU time	0.38 seconds
Started	May 05 12:19:19 PM PDT 24
Finished	May 05 12:19:20 PM PDT 24
Peak memory	144988 kb
Host	smart-6f631bb3-307f-4de3-8471-30c7f1d11607
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1437768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1437768
Directory	/workspace/12.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/13.prim_sync_alert.312259461
Short name	T32
Test name
Test status
Simulation time	8705977 ps
CPU time	0.38 seconds
Started	May 05 12:19:26 PM PDT 24
Finished	May 05 12:19:28 PM PDT 24
Peak memory	145200 kb
Host	smart-be11029a-410e-4530-abdf-552e4dd618c8
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=312259461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.312259461
Directory	/workspace/13.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/14.prim_sync_alert.1807372296
Short name	T25
Test name
Test status
Simulation time	9246820 ps
CPU time	0.4 seconds
Started	May 05 12:23:40 PM PDT 24
Finished	May 05 12:23:41 PM PDT 24
Peak memory	142528 kb
Host	smart-b84801ad-e918-4bd6-bdaf-8051db222718
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1807372296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1807372296
Directory	/workspace/14.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/15.prim_sync_alert.614554871
Short name	T28
Test name
Test status
Simulation time	9570663 ps
CPU time	0.41 seconds
Started	May 05 12:19:27 PM PDT 24
Finished	May 05 12:19:28 PM PDT 24
Peak memory	145200 kb
Host	smart-9b83826a-3dd8-4a28-aacf-1c3a9a3f72e8
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=614554871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.614554871
Directory	/workspace/15.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/17.prim_sync_alert.4106285802
Short name	T35
Test name
Test status
Simulation time	8436195 ps
CPU time	0.37 seconds
Started	May 05 12:19:19 PM PDT 24
Finished	May 05 12:19:21 PM PDT 24
Peak memory	144988 kb
Host	smart-d6f45984-0503-42d3-b80e-fc7b89617d75
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4106285802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.4106285802
Directory	/workspace/17.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/18.prim_sync_alert.1527635296
Short name	T29
Test name
Test status
Simulation time	8983943 ps
CPU time	0.36 seconds
Started	May 05 12:23:42 PM PDT 24
Finished	May 05 12:23:43 PM PDT 24
Peak memory	145140 kb
Host	smart-ea67d18a-38c7-48bd-a4b9-763b0328bcff
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1527635296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1527635296
Directory	/workspace/18.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/19.prim_sync_alert.777658461
Short name	T63
Test name
Test status
Simulation time	9456786 ps
CPU time	0.4 seconds
Started	May 05 12:22:07 PM PDT 24
Finished	May 05 12:22:08 PM PDT 24
Peak memory	145672 kb
Host	smart-7e56fd01-089a-45a0-84e9-fafdbccd4381
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=777658461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.777658461
Directory	/workspace/19.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/2.prim_sync_alert.3518601749
Short name	T40
Test name
Test status
Simulation time	9070588 ps
CPU time	0.4 seconds
Started	May 05 12:22:09 PM PDT 24
Finished	May 05 12:22:10 PM PDT 24
Peak memory	145448 kb
Host	smart-b88d30cd-b29d-47d9-bbd8-bf12a65c83f9
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3518601749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3518601749
Directory	/workspace/2.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/3.prim_sync_alert.1963619892
Short name	T27
Test name
Test status
Simulation time	9261002 ps
CPU time	0.36 seconds
Started	May 05 12:19:26 PM PDT 24
Finished	May 05 12:19:27 PM PDT 24
Peak memory	145204 kb
Host	smart-b2b6186f-c97e-4a80-80d7-e76db2d660d7
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1963619892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1963619892
Directory	/workspace/3.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/4.prim_sync_alert.543190276
Short name	T38
Test name
Test status
Simulation time	8985106 ps
CPU time	0.39 seconds
Started	May 05 12:22:09 PM PDT 24
Finished	May 05 12:22:10 PM PDT 24
Peak memory	145440 kb
Host	smart-669f7213-c7e5-4bc5-8fb5-28e20795be1e
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=543190276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.543190276
Directory	/workspace/4.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/5.prim_sync_alert.1014292698
Short name	T31
Test name
Test status
Simulation time	9555044 ps
CPU time	0.41 seconds
Started	May 05 12:19:41 PM PDT 24
Finished	May 05 12:19:42 PM PDT 24
Peak memory	145432 kb
Host	smart-7abde614-a69a-430e-981a-87033d01cae5
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1014292698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1014292698
Directory	/workspace/5.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/6.prim_sync_alert.2509008959
Short name	T37
Test name
Test status
Simulation time	9474075 ps
CPU time	0.4 seconds
Started	May 05 12:23:40 PM PDT 24
Finished	May 05 12:23:41 PM PDT 24
Peak memory	143588 kb
Host	smart-cdfc826b-cdce-4b90-bb32-2371fc63f04e
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2509008959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2509008959
Directory	/workspace/6.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/7.prim_sync_alert.3005681318
Short name	T34
Test name
Test status
Simulation time	8857056 ps
CPU time	0.37 seconds
Started	May 05 12:22:17 PM PDT 24
Finished	May 05 12:22:18 PM PDT 24
Peak memory	145460 kb
Host	smart-a1753ddc-f32a-4139-a560-7642d7a136b1
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3005681318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3005681318
Directory	/workspace/7.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/8.prim_sync_alert.1544825826
Short name	T61
Test name
Test status
Simulation time	10107057 ps
CPU time	0.37 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:18 PM PDT 24
Peak memory	145012 kb
Host	smart-e94ef15b-47f8-4d59-aafc-1b1b84299207
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1544825826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1544825826
Directory	/workspace/8.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/9.prim_sync_alert.2282655910
Short name	T41
Test name
Test status
Simulation time	9066456 ps
CPU time	0.38 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:18 PM PDT 24
Peak memory	145012 kb
Host	smart-08ea6907-dad7-40c8-bf22-f103f3bc6e9e
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2282655910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2282655910
Directory	/workspace/9.prim_sync_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1484359406
Short name	T72
Test name
Test status
Simulation time	27789761 ps
CPU time	0.39 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:19 PM PDT 24
Peak memory	145540 kb
Host	smart-096f026d-1b95-42c5-b541-c8ec965cbcc0
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1484359406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1484359406
Directory	/workspace/0.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2064305374
Short name	T67
Test name
Test status
Simulation time	26781455 ps
CPU time	0.38 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:19 PM PDT 24
Peak memory	144956 kb
Host	smart-267b45be-0faa-4648-80dd-924aa948d044
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2064305374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2064305374
Directory	/workspace/1.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2277803243
Short name	T71
Test name
Test status
Simulation time	28958789 ps
CPU time	0.44 seconds
Started	May 05 12:24:01 PM PDT 24
Finished	May 05 12:24:03 PM PDT 24
Peak memory	144360 kb
Host	smart-d61a5e23-1513-4311-affd-3e9a182b4fc2
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2277803243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2277803243
Directory	/workspace/10.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3722125143
Short name	T13
Test name
Test status
Simulation time	27458547 ps
CPU time	0.38 seconds
Started	May 05 12:19:27 PM PDT 24
Finished	May 05 12:19:28 PM PDT 24
Peak memory	145188 kb
Host	smart-24147648-dd1b-45e4-ba5b-25dfc3a27af2
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3722125143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3722125143
Directory	/workspace/11.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.652301405
Short name	T5
Test name
Test status
Simulation time	28556055 ps
CPU time	0.43 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:19 PM PDT 24
Peak memory	145332 kb
Host	smart-f95b6b95-e990-4ff0-9c5f-583979da02bb
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=652301405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.652301405
Directory	/workspace/12.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4053956809
Short name	T6
Test name
Test status
Simulation time	27133558 ps
CPU time	0.39 seconds
Started	May 05 12:19:18 PM PDT 24
Finished	May 05 12:19:20 PM PDT 24
Peak memory	144996 kb
Host	smart-f2bd7a5a-3d40-466a-b9ed-229753155b00
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4053956809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.4053956809
Directory	/workspace/13.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2561306859
Short name	T65
Test name
Test status
Simulation time	27276419 ps
CPU time	0.4 seconds
Started	May 05 12:19:19 PM PDT 24
Finished	May 05 12:19:21 PM PDT 24
Peak memory	145012 kb
Host	smart-7e20f394-0dfa-4115-8757-fb07958d8032
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2561306859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2561306859
Directory	/workspace/14.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3803709019
Short name	T66
Test name
Test status
Simulation time	27983677 ps
CPU time	0.43 seconds
Started	May 05 12:19:17 PM PDT 24
Finished	May 05 12:19:18 PM PDT 24
Peak memory	145884 kb
Host	smart-acf4d156-7448-4b4e-be25-4d7dc3733cf7
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3803709019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3803709019
Directory	/workspace/15.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3124262122
Short name	T74
Test name
Test status
Simulation time	28824853 ps
CPU time	0.45 seconds
Started	May 05 12:23:40 PM PDT 24
Finished	May 05 12:23:41 PM PDT 24
Peak memory	142312 kb
Host	smart-1f8f1a00-ae2b-4012-a4fb-5a8fcf05af05
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3124262122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3124262122
Directory	/workspace/16.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2471062804
Short name	T79
Test name
Test status
Simulation time	27388925 ps
CPU time	0.39 seconds
Started	May 05 12:19:18 PM PDT 24
Finished	May 05 12:19:20 PM PDT 24
Peak memory	145020 kb
Host	smart-479f8d36-879d-4204-a62c-6bd159345a86
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2471062804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2471062804
Directory	/workspace/17.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2729289917
Short name	T80
Test name
Test status
Simulation time	26680819 ps
CPU time	0.4 seconds
Started	May 05 12:20:03 PM PDT 24
Finished	May 05 12:20:05 PM PDT 24
Peak memory	145676 kb
Host	smart-4c4d58fa-e499-440b-b4b2-3c3161e4d742
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2729289917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2729289917
Directory	/workspace/18.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3836134984
Short name	T64
Test name
Test status
Simulation time	27262689 ps
CPU time	0.39 seconds
Started	May 05 12:19:26 PM PDT 24
Finished	May 05 12:19:27 PM PDT 24
Peak memory	145212 kb
Host	smart-cd7f44d3-9e6f-403e-b0d6-bdd5d082370b
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3836134984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3836134984
Directory	/workspace/19.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.821428507
Short name	T73
Test name
Test status
Simulation time	26026024 ps
CPU time	0.44 seconds
Started	May 05 12:22:06 PM PDT 24
Finished	May 05 12:22:07 PM PDT 24
Peak memory	145668 kb
Host	smart-d62b1d0a-32b6-4be1-bbea-e79fd02b849c
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=821428507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.821428507
Directory	/workspace/2.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.527288210
Short name	T76
Test name
Test status
Simulation time	28568698 ps
CPU time	0.42 seconds
Started	May 05 12:22:07 PM PDT 24
Finished	May 05 12:22:09 PM PDT 24
Peak memory	145448 kb
Host	smart-bc3b303c-d20d-40a0-8092-a5878ca9f0fa
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=527288210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.527288210
Directory	/workspace/3.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3940701101
Short name	T75
Test name
Test status
Simulation time	26346158 ps
CPU time	0.47 seconds
Started	May 05 12:23:42 PM PDT 24
Finished	May 05 12:23:43 PM PDT 24
Peak memory	143288 kb
Host	smart-1faf2448-8823-4239-a297-12e9728183f6
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3940701101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3940701101
Directory	/workspace/4.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2138392037
Short name	T69
Test name
Test status
Simulation time	25220884 ps
CPU time	0.42 seconds
Started	May 05 12:21:15 PM PDT 24
Finished	May 05 12:21:16 PM PDT 24
Peak memory	145452 kb
Host	smart-21d15af8-177b-42b4-b1d6-e775e3de20c8
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2138392037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2138392037
Directory	/workspace/5.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.445815626
Short name	T78
Test name
Test status
Simulation time	27961654 ps
CPU time	0.46 seconds
Started	May 05 12:23:42 PM PDT 24
Finished	May 05 12:23:43 PM PDT 24
Peak memory	143316 kb
Host	smart-bf5da73b-f06c-4b48-93e0-d4bbcf049733
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=445815626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.445815626
Directory	/workspace/6.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4116129814
Short name	T77
Test name
Test status
Simulation time	26880809 ps
CPU time	0.41 seconds
Started	May 05 12:22:37 PM PDT 24
Finished	May 05 12:22:38 PM PDT 24
Peak memory	145520 kb
Host	smart-9d42ac46-eacb-4930-a3d9-07d943311d4e
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4116129814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.4116129814
Directory	/workspace/7.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.329870007
Short name	T68
Test name
Test status
Simulation time	28092977 ps
CPU time	0.42 seconds
Started	May 05 12:19:18 PM PDT 24
Finished	May 05 12:19:20 PM PDT 24
Peak memory	144984 kb
Host	smart-cd09aae2-25de-46c9-b05c-cae304f76985
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=329870007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.329870007
Directory	/workspace/8.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2484072985
Short name	T70
Test name
Test status
Simulation time	26540066 ps
CPU time	0.39 seconds
Started	May 05 12:19:19 PM PDT 24
Finished	May 05 12:19:20 PM PDT 24
Peak memory	144976 kb
Host	smart-853640fd-f0ce-4864-b980-229c68c2c819
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2484072985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2484072985
Directory	/workspace/9.prim_sync_fatal_alert/latest