| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 89.27 | 89.27 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/17.prim_async_alert.464592246 |
| 92.39 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/3.prim_sync_alert.1773930640 |
| 94.15 | 1.76 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2887596865 |
| 94.50 | 0.35 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/15.prim_async_alert.323281384 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.405861223 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.2772292505 |
| /workspace/coverage/default/1.prim_async_alert.1660773029 |
| /workspace/coverage/default/10.prim_async_alert.1945574007 |
| /workspace/coverage/default/11.prim_async_alert.2999009354 |
| /workspace/coverage/default/12.prim_async_alert.2865670690 |
| /workspace/coverage/default/13.prim_async_alert.3253347356 |
| /workspace/coverage/default/14.prim_async_alert.661650678 |
| /workspace/coverage/default/16.prim_async_alert.2065548557 |
| /workspace/coverage/default/18.prim_async_alert.653161743 |
| /workspace/coverage/default/19.prim_async_alert.497084832 |
| /workspace/coverage/default/2.prim_async_alert.384094386 |
| /workspace/coverage/default/4.prim_async_alert.79347938 |
| /workspace/coverage/default/5.prim_async_alert.3933499810 |
| /workspace/coverage/default/7.prim_async_alert.286106585 |
| /workspace/coverage/default/8.prim_async_alert.1249649321 |
| /workspace/coverage/default/9.prim_async_alert.2734799302 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1243655280 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3506324301 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.518224901 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.682452050 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.318552004 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.879425261 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2292439859 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2076629744 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3256694321 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.267319293 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3725273889 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3755302861 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4014222491 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2610609571 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3768485173 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1996212224 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2191957999 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3243369888 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.4139255166 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.1706511984 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.1594821021 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1922388153 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3726963334 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.895121228 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.692440920 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.2292740417 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.1792910020 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.1442070252 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.1849122953 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.2414412669 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2176681283 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.224490224 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.151836047 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.2278606249 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.990268954 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.169478335 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.3099387154 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4226197196 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2429835119 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1120835212 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4172741025 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3388596150 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3052259406 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1085982640 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2030551728 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2513010212 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3977460736 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3340142716 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1354706364 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3509951153 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.66204629 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.729291504 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2599862359 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4097506588 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2292131980 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3080055326 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/17.prim_async_alert.464592246 | May 07 12:25:47 PM PDT 24 | May 07 12:25:48 PM PDT 24 | 12538474 ps | ||
| T2 | /workspace/coverage/default/7.prim_async_alert.286106585 | May 07 12:25:42 PM PDT 24 | May 07 12:25:44 PM PDT 24 | 10882552 ps | ||
| T3 | /workspace/coverage/default/18.prim_async_alert.653161743 | May 07 12:25:53 PM PDT 24 | May 07 12:25:54 PM PDT 24 | 11554847 ps | ||
| T18 | /workspace/coverage/default/0.prim_async_alert.2772292505 | May 07 12:25:45 PM PDT 24 | May 07 12:25:47 PM PDT 24 | 10481718 ps | ||
| T10 | /workspace/coverage/default/19.prim_async_alert.497084832 | May 07 12:25:47 PM PDT 24 | May 07 12:25:48 PM PDT 24 | 11518075 ps | ||
| T6 | /workspace/coverage/default/15.prim_async_alert.323281384 | May 07 12:25:54 PM PDT 24 | May 07 12:25:55 PM PDT 24 | 11029085 ps | ||
| T8 | /workspace/coverage/default/9.prim_async_alert.2734799302 | May 07 12:25:38 PM PDT 24 | May 07 12:25:39 PM PDT 24 | 11796675 ps | ||
| T19 | /workspace/coverage/default/14.prim_async_alert.661650678 | May 07 12:25:48 PM PDT 24 | May 07 12:25:50 PM PDT 24 | 11063203 ps | ||
| T15 | /workspace/coverage/default/5.prim_async_alert.3933499810 | May 07 12:25:47 PM PDT 24 | May 07 12:25:49 PM PDT 24 | 11413992 ps | ||
| T9 | /workspace/coverage/default/13.prim_async_alert.3253347356 | May 07 12:25:45 PM PDT 24 | May 07 12:25:47 PM PDT 24 | 12445458 ps | ||
| T20 | /workspace/coverage/default/1.prim_async_alert.1660773029 | May 07 12:25:56 PM PDT 24 | May 07 12:25:57 PM PDT 24 | 11104059 ps | ||
| T11 | /workspace/coverage/default/2.prim_async_alert.384094386 | May 07 12:25:57 PM PDT 24 | May 07 12:25:58 PM PDT 24 | 12262068 ps | ||
| T12 | /workspace/coverage/default/4.prim_async_alert.79347938 | May 07 12:25:45 PM PDT 24 | May 07 12:25:47 PM PDT 24 | 11561250 ps | ||
| T43 | /workspace/coverage/default/12.prim_async_alert.2865670690 | May 07 12:25:58 PM PDT 24 | May 07 12:25:59 PM PDT 24 | 11106314 ps | ||
| T21 | /workspace/coverage/default/11.prim_async_alert.2999009354 | May 07 12:25:38 PM PDT 24 | May 07 12:25:39 PM PDT 24 | 12140993 ps | ||
| T22 | /workspace/coverage/default/10.prim_async_alert.1945574007 | May 07 12:25:42 PM PDT 24 | May 07 12:25:43 PM PDT 24 | 10674337 ps | ||
| T7 | /workspace/coverage/default/8.prim_async_alert.1249649321 | May 07 12:25:56 PM PDT 24 | May 07 12:25:57 PM PDT 24 | 11689409 ps | ||
| T44 | /workspace/coverage/default/16.prim_async_alert.2065548557 | May 07 12:25:53 PM PDT 24 | May 07 12:25:54 PM PDT 24 | 10607723 ps | ||
| T13 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3755302861 | May 07 12:26:01 PM PDT 24 | May 07 12:26:02 PM PDT 24 | 28280489 ps | ||
| T36 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1996212224 | May 07 12:25:51 PM PDT 24 | May 07 12:25:52 PM PDT 24 | 30373454 ps | ||
| T16 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2887596865 | May 07 12:26:04 PM PDT 24 | May 07 12:26:06 PM PDT 24 | 31684493 ps | ||
| T37 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.318552004 | May 07 12:25:50 PM PDT 24 | May 07 12:25:51 PM PDT 24 | 30913338 ps | ||
| T38 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2076629744 | May 07 12:25:58 PM PDT 24 | May 07 12:25:59 PM PDT 24 | 32345784 ps | ||
| T39 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1243655280 | May 07 12:25:53 PM PDT 24 | May 07 12:25:54 PM PDT 24 | 29627295 ps | ||
| T40 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.879425261 | May 07 12:25:47 PM PDT 24 | May 07 12:25:48 PM PDT 24 | 31416775 ps | ||
| T41 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4014222491 | May 07 12:25:54 PM PDT 24 | May 07 12:25:55 PM PDT 24 | 29482641 ps | ||
| T42 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2610609571 | May 07 12:25:56 PM PDT 24 | May 07 12:25:57 PM PDT 24 | 29260148 ps | ||
| T14 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3768485173 | May 07 12:25:55 PM PDT 24 | May 07 12:25:56 PM PDT 24 | 29391358 ps | ||
| T45 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3506324301 | May 07 12:25:49 PM PDT 24 | May 07 12:25:50 PM PDT 24 | 27560597 ps | ||
| T46 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.518224901 | May 07 12:26:08 PM PDT 24 | May 07 12:26:09 PM PDT 24 | 28077363 ps | ||
| T47 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2191957999 | May 07 12:25:55 PM PDT 24 | May 07 12:25:56 PM PDT 24 | 31345712 ps | ||
| T48 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.682452050 | May 07 12:26:08 PM PDT 24 | May 07 12:26:09 PM PDT 24 | 30459533 ps | ||
| T49 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3243369888 | May 07 12:25:51 PM PDT 24 | May 07 12:25:52 PM PDT 24 | 29574926 ps | ||
| T50 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.267319293 | May 07 12:25:59 PM PDT 24 | May 07 12:26:01 PM PDT 24 | 28534059 ps | ||
| T51 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2292439859 | May 07 12:25:56 PM PDT 24 | May 07 12:25:57 PM PDT 24 | 29969652 ps | ||
| T52 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3725273889 | May 07 12:26:01 PM PDT 24 | May 07 12:26:02 PM PDT 24 | 29382197 ps | ||
| T53 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3256694321 | May 07 12:25:49 PM PDT 24 | May 07 12:25:50 PM PDT 24 | 30613393 ps | ||
| T23 | /workspace/coverage/sync_alert/3.prim_sync_alert.1773930640 | May 07 02:28:32 PM PDT 24 | May 07 02:28:33 PM PDT 24 | 9307916 ps | ||
| T17 | /workspace/coverage/sync_alert/6.prim_sync_alert.2278606249 | May 07 02:28:39 PM PDT 24 | May 07 02:28:40 PM PDT 24 | 9337992 ps | ||
| T33 | /workspace/coverage/sync_alert/12.prim_sync_alert.3726963334 | May 07 02:28:37 PM PDT 24 | May 07 02:28:38 PM PDT 24 | 9462555 ps | ||
| T34 | /workspace/coverage/sync_alert/11.prim_sync_alert.1922388153 | May 07 02:28:40 PM PDT 24 | May 07 02:28:41 PM PDT 24 | 10093821 ps | ||
| T24 | /workspace/coverage/sync_alert/19.prim_sync_alert.2414412669 | May 07 02:28:39 PM PDT 24 | May 07 02:28:40 PM PDT 24 | 7774089 ps | ||
| T25 | /workspace/coverage/sync_alert/14.prim_sync_alert.692440920 | May 07 02:28:39 PM PDT 24 | May 07 02:28:40 PM PDT 24 | 8969096 ps | ||
| T26 | /workspace/coverage/sync_alert/4.prim_sync_alert.224490224 | May 07 02:28:33 PM PDT 24 | May 07 02:28:34 PM PDT 24 | 9331469 ps | ||
| T27 | /workspace/coverage/sync_alert/1.prim_sync_alert.1706511984 | May 07 02:28:34 PM PDT 24 | May 07 02:28:35 PM PDT 24 | 8649084 ps | ||
| T28 | /workspace/coverage/sync_alert/7.prim_sync_alert.990268954 | May 07 02:28:37 PM PDT 24 | May 07 02:28:38 PM PDT 24 | 8696359 ps | ||
| T35 | /workspace/coverage/sync_alert/16.prim_sync_alert.1792910020 | May 07 02:28:36 PM PDT 24 | May 07 02:28:37 PM PDT 24 | 8178392 ps | ||
| T29 | /workspace/coverage/sync_alert/8.prim_sync_alert.169478335 | May 07 02:28:38 PM PDT 24 | May 07 02:28:39 PM PDT 24 | 8910515 ps | ||
| T30 | /workspace/coverage/sync_alert/10.prim_sync_alert.1594821021 | May 07 02:28:39 PM PDT 24 | May 07 02:28:40 PM PDT 24 | 8548630 ps | ||
| T54 | /workspace/coverage/sync_alert/15.prim_sync_alert.2292740417 | May 07 02:28:39 PM PDT 24 | May 07 02:28:40 PM PDT 24 | 9481737 ps | ||
| T55 | /workspace/coverage/sync_alert/5.prim_sync_alert.151836047 | May 07 02:28:32 PM PDT 24 | May 07 02:28:33 PM PDT 24 | 10766997 ps | ||
| T56 | /workspace/coverage/sync_alert/0.prim_sync_alert.4139255166 | May 07 02:28:33 PM PDT 24 | May 07 02:28:34 PM PDT 24 | 8637852 ps | ||
| T31 | /workspace/coverage/sync_alert/9.prim_sync_alert.3099387154 | May 07 02:28:37 PM PDT 24 | May 07 02:28:38 PM PDT 24 | 9784391 ps | ||
| T57 | /workspace/coverage/sync_alert/18.prim_sync_alert.1849122953 | May 07 02:28:38 PM PDT 24 | May 07 02:28:39 PM PDT 24 | 9139951 ps | ||
| T32 | /workspace/coverage/sync_alert/13.prim_sync_alert.895121228 | May 07 02:28:38 PM PDT 24 | May 07 02:28:39 PM PDT 24 | 9836539 ps | ||
| T58 | /workspace/coverage/sync_alert/17.prim_sync_alert.1442070252 | May 07 02:28:39 PM PDT 24 | May 07 02:28:40 PM PDT 24 | 10166168 ps | ||
| T59 | /workspace/coverage/sync_alert/2.prim_sync_alert.2176681283 | May 07 02:28:31 PM PDT 24 | May 07 02:28:31 PM PDT 24 | 9231316 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3052259406 | May 07 02:16:36 PM PDT 24 | May 07 02:16:37 PM PDT 24 | 27842187 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2599862359 | May 07 02:16:30 PM PDT 24 | May 07 02:16:31 PM PDT 24 | 29873793 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1120835212 | May 07 02:16:35 PM PDT 24 | May 07 02:16:36 PM PDT 24 | 26338862 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4226197196 | May 07 02:16:33 PM PDT 24 | May 07 02:16:34 PM PDT 24 | 29974000 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2429835119 | May 07 02:16:33 PM PDT 24 | May 07 02:16:33 PM PDT 24 | 27573864 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2292131980 | May 07 02:16:37 PM PDT 24 | May 07 02:16:38 PM PDT 24 | 28249678 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4172741025 | May 07 02:16:35 PM PDT 24 | May 07 02:16:36 PM PDT 24 | 26345921 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2030551728 | May 07 02:16:39 PM PDT 24 | May 07 02:16:40 PM PDT 24 | 29404097 ps | ||
| T4 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.405861223 | May 07 02:16:35 PM PDT 24 | May 07 02:16:36 PM PDT 24 | 27436870 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3977460736 | May 07 02:16:40 PM PDT 24 | May 07 02:16:41 PM PDT 24 | 27117582 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3509951153 | May 07 02:16:31 PM PDT 24 | May 07 02:16:32 PM PDT 24 | 28006541 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.66204629 | May 07 02:16:34 PM PDT 24 | May 07 02:16:35 PM PDT 24 | 27028902 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.729291504 | May 07 02:16:33 PM PDT 24 | May 07 02:16:34 PM PDT 24 | 26261153 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4097506588 | May 07 02:16:33 PM PDT 24 | May 07 02:16:34 PM PDT 24 | 26758496 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3340142716 | May 07 02:16:41 PM PDT 24 | May 07 02:16:42 PM PDT 24 | 26312014 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2513010212 | May 07 02:16:39 PM PDT 24 | May 07 02:16:40 PM PDT 24 | 27413733 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1085982640 | May 07 02:16:35 PM PDT 24 | May 07 02:16:36 PM PDT 24 | 26808983 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3080055326 | May 07 02:16:40 PM PDT 24 | May 07 02:16:41 PM PDT 24 | 28494141 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3388596150 | May 07 02:16:37 PM PDT 24 | May 07 02:16:38 PM PDT 24 | 26241664 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1354706364 | May 07 02:16:35 PM PDT 24 | May 07 02:16:36 PM PDT 24 | 27929461 ps |
| Test location | /workspace/coverage/default/17.prim_async_alert.464592246 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12538474 ps |
| CPU time | 0.38 seconds |
| Started | May 07 12:25:47 PM PDT 24 |
| Finished | May 07 12:25:48 PM PDT 24 |
| Peak memory | 145500 kb |
| Host | smart-da149fed-2d1a-4626-8eee-74d8905d1e31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=464592246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.464592246 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.1773930640 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9307916 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:28:32 PM PDT 24 |
| Finished | May 07 02:28:33 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-70a73e9f-7447-467a-894d-ee0cfcc281ca |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1773930640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1773930640 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2887596865 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 31684493 ps |
| CPU time | 0.43 seconds |
| Started | May 07 12:26:04 PM PDT 24 |
| Finished | May 07 12:26:06 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-088edbbb-8865-4ba9-92bc-b6946c42c210 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2887596865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2887596865 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.323281384 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11029085 ps |
| CPU time | 0.39 seconds |
| Started | May 07 12:25:54 PM PDT 24 |
| Finished | May 07 12:25:55 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-61c3e183-2443-4d69-96cd-0fef9ed769b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323281384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.323281384 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.405861223 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 27436870 ps |
| CPU time | 0.4 seconds |
| Started | May 07 02:16:35 PM PDT 24 |
| Finished | May 07 02:16:36 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-576bed55-56a4-4ead-b836-86df2d58f3d5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=405861223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.405861223 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.2772292505 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10481718 ps |
| CPU time | 0.43 seconds |
| Started | May 07 12:25:45 PM PDT 24 |
| Finished | May 07 12:25:47 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-465daf8e-2048-406f-96a7-72912ca2d768 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772292505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2772292505 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1660773029 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11104059 ps |
| CPU time | 0.39 seconds |
| Started | May 07 12:25:56 PM PDT 24 |
| Finished | May 07 12:25:57 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-0522aab5-5ef4-48e9-9680-103009788467 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660773029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1660773029 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.1945574007 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10674337 ps |
| CPU time | 0.38 seconds |
| Started | May 07 12:25:42 PM PDT 24 |
| Finished | May 07 12:25:43 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-8aafb3de-c9a6-4826-b4d0-b079a83e6c8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945574007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1945574007 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.2999009354 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12140993 ps |
| CPU time | 0.38 seconds |
| Started | May 07 12:25:38 PM PDT 24 |
| Finished | May 07 12:25:39 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-324a5b3f-d074-48b7-bbd6-6c4ad929ff41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2999009354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2999009354 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.2865670690 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11106314 ps |
| CPU time | 0.39 seconds |
| Started | May 07 12:25:58 PM PDT 24 |
| Finished | May 07 12:25:59 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-56b83334-3464-419a-b496-3b09f1d4eae0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865670690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2865670690 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3253347356 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12445458 ps |
| CPU time | 0.39 seconds |
| Started | May 07 12:25:45 PM PDT 24 |
| Finished | May 07 12:25:47 PM PDT 24 |
| Peak memory | 145504 kb |
| Host | smart-f2924015-9c74-4a81-861a-1d0f79076335 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253347356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3253347356 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.661650678 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11063203 ps |
| CPU time | 0.45 seconds |
| Started | May 07 12:25:48 PM PDT 24 |
| Finished | May 07 12:25:50 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-b764164e-830a-4ab7-8f63-56c72700a2be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=661650678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.661650678 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.2065548557 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10607723 ps |
| CPU time | 0.38 seconds |
| Started | May 07 12:25:53 PM PDT 24 |
| Finished | May 07 12:25:54 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-291d7a6f-ef77-4f09-a7ad-8eb107933e4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2065548557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2065548557 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.653161743 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11554847 ps |
| CPU time | 0.4 seconds |
| Started | May 07 12:25:53 PM PDT 24 |
| Finished | May 07 12:25:54 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-07349329-697e-4ea1-8335-9867931476e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=653161743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.653161743 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.497084832 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11518075 ps |
| CPU time | 0.41 seconds |
| Started | May 07 12:25:47 PM PDT 24 |
| Finished | May 07 12:25:48 PM PDT 24 |
| Peak memory | 145752 kb |
| Host | smart-b9e528db-bddd-4034-9668-5155992b0fce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497084832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.497084832 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.384094386 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12262068 ps |
| CPU time | 0.4 seconds |
| Started | May 07 12:25:57 PM PDT 24 |
| Finished | May 07 12:25:58 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-9d5726df-2907-413c-994a-df857c052323 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384094386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.384094386 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.79347938 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11561250 ps |
| CPU time | 0.4 seconds |
| Started | May 07 12:25:45 PM PDT 24 |
| Finished | May 07 12:25:47 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-4faad574-08c2-42ce-bd5b-f2530c1c5146 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79347938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.79347938 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3933499810 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11413992 ps |
| CPU time | 0.38 seconds |
| Started | May 07 12:25:47 PM PDT 24 |
| Finished | May 07 12:25:49 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-65e73cf0-294e-42e5-a9ae-5f07120a81fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3933499810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3933499810 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.286106585 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10882552 ps |
| CPU time | 0.38 seconds |
| Started | May 07 12:25:42 PM PDT 24 |
| Finished | May 07 12:25:44 PM PDT 24 |
| Peak memory | 145524 kb |
| Host | smart-989e572f-86ae-4af2-b3df-21e6f263053b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286106585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.286106585 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.1249649321 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11689409 ps |
| CPU time | 0.39 seconds |
| Started | May 07 12:25:56 PM PDT 24 |
| Finished | May 07 12:25:57 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-d142fcc2-05c0-4400-8403-cef8356487a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249649321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1249649321 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.2734799302 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11796675 ps |
| CPU time | 0.42 seconds |
| Started | May 07 12:25:38 PM PDT 24 |
| Finished | May 07 12:25:39 PM PDT 24 |
| Peak memory | 145504 kb |
| Host | smart-33b64e10-03e2-484d-96b0-a1ffb270d7ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734799302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2734799302 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1243655280 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 29627295 ps |
| CPU time | 0.4 seconds |
| Started | May 07 12:25:53 PM PDT 24 |
| Finished | May 07 12:25:54 PM PDT 24 |
| Peak memory | 145376 kb |
| Host | smart-efaa2eaa-2eb6-4685-adba-1e2c4bb5a0e2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1243655280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1243655280 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3506324301 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 27560597 ps |
| CPU time | 0.45 seconds |
| Started | May 07 12:25:49 PM PDT 24 |
| Finished | May 07 12:25:50 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-2bfb9a7f-5789-4641-a2e5-ad8e179bb28b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3506324301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3506324301 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.518224901 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 28077363 ps |
| CPU time | 0.41 seconds |
| Started | May 07 12:26:08 PM PDT 24 |
| Finished | May 07 12:26:09 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-c2b98175-c274-4f2b-a2ea-fddf424632da |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=518224901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.518224901 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.682452050 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30459533 ps |
| CPU time | 0.4 seconds |
| Started | May 07 12:26:08 PM PDT 24 |
| Finished | May 07 12:26:09 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-d55ac7e2-a68d-44f8-a45d-ab79e8d9acc5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=682452050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.682452050 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.318552004 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 30913338 ps |
| CPU time | 0.41 seconds |
| Started | May 07 12:25:50 PM PDT 24 |
| Finished | May 07 12:25:51 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-4a25197b-6c90-44a5-981f-3e776e95bcea |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=318552004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.318552004 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.879425261 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 31416775 ps |
| CPU time | 0.41 seconds |
| Started | May 07 12:25:47 PM PDT 24 |
| Finished | May 07 12:25:48 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-fd43f5d6-f19d-4afb-bbf3-99e0025223ce |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=879425261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.879425261 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2292439859 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29969652 ps |
| CPU time | 0.39 seconds |
| Started | May 07 12:25:56 PM PDT 24 |
| Finished | May 07 12:25:57 PM PDT 24 |
| Peak memory | 145480 kb |
| Host | smart-9305ac6a-c52e-4086-bb67-3f18ab857565 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2292439859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2292439859 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2076629744 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 32345784 ps |
| CPU time | 0.4 seconds |
| Started | May 07 12:25:58 PM PDT 24 |
| Finished | May 07 12:25:59 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-b36dfc68-1577-49e8-aa7b-075ced5251e7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2076629744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2076629744 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3256694321 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30613393 ps |
| CPU time | 0.44 seconds |
| Started | May 07 12:25:49 PM PDT 24 |
| Finished | May 07 12:25:50 PM PDT 24 |
| Peak memory | 145524 kb |
| Host | smart-b7e87d16-d38e-4ead-801c-775ee71dc07d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3256694321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3256694321 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.267319293 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 28534059 ps |
| CPU time | 0.41 seconds |
| Started | May 07 12:25:59 PM PDT 24 |
| Finished | May 07 12:26:01 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-b19c4e8c-243e-4ca9-982d-032eb3deca9f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=267319293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.267319293 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3725273889 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 29382197 ps |
| CPU time | 0.4 seconds |
| Started | May 07 12:26:01 PM PDT 24 |
| Finished | May 07 12:26:02 PM PDT 24 |
| Peak memory | 145508 kb |
| Host | smart-fd027581-ec7c-4786-a143-4dea6bb129c8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3725273889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3725273889 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3755302861 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 28280489 ps |
| CPU time | 0.39 seconds |
| Started | May 07 12:26:01 PM PDT 24 |
| Finished | May 07 12:26:02 PM PDT 24 |
| Peak memory | 145504 kb |
| Host | smart-9c6ba507-ee51-4e14-b2b8-34f8875c02b9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3755302861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3755302861 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4014222491 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29482641 ps |
| CPU time | 0.41 seconds |
| Started | May 07 12:25:54 PM PDT 24 |
| Finished | May 07 12:25:55 PM PDT 24 |
| Peak memory | 145508 kb |
| Host | smart-0ba4a62b-208f-42f9-b72e-3a5e35f57af2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4014222491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.4014222491 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2610609571 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29260148 ps |
| CPU time | 0.41 seconds |
| Started | May 07 12:25:56 PM PDT 24 |
| Finished | May 07 12:25:57 PM PDT 24 |
| Peak memory | 145536 kb |
| Host | smart-6cd6d943-200d-4ac6-a848-5c5d70fe06c5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2610609571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2610609571 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3768485173 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 29391358 ps |
| CPU time | 0.41 seconds |
| Started | May 07 12:25:55 PM PDT 24 |
| Finished | May 07 12:25:56 PM PDT 24 |
| Peak memory | 145888 kb |
| Host | smart-73855989-a1f9-4330-868b-a1a9c74e5f52 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3768485173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3768485173 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1996212224 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 30373454 ps |
| CPU time | 0.41 seconds |
| Started | May 07 12:25:51 PM PDT 24 |
| Finished | May 07 12:25:52 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-ef0b90cd-f665-47f0-9beb-8030291d6886 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1996212224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1996212224 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2191957999 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 31345712 ps |
| CPU time | 0.41 seconds |
| Started | May 07 12:25:55 PM PDT 24 |
| Finished | May 07 12:25:56 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-5b7e5901-72dc-46f5-b66f-d5e2be9e7bf0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2191957999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2191957999 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3243369888 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29574926 ps |
| CPU time | 0.4 seconds |
| Started | May 07 12:25:51 PM PDT 24 |
| Finished | May 07 12:25:52 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-82008704-5d64-46a5-a99b-8b20148ce988 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3243369888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3243369888 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.4139255166 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8637852 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:28:33 PM PDT 24 |
| Finished | May 07 02:28:34 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-0b9d8fd8-cf37-4aca-85ee-9d3bb8eabd93 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4139255166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4139255166 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.1706511984 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8649084 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:28:34 PM PDT 24 |
| Finished | May 07 02:28:35 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-c565f5d0-8565-40b1-a0b2-9f9b3db9ac4a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1706511984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1706511984 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.1594821021 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8548630 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:28:39 PM PDT 24 |
| Finished | May 07 02:28:40 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-f0044cfa-b046-416c-bf53-c4f3ba2f8a6d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1594821021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1594821021 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1922388153 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10093821 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:28:40 PM PDT 24 |
| Finished | May 07 02:28:41 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-fabf9324-b294-4062-bfa8-845ac0a84927 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1922388153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1922388153 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3726963334 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9462555 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:28:37 PM PDT 24 |
| Finished | May 07 02:28:38 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-1614fd0c-aac3-4d4b-8f0b-c84bfaae29e9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3726963334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3726963334 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.895121228 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9836539 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:28:38 PM PDT 24 |
| Finished | May 07 02:28:39 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-64cba3d4-b610-4c76-92f9-929ad13caa4f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=895121228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.895121228 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.692440920 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8969096 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:28:39 PM PDT 24 |
| Finished | May 07 02:28:40 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-e6e1c5bb-9c47-490c-981f-a38e9a01adfc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=692440920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.692440920 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.2292740417 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 9481737 ps |
| CPU time | 0.36 seconds |
| Started | May 07 02:28:39 PM PDT 24 |
| Finished | May 07 02:28:40 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-960e6347-3ab3-4341-b110-690b8fe8360b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2292740417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2292740417 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.1792910020 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8178392 ps |
| CPU time | 0.36 seconds |
| Started | May 07 02:28:36 PM PDT 24 |
| Finished | May 07 02:28:37 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-e30b505c-cbd2-43e2-b176-204e44f913bd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1792910020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1792910020 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.1442070252 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 10166168 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:28:39 PM PDT 24 |
| Finished | May 07 02:28:40 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-3173ce56-564f-4c66-a0fd-2f906948f365 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1442070252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1442070252 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.1849122953 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9139951 ps |
| CPU time | 0.4 seconds |
| Started | May 07 02:28:38 PM PDT 24 |
| Finished | May 07 02:28:39 PM PDT 24 |
| Peak memory | 145328 kb |
| Host | smart-9e04448c-2147-4ebb-9788-dc0b148d7480 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1849122953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1849122953 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.2414412669 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7774089 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:28:39 PM PDT 24 |
| Finished | May 07 02:28:40 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-204bde2f-9fd8-4161-a3d4-91e279b97cf3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2414412669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2414412669 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2176681283 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9231316 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:28:31 PM PDT 24 |
| Finished | May 07 02:28:31 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-8b2d7c1d-a79e-4fba-8544-dc2516c27117 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2176681283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2176681283 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.224490224 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9331469 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:28:33 PM PDT 24 |
| Finished | May 07 02:28:34 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-53c3fa12-be35-4804-9d90-e42714012a97 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=224490224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.224490224 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.151836047 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 10766997 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:28:32 PM PDT 24 |
| Finished | May 07 02:28:33 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-8c79f264-2754-45da-9a28-e222a298035f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=151836047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.151836047 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.2278606249 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9337992 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:28:39 PM PDT 24 |
| Finished | May 07 02:28:40 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-0520d3a2-8267-4885-8f53-4528bc1cbc7d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2278606249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2278606249 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.990268954 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8696359 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:28:37 PM PDT 24 |
| Finished | May 07 02:28:38 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-13e27a4f-29a1-43d7-8c75-110601e50163 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=990268954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.990268954 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.169478335 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8910515 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:28:38 PM PDT 24 |
| Finished | May 07 02:28:39 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-40549ed6-4c2d-40b3-ae78-d4451e9b669f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=169478335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.169478335 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.3099387154 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9784391 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:28:37 PM PDT 24 |
| Finished | May 07 02:28:38 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-572d8e23-18a7-4fea-8257-9b8b3c83d6df |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3099387154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3099387154 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4226197196 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 29974000 ps |
| CPU time | 0.42 seconds |
| Started | May 07 02:16:33 PM PDT 24 |
| Finished | May 07 02:16:34 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-c1eebf06-4357-42be-8223-0dba1442e10e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4226197196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4226197196 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2429835119 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27573864 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:16:33 PM PDT 24 |
| Finished | May 07 02:16:33 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-f5711300-2ae5-47b2-a19b-3d2d759cbe75 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2429835119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2429835119 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1120835212 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 26338862 ps |
| CPU time | 0.4 seconds |
| Started | May 07 02:16:35 PM PDT 24 |
| Finished | May 07 02:16:36 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-229de737-88c7-4b68-a04a-26f273e9923f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1120835212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1120835212 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4172741025 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26345921 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:16:35 PM PDT 24 |
| Finished | May 07 02:16:36 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-432a0f55-89f1-4e02-97be-5679e7555885 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4172741025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4172741025 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3388596150 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 26241664 ps |
| CPU time | 0.4 seconds |
| Started | May 07 02:16:37 PM PDT 24 |
| Finished | May 07 02:16:38 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-c7f3bbde-0169-4cbc-8918-632c0372f332 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3388596150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3388596150 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3052259406 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 27842187 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:16:36 PM PDT 24 |
| Finished | May 07 02:16:37 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-2c5c08db-e7bb-4ef8-997d-494f2c5a1813 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3052259406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3052259406 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1085982640 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26808983 ps |
| CPU time | 0.37 seconds |
| Started | May 07 02:16:35 PM PDT 24 |
| Finished | May 07 02:16:36 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-a3816bd7-7042-400c-ab2f-8ee1907b2e1d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1085982640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1085982640 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2030551728 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 29404097 ps |
| CPU time | 0.4 seconds |
| Started | May 07 02:16:39 PM PDT 24 |
| Finished | May 07 02:16:40 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-2e90da81-bc8a-404e-b428-fa25d9e17af9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2030551728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2030551728 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2513010212 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27413733 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:16:39 PM PDT 24 |
| Finished | May 07 02:16:40 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-ff7c1d9e-5797-4f98-bbf4-cae3ed731b3f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2513010212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2513010212 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3977460736 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27117582 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:16:40 PM PDT 24 |
| Finished | May 07 02:16:41 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-369561b7-5dbf-4882-b723-8ae64c8f7601 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3977460736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3977460736 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3340142716 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26312014 ps |
| CPU time | 0.43 seconds |
| Started | May 07 02:16:41 PM PDT 24 |
| Finished | May 07 02:16:42 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-a34be588-347b-4f7a-bdfd-c45f6e7d895e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3340142716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3340142716 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1354706364 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27929461 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:16:35 PM PDT 24 |
| Finished | May 07 02:16:36 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-ad99454d-fe3c-4202-b065-25afe73a1ac7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1354706364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1354706364 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3509951153 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28006541 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:16:31 PM PDT 24 |
| Finished | May 07 02:16:32 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-e634ee77-1982-42c8-9105-e080a814518c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3509951153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3509951153 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.66204629 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27028902 ps |
| CPU time | 0.4 seconds |
| Started | May 07 02:16:34 PM PDT 24 |
| Finished | May 07 02:16:35 PM PDT 24 |
| Peak memory | 145516 kb |
| Host | smart-3e65f418-bcaf-4111-b1a2-94beb0a6dfa9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=66204629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.66204629 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.729291504 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26261153 ps |
| CPU time | 0.38 seconds |
| Started | May 07 02:16:33 PM PDT 24 |
| Finished | May 07 02:16:34 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-e23b5089-35e5-4b00-a98c-3dd3aad9ff83 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=729291504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.729291504 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2599862359 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 29873793 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:16:30 PM PDT 24 |
| Finished | May 07 02:16:31 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-aacdc951-a34b-4d50-a06c-20f8f2e1c966 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2599862359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2599862359 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4097506588 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26758496 ps |
| CPU time | 0.41 seconds |
| Started | May 07 02:16:33 PM PDT 24 |
| Finished | May 07 02:16:34 PM PDT 24 |
| Peak memory | 145520 kb |
| Host | smart-56f5fb26-3c42-40f5-9c63-af1dac8fd6bc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4097506588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.4097506588 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2292131980 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28249678 ps |
| CPU time | 0.4 seconds |
| Started | May 07 02:16:37 PM PDT 24 |
| Finished | May 07 02:16:38 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-2fd11e50-ef96-487f-9383-87f99ac8c82c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2292131980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2292131980 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3080055326 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 28494141 ps |
| CPU time | 0.39 seconds |
| Started | May 07 02:16:40 PM PDT 24 |
| Finished | May 07 02:16:41 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-44ce200a-b062-423e-b525-764b776e3322 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3080055326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3080055326 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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