| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.88 | 88.88 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/18.prim_async_alert.2058943987 |
| 92.60 | 3.72 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 89.29 | 10.71 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/7.prim_sync_alert.2223479637 |
| 94.15 | 1.55 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 9.30 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.383233292 |
| 94.50 | 0.35 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/0.prim_async_alert.1823360100 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1638175569 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4203127314 |
| Name |
|---|
| /workspace/coverage/default/1.prim_async_alert.1736673160 |
| /workspace/coverage/default/10.prim_async_alert.361804818 |
| /workspace/coverage/default/11.prim_async_alert.1072806230 |
| /workspace/coverage/default/12.prim_async_alert.3596513426 |
| /workspace/coverage/default/13.prim_async_alert.3025612179 |
| /workspace/coverage/default/14.prim_async_alert.642645142 |
| /workspace/coverage/default/15.prim_async_alert.3025831005 |
| /workspace/coverage/default/16.prim_async_alert.4219106227 |
| /workspace/coverage/default/17.prim_async_alert.1856965341 |
| /workspace/coverage/default/19.prim_async_alert.3967708779 |
| /workspace/coverage/default/2.prim_async_alert.1711820276 |
| /workspace/coverage/default/3.prim_async_alert.3398146209 |
| /workspace/coverage/default/4.prim_async_alert.4200820888 |
| /workspace/coverage/default/5.prim_async_alert.1709820828 |
| /workspace/coverage/default/6.prim_async_alert.2090922477 |
| /workspace/coverage/default/7.prim_async_alert.1005607020 |
| /workspace/coverage/default/8.prim_async_alert.2889721609 |
| /workspace/coverage/default/9.prim_async_alert.1724785768 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1924993006 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1122956325 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2326330306 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.751135446 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.793228837 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2397288774 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.177463353 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1984708646 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.648461815 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2541206639 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4104898025 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2056436392 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1400051154 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2737783066 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3704703957 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1700017880 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.985970288 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4001163153 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.637573892 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.2671276470 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3857305706 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1058590345 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3884825316 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1620858517 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.2762211621 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.3224168945 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.2335391035 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.680217652 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.462842817 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.2191118260 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.1523695657 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3176510334 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.960289924 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.476450739 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1162307321 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.2737543291 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.981530741 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2424947540 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3026120359 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1379159735 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2223846159 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1490745264 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3235387900 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3291374282 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1983490062 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3708342192 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.258767062 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2351969550 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2605146844 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3098761827 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3956295116 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1656598624 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2939837718 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2257610700 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1102715008 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4060880230 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_async_alert.1724785768 | May 09 01:43:56 PM PDT 24 | May 09 01:43:58 PM PDT 24 | 11461741 ps | ||
| T2 | /workspace/coverage/default/18.prim_async_alert.2058943987 | May 09 01:43:58 PM PDT 24 | May 09 01:44:01 PM PDT 24 | 11526521 ps | ||
| T3 | /workspace/coverage/default/8.prim_async_alert.2889721609 | May 09 01:44:19 PM PDT 24 | May 09 01:44:21 PM PDT 24 | 10800057 ps | ||
| T7 | /workspace/coverage/default/3.prim_async_alert.3398146209 | May 09 01:43:58 PM PDT 24 | May 09 01:44:01 PM PDT 24 | 11146693 ps | ||
| T19 | /workspace/coverage/default/14.prim_async_alert.642645142 | May 09 01:43:57 PM PDT 24 | May 09 01:44:00 PM PDT 24 | 10828507 ps | ||
| T20 | /workspace/coverage/default/2.prim_async_alert.1711820276 | May 09 01:44:07 PM PDT 24 | May 09 01:44:10 PM PDT 24 | 11228195 ps | ||
| T8 | /workspace/coverage/default/19.prim_async_alert.3967708779 | May 09 01:44:05 PM PDT 24 | May 09 01:44:08 PM PDT 24 | 10033129 ps | ||
| T9 | /workspace/coverage/default/12.prim_async_alert.3596513426 | May 09 01:44:04 PM PDT 24 | May 09 01:44:06 PM PDT 24 | 11200465 ps | ||
| T12 | /workspace/coverage/default/0.prim_async_alert.1823360100 | May 09 01:44:02 PM PDT 24 | May 09 01:44:04 PM PDT 24 | 12103030 ps | ||
| T21 | /workspace/coverage/default/17.prim_async_alert.1856965341 | May 09 01:44:06 PM PDT 24 | May 09 01:44:09 PM PDT 24 | 10812348 ps | ||
| T16 | /workspace/coverage/default/7.prim_async_alert.1005607020 | May 09 01:44:06 PM PDT 24 | May 09 01:44:09 PM PDT 24 | 10655623 ps | ||
| T13 | /workspace/coverage/default/4.prim_async_alert.4200820888 | May 09 01:43:56 PM PDT 24 | May 09 01:43:58 PM PDT 24 | 11605711 ps | ||
| T14 | /workspace/coverage/default/13.prim_async_alert.3025612179 | May 09 01:44:05 PM PDT 24 | May 09 01:44:08 PM PDT 24 | 12100942 ps | ||
| T10 | /workspace/coverage/default/11.prim_async_alert.1072806230 | May 09 01:43:57 PM PDT 24 | May 09 01:44:00 PM PDT 24 | 10634698 ps | ||
| T22 | /workspace/coverage/default/6.prim_async_alert.2090922477 | May 09 01:44:01 PM PDT 24 | May 09 01:44:03 PM PDT 24 | 11482164 ps | ||
| T17 | /workspace/coverage/default/10.prim_async_alert.361804818 | May 09 01:44:07 PM PDT 24 | May 09 01:44:10 PM PDT 24 | 11745117 ps | ||
| T23 | /workspace/coverage/default/16.prim_async_alert.4219106227 | May 09 01:43:55 PM PDT 24 | May 09 01:43:57 PM PDT 24 | 10792978 ps | ||
| T24 | /workspace/coverage/default/1.prim_async_alert.1736673160 | May 09 01:44:05 PM PDT 24 | May 09 01:44:07 PM PDT 24 | 10636147 ps | ||
| T18 | /workspace/coverage/default/15.prim_async_alert.3025831005 | May 09 01:44:02 PM PDT 24 | May 09 01:44:03 PM PDT 24 | 11826821 ps | ||
| T51 | /workspace/coverage/default/5.prim_async_alert.1709820828 | May 09 01:43:55 PM PDT 24 | May 09 01:43:56 PM PDT 24 | 10659548 ps | ||
| T43 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2397288774 | May 09 12:22:10 PM PDT 24 | May 09 12:22:14 PM PDT 24 | 30335161 ps | ||
| T25 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.383233292 | May 09 12:22:09 PM PDT 24 | May 09 12:22:11 PM PDT 24 | 31529601 ps | ||
| T44 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.751135446 | May 09 12:22:21 PM PDT 24 | May 09 12:22:23 PM PDT 24 | 30256670 ps | ||
| T45 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1400051154 | May 09 12:22:11 PM PDT 24 | May 09 12:22:14 PM PDT 24 | 30577136 ps | ||
| T46 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1924993006 | May 09 12:22:09 PM PDT 24 | May 09 12:22:11 PM PDT 24 | 30928389 ps | ||
| T4 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2541206639 | May 09 12:22:24 PM PDT 24 | May 09 12:22:26 PM PDT 24 | 31145000 ps | ||
| T47 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2737783066 | May 09 12:23:09 PM PDT 24 | May 09 12:23:11 PM PDT 24 | 28964915 ps | ||
| T48 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.648461815 | May 09 12:22:11 PM PDT 24 | May 09 12:22:15 PM PDT 24 | 29617378 ps | ||
| T49 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.793228837 | May 09 12:22:10 PM PDT 24 | May 09 12:22:14 PM PDT 24 | 30693510 ps | ||
| T50 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4104898025 | May 09 12:22:07 PM PDT 24 | May 09 12:22:09 PM PDT 24 | 30249176 ps | ||
| T52 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2056436392 | May 09 12:22:08 PM PDT 24 | May 09 12:22:09 PM PDT 24 | 30197455 ps | ||
| T26 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3704703957 | May 09 12:23:10 PM PDT 24 | May 09 12:23:13 PM PDT 24 | 30458432 ps | ||
| T53 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1700017880 | May 09 12:22:10 PM PDT 24 | May 09 12:22:13 PM PDT 24 | 30527698 ps | ||
| T5 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1638175569 | May 09 12:22:10 PM PDT 24 | May 09 12:22:12 PM PDT 24 | 30853094 ps | ||
| T54 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4001163153 | May 09 12:22:07 PM PDT 24 | May 09 12:22:09 PM PDT 24 | 32324138 ps | ||
| T55 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.985970288 | May 09 12:22:11 PM PDT 24 | May 09 12:22:15 PM PDT 24 | 28766631 ps | ||
| T56 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1984708646 | May 09 12:22:11 PM PDT 24 | May 09 12:22:14 PM PDT 24 | 31849089 ps | ||
| T57 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.177463353 | May 09 12:22:06 PM PDT 24 | May 09 12:22:08 PM PDT 24 | 31029957 ps | ||
| T58 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1122956325 | May 09 12:22:06 PM PDT 24 | May 09 12:22:08 PM PDT 24 | 30162877 ps | ||
| T59 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2326330306 | May 09 12:23:09 PM PDT 24 | May 09 12:23:11 PM PDT 24 | 30954024 ps | ||
| T15 | /workspace/coverage/sync_alert/9.prim_sync_alert.981530741 | May 09 12:22:11 PM PDT 24 | May 09 12:22:15 PM PDT 24 | 9676235 ps | ||
| T36 | /workspace/coverage/sync_alert/7.prim_sync_alert.2223479637 | May 09 12:23:09 PM PDT 24 | May 09 12:23:11 PM PDT 24 | 8932362 ps | ||
| T37 | /workspace/coverage/sync_alert/16.prim_sync_alert.2335391035 | May 09 12:22:10 PM PDT 24 | May 09 12:22:14 PM PDT 24 | 8695335 ps | ||
| T38 | /workspace/coverage/sync_alert/6.prim_sync_alert.1162307321 | May 09 12:22:11 PM PDT 24 | May 09 12:22:15 PM PDT 24 | 8581538 ps | ||
| T39 | /workspace/coverage/sync_alert/10.prim_sync_alert.3857305706 | May 09 12:23:10 PM PDT 24 | May 09 12:23:13 PM PDT 24 | 9600186 ps | ||
| T27 | /workspace/coverage/sync_alert/1.prim_sync_alert.2671276470 | May 09 12:22:10 PM PDT 24 | May 09 12:22:13 PM PDT 24 | 8407729 ps | ||
| T40 | /workspace/coverage/sync_alert/13.prim_sync_alert.1620858517 | May 09 12:22:11 PM PDT 24 | May 09 12:22:14 PM PDT 24 | 9705441 ps | ||
| T41 | /workspace/coverage/sync_alert/18.prim_sync_alert.462842817 | May 09 12:22:12 PM PDT 24 | May 09 12:22:15 PM PDT 24 | 8522933 ps | ||
| T28 | /workspace/coverage/sync_alert/19.prim_sync_alert.2191118260 | May 09 12:22:11 PM PDT 24 | May 09 12:22:14 PM PDT 24 | 9443754 ps | ||
| T42 | /workspace/coverage/sync_alert/0.prim_sync_alert.637573892 | May 09 12:23:09 PM PDT 24 | May 09 12:23:11 PM PDT 24 | 10055744 ps | ||
| T29 | /workspace/coverage/sync_alert/4.prim_sync_alert.960289924 | May 09 12:22:09 PM PDT 24 | May 09 12:22:12 PM PDT 24 | 8397547 ps | ||
| T60 | /workspace/coverage/sync_alert/2.prim_sync_alert.1523695657 | May 09 12:22:11 PM PDT 24 | May 09 12:22:14 PM PDT 24 | 9206308 ps | ||
| T61 | /workspace/coverage/sync_alert/5.prim_sync_alert.476450739 | May 09 12:23:09 PM PDT 24 | May 09 12:23:11 PM PDT 24 | 9240953 ps | ||
| T62 | /workspace/coverage/sync_alert/3.prim_sync_alert.3176510334 | May 09 12:22:10 PM PDT 24 | May 09 12:22:12 PM PDT 24 | 8418561 ps | ||
| T30 | /workspace/coverage/sync_alert/17.prim_sync_alert.680217652 | May 09 12:22:10 PM PDT 24 | May 09 12:22:13 PM PDT 24 | 9400032 ps | ||
| T63 | /workspace/coverage/sync_alert/14.prim_sync_alert.2762211621 | May 09 12:22:11 PM PDT 24 | May 09 12:22:15 PM PDT 24 | 9197084 ps | ||
| T64 | /workspace/coverage/sync_alert/12.prim_sync_alert.3884825316 | May 09 12:22:06 PM PDT 24 | May 09 12:22:08 PM PDT 24 | 9349789 ps | ||
| T65 | /workspace/coverage/sync_alert/15.prim_sync_alert.3224168945 | May 09 12:23:09 PM PDT 24 | May 09 12:23:11 PM PDT 24 | 9036145 ps | ||
| T31 | /workspace/coverage/sync_alert/11.prim_sync_alert.1058590345 | May 09 12:22:10 PM PDT 24 | May 09 12:22:13 PM PDT 24 | 8936782 ps | ||
| T32 | /workspace/coverage/sync_alert/8.prim_sync_alert.2737543291 | May 09 12:22:11 PM PDT 24 | May 09 12:22:15 PM PDT 24 | 8744531 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2939837718 | May 09 12:29:54 PM PDT 24 | May 09 12:29:57 PM PDT 24 | 28800359 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3026120359 | May 09 12:28:37 PM PDT 24 | May 09 12:28:39 PM PDT 24 | 27776279 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3708342192 | May 09 12:27:13 PM PDT 24 | May 09 12:27:14 PM PDT 24 | 29949834 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1102715008 | May 09 12:28:06 PM PDT 24 | May 09 12:28:07 PM PDT 24 | 27566519 ps | ||
| T33 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4060880230 | May 09 12:29:42 PM PDT 24 | May 09 12:29:46 PM PDT 24 | 29315968 ps | ||
| T34 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1490745264 | May 09 12:25:41 PM PDT 24 | May 09 12:25:42 PM PDT 24 | 28409518 ps | ||
| T35 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.258767062 | May 09 12:25:31 PM PDT 24 | May 09 12:25:32 PM PDT 24 | 29768027 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2424947540 | May 09 12:25:49 PM PDT 24 | May 09 12:25:50 PM PDT 24 | 27748732 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1983490062 | May 09 12:29:43 PM PDT 24 | May 09 12:29:47 PM PDT 24 | 26878219 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2605146844 | May 09 12:26:53 PM PDT 24 | May 09 12:26:54 PM PDT 24 | 25397883 ps | ||
| T11 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4203127314 | May 09 12:26:56 PM PDT 24 | May 09 12:26:57 PM PDT 24 | 26153465 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1379159735 | May 09 12:29:57 PM PDT 24 | May 09 12:29:59 PM PDT 24 | 27960764 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3098761827 | May 09 12:26:15 PM PDT 24 | May 09 12:26:16 PM PDT 24 | 29550360 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2223846159 | May 09 12:25:28 PM PDT 24 | May 09 12:25:30 PM PDT 24 | 28204600 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3235387900 | May 09 12:28:34 PM PDT 24 | May 09 12:28:36 PM PDT 24 | 26628954 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1656598624 | May 09 12:29:57 PM PDT 24 | May 09 12:29:59 PM PDT 24 | 27500392 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3291374282 | May 09 12:27:42 PM PDT 24 | May 09 12:27:44 PM PDT 24 | 26344772 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3956295116 | May 09 12:30:07 PM PDT 24 | May 09 12:30:09 PM PDT 24 | 27860222 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2351969550 | May 09 12:30:03 PM PDT 24 | May 09 12:30:05 PM PDT 24 | 26295728 ps | ||
| T80 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2257610700 | May 09 12:26:07 PM PDT 24 | May 09 12:26:08 PM PDT 24 | 28212121 ps |
| Test location | /workspace/coverage/default/18.prim_async_alert.2058943987 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11526521 ps |
| CPU time | 0.4 seconds |
| Started | May 09 01:43:58 PM PDT 24 |
| Finished | May 09 01:44:01 PM PDT 24 |
| Peak memory | 145840 kb |
| Host | smart-c9b7c472-dac5-4785-a210-5a1b72e97a1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058943987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2058943987 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.2223479637 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8932362 ps |
| CPU time | 0.42 seconds |
| Started | May 09 12:23:09 PM PDT 24 |
| Finished | May 09 12:23:11 PM PDT 24 |
| Peak memory | 144576 kb |
| Host | smart-babe21b2-f5cc-44d3-b5ac-ddd1458736ee |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2223479637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2223479637 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.383233292 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 31529601 ps |
| CPU time | 0.42 seconds |
| Started | May 09 12:22:09 PM PDT 24 |
| Finished | May 09 12:22:11 PM PDT 24 |
| Peak memory | 145936 kb |
| Host | smart-b30010c9-2623-44dc-b613-ccd7aee81b97 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=383233292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.383233292 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.1823360100 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12103030 ps |
| CPU time | 0.4 seconds |
| Started | May 09 01:44:02 PM PDT 24 |
| Finished | May 09 01:44:04 PM PDT 24 |
| Peak memory | 145864 kb |
| Host | smart-b6a7d7a5-5d59-415a-9ba4-8735a8d7eaf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1823360100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1823360100 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1638175569 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30853094 ps |
| CPU time | 0.4 seconds |
| Started | May 09 12:22:10 PM PDT 24 |
| Finished | May 09 12:22:12 PM PDT 24 |
| Peak memory | 145936 kb |
| Host | smart-0cf552f6-b04c-4587-ac7f-36120df817b6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1638175569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1638175569 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4203127314 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 26153465 ps |
| CPU time | 0.46 seconds |
| Started | May 09 12:26:56 PM PDT 24 |
| Finished | May 09 12:26:57 PM PDT 24 |
| Peak memory | 145412 kb |
| Host | smart-c8d077e4-5632-4c5c-80c6-ae3484b0d561 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4203127314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.4203127314 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1736673160 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10636147 ps |
| CPU time | 0.39 seconds |
| Started | May 09 01:44:05 PM PDT 24 |
| Finished | May 09 01:44:07 PM PDT 24 |
| Peak memory | 145732 kb |
| Host | smart-f752306f-f843-4f47-bb28-cecf7567cb7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1736673160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1736673160 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.361804818 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11745117 ps |
| CPU time | 0.39 seconds |
| Started | May 09 01:44:07 PM PDT 24 |
| Finished | May 09 01:44:10 PM PDT 24 |
| Peak memory | 145864 kb |
| Host | smart-0ca160fa-ba3a-4929-83ce-30a1488e7dbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361804818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.361804818 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.1072806230 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10634698 ps |
| CPU time | 0.38 seconds |
| Started | May 09 01:43:57 PM PDT 24 |
| Finished | May 09 01:44:00 PM PDT 24 |
| Peak memory | 145848 kb |
| Host | smart-db712ac7-e605-40f2-9632-0cf3b1eaf972 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072806230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1072806230 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3596513426 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11200465 ps |
| CPU time | 0.39 seconds |
| Started | May 09 01:44:04 PM PDT 24 |
| Finished | May 09 01:44:06 PM PDT 24 |
| Peak memory | 145860 kb |
| Host | smart-69794f99-80ea-4fa8-b165-a4140b0398b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596513426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3596513426 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3025612179 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12100942 ps |
| CPU time | 0.4 seconds |
| Started | May 09 01:44:05 PM PDT 24 |
| Finished | May 09 01:44:08 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-2203920b-632c-498d-8280-98506712df53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025612179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3025612179 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.642645142 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10828507 ps |
| CPU time | 0.38 seconds |
| Started | May 09 01:43:57 PM PDT 24 |
| Finished | May 09 01:44:00 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-cf091a94-dbeb-45d5-832b-ea131a77f49a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=642645142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.642645142 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3025831005 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11826821 ps |
| CPU time | 0.39 seconds |
| Started | May 09 01:44:02 PM PDT 24 |
| Finished | May 09 01:44:03 PM PDT 24 |
| Peak memory | 145856 kb |
| Host | smart-d6f0ab45-8634-4a66-a3c6-1c7615a1bc0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025831005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3025831005 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.4219106227 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10792978 ps |
| CPU time | 0.38 seconds |
| Started | May 09 01:43:55 PM PDT 24 |
| Finished | May 09 01:43:57 PM PDT 24 |
| Peak memory | 145848 kb |
| Host | smart-66bad5c2-81be-4ade-9ac2-21c92668cfa1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4219106227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.4219106227 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1856965341 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10812348 ps |
| CPU time | 0.4 seconds |
| Started | May 09 01:44:06 PM PDT 24 |
| Finished | May 09 01:44:09 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-bd26b660-4db1-4e66-a5c0-033173ced2e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856965341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1856965341 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3967708779 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10033129 ps |
| CPU time | 0.38 seconds |
| Started | May 09 01:44:05 PM PDT 24 |
| Finished | May 09 01:44:08 PM PDT 24 |
| Peak memory | 145848 kb |
| Host | smart-dd1daeab-0109-46a6-b4e7-fcaa9f539995 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3967708779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3967708779 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.1711820276 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11228195 ps |
| CPU time | 0.39 seconds |
| Started | May 09 01:44:07 PM PDT 24 |
| Finished | May 09 01:44:10 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-e37479e9-44a1-4062-9379-a8f9f69b892c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711820276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1711820276 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.3398146209 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11146693 ps |
| CPU time | 0.4 seconds |
| Started | May 09 01:43:58 PM PDT 24 |
| Finished | May 09 01:44:01 PM PDT 24 |
| Peak memory | 145844 kb |
| Host | smart-cd29c9c5-d04c-49dc-9b11-03db49a04cc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3398146209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3398146209 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.4200820888 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11605711 ps |
| CPU time | 0.4 seconds |
| Started | May 09 01:43:56 PM PDT 24 |
| Finished | May 09 01:43:58 PM PDT 24 |
| Peak memory | 145844 kb |
| Host | smart-f227a21d-086d-4947-b68b-df769c7051c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4200820888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.4200820888 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1709820828 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 10659548 ps |
| CPU time | 0.39 seconds |
| Started | May 09 01:43:55 PM PDT 24 |
| Finished | May 09 01:43:56 PM PDT 24 |
| Peak memory | 145856 kb |
| Host | smart-96992060-92cb-42c9-bc1c-1a7e797c72c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1709820828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1709820828 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2090922477 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11482164 ps |
| CPU time | 0.39 seconds |
| Started | May 09 01:44:01 PM PDT 24 |
| Finished | May 09 01:44:03 PM PDT 24 |
| Peak memory | 145732 kb |
| Host | smart-9d838175-b9fc-406e-90be-2954a5295270 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2090922477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2090922477 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.1005607020 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10655623 ps |
| CPU time | 0.38 seconds |
| Started | May 09 01:44:06 PM PDT 24 |
| Finished | May 09 01:44:09 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-a2d4dedf-38fb-40d1-9eab-e076d0716e68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005607020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1005607020 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2889721609 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10800057 ps |
| CPU time | 0.38 seconds |
| Started | May 09 01:44:19 PM PDT 24 |
| Finished | May 09 01:44:21 PM PDT 24 |
| Peak memory | 145840 kb |
| Host | smart-bf684580-986a-4b9c-b4a0-7760f0b8d135 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889721609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2889721609 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1724785768 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11461741 ps |
| CPU time | 0.38 seconds |
| Started | May 09 01:43:56 PM PDT 24 |
| Finished | May 09 01:43:58 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-69865ae1-6034-4b02-94c9-3bbd14bf623c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1724785768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1724785768 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1924993006 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 30928389 ps |
| CPU time | 0.42 seconds |
| Started | May 09 12:22:09 PM PDT 24 |
| Finished | May 09 12:22:11 PM PDT 24 |
| Peak memory | 145932 kb |
| Host | smart-043cf372-6eed-4101-bbe3-0ccca6e1edcc |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1924993006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1924993006 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1122956325 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 30162877 ps |
| CPU time | 0.46 seconds |
| Started | May 09 12:22:06 PM PDT 24 |
| Finished | May 09 12:22:08 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-b6582d06-64d5-46e6-8a51-8be52ef83425 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1122956325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1122956325 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2326330306 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 30954024 ps |
| CPU time | 0.45 seconds |
| Started | May 09 12:23:09 PM PDT 24 |
| Finished | May 09 12:23:11 PM PDT 24 |
| Peak memory | 144528 kb |
| Host | smart-abb77360-85f7-4035-b109-ad35a8772a4f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2326330306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2326330306 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.751135446 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30256670 ps |
| CPU time | 0.41 seconds |
| Started | May 09 12:22:21 PM PDT 24 |
| Finished | May 09 12:22:23 PM PDT 24 |
| Peak memory | 145692 kb |
| Host | smart-1fdd0021-2cee-466e-adec-4e086a5d3ec1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=751135446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.751135446 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.793228837 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 30693510 ps |
| CPU time | 0.41 seconds |
| Started | May 09 12:22:10 PM PDT 24 |
| Finished | May 09 12:22:14 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-d51105b9-3fca-47e1-a43c-1177031fb2eb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=793228837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.793228837 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2397288774 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30335161 ps |
| CPU time | 0.4 seconds |
| Started | May 09 12:22:10 PM PDT 24 |
| Finished | May 09 12:22:14 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-0b8cad20-5247-4a5d-b7c5-b0e805410403 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2397288774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2397288774 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.177463353 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 31029957 ps |
| CPU time | 0.45 seconds |
| Started | May 09 12:22:06 PM PDT 24 |
| Finished | May 09 12:22:08 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-13a3f80a-69dc-43dd-970a-254b944dd52e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=177463353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.177463353 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1984708646 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 31849089 ps |
| CPU time | 0.41 seconds |
| Started | May 09 12:22:11 PM PDT 24 |
| Finished | May 09 12:22:14 PM PDT 24 |
| Peak memory | 145936 kb |
| Host | smart-07f37a0e-54e1-4f70-a890-9a1f6db1b3da |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1984708646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1984708646 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.648461815 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29617378 ps |
| CPU time | 0.4 seconds |
| Started | May 09 12:22:11 PM PDT 24 |
| Finished | May 09 12:22:15 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-2977862f-aa8d-4803-9c1c-545c34792ac8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=648461815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.648461815 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2541206639 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 31145000 ps |
| CPU time | 0.41 seconds |
| Started | May 09 12:22:24 PM PDT 24 |
| Finished | May 09 12:22:26 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-0b235b41-8945-4d02-804b-fae9302c8bab |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2541206639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2541206639 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4104898025 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30249176 ps |
| CPU time | 0.42 seconds |
| Started | May 09 12:22:07 PM PDT 24 |
| Finished | May 09 12:22:09 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-66f9bdd5-d1d3-4b72-9c3a-72a0cd273b0c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4104898025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4104898025 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2056436392 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30197455 ps |
| CPU time | 0.4 seconds |
| Started | May 09 12:22:08 PM PDT 24 |
| Finished | May 09 12:22:09 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-227d8c49-5374-4e7b-a370-46526a883d66 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2056436392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2056436392 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1400051154 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30577136 ps |
| CPU time | 0.41 seconds |
| Started | May 09 12:22:11 PM PDT 24 |
| Finished | May 09 12:22:14 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-95adb65b-8226-4078-8360-943e0570416e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1400051154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1400051154 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2737783066 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 28964915 ps |
| CPU time | 0.51 seconds |
| Started | May 09 12:23:09 PM PDT 24 |
| Finished | May 09 12:23:11 PM PDT 24 |
| Peak memory | 144380 kb |
| Host | smart-494f3ed9-236d-409e-8cfa-25cf4831bc07 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2737783066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2737783066 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3704703957 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 30458432 ps |
| CPU time | 0.39 seconds |
| Started | May 09 12:23:10 PM PDT 24 |
| Finished | May 09 12:23:13 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-4296b14e-5d34-40b2-a0d4-e0d65e237cfa |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3704703957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3704703957 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1700017880 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30527698 ps |
| CPU time | 0.39 seconds |
| Started | May 09 12:22:10 PM PDT 24 |
| Finished | May 09 12:22:13 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-ecf38b65-3287-4aed-aa57-52a8244e3a74 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1700017880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1700017880 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.985970288 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 28766631 ps |
| CPU time | 0.4 seconds |
| Started | May 09 12:22:11 PM PDT 24 |
| Finished | May 09 12:22:15 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-8caa2e1c-b863-4502-a36b-57c09cabaf0d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=985970288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.985970288 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4001163153 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 32324138 ps |
| CPU time | 0.41 seconds |
| Started | May 09 12:22:07 PM PDT 24 |
| Finished | May 09 12:22:09 PM PDT 24 |
| Peak memory | 145700 kb |
| Host | smart-73d073f4-b087-4fb7-98df-71a5b98bec81 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4001163153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.4001163153 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.637573892 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10055744 ps |
| CPU time | 0.36 seconds |
| Started | May 09 12:23:09 PM PDT 24 |
| Finished | May 09 12:23:11 PM PDT 24 |
| Peak memory | 145960 kb |
| Host | smart-c615f64a-ca15-455c-b99a-6672c4acc959 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=637573892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.637573892 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.2671276470 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8407729 ps |
| CPU time | 0.38 seconds |
| Started | May 09 12:22:10 PM PDT 24 |
| Finished | May 09 12:22:13 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-af797a6f-5871-459d-965a-e9240d9f704d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2671276470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2671276470 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3857305706 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9600186 ps |
| CPU time | 0.37 seconds |
| Started | May 09 12:23:10 PM PDT 24 |
| Finished | May 09 12:23:13 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-2429ee71-e23f-4208-881a-212447d0c234 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3857305706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3857305706 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1058590345 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8936782 ps |
| CPU time | 0.38 seconds |
| Started | May 09 12:22:10 PM PDT 24 |
| Finished | May 09 12:22:13 PM PDT 24 |
| Peak memory | 145456 kb |
| Host | smart-2823d516-2bbc-49fb-ba5c-cfca7e5e2727 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1058590345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1058590345 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3884825316 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 9349789 ps |
| CPU time | 0.39 seconds |
| Started | May 09 12:22:06 PM PDT 24 |
| Finished | May 09 12:22:08 PM PDT 24 |
| Peak memory | 145456 kb |
| Host | smart-acd8df0a-ee44-4e3a-90ba-748d9ff68152 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3884825316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3884825316 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1620858517 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9705441 ps |
| CPU time | 0.39 seconds |
| Started | May 09 12:22:11 PM PDT 24 |
| Finished | May 09 12:22:14 PM PDT 24 |
| Peak memory | 145524 kb |
| Host | smart-e3b3f3e7-cc30-45ca-9c31-81e2ddebfb4c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1620858517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1620858517 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.2762211621 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 9197084 ps |
| CPU time | 0.39 seconds |
| Started | May 09 12:22:11 PM PDT 24 |
| Finished | May 09 12:22:15 PM PDT 24 |
| Peak memory | 145476 kb |
| Host | smart-f422573e-e9c4-45e0-ba2d-ebfabc859f2e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2762211621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2762211621 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3224168945 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 9036145 ps |
| CPU time | 0.45 seconds |
| Started | May 09 12:23:09 PM PDT 24 |
| Finished | May 09 12:23:11 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-719c907f-1cd2-43c7-846b-c69a6f5c2f71 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3224168945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3224168945 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.2335391035 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8695335 ps |
| CPU time | 0.37 seconds |
| Started | May 09 12:22:10 PM PDT 24 |
| Finished | May 09 12:22:14 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-1aadd304-86a5-4bc2-9fd7-fa14bcc0cbb3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2335391035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2335391035 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.680217652 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9400032 ps |
| CPU time | 0.39 seconds |
| Started | May 09 12:22:10 PM PDT 24 |
| Finished | May 09 12:22:13 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-6b487ae7-f09f-4099-bda3-573658df92fa |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=680217652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.680217652 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.462842817 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8522933 ps |
| CPU time | 0.38 seconds |
| Started | May 09 12:22:12 PM PDT 24 |
| Finished | May 09 12:22:15 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-10463343-e5e1-4629-930c-3081be496b56 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=462842817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.462842817 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.2191118260 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9443754 ps |
| CPU time | 0.42 seconds |
| Started | May 09 12:22:11 PM PDT 24 |
| Finished | May 09 12:22:14 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-31782025-cc5f-4ce3-b105-7416ee9b8bac |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2191118260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2191118260 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.1523695657 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9206308 ps |
| CPU time | 0.39 seconds |
| Started | May 09 12:22:11 PM PDT 24 |
| Finished | May 09 12:22:14 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-5c072e14-8a17-4ac9-b142-fb75d62ac71a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1523695657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1523695657 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3176510334 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 8418561 ps |
| CPU time | 0.37 seconds |
| Started | May 09 12:22:10 PM PDT 24 |
| Finished | May 09 12:22:12 PM PDT 24 |
| Peak memory | 145456 kb |
| Host | smart-29d867b2-86aa-4bcf-950a-ce7901e9108b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3176510334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3176510334 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.960289924 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8397547 ps |
| CPU time | 0.41 seconds |
| Started | May 09 12:22:09 PM PDT 24 |
| Finished | May 09 12:22:12 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-dff6ddc2-7405-4b31-93a0-adf5a2a60c42 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=960289924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.960289924 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.476450739 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9240953 ps |
| CPU time | 0.47 seconds |
| Started | May 09 12:23:09 PM PDT 24 |
| Finished | May 09 12:23:11 PM PDT 24 |
| Peak memory | 144240 kb |
| Host | smart-bffdbc46-7349-41ca-8986-d451ab874db4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=476450739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.476450739 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1162307321 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8581538 ps |
| CPU time | 0.37 seconds |
| Started | May 09 12:22:11 PM PDT 24 |
| Finished | May 09 12:22:15 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-992aceea-ad52-487d-86ca-05cc6b5edb85 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1162307321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1162307321 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.2737543291 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8744531 ps |
| CPU time | 0.38 seconds |
| Started | May 09 12:22:11 PM PDT 24 |
| Finished | May 09 12:22:15 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-90d715a9-2ed3-4d19-8019-af42271143d3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2737543291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2737543291 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.981530741 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9676235 ps |
| CPU time | 0.43 seconds |
| Started | May 09 12:22:11 PM PDT 24 |
| Finished | May 09 12:22:15 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-1a7f389b-dbf9-4187-8881-3b69f46d7612 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=981530741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.981530741 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2424947540 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27748732 ps |
| CPU time | 0.4 seconds |
| Started | May 09 12:25:49 PM PDT 24 |
| Finished | May 09 12:25:50 PM PDT 24 |
| Peak memory | 145516 kb |
| Host | smart-d6f0a442-c4e2-431b-9a51-316ba14d8515 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2424947540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2424947540 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3026120359 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27776279 ps |
| CPU time | 0.44 seconds |
| Started | May 09 12:28:37 PM PDT 24 |
| Finished | May 09 12:28:39 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-fde1b2c5-bdb3-4f04-9db3-7836f154bb36 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3026120359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3026120359 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1379159735 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27960764 ps |
| CPU time | 0.42 seconds |
| Started | May 09 12:29:57 PM PDT 24 |
| Finished | May 09 12:29:59 PM PDT 24 |
| Peak memory | 145396 kb |
| Host | smart-6b0bb4a8-18d4-4f9a-abc8-ed551bc4d15c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1379159735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1379159735 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2223846159 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28204600 ps |
| CPU time | 0.4 seconds |
| Started | May 09 12:25:28 PM PDT 24 |
| Finished | May 09 12:25:30 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-bfecccd4-4b0c-480f-922d-a8de89cf1559 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2223846159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2223846159 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1490745264 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 28409518 ps |
| CPU time | 0.42 seconds |
| Started | May 09 12:25:41 PM PDT 24 |
| Finished | May 09 12:25:42 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-fd3e7cf7-6017-4db6-b0eb-c4abca220498 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1490745264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1490745264 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3235387900 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26628954 ps |
| CPU time | 0.39 seconds |
| Started | May 09 12:28:34 PM PDT 24 |
| Finished | May 09 12:28:36 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-18e67f21-ab74-48d8-8d44-5d1ba0d4e9a9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3235387900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3235387900 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3291374282 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 26344772 ps |
| CPU time | 0.4 seconds |
| Started | May 09 12:27:42 PM PDT 24 |
| Finished | May 09 12:27:44 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-86d61043-1a12-479b-a0c2-74ad106442ef |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3291374282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3291374282 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1983490062 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 26878219 ps |
| CPU time | 0.38 seconds |
| Started | May 09 12:29:43 PM PDT 24 |
| Finished | May 09 12:29:47 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-a5460622-07f0-4aa8-b7e4-e267f9559584 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1983490062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1983490062 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3708342192 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 29949834 ps |
| CPU time | 0.41 seconds |
| Started | May 09 12:27:13 PM PDT 24 |
| Finished | May 09 12:27:14 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-446fa508-953b-4f26-b2fc-f9ddf6bed19b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3708342192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3708342192 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.258767062 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 29768027 ps |
| CPU time | 0.44 seconds |
| Started | May 09 12:25:31 PM PDT 24 |
| Finished | May 09 12:25:32 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-8cda99c8-be2e-492d-aace-eac674780b3a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=258767062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.258767062 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2351969550 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 26295728 ps |
| CPU time | 0.4 seconds |
| Started | May 09 12:30:03 PM PDT 24 |
| Finished | May 09 12:30:05 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-dcf17505-a070-4c4e-9057-5cfc5115f84a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2351969550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2351969550 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2605146844 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 25397883 ps |
| CPU time | 0.43 seconds |
| Started | May 09 12:26:53 PM PDT 24 |
| Finished | May 09 12:26:54 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-fe9c5f67-f7b7-4a93-adee-dc8ade7207f3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2605146844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2605146844 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3098761827 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 29550360 ps |
| CPU time | 0.4 seconds |
| Started | May 09 12:26:15 PM PDT 24 |
| Finished | May 09 12:26:16 PM PDT 24 |
| Peak memory | 145396 kb |
| Host | smart-4f58ee63-990b-4f50-81b4-9e1a8db638cb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3098761827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3098761827 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3956295116 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 27860222 ps |
| CPU time | 0.43 seconds |
| Started | May 09 12:30:07 PM PDT 24 |
| Finished | May 09 12:30:09 PM PDT 24 |
| Peak memory | 145420 kb |
| Host | smart-4a257f8e-ccd7-43fe-8f9e-a2801c7e13b7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3956295116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3956295116 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1656598624 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27500392 ps |
| CPU time | 0.39 seconds |
| Started | May 09 12:29:57 PM PDT 24 |
| Finished | May 09 12:29:59 PM PDT 24 |
| Peak memory | 145396 kb |
| Host | smart-c5a5161b-fd53-405f-aa18-5355ce68967c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1656598624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1656598624 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2939837718 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 28800359 ps |
| CPU time | 0.4 seconds |
| Started | May 09 12:29:54 PM PDT 24 |
| Finished | May 09 12:29:57 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-ffed3ffe-6a3f-4d8c-9979-4a3ec3059db6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2939837718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2939837718 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2257610700 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 28212121 ps |
| CPU time | 0.41 seconds |
| Started | May 09 12:26:07 PM PDT 24 |
| Finished | May 09 12:26:08 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-7303f9c5-14f9-4c8b-b596-72b794ddb423 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2257610700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2257610700 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1102715008 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27566519 ps |
| CPU time | 0.4 seconds |
| Started | May 09 12:28:06 PM PDT 24 |
| Finished | May 09 12:28:07 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-23a00e61-d56f-4265-96ce-38659a4c9164 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1102715008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1102715008 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4060880230 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 29315968 ps |
| CPU time | 0.38 seconds |
| Started | May 09 12:29:42 PM PDT 24 |
| Finished | May 09 12:29:46 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-76fd7e22-acde-423b-894a-101cba3ccc43 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4060880230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.4060880230 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
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