| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.53 | 88.53 | 100.00 | 100.00 | 91.67 | 91.67 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/9.prim_async_alert.477932137 |
| 91.41 | 2.88 | 100.00 | 0.00 | 93.75 | 2.08 | 100.00 | 0.00 | 82.14 | 3.57 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/5.prim_sync_alert.1282038046 |
| 94.11 | 2.70 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 7.14 | 95.83 | 0.00 | 83.72 | 6.98 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1356408713 |
| 94.85 | 0.73 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 2.33 | /workspace/coverage/default/19.prim_async_alert.3816495616 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2458854633 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.1232703913 |
| /workspace/coverage/default/1.prim_async_alert.203327752 |
| /workspace/coverage/default/10.prim_async_alert.170475763 |
| /workspace/coverage/default/11.prim_async_alert.2211534344 |
| /workspace/coverage/default/12.prim_async_alert.300219486 |
| /workspace/coverage/default/13.prim_async_alert.1672914091 |
| /workspace/coverage/default/14.prim_async_alert.3828656589 |
| /workspace/coverage/default/15.prim_async_alert.3637576796 |
| /workspace/coverage/default/16.prim_async_alert.246528734 |
| /workspace/coverage/default/17.prim_async_alert.1330082632 |
| /workspace/coverage/default/18.prim_async_alert.4245602233 |
| /workspace/coverage/default/2.prim_async_alert.1441950184 |
| /workspace/coverage/default/3.prim_async_alert.4082624045 |
| /workspace/coverage/default/4.prim_async_alert.3015088848 |
| /workspace/coverage/default/5.prim_async_alert.3215690981 |
| /workspace/coverage/default/6.prim_async_alert.71010259 |
| /workspace/coverage/default/7.prim_async_alert.1770051759 |
| /workspace/coverage/default/8.prim_async_alert.1903708061 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2348176091 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.824940606 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3908102014 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3813563136 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2588727243 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3818020769 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4081152299 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4217097369 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2534799650 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.232930638 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.511015687 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2938358536 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.68891781 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2084913016 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3479428074 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.844260251 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1946237177 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1953172341 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.2619173149 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.4167701951 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3277490110 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.3385052852 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.4290818969 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.740399661 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.669245648 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.944228756 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.1745637091 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.647644103 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.3739224922 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.2761480417 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.757956398 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3674922623 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.2305710386 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.251449182 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1563086894 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.4016660183 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1203445946 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2858866167 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2836863783 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1037562284 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1990181507 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3595017002 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2259008149 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3803598569 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3140436439 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2547713320 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3090432672 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3912997013 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3086093743 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2422585744 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2097182828 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.146697098 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.30542933 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2158665832 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1325872047 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.635212106 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/2.prim_async_alert.1441950184 | May 12 01:54:43 PM PDT 24 | May 12 01:54:44 PM PDT 24 | 10937414 ps | ||
| T2 | /workspace/coverage/default/9.prim_async_alert.477932137 | May 12 01:54:53 PM PDT 24 | May 12 01:54:53 PM PDT 24 | 11896321 ps | ||
| T3 | /workspace/coverage/default/18.prim_async_alert.4245602233 | May 12 01:55:07 PM PDT 24 | May 12 01:55:08 PM PDT 24 | 11867012 ps | ||
| T9 | /workspace/coverage/default/0.prim_async_alert.1232703913 | May 12 01:54:43 PM PDT 24 | May 12 01:54:44 PM PDT 24 | 11597450 ps | ||
| T7 | /workspace/coverage/default/19.prim_async_alert.3816495616 | May 12 01:55:07 PM PDT 24 | May 12 01:55:08 PM PDT 24 | 10443200 ps | ||
| T19 | /workspace/coverage/default/7.prim_async_alert.1770051759 | May 12 01:54:49 PM PDT 24 | May 12 01:54:49 PM PDT 24 | 11241463 ps | ||
| T12 | /workspace/coverage/default/4.prim_async_alert.3015088848 | May 12 01:54:46 PM PDT 24 | May 12 01:54:47 PM PDT 24 | 11932829 ps | ||
| T20 | /workspace/coverage/default/8.prim_async_alert.1903708061 | May 12 01:54:52 PM PDT 24 | May 12 01:54:53 PM PDT 24 | 11167344 ps | ||
| T21 | /workspace/coverage/default/1.prim_async_alert.203327752 | May 12 01:54:43 PM PDT 24 | May 12 01:54:43 PM PDT 24 | 10760453 ps | ||
| T22 | /workspace/coverage/default/17.prim_async_alert.1330082632 | May 12 01:55:04 PM PDT 24 | May 12 01:55:05 PM PDT 24 | 11920951 ps | ||
| T8 | /workspace/coverage/default/14.prim_async_alert.3828656589 | May 12 01:54:55 PM PDT 24 | May 12 01:54:56 PM PDT 24 | 11892396 ps | ||
| T13 | /workspace/coverage/default/13.prim_async_alert.1672914091 | May 12 01:54:59 PM PDT 24 | May 12 01:55:00 PM PDT 24 | 12440713 ps | ||
| T47 | /workspace/coverage/default/11.prim_async_alert.2211534344 | May 12 01:54:55 PM PDT 24 | May 12 01:54:56 PM PDT 24 | 12452933 ps | ||
| T16 | /workspace/coverage/default/16.prim_async_alert.246528734 | May 12 01:55:01 PM PDT 24 | May 12 01:55:01 PM PDT 24 | 11224572 ps | ||
| T17 | /workspace/coverage/default/3.prim_async_alert.4082624045 | May 12 01:54:44 PM PDT 24 | May 12 01:54:45 PM PDT 24 | 11430646 ps | ||
| T23 | /workspace/coverage/default/15.prim_async_alert.3637576796 | May 12 01:54:58 PM PDT 24 | May 12 01:54:59 PM PDT 24 | 10420435 ps | ||
| T48 | /workspace/coverage/default/5.prim_async_alert.3215690981 | May 12 01:54:45 PM PDT 24 | May 12 01:54:45 PM PDT 24 | 10857729 ps | ||
| T49 | /workspace/coverage/default/12.prim_async_alert.300219486 | May 12 01:54:55 PM PDT 24 | May 12 01:54:56 PM PDT 24 | 10793995 ps | ||
| T50 | /workspace/coverage/default/10.prim_async_alert.170475763 | May 12 01:54:52 PM PDT 24 | May 12 01:54:53 PM PDT 24 | 11383713 ps | ||
| T51 | /workspace/coverage/default/6.prim_async_alert.71010259 | May 12 01:54:49 PM PDT 24 | May 12 01:54:49 PM PDT 24 | 10504600 ps | ||
| T39 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3479428074 | May 12 01:55:16 PM PDT 24 | May 12 01:55:17 PM PDT 24 | 32072234 ps | ||
| T18 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2938358536 | May 12 01:55:15 PM PDT 24 | May 12 01:55:16 PM PDT 24 | 32592456 ps | ||
| T40 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2084913016 | May 12 01:55:15 PM PDT 24 | May 12 01:55:16 PM PDT 24 | 28744868 ps | ||
| T14 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1356408713 | May 12 01:55:28 PM PDT 24 | May 12 01:55:29 PM PDT 24 | 30277582 ps | ||
| T41 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.68891781 | May 12 01:55:15 PM PDT 24 | May 12 01:55:16 PM PDT 24 | 29846865 ps | ||
| T42 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4081152299 | May 12 01:55:25 PM PDT 24 | May 12 01:55:25 PM PDT 24 | 30066903 ps | ||
| T43 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2588727243 | May 12 01:55:21 PM PDT 24 | May 12 01:55:22 PM PDT 24 | 31135220 ps | ||
| T44 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3813563136 | May 12 01:55:21 PM PDT 24 | May 12 01:55:22 PM PDT 24 | 27733324 ps | ||
| T45 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.844260251 | May 12 01:55:18 PM PDT 24 | May 12 01:55:18 PM PDT 24 | 33040950 ps | ||
| T46 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2348176091 | May 12 01:55:12 PM PDT 24 | May 12 01:55:12 PM PDT 24 | 31048493 ps | ||
| T52 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1946237177 | May 12 01:55:17 PM PDT 24 | May 12 01:55:18 PM PDT 24 | 29565867 ps | ||
| T53 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4217097369 | May 12 01:55:23 PM PDT 24 | May 12 01:55:24 PM PDT 24 | 30380586 ps | ||
| T54 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2534799650 | May 12 01:55:25 PM PDT 24 | May 12 01:55:26 PM PDT 24 | 29539285 ps | ||
| T55 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.232930638 | May 12 01:55:28 PM PDT 24 | May 12 01:55:29 PM PDT 24 | 29647369 ps | ||
| T15 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3908102014 | May 12 01:55:18 PM PDT 24 | May 12 01:55:19 PM PDT 24 | 31531397 ps | ||
| T56 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.511015687 | May 12 01:55:15 PM PDT 24 | May 12 01:55:16 PM PDT 24 | 31013061 ps | ||
| T57 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1953172341 | May 12 01:55:18 PM PDT 24 | May 12 01:55:19 PM PDT 24 | 30779762 ps | ||
| T58 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3818020769 | May 12 01:55:25 PM PDT 24 | May 12 01:55:26 PM PDT 24 | 32204749 ps | ||
| T59 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.824940606 | May 12 01:55:17 PM PDT 24 | May 12 01:55:17 PM PDT 24 | 31162816 ps | ||
| T24 | /workspace/coverage/sync_alert/14.prim_sync_alert.669245648 | May 12 01:55:40 PM PDT 24 | May 12 01:55:41 PM PDT 24 | 8635000 ps | ||
| T25 | /workspace/coverage/sync_alert/3.prim_sync_alert.3674922623 | May 12 01:55:30 PM PDT 24 | May 12 01:55:31 PM PDT 24 | 9142308 ps | ||
| T34 | /workspace/coverage/sync_alert/10.prim_sync_alert.3277490110 | May 12 01:55:35 PM PDT 24 | May 12 01:55:35 PM PDT 24 | 9473682 ps | ||
| T26 | /workspace/coverage/sync_alert/9.prim_sync_alert.1203445946 | May 12 01:55:31 PM PDT 24 | May 12 01:55:32 PM PDT 24 | 9012900 ps | ||
| T10 | /workspace/coverage/sync_alert/5.prim_sync_alert.1282038046 | May 12 01:55:33 PM PDT 24 | May 12 01:55:34 PM PDT 24 | 9488930 ps | ||
| T35 | /workspace/coverage/sync_alert/17.prim_sync_alert.647644103 | May 12 01:55:39 PM PDT 24 | May 12 01:55:39 PM PDT 24 | 8365072 ps | ||
| T36 | /workspace/coverage/sync_alert/18.prim_sync_alert.3739224922 | May 12 01:55:42 PM PDT 24 | May 12 01:55:42 PM PDT 24 | 9515558 ps | ||
| T37 | /workspace/coverage/sync_alert/13.prim_sync_alert.740399661 | May 12 01:55:39 PM PDT 24 | May 12 01:55:40 PM PDT 24 | 9668213 ps | ||
| T27 | /workspace/coverage/sync_alert/2.prim_sync_alert.757956398 | May 12 01:55:29 PM PDT 24 | May 12 01:55:29 PM PDT 24 | 9619863 ps | ||
| T38 | /workspace/coverage/sync_alert/0.prim_sync_alert.2619173149 | May 12 01:55:28 PM PDT 24 | May 12 01:55:28 PM PDT 24 | 9475626 ps | ||
| T60 | /workspace/coverage/sync_alert/4.prim_sync_alert.2305710386 | May 12 01:55:30 PM PDT 24 | May 12 01:55:31 PM PDT 24 | 9586973 ps | ||
| T61 | /workspace/coverage/sync_alert/11.prim_sync_alert.3385052852 | May 12 01:55:38 PM PDT 24 | May 12 01:55:39 PM PDT 24 | 8856449 ps | ||
| T28 | /workspace/coverage/sync_alert/7.prim_sync_alert.1563086894 | May 12 01:55:31 PM PDT 24 | May 12 01:55:31 PM PDT 24 | 9374757 ps | ||
| T62 | /workspace/coverage/sync_alert/19.prim_sync_alert.2761480417 | May 12 01:55:41 PM PDT 24 | May 12 01:55:42 PM PDT 24 | 10813590 ps | ||
| T63 | /workspace/coverage/sync_alert/12.prim_sync_alert.4290818969 | May 12 01:55:38 PM PDT 24 | May 12 01:55:39 PM PDT 24 | 10861661 ps | ||
| T64 | /workspace/coverage/sync_alert/6.prim_sync_alert.251449182 | May 12 01:55:30 PM PDT 24 | May 12 01:55:31 PM PDT 24 | 9468067 ps | ||
| T29 | /workspace/coverage/sync_alert/16.prim_sync_alert.1745637091 | May 12 01:55:38 PM PDT 24 | May 12 01:55:39 PM PDT 24 | 9440869 ps | ||
| T30 | /workspace/coverage/sync_alert/1.prim_sync_alert.4167701951 | May 12 01:55:28 PM PDT 24 | May 12 01:55:29 PM PDT 24 | 9242830 ps | ||
| T65 | /workspace/coverage/sync_alert/15.prim_sync_alert.944228756 | May 12 01:55:38 PM PDT 24 | May 12 01:55:39 PM PDT 24 | 9318369 ps | ||
| T66 | /workspace/coverage/sync_alert/8.prim_sync_alert.4016660183 | May 12 01:55:32 PM PDT 24 | May 12 01:55:32 PM PDT 24 | 9408994 ps | ||
| T31 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.146697098 | May 12 01:55:48 PM PDT 24 | May 12 01:55:49 PM PDT 24 | 28674173 ps | ||
| T32 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.30542933 | May 12 01:55:48 PM PDT 24 | May 12 01:55:49 PM PDT 24 | 26910919 ps | ||
| T11 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2836863783 | May 12 01:55:48 PM PDT 24 | May 12 01:55:49 PM PDT 24 | 26973476 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2422585744 | May 12 01:55:44 PM PDT 24 | May 12 01:55:45 PM PDT 24 | 28672930 ps | ||
| T33 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2858866167 | May 12 01:55:45 PM PDT 24 | May 12 01:55:45 PM PDT 24 | 27691616 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3595017002 | May 12 01:55:48 PM PDT 24 | May 12 01:55:49 PM PDT 24 | 30633398 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1990181507 | May 12 01:55:50 PM PDT 24 | May 12 01:55:50 PM PDT 24 | 27643067 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2259008149 | May 12 01:55:48 PM PDT 24 | May 12 01:55:49 PM PDT 24 | 28156597 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1325872047 | May 12 01:55:48 PM PDT 24 | May 12 01:55:49 PM PDT 24 | 27318855 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3140436439 | May 12 01:55:51 PM PDT 24 | May 12 01:55:51 PM PDT 24 | 26393813 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2547713320 | May 12 01:55:51 PM PDT 24 | May 12 01:55:52 PM PDT 24 | 26696830 ps | ||
| T4 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2097182828 | May 12 01:55:45 PM PDT 24 | May 12 01:55:46 PM PDT 24 | 25852999 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3803598569 | May 12 01:55:53 PM PDT 24 | May 12 01:55:53 PM PDT 24 | 29093392 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2458854633 | May 12 01:55:41 PM PDT 24 | May 12 01:55:42 PM PDT 24 | 28035275 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3090432672 | May 12 01:55:52 PM PDT 24 | May 12 01:55:53 PM PDT 24 | 26484248 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.635212106 | May 12 01:55:53 PM PDT 24 | May 12 01:55:53 PM PDT 24 | 26165586 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3912997013 | May 12 01:55:52 PM PDT 24 | May 12 01:55:53 PM PDT 24 | 29311069 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1037562284 | May 12 01:55:47 PM PDT 24 | May 12 01:55:48 PM PDT 24 | 27765696 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2158665832 | May 12 01:55:53 PM PDT 24 | May 12 01:55:53 PM PDT 24 | 26482611 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3086093743 | May 12 01:55:43 PM PDT 24 | May 12 01:55:44 PM PDT 24 | 27726051 ps |
| Test location | /workspace/coverage/default/9.prim_async_alert.477932137 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11896321 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:54:53 PM PDT 24 |
| Finished | May 12 01:54:53 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-9154cf9b-7c32-4e5b-afb4-6aae54b9c901 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=477932137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.477932137 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1282038046 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9488930 ps |
| CPU time | 0.44 seconds |
| Started | May 12 01:55:33 PM PDT 24 |
| Finished | May 12 01:55:34 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-2c037a85-51be-4306-8c5f-4b0684aef602 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1282038046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1282038046 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1356408713 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 30277582 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:28 PM PDT 24 |
| Finished | May 12 01:55:29 PM PDT 24 |
| Peak memory | 145700 kb |
| Host | smart-5039e53d-20f4-404a-b7b7-c71ee66ba78c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1356408713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1356408713 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3816495616 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10443200 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:07 PM PDT 24 |
| Finished | May 12 01:55:08 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-a58099a0-d541-44a9-87bb-8a614f871c09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3816495616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3816495616 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2458854633 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 28035275 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:41 PM PDT 24 |
| Finished | May 12 01:55:42 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-6f9223c9-cf6a-4ecb-ba2f-71e6af716fdc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2458854633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2458854633 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.1232703913 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11597450 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:54:43 PM PDT 24 |
| Finished | May 12 01:54:44 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-6c00c12d-8b37-4897-bad8-7f24a8a1e52c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1232703913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1232703913 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.203327752 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10760453 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:54:43 PM PDT 24 |
| Finished | May 12 01:54:43 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-b62110c5-2f3d-4193-961f-878848fbb2a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203327752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.203327752 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.170475763 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11383713 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:54:52 PM PDT 24 |
| Finished | May 12 01:54:53 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-6f2b9864-36fb-4a0e-a868-5cf398ca8798 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=170475763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.170475763 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.2211534344 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12452933 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:54:55 PM PDT 24 |
| Finished | May 12 01:54:56 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-d8c0d05d-c380-40b0-9af5-916fdc545325 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2211534344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2211534344 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.300219486 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10793995 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:54:55 PM PDT 24 |
| Finished | May 12 01:54:56 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-e46383fd-8c75-43e1-bbaf-215d554feed3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=300219486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.300219486 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1672914091 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12440713 ps |
| CPU time | 0.44 seconds |
| Started | May 12 01:54:59 PM PDT 24 |
| Finished | May 12 01:55:00 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-227fd101-903a-423d-9860-d327a2a1f7c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672914091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1672914091 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.3828656589 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11892396 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:54:55 PM PDT 24 |
| Finished | May 12 01:54:56 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-edb09220-621d-4b65-bd5c-a145111517f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828656589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3828656589 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3637576796 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10420435 ps |
| CPU time | 0.44 seconds |
| Started | May 12 01:54:58 PM PDT 24 |
| Finished | May 12 01:54:59 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-d22b3faa-6227-4b97-b376-d11909aa4566 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3637576796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3637576796 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.246528734 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11224572 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:01 PM PDT 24 |
| Finished | May 12 01:55:01 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-d052cd14-f08a-4bd0-bccf-9d9b2034441a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=246528734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.246528734 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1330082632 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11920951 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:04 PM PDT 24 |
| Finished | May 12 01:55:05 PM PDT 24 |
| Peak memory | 145892 kb |
| Host | smart-9e67cf7e-a5b0-441e-8a8b-970fb332c925 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330082632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1330082632 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.4245602233 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11867012 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:07 PM PDT 24 |
| Finished | May 12 01:55:08 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-92c81518-f48f-4115-b638-b65b2fc4c77c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4245602233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.4245602233 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.1441950184 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10937414 ps |
| CPU time | 0.41 seconds |
| Started | May 12 01:54:43 PM PDT 24 |
| Finished | May 12 01:54:44 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-32028b06-9c68-4be9-a95a-afe73065874f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441950184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1441950184 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.4082624045 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11430646 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:54:44 PM PDT 24 |
| Finished | May 12 01:54:45 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-d6d1790d-073f-4f49-bc97-3a717d11ee0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4082624045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.4082624045 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.3015088848 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11932829 ps |
| CPU time | 0.41 seconds |
| Started | May 12 01:54:46 PM PDT 24 |
| Finished | May 12 01:54:47 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-bfbf810e-af8d-4fae-820b-30b55a8579fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015088848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3015088848 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3215690981 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10857729 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:54:45 PM PDT 24 |
| Finished | May 12 01:54:45 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-ec23ae32-cdd7-455b-a36d-3917682a12d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215690981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3215690981 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.71010259 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 10504600 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:54:49 PM PDT 24 |
| Finished | May 12 01:54:49 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-2c69ceed-08e0-43cf-a008-4954879f30e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71010259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.71010259 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.1770051759 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11241463 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:54:49 PM PDT 24 |
| Finished | May 12 01:54:49 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-8c250998-54f0-483d-8c43-e3e3e391566d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770051759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1770051759 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.1903708061 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11167344 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:54:52 PM PDT 24 |
| Finished | May 12 01:54:53 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-404f431a-0d16-4722-aab0-01011151f21a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1903708061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1903708061 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2348176091 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 31048493 ps |
| CPU time | 0.41 seconds |
| Started | May 12 01:55:12 PM PDT 24 |
| Finished | May 12 01:55:12 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-a9aebc6e-bbe1-4488-9490-77c7a6aaa25d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2348176091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2348176091 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.824940606 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 31162816 ps |
| CPU time | 0.41 seconds |
| Started | May 12 01:55:17 PM PDT 24 |
| Finished | May 12 01:55:17 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-41514403-d5af-4704-a26c-4d113f58c01a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=824940606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.824940606 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3908102014 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 31531397 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:18 PM PDT 24 |
| Finished | May 12 01:55:19 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-2608af22-9112-4a62-8442-08f191d8b64a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3908102014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3908102014 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3813563136 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 27733324 ps |
| CPU time | 0.41 seconds |
| Started | May 12 01:55:21 PM PDT 24 |
| Finished | May 12 01:55:22 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-19274f17-ad6c-460b-a352-5701238f737c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3813563136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3813563136 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2588727243 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31135220 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:21 PM PDT 24 |
| Finished | May 12 01:55:22 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-d115fcb1-55d7-4a90-97f9-c125d7dce29b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2588727243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2588727243 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3818020769 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 32204749 ps |
| CPU time | 0.43 seconds |
| Started | May 12 01:55:25 PM PDT 24 |
| Finished | May 12 01:55:26 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-b404ae9c-39bb-4ddd-a95d-baeb727c2abb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3818020769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3818020769 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4081152299 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30066903 ps |
| CPU time | 0.41 seconds |
| Started | May 12 01:55:25 PM PDT 24 |
| Finished | May 12 01:55:25 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-64a56c70-b244-4d60-8d84-5ebb1fca28b5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4081152299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.4081152299 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.4217097369 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30380586 ps |
| CPU time | 0.43 seconds |
| Started | May 12 01:55:23 PM PDT 24 |
| Finished | May 12 01:55:24 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-2e9c2846-91d0-4a57-970d-d47a20516cd2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4217097369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.4217097369 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2534799650 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 29539285 ps |
| CPU time | 0.41 seconds |
| Started | May 12 01:55:25 PM PDT 24 |
| Finished | May 12 01:55:26 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-4f686875-7c31-49e2-b55b-9c5a50b22165 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2534799650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2534799650 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.232930638 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29647369 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:28 PM PDT 24 |
| Finished | May 12 01:55:29 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-4cee3da3-1266-417e-bf96-6c93cad9358e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=232930638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.232930638 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.511015687 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 31013061 ps |
| CPU time | 0.41 seconds |
| Started | May 12 01:55:15 PM PDT 24 |
| Finished | May 12 01:55:16 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-9f561d43-ee16-4934-8115-73dfea09ff48 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=511015687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.511015687 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2938358536 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 32592456 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:15 PM PDT 24 |
| Finished | May 12 01:55:16 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-f9405e42-5dbd-4f1b-b83d-03a421ae88d7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2938358536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2938358536 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.68891781 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29846865 ps |
| CPU time | 0.42 seconds |
| Started | May 12 01:55:15 PM PDT 24 |
| Finished | May 12 01:55:16 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-a1b1ed12-f1ca-4675-9b15-3abccaede23c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=68891781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.68891781 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2084913016 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 28744868 ps |
| CPU time | 0.44 seconds |
| Started | May 12 01:55:15 PM PDT 24 |
| Finished | May 12 01:55:16 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-85d1d568-21ee-4c4a-bb18-381a037bf6d9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2084913016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2084913016 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3479428074 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 32072234 ps |
| CPU time | 0.41 seconds |
| Started | May 12 01:55:16 PM PDT 24 |
| Finished | May 12 01:55:17 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-895199d8-803c-4f03-9738-110ac97d5805 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3479428074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3479428074 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.844260251 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 33040950 ps |
| CPU time | 0.41 seconds |
| Started | May 12 01:55:18 PM PDT 24 |
| Finished | May 12 01:55:18 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-eaf5f67c-37ff-430d-8efe-57d70044fe35 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=844260251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.844260251 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1946237177 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 29565867 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:17 PM PDT 24 |
| Finished | May 12 01:55:18 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-4f5a392a-512a-4069-91b9-ae89ce571757 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1946237177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1946237177 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1953172341 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 30779762 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:18 PM PDT 24 |
| Finished | May 12 01:55:19 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-90cf4631-d45d-46f9-8188-07f4f202b883 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1953172341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1953172341 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.2619173149 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9475626 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:55:28 PM PDT 24 |
| Finished | May 12 01:55:28 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-c0ded35b-8a8a-40f7-8d85-3dcc01347732 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2619173149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2619173149 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.4167701951 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9242830 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:28 PM PDT 24 |
| Finished | May 12 01:55:29 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-f709f7bd-b999-42ba-8b49-94eca3be844f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4167701951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.4167701951 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3277490110 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9473682 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:55:35 PM PDT 24 |
| Finished | May 12 01:55:35 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-6b0aa7be-5f7d-4865-803a-7a0c301f554b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3277490110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3277490110 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.3385052852 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 8856449 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:38 PM PDT 24 |
| Finished | May 12 01:55:39 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-caa79d3b-5f06-4246-922d-88cba9f634c2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3385052852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3385052852 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.4290818969 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 10861661 ps |
| CPU time | 0.41 seconds |
| Started | May 12 01:55:38 PM PDT 24 |
| Finished | May 12 01:55:39 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-c3e8473f-a85d-45bb-8a08-debfb2ce0d03 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4290818969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.4290818969 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.740399661 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9668213 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:39 PM PDT 24 |
| Finished | May 12 01:55:40 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-26e820bc-7e84-4e8c-aa6e-e25b674e117a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=740399661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.740399661 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.669245648 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8635000 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:40 PM PDT 24 |
| Finished | May 12 01:55:41 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-7d6ce135-d577-495c-a7c2-0c17126a479f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=669245648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.669245648 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.944228756 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 9318369 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:55:38 PM PDT 24 |
| Finished | May 12 01:55:39 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-1c33f439-3ebb-4b06-ba62-4607588966f2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=944228756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.944228756 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.1745637091 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9440869 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:55:38 PM PDT 24 |
| Finished | May 12 01:55:39 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-c8a548a9-6b03-4916-9aa5-62ef4b5d07fb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1745637091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1745637091 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.647644103 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8365072 ps |
| CPU time | 0.37 seconds |
| Started | May 12 01:55:39 PM PDT 24 |
| Finished | May 12 01:55:39 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-8bda19b4-2bb8-4cf0-b4ff-e39e1b06ffe2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=647644103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.647644103 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.3739224922 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9515558 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:55:42 PM PDT 24 |
| Finished | May 12 01:55:42 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-72ded174-a5ab-4ac5-b692-d1fe390417d8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3739224922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3739224922 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.2761480417 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 10813590 ps |
| CPU time | 0.43 seconds |
| Started | May 12 01:55:41 PM PDT 24 |
| Finished | May 12 01:55:42 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-f4e7e34f-d934-4538-9a54-e5c12dd2c66c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2761480417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2761480417 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.757956398 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9619863 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:55:29 PM PDT 24 |
| Finished | May 12 01:55:29 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-ff9354a8-cfbb-44c7-aa5c-021d6551072e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=757956398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.757956398 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3674922623 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9142308 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:30 PM PDT 24 |
| Finished | May 12 01:55:31 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-3b5c1ce0-8ed7-4b53-bd54-a62e36096ad2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3674922623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3674922623 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.2305710386 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9586973 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:30 PM PDT 24 |
| Finished | May 12 01:55:31 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-8a71b276-1ed0-44f2-8c2e-332541a993ce |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2305710386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2305710386 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.251449182 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 9468067 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:30 PM PDT 24 |
| Finished | May 12 01:55:31 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-57e08732-9ac4-4088-895b-28b04eaed80f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=251449182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.251449182 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1563086894 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9374757 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:31 PM PDT 24 |
| Finished | May 12 01:55:31 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-0bebf0ab-adc6-4c51-956b-08771a1a3ca8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1563086894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1563086894 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.4016660183 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 9408994 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:55:32 PM PDT 24 |
| Finished | May 12 01:55:32 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-b056d83d-dc80-4cd5-bdab-e1c250a59c08 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4016660183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.4016660183 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1203445946 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9012900 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:55:31 PM PDT 24 |
| Finished | May 12 01:55:32 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-27d9356a-520b-462b-a17e-43356bff4dff |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1203445946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1203445946 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2858866167 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 27691616 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:45 PM PDT 24 |
| Finished | May 12 01:55:45 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-f725b59f-bb28-4515-be74-ebac656c02d0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2858866167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2858866167 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2836863783 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 26973476 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:48 PM PDT 24 |
| Finished | May 12 01:55:49 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-31241f4f-044f-461b-a9f3-c9867f465fd7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2836863783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2836863783 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1037562284 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27765696 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:47 PM PDT 24 |
| Finished | May 12 01:55:48 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-702195d8-a13f-4182-9a90-6f53bfc5e574 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1037562284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1037562284 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1990181507 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27643067 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:50 PM PDT 24 |
| Finished | May 12 01:55:50 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-634a6e1a-ba20-4a9e-bf69-a911183e1f70 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1990181507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1990181507 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3595017002 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 30633398 ps |
| CPU time | 0.45 seconds |
| Started | May 12 01:55:48 PM PDT 24 |
| Finished | May 12 01:55:49 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-dbcb1982-6325-44a1-8e90-68340dcc6795 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3595017002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3595017002 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2259008149 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28156597 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:48 PM PDT 24 |
| Finished | May 12 01:55:49 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-fb745d2b-fadf-4466-8a16-0c523b13cefc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2259008149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2259008149 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3803598569 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 29093392 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:53 PM PDT 24 |
| Finished | May 12 01:55:53 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-66091c83-687f-4bcf-8fd3-f3fa270e32d8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3803598569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3803598569 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3140436439 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26393813 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:51 PM PDT 24 |
| Finished | May 12 01:55:51 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-5e1953dc-3825-4357-adae-64b35a21ec22 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3140436439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3140436439 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2547713320 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26696830 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:51 PM PDT 24 |
| Finished | May 12 01:55:52 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-cf01cc5c-d638-4cb1-9b8a-3033a612f8f6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2547713320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2547713320 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3090432672 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26484248 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:52 PM PDT 24 |
| Finished | May 12 01:55:53 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-eddd0ffa-8c8d-4f81-ae90-fd96d54c505b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3090432672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3090432672 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3912997013 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 29311069 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:52 PM PDT 24 |
| Finished | May 12 01:55:53 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-792ec0d5-5d42-4601-b0f9-2f65836b590e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3912997013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3912997013 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3086093743 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 27726051 ps |
| CPU time | 0.44 seconds |
| Started | May 12 01:55:43 PM PDT 24 |
| Finished | May 12 01:55:44 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-026d5753-aa00-448b-8ed5-46722c5f3023 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3086093743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3086093743 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2422585744 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28672930 ps |
| CPU time | 0.41 seconds |
| Started | May 12 01:55:44 PM PDT 24 |
| Finished | May 12 01:55:45 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-b808a87a-5c67-4b96-a92a-71c7a1c6195c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2422585744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2422585744 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2097182828 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 25852999 ps |
| CPU time | 0.4 seconds |
| Started | May 12 01:55:45 PM PDT 24 |
| Finished | May 12 01:55:46 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-c96fd4de-58e7-4850-9b83-b79a0e29bea3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2097182828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2097182828 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.146697098 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 28674173 ps |
| CPU time | 0.38 seconds |
| Started | May 12 01:55:48 PM PDT 24 |
| Finished | May 12 01:55:49 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-77f28fe5-7b0d-4e98-8d61-93c1a0e3879f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=146697098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.146697098 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.30542933 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 26910919 ps |
| CPU time | 0.42 seconds |
| Started | May 12 01:55:48 PM PDT 24 |
| Finished | May 12 01:55:49 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-850d3e94-5029-421e-a7ae-36c4d10a0a9d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=30542933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.30542933 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2158665832 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26482611 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:53 PM PDT 24 |
| Finished | May 12 01:55:53 PM PDT 24 |
| Peak memory | 145448 kb |
| Host | smart-7f4a34c3-8da6-4e40-a179-0466ecc069dc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2158665832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2158665832 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1325872047 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27318855 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:48 PM PDT 24 |
| Finished | May 12 01:55:49 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-5840bd56-a7d6-49b0-9e97-9caf11c18375 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1325872047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1325872047 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.635212106 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 26165586 ps |
| CPU time | 0.39 seconds |
| Started | May 12 01:55:53 PM PDT 24 |
| Finished | May 12 01:55:53 PM PDT 24 |
| Peak memory | 145480 kb |
| Host | smart-87985c0c-ca39-48e0-81fa-0ad08f34c890 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=635212106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.635212106 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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