| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.67 | 88.67 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 75.00 | 75.00 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/12.prim_async_alert.1606430070 |
| 92.39 | 3.72 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/14.prim_sync_alert.22765091 |
| 94.25 | 1.86 | 100.00 | 0.00 | 97.92 | 4.17 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3356813731 |
| 94.85 | 0.60 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/7.prim_async_alert.2531343722 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/12.prim_sync_alert.2667212680 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.3536436808 |
| /workspace/coverage/default/1.prim_async_alert.1654391807 |
| /workspace/coverage/default/10.prim_async_alert.3003105494 |
| /workspace/coverage/default/11.prim_async_alert.4026745612 |
| /workspace/coverage/default/13.prim_async_alert.3237970164 |
| /workspace/coverage/default/14.prim_async_alert.1370717442 |
| /workspace/coverage/default/15.prim_async_alert.1057662788 |
| /workspace/coverage/default/16.prim_async_alert.1893178924 |
| /workspace/coverage/default/17.prim_async_alert.1964499065 |
| /workspace/coverage/default/18.prim_async_alert.2533648751 |
| /workspace/coverage/default/19.prim_async_alert.710228395 |
| /workspace/coverage/default/2.prim_async_alert.3101981693 |
| /workspace/coverage/default/3.prim_async_alert.1151876674 |
| /workspace/coverage/default/4.prim_async_alert.816177345 |
| /workspace/coverage/default/5.prim_async_alert.3446424443 |
| /workspace/coverage/default/6.prim_async_alert.1185872743 |
| /workspace/coverage/default/8.prim_async_alert.1221249403 |
| /workspace/coverage/default/9.prim_async_alert.414140225 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1765899035 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1821349103 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.930735119 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.4038730289 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4246798789 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3191704786 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1362108610 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1451448239 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1040519561 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2765630218 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4269299418 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1270700933 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.217404212 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.515680138 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.670655152 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1325981803 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3627521752 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.271705622 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.4134657717 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.844028463 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3148921445 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1057621951 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1397000573 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.729390736 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.3043074927 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.3812282721 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.86610598 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.2373170140 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.875837715 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.608480148 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.2688821762 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.1159409372 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.3496246172 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.3270281251 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.1630444573 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1638635747 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2320330218 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1024067717 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2647782746 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.151252528 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3778279261 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4260907905 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1606577249 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1606305908 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1422382034 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1018286404 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4240569503 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3779118704 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3082179739 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2217629708 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.585793684 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2925613543 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3279976242 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.462088828 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1062212393 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3827238839 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/17.prim_async_alert.1964499065 | May 14 01:40:55 PM PDT 24 | May 14 01:40:57 PM PDT 24 | 11314339 ps | ||
| T2 | /workspace/coverage/default/0.prim_async_alert.3536436808 | May 14 01:40:42 PM PDT 24 | May 14 01:40:44 PM PDT 24 | 10532290 ps | ||
| T3 | /workspace/coverage/default/7.prim_async_alert.2531343722 | May 14 01:40:46 PM PDT 24 | May 14 01:40:47 PM PDT 24 | 11124265 ps | ||
| T13 | /workspace/coverage/default/8.prim_async_alert.1221249403 | May 14 01:40:45 PM PDT 24 | May 14 01:40:47 PM PDT 24 | 11238425 ps | ||
| T7 | /workspace/coverage/default/10.prim_async_alert.3003105494 | May 14 01:40:43 PM PDT 24 | May 14 01:40:45 PM PDT 24 | 11291665 ps | ||
| T21 | /workspace/coverage/default/11.prim_async_alert.4026745612 | May 14 01:40:45 PM PDT 24 | May 14 01:40:47 PM PDT 24 | 11730072 ps | ||
| T12 | /workspace/coverage/default/1.prim_async_alert.1654391807 | May 14 01:40:45 PM PDT 24 | May 14 01:40:47 PM PDT 24 | 12204729 ps | ||
| T8 | /workspace/coverage/default/12.prim_async_alert.1606430070 | May 14 01:40:43 PM PDT 24 | May 14 01:40:45 PM PDT 24 | 12118820 ps | ||
| T22 | /workspace/coverage/default/4.prim_async_alert.816177345 | May 14 01:40:44 PM PDT 24 | May 14 01:40:46 PM PDT 24 | 11114129 ps | ||
| T16 | /workspace/coverage/default/9.prim_async_alert.414140225 | May 14 01:40:44 PM PDT 24 | May 14 01:40:46 PM PDT 24 | 11207817 ps | ||
| T17 | /workspace/coverage/default/6.prim_async_alert.1185872743 | May 14 01:40:44 PM PDT 24 | May 14 01:40:46 PM PDT 24 | 11506907 ps | ||
| T23 | /workspace/coverage/default/18.prim_async_alert.2533648751 | May 14 01:40:53 PM PDT 24 | May 14 01:40:54 PM PDT 24 | 11230477 ps | ||
| T9 | /workspace/coverage/default/15.prim_async_alert.1057662788 | May 14 01:40:43 PM PDT 24 | May 14 01:40:45 PM PDT 24 | 11077569 ps | ||
| T24 | /workspace/coverage/default/19.prim_async_alert.710228395 | May 14 01:40:53 PM PDT 24 | May 14 01:40:55 PM PDT 24 | 12852807 ps | ||
| T46 | /workspace/coverage/default/2.prim_async_alert.3101981693 | May 14 01:40:45 PM PDT 24 | May 14 01:40:47 PM PDT 24 | 11297806 ps | ||
| T47 | /workspace/coverage/default/3.prim_async_alert.1151876674 | May 14 01:40:43 PM PDT 24 | May 14 01:40:45 PM PDT 24 | 10571869 ps | ||
| T48 | /workspace/coverage/default/5.prim_async_alert.3446424443 | May 14 01:40:44 PM PDT 24 | May 14 01:40:46 PM PDT 24 | 11232561 ps | ||
| T19 | /workspace/coverage/default/13.prim_async_alert.3237970164 | May 14 01:40:48 PM PDT 24 | May 14 01:40:49 PM PDT 24 | 10119750 ps | ||
| T49 | /workspace/coverage/default/16.prim_async_alert.1893178924 | May 14 01:40:53 PM PDT 24 | May 14 01:40:55 PM PDT 24 | 11037280 ps | ||
| T25 | /workspace/coverage/default/14.prim_async_alert.1370717442 | May 14 01:40:44 PM PDT 24 | May 14 01:40:46 PM PDT 24 | 11406891 ps | ||
| T14 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.670655152 | May 14 01:17:17 PM PDT 24 | May 14 01:17:19 PM PDT 24 | 29706438 ps | ||
| T40 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1040519561 | May 14 01:17:22 PM PDT 24 | May 14 01:17:26 PM PDT 24 | 28327048 ps | ||
| T26 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2765630218 | May 14 01:17:19 PM PDT 24 | May 14 01:17:21 PM PDT 24 | 30421201 ps | ||
| T41 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1362108610 | May 14 01:17:20 PM PDT 24 | May 14 01:17:23 PM PDT 24 | 30485224 ps | ||
| T42 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.515680138 | May 14 01:17:20 PM PDT 24 | May 14 01:17:23 PM PDT 24 | 28868419 ps | ||
| T4 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3356813731 | May 14 01:17:20 PM PDT 24 | May 14 01:17:23 PM PDT 24 | 29623504 ps | ||
| T43 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3627521752 | May 14 01:17:21 PM PDT 24 | May 14 01:17:24 PM PDT 24 | 31352097 ps | ||
| T44 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4269299418 | May 14 01:17:25 PM PDT 24 | May 14 01:17:30 PM PDT 24 | 32031156 ps | ||
| T15 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.217404212 | May 14 01:17:17 PM PDT 24 | May 14 01:17:19 PM PDT 24 | 32987684 ps | ||
| T45 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1451448239 | May 14 01:17:24 PM PDT 24 | May 14 01:17:29 PM PDT 24 | 27553581 ps | ||
| T50 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1765899035 | May 14 01:17:24 PM PDT 24 | May 14 01:17:29 PM PDT 24 | 29227700 ps | ||
| T51 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.930735119 | May 14 01:17:23 PM PDT 24 | May 14 01:17:27 PM PDT 24 | 30911341 ps | ||
| T52 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1325981803 | May 14 01:17:18 PM PDT 24 | May 14 01:17:20 PM PDT 24 | 29685691 ps | ||
| T18 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1270700933 | May 14 01:17:21 PM PDT 24 | May 14 01:17:24 PM PDT 24 | 29241534 ps | ||
| T20 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3191704786 | May 14 01:17:23 PM PDT 24 | May 14 01:17:27 PM PDT 24 | 28552753 ps | ||
| T53 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.271705622 | May 14 01:17:24 PM PDT 24 | May 14 01:17:29 PM PDT 24 | 33219900 ps | ||
| T54 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1821349103 | May 14 01:17:23 PM PDT 24 | May 14 01:17:27 PM PDT 24 | 29538264 ps | ||
| T55 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.4038730289 | May 14 01:17:16 PM PDT 24 | May 14 01:17:18 PM PDT 24 | 29318414 ps | ||
| T56 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4246798789 | May 14 01:17:24 PM PDT 24 | May 14 01:17:29 PM PDT 24 | 29589184 ps | ||
| T35 | /workspace/coverage/sync_alert/8.prim_sync_alert.1630444573 | May 14 01:17:20 PM PDT 24 | May 14 01:17:22 PM PDT 24 | 9319605 ps | ||
| T27 | /workspace/coverage/sync_alert/14.prim_sync_alert.22765091 | May 14 01:17:26 PM PDT 24 | May 14 01:17:30 PM PDT 24 | 9517041 ps | ||
| T10 | /workspace/coverage/sync_alert/12.prim_sync_alert.2667212680 | May 14 01:17:23 PM PDT 24 | May 14 01:17:28 PM PDT 24 | 8421656 ps | ||
| T28 | /workspace/coverage/sync_alert/17.prim_sync_alert.3812282721 | May 14 01:17:40 PM PDT 24 | May 14 01:17:42 PM PDT 24 | 9537532 ps | ||
| T36 | /workspace/coverage/sync_alert/18.prim_sync_alert.86610598 | May 14 01:17:39 PM PDT 24 | May 14 01:17:41 PM PDT 24 | 9013056 ps | ||
| T37 | /workspace/coverage/sync_alert/3.prim_sync_alert.608480148 | May 14 01:17:24 PM PDT 24 | May 14 01:17:28 PM PDT 24 | 9852543 ps | ||
| T38 | /workspace/coverage/sync_alert/11.prim_sync_alert.1057621951 | May 14 01:17:23 PM PDT 24 | May 14 01:17:28 PM PDT 24 | 9176899 ps | ||
| T29 | /workspace/coverage/sync_alert/7.prim_sync_alert.3270281251 | May 14 01:17:21 PM PDT 24 | May 14 01:17:25 PM PDT 24 | 10063843 ps | ||
| T30 | /workspace/coverage/sync_alert/19.prim_sync_alert.2373170140 | May 14 01:17:38 PM PDT 24 | May 14 01:17:40 PM PDT 24 | 9598028 ps | ||
| T39 | /workspace/coverage/sync_alert/16.prim_sync_alert.3043074927 | May 14 01:17:20 PM PDT 24 | May 14 01:17:23 PM PDT 24 | 9938007 ps | ||
| T57 | /workspace/coverage/sync_alert/5.prim_sync_alert.1159409372 | May 14 01:17:20 PM PDT 24 | May 14 01:17:22 PM PDT 24 | 8994622 ps | ||
| T58 | /workspace/coverage/sync_alert/6.prim_sync_alert.3496246172 | May 14 01:17:21 PM PDT 24 | May 14 01:17:24 PM PDT 24 | 8710902 ps | ||
| T31 | /workspace/coverage/sync_alert/10.prim_sync_alert.3148921445 | May 14 01:17:23 PM PDT 24 | May 14 01:17:27 PM PDT 24 | 8875852 ps | ||
| T32 | /workspace/coverage/sync_alert/15.prim_sync_alert.729390736 | May 14 01:17:25 PM PDT 24 | May 14 01:17:30 PM PDT 24 | 8032084 ps | ||
| T59 | /workspace/coverage/sync_alert/13.prim_sync_alert.1397000573 | May 14 01:17:26 PM PDT 24 | May 14 01:17:30 PM PDT 24 | 8999707 ps | ||
| T60 | /workspace/coverage/sync_alert/9.prim_sync_alert.1638635747 | May 14 01:17:27 PM PDT 24 | May 14 01:17:31 PM PDT 24 | 9579136 ps | ||
| T33 | /workspace/coverage/sync_alert/0.prim_sync_alert.4134657717 | May 14 01:17:23 PM PDT 24 | May 14 01:17:28 PM PDT 24 | 8470757 ps | ||
| T61 | /workspace/coverage/sync_alert/2.prim_sync_alert.875837715 | May 14 01:17:23 PM PDT 24 | May 14 01:17:28 PM PDT 24 | 9095669 ps | ||
| T62 | /workspace/coverage/sync_alert/4.prim_sync_alert.2688821762 | May 14 01:17:21 PM PDT 24 | May 14 01:17:25 PM PDT 24 | 9740686 ps | ||
| T63 | /workspace/coverage/sync_alert/1.prim_sync_alert.844028463 | May 14 01:17:23 PM PDT 24 | May 14 01:17:28 PM PDT 24 | 9406318 ps | ||
| T34 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1422382034 | May 14 01:56:59 PM PDT 24 | May 14 01:57:01 PM PDT 24 | 25676431 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.585793684 | May 14 01:56:54 PM PDT 24 | May 14 01:56:55 PM PDT 24 | 26597650 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1024067717 | May 14 01:56:55 PM PDT 24 | May 14 01:56:56 PM PDT 24 | 27847747 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2217629708 | May 14 01:56:52 PM PDT 24 | May 14 01:56:54 PM PDT 24 | 28677222 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.151252528 | May 14 01:57:01 PM PDT 24 | May 14 01:57:02 PM PDT 24 | 25440969 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3778279261 | May 14 01:57:01 PM PDT 24 | May 14 01:57:03 PM PDT 24 | 28798253 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3082179739 | May 14 01:56:53 PM PDT 24 | May 14 01:56:54 PM PDT 24 | 27352523 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2647782746 | May 14 01:57:02 PM PDT 24 | May 14 01:57:03 PM PDT 24 | 27906788 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2925613543 | May 14 01:56:55 PM PDT 24 | May 14 01:56:56 PM PDT 24 | 26215263 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4240569503 | May 14 01:57:08 PM PDT 24 | May 14 01:57:10 PM PDT 24 | 28229935 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1062212393 | May 14 01:56:53 PM PDT 24 | May 14 01:56:55 PM PDT 24 | 30544132 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1606577249 | May 14 01:57:01 PM PDT 24 | May 14 01:57:02 PM PDT 24 | 28309937 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1018286404 | May 14 01:57:10 PM PDT 24 | May 14 01:57:11 PM PDT 24 | 28699781 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4260907905 | May 14 01:57:03 PM PDT 24 | May 14 01:57:04 PM PDT 24 | 27424630 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.462088828 | May 14 01:56:54 PM PDT 24 | May 14 01:56:55 PM PDT 24 | 28203318 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3779118704 | May 14 01:57:08 PM PDT 24 | May 14 01:57:09 PM PDT 24 | 26410705 ps | ||
| T11 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2320330218 | May 14 01:56:55 PM PDT 24 | May 14 01:56:56 PM PDT 24 | 26574699 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1606305908 | May 14 01:57:02 PM PDT 24 | May 14 01:57:03 PM PDT 24 | 26488380 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3827238839 | May 14 01:56:56 PM PDT 24 | May 14 01:56:57 PM PDT 24 | 26634444 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3279976242 | May 14 01:56:52 PM PDT 24 | May 14 01:56:53 PM PDT 24 | 27212233 ps |
| Test location | /workspace/coverage/default/12.prim_async_alert.1606430070 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12118820 ps |
| CPU time | 0.43 seconds |
| Started | May 14 01:40:43 PM PDT 24 |
| Finished | May 14 01:40:45 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-12228d0f-f6f4-4688-a8d0-6c2e710e5ca6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606430070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1606430070 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.22765091 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9517041 ps |
| CPU time | 0.44 seconds |
| Started | May 14 01:17:26 PM PDT 24 |
| Finished | May 14 01:17:30 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-e777d0e1-4c6a-4133-82b5-747319a9992b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=22765091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.22765091 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3356813731 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 29623504 ps |
| CPU time | 0.42 seconds |
| Started | May 14 01:17:20 PM PDT 24 |
| Finished | May 14 01:17:23 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-4afcb479-53c9-43c7-8882-22d04646ca33 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3356813731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3356813731 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.2531343722 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11124265 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:40:46 PM PDT 24 |
| Finished | May 14 01:40:47 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-bc8ebb09-f6a6-42f8-a74e-623d47223484 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2531343722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2531343722 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.2667212680 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8421656 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:17:28 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-2a5e9411-9fe4-492e-9696-6ef908470705 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2667212680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2667212680 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.3536436808 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10532290 ps |
| CPU time | 0.42 seconds |
| Started | May 14 01:40:42 PM PDT 24 |
| Finished | May 14 01:40:44 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-4c2856e3-6c31-4d7b-9c6d-da9d58cb43e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3536436808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3536436808 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1654391807 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12204729 ps |
| CPU time | 0.41 seconds |
| Started | May 14 01:40:45 PM PDT 24 |
| Finished | May 14 01:40:47 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-7fdce32b-18f1-4369-9d0e-d8fd20cea495 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654391807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1654391807 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.3003105494 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11291665 ps |
| CPU time | 0.38 seconds |
| Started | May 14 01:40:43 PM PDT 24 |
| Finished | May 14 01:40:45 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-91e2e29f-2e3d-4094-9f92-99bae8772a00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003105494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3003105494 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.4026745612 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11730072 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:40:45 PM PDT 24 |
| Finished | May 14 01:40:47 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-be974da0-0eed-458c-b72c-e76ea8cf3c04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026745612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4026745612 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3237970164 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10119750 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:40:48 PM PDT 24 |
| Finished | May 14 01:40:49 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-cb843af8-4ef4-47b3-99d8-5255ef41e393 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3237970164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3237970164 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1370717442 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11406891 ps |
| CPU time | 0.38 seconds |
| Started | May 14 01:40:44 PM PDT 24 |
| Finished | May 14 01:40:46 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-94d17323-9d50-48e5-b276-6c28fd044fb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370717442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1370717442 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1057662788 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11077569 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:40:43 PM PDT 24 |
| Finished | May 14 01:40:45 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-f9c3dc05-f39d-4db8-97c3-15c51b77b47a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057662788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1057662788 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.1893178924 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11037280 ps |
| CPU time | 0.42 seconds |
| Started | May 14 01:40:53 PM PDT 24 |
| Finished | May 14 01:40:55 PM PDT 24 |
| Peak memory | 145876 kb |
| Host | smart-8428d660-b35e-43de-ba43-4aebe0342320 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1893178924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1893178924 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1964499065 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11314339 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:40:55 PM PDT 24 |
| Finished | May 14 01:40:57 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-ee246d9c-7699-4a30-91d6-cb052e72fdc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964499065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1964499065 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.2533648751 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11230477 ps |
| CPU time | 0.38 seconds |
| Started | May 14 01:40:53 PM PDT 24 |
| Finished | May 14 01:40:54 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-17d0c23f-0813-4a37-911c-cbb6700c46d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533648751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2533648751 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.710228395 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12852807 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:40:53 PM PDT 24 |
| Finished | May 14 01:40:55 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-f7c448f3-6393-4f7f-968e-b170c8f7dcf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710228395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.710228395 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3101981693 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11297806 ps |
| CPU time | 0.44 seconds |
| Started | May 14 01:40:45 PM PDT 24 |
| Finished | May 14 01:40:47 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-380860d9-1a76-41fc-8984-b018e818e33a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101981693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3101981693 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.1151876674 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10571869 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:40:43 PM PDT 24 |
| Finished | May 14 01:40:45 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-10c3b150-9998-45d3-abef-452eed634bbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1151876674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1151876674 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.816177345 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11114129 ps |
| CPU time | 0.38 seconds |
| Started | May 14 01:40:44 PM PDT 24 |
| Finished | May 14 01:40:46 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-3228dd89-03c2-4897-a51d-c55366862532 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=816177345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.816177345 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3446424443 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11232561 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:40:44 PM PDT 24 |
| Finished | May 14 01:40:46 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-f55fbf38-001b-460c-9850-7f6519662713 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446424443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3446424443 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.1185872743 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11506907 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:40:44 PM PDT 24 |
| Finished | May 14 01:40:46 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-b3648df4-791f-4c1b-9d8e-ef72478637a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185872743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1185872743 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.1221249403 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11238425 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:40:45 PM PDT 24 |
| Finished | May 14 01:40:47 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-6454ab95-3b74-4d3d-86f5-ee7e14cf5f9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221249403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1221249403 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.414140225 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11207817 ps |
| CPU time | 0.38 seconds |
| Started | May 14 01:40:44 PM PDT 24 |
| Finished | May 14 01:40:46 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-a9c43e11-ef9f-42c9-b466-89511d803483 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414140225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.414140225 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1765899035 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 29227700 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:17:24 PM PDT 24 |
| Finished | May 14 01:17:29 PM PDT 24 |
| Peak memory | 145692 kb |
| Host | smart-6004a080-a30d-408f-b361-19e8405c6579 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1765899035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1765899035 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1821349103 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 29538264 ps |
| CPU time | 0.41 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:17:27 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-8f43c252-7dc5-4093-8041-9548b7696f39 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1821349103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1821349103 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.930735119 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30911341 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:17:27 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-442ab878-b06c-42e1-8cb1-291237a42059 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=930735119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.930735119 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.4038730289 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29318414 ps |
| CPU time | 0.44 seconds |
| Started | May 14 01:17:16 PM PDT 24 |
| Finished | May 14 01:17:18 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-321577ac-d511-4105-855a-72a68965fad9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4038730289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.4038730289 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4246798789 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 29589184 ps |
| CPU time | 0.43 seconds |
| Started | May 14 01:17:24 PM PDT 24 |
| Finished | May 14 01:17:29 PM PDT 24 |
| Peak memory | 145748 kb |
| Host | smart-140337f5-5bc3-4a51-8a0a-f02df480d1c6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4246798789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.4246798789 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3191704786 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 28552753 ps |
| CPU time | 0.41 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:17:27 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-fe79b8d2-51b5-4a23-901a-29a52e1d31fa |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3191704786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3191704786 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1362108610 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30485224 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:17:20 PM PDT 24 |
| Finished | May 14 01:17:23 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-bba942d7-3e84-437e-becc-5b8d72f52058 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1362108610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1362108610 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1451448239 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 27553581 ps |
| CPU time | 0.44 seconds |
| Started | May 14 01:17:24 PM PDT 24 |
| Finished | May 14 01:17:29 PM PDT 24 |
| Peak memory | 145748 kb |
| Host | smart-edf95a97-fa39-40c9-9d92-60f01ff8dc85 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1451448239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1451448239 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1040519561 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 28327048 ps |
| CPU time | 0.42 seconds |
| Started | May 14 01:17:22 PM PDT 24 |
| Finished | May 14 01:17:26 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-86ad5c1a-53fa-4364-bc7e-1496747c9129 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1040519561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1040519561 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2765630218 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 30421201 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:17:19 PM PDT 24 |
| Finished | May 14 01:17:21 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-c35212fa-b620-4b47-8c56-e02fe3744609 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2765630218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2765630218 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4269299418 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 32031156 ps |
| CPU time | 0.46 seconds |
| Started | May 14 01:17:25 PM PDT 24 |
| Finished | May 14 01:17:30 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-ebf5f61e-f7ac-4fcb-be3d-3bad7a18f60d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4269299418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.4269299418 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1270700933 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 29241534 ps |
| CPU time | 0.41 seconds |
| Started | May 14 01:17:21 PM PDT 24 |
| Finished | May 14 01:17:24 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-f5d17df4-3efa-4c12-b135-37f2b44ec928 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1270700933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1270700933 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.217404212 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 32987684 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:17:17 PM PDT 24 |
| Finished | May 14 01:17:19 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-5560b1a4-bceb-443f-8a39-ee3358a99672 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=217404212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.217404212 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.515680138 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 28868419 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:17:20 PM PDT 24 |
| Finished | May 14 01:17:23 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-4cd123be-f072-43bf-af3d-cb4e1eff3c29 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=515680138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.515680138 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.670655152 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 29706438 ps |
| CPU time | 0.41 seconds |
| Started | May 14 01:17:17 PM PDT 24 |
| Finished | May 14 01:17:19 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-bb143d01-8a56-4ca6-bf62-9de5af8a80b3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=670655152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.670655152 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1325981803 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 29685691 ps |
| CPU time | 0.41 seconds |
| Started | May 14 01:17:18 PM PDT 24 |
| Finished | May 14 01:17:20 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-71eca895-9917-4847-a3d4-6bf9a18a0499 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1325981803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1325981803 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3627521752 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31352097 ps |
| CPU time | 0.44 seconds |
| Started | May 14 01:17:21 PM PDT 24 |
| Finished | May 14 01:17:24 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-cbf0122a-89de-4ef8-9b55-23bc263e082e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3627521752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3627521752 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.271705622 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 33219900 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:17:24 PM PDT 24 |
| Finished | May 14 01:17:29 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-37b00536-0c00-47b6-9302-0413ef1961fb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=271705622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.271705622 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.4134657717 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8470757 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:17:28 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-7a029d41-816c-4e1d-b058-5360ef1228b5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4134657717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4134657717 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.844028463 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 9406318 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:17:28 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-c0ebfd39-d76a-4ed9-b116-4bf622f89d9e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=844028463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.844028463 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3148921445 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8875852 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:17:27 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-fb630ae4-3789-40aa-a00b-c5f58d7febcf |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3148921445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3148921445 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1057621951 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9176899 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:17:28 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-1b2f71da-3a4c-4a0e-a73b-72c4e27fe8d6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1057621951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1057621951 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1397000573 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8999707 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:17:26 PM PDT 24 |
| Finished | May 14 01:17:30 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-61693346-359f-45df-90dc-8b3b6fe0bdcb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1397000573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1397000573 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.729390736 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8032084 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:17:25 PM PDT 24 |
| Finished | May 14 01:17:30 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-8cfeb4d5-0cd8-4326-86ff-62cc2230d9f8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=729390736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.729390736 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.3043074927 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9938007 ps |
| CPU time | 0.37 seconds |
| Started | May 14 01:17:20 PM PDT 24 |
| Finished | May 14 01:17:23 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-75851897-b30b-4a60-b8e4-5423dd42e81f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3043074927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3043074927 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.3812282721 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9537532 ps |
| CPU time | 0.38 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:17:42 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-4a9b8538-4a80-46e2-9b77-2353997fde5e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3812282721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3812282721 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.86610598 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9013056 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:17:39 PM PDT 24 |
| Finished | May 14 01:17:41 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-e8d68429-846a-497a-9263-f280e5791326 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=86610598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.86610598 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.2373170140 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9598028 ps |
| CPU time | 0.38 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:17:40 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-8667a0a3-2fd5-4192-a207-65127508e118 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2373170140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2373170140 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.875837715 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9095669 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:17:28 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-79154f14-aa3e-4046-92e6-1a22fd488995 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=875837715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.875837715 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.608480148 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9852543 ps |
| CPU time | 0.46 seconds |
| Started | May 14 01:17:24 PM PDT 24 |
| Finished | May 14 01:17:28 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-9671b9e4-a245-496a-99ac-07919f81f926 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=608480148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.608480148 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.2688821762 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 9740686 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:17:21 PM PDT 24 |
| Finished | May 14 01:17:25 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-8a4fa0b6-66cc-4f50-808b-0f3b3f8c3eb6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2688821762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2688821762 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1159409372 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8994622 ps |
| CPU time | 0.38 seconds |
| Started | May 14 01:17:20 PM PDT 24 |
| Finished | May 14 01:17:22 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-09f745e3-35f0-47c3-93d4-68dd3ba19a89 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1159409372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1159409372 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.3496246172 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8710902 ps |
| CPU time | 0.38 seconds |
| Started | May 14 01:17:21 PM PDT 24 |
| Finished | May 14 01:17:24 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-b1568a8c-5b44-4bfc-b9e6-a07c81e46702 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3496246172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3496246172 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.3270281251 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10063843 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:17:21 PM PDT 24 |
| Finished | May 14 01:17:25 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-d92bfd86-7ac9-49f7-865b-7220da53c39b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3270281251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3270281251 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1630444573 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9319605 ps |
| CPU time | 0.38 seconds |
| Started | May 14 01:17:20 PM PDT 24 |
| Finished | May 14 01:17:22 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-e1d23b62-7893-402b-b52d-c9e327633487 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1630444573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1630444573 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1638635747 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9579136 ps |
| CPU time | 0.41 seconds |
| Started | May 14 01:17:27 PM PDT 24 |
| Finished | May 14 01:17:31 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-0132e553-db91-4d53-b965-978d12cc1f25 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1638635747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1638635747 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2320330218 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 26574699 ps |
| CPU time | 0.41 seconds |
| Started | May 14 01:56:55 PM PDT 24 |
| Finished | May 14 01:56:56 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-0e1a83f0-b0f3-4d08-a175-3445a136574b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2320330218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2320330218 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1024067717 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27847747 ps |
| CPU time | 0.46 seconds |
| Started | May 14 01:56:55 PM PDT 24 |
| Finished | May 14 01:56:56 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-4ecc8442-4521-4c8e-a51a-4ccd9833b904 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1024067717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1024067717 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2647782746 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27906788 ps |
| CPU time | 0.38 seconds |
| Started | May 14 01:57:02 PM PDT 24 |
| Finished | May 14 01:57:03 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-936ca644-9b28-452d-a25a-d151c109e871 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2647782746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2647782746 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.151252528 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 25440969 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:57:01 PM PDT 24 |
| Finished | May 14 01:57:02 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-94746d56-a121-4b9a-bece-b22639519247 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=151252528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.151252528 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3778279261 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28798253 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:57:01 PM PDT 24 |
| Finished | May 14 01:57:03 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-0c288f50-0538-485a-88a5-3e63e05e637c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3778279261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3778279261 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4260907905 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27424630 ps |
| CPU time | 0.41 seconds |
| Started | May 14 01:57:03 PM PDT 24 |
| Finished | May 14 01:57:04 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-9168b4bc-57c3-49ec-9609-850469d9bfb6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4260907905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.4260907905 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1606577249 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28309937 ps |
| CPU time | 0.41 seconds |
| Started | May 14 01:57:01 PM PDT 24 |
| Finished | May 14 01:57:02 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-2737bbb7-6f25-4f02-9dbd-12176b00c00b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1606577249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1606577249 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1606305908 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 26488380 ps |
| CPU time | 0.41 seconds |
| Started | May 14 01:57:02 PM PDT 24 |
| Finished | May 14 01:57:03 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-1e31e630-35ce-443c-a74a-eb7036cb6acc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1606305908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1606305908 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1422382034 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 25676431 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:56:59 PM PDT 24 |
| Finished | May 14 01:57:01 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-672ea022-bccc-4d9a-b076-39b3e9d86b54 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1422382034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1422382034 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1018286404 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 28699781 ps |
| CPU time | 0.44 seconds |
| Started | May 14 01:57:10 PM PDT 24 |
| Finished | May 14 01:57:11 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-d68639e6-47bd-40dd-b13e-f92c427a7b0a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1018286404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1018286404 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4240569503 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28229935 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:57:08 PM PDT 24 |
| Finished | May 14 01:57:10 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-60f6d25e-ec15-4463-9410-10da276f5181 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4240569503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.4240569503 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3779118704 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 26410705 ps |
| CPU time | 0.38 seconds |
| Started | May 14 01:57:08 PM PDT 24 |
| Finished | May 14 01:57:09 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-33c9723c-202d-4f14-9d5e-a43d175a7a77 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3779118704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3779118704 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3082179739 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27352523 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:56:53 PM PDT 24 |
| Finished | May 14 01:56:54 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-a4a29642-140a-40b5-949b-d2778b9b6825 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3082179739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3082179739 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2217629708 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28677222 ps |
| CPU time | 0.41 seconds |
| Started | May 14 01:56:52 PM PDT 24 |
| Finished | May 14 01:56:54 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-958a7f16-16e1-4460-ad62-8c8cbcc9a150 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2217629708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2217629708 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.585793684 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 26597650 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:56:54 PM PDT 24 |
| Finished | May 14 01:56:55 PM PDT 24 |
| Peak memory | 145520 kb |
| Host | smart-4e8c27ba-2eb9-44a7-a26a-9e6153920c8d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=585793684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.585793684 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2925613543 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 26215263 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:56:55 PM PDT 24 |
| Finished | May 14 01:56:56 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-4c27d476-d287-40c3-9a88-3c6d4249d256 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2925613543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2925613543 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3279976242 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 27212233 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:56:52 PM PDT 24 |
| Finished | May 14 01:56:53 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-59c25a65-925a-471a-9880-6bf19ad5b9d2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3279976242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3279976242 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.462088828 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 28203318 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:56:54 PM PDT 24 |
| Finished | May 14 01:56:55 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-94b75569-d831-4910-9aab-ebb74b571413 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=462088828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.462088828 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1062212393 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 30544132 ps |
| CPU time | 0.39 seconds |
| Started | May 14 01:56:53 PM PDT 24 |
| Finished | May 14 01:56:55 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-96c62e7c-dc84-41bb-bc6b-a8466eab2511 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1062212393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1062212393 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3827238839 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26634444 ps |
| CPU time | 0.4 seconds |
| Started | May 14 01:56:56 PM PDT 24 |
| Finished | May 14 01:56:57 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-7b34be30-b4fc-4935-959a-09689046b465 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3827238839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3827238839 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |