| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.67 | 88.67 | 100.00 | 100.00 | 93.75 | 93.75 | 96.43 | 96.43 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/8.prim_async_alert.1783997160 |
| 91.80 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 96.43 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/19.prim_sync_alert.1135339289 |
| 94.15 | 2.35 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 3.57 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2621926390 |
| 94.50 | 0.35 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/12.prim_async_alert.1732700872 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.118565231 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/5.prim_sync_alert.1251923412 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.2098110461 |
| /workspace/coverage/default/1.prim_async_alert.1527795650 |
| /workspace/coverage/default/10.prim_async_alert.330497936 |
| /workspace/coverage/default/11.prim_async_alert.4053031355 |
| /workspace/coverage/default/13.prim_async_alert.3040034060 |
| /workspace/coverage/default/14.prim_async_alert.1567539238 |
| /workspace/coverage/default/15.prim_async_alert.742781178 |
| /workspace/coverage/default/16.prim_async_alert.729567277 |
| /workspace/coverage/default/17.prim_async_alert.90163340 |
| /workspace/coverage/default/18.prim_async_alert.4145505106 |
| /workspace/coverage/default/19.prim_async_alert.3466613634 |
| /workspace/coverage/default/2.prim_async_alert.3679825326 |
| /workspace/coverage/default/4.prim_async_alert.2646456965 |
| /workspace/coverage/default/5.prim_async_alert.187539197 |
| /workspace/coverage/default/6.prim_async_alert.2245966180 |
| /workspace/coverage/default/7.prim_async_alert.3066970680 |
| /workspace/coverage/default/9.prim_async_alert.3437134179 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.93379175 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.356601075 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1644532090 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1613274616 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.291048585 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.753348429 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3189639433 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3251172840 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1303359405 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1474509497 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3862588346 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3271247476 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4196890611 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2146625604 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.611136981 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2217372642 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.1658380438 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.4043507416 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.2591874193 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1159500363 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.2269500788 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1817231762 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.2340196891 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.1353692839 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.2929334277 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.4234146563 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.96888207 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.1194702152 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.1176276646 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.1380109754 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.4190114678 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1740846808 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.1989777780 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.810201055 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.332827903 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1415987437 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2559512870 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3507171449 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.622029299 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4214288742 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3228187523 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.662888463 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1508141780 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2202383054 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3240845451 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3283326254 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4169378860 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.943009180 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2138134826 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3993776200 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.415220205 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.69149805 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3827430820 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3550712479 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/7.prim_async_alert.3066970680 | May 16 01:49:39 PM PDT 24 | May 16 01:49:41 PM PDT 24 | 11776258 ps | ||
| T2 | /workspace/coverage/default/17.prim_async_alert.90163340 | May 16 01:49:39 PM PDT 24 | May 16 01:49:41 PM PDT 24 | 11248779 ps | ||
| T3 | /workspace/coverage/default/2.prim_async_alert.3679825326 | May 16 01:49:35 PM PDT 24 | May 16 01:49:37 PM PDT 24 | 10922118 ps | ||
| T10 | /workspace/coverage/default/5.prim_async_alert.187539197 | May 16 01:49:37 PM PDT 24 | May 16 01:49:40 PM PDT 24 | 12131395 ps | ||
| T7 | /workspace/coverage/default/13.prim_async_alert.3040034060 | May 16 01:49:36 PM PDT 24 | May 16 01:49:38 PM PDT 24 | 11404910 ps | ||
| T11 | /workspace/coverage/default/19.prim_async_alert.3466613634 | May 16 01:49:36 PM PDT 24 | May 16 01:49:38 PM PDT 24 | 12304533 ps | ||
| T18 | /workspace/coverage/default/4.prim_async_alert.2646456965 | May 16 01:49:37 PM PDT 24 | May 16 01:49:39 PM PDT 24 | 10815845 ps | ||
| T19 | /workspace/coverage/default/11.prim_async_alert.4053031355 | May 16 01:49:37 PM PDT 24 | May 16 01:49:39 PM PDT 24 | 11948774 ps | ||
| T20 | /workspace/coverage/default/12.prim_async_alert.1732700872 | May 16 01:49:37 PM PDT 24 | May 16 01:49:39 PM PDT 24 | 11193466 ps | ||
| T14 | /workspace/coverage/default/8.prim_async_alert.1783997160 | May 16 01:49:38 PM PDT 24 | May 16 01:49:40 PM PDT 24 | 10873326 ps | ||
| T15 | /workspace/coverage/default/1.prim_async_alert.1527795650 | May 16 01:49:38 PM PDT 24 | May 16 01:49:40 PM PDT 24 | 10644850 ps | ||
| T49 | /workspace/coverage/default/14.prim_async_alert.1567539238 | May 16 01:49:38 PM PDT 24 | May 16 01:49:40 PM PDT 24 | 11258121 ps | ||
| T16 | /workspace/coverage/default/6.prim_async_alert.2245966180 | May 16 01:49:36 PM PDT 24 | May 16 01:49:38 PM PDT 24 | 11377009 ps | ||
| T44 | /workspace/coverage/default/18.prim_async_alert.4145505106 | May 16 01:49:36 PM PDT 24 | May 16 01:49:38 PM PDT 24 | 11435886 ps | ||
| T41 | /workspace/coverage/default/0.prim_async_alert.2098110461 | May 16 01:49:38 PM PDT 24 | May 16 01:49:41 PM PDT 24 | 11749868 ps | ||
| T12 | /workspace/coverage/default/10.prim_async_alert.330497936 | May 16 01:49:40 PM PDT 24 | May 16 01:49:42 PM PDT 24 | 11870746 ps | ||
| T17 | /workspace/coverage/default/9.prim_async_alert.3437134179 | May 16 01:49:36 PM PDT 24 | May 16 01:49:37 PM PDT 24 | 12407319 ps | ||
| T21 | /workspace/coverage/default/15.prim_async_alert.742781178 | May 16 01:49:36 PM PDT 24 | May 16 01:49:37 PM PDT 24 | 10829132 ps | ||
| T22 | /workspace/coverage/default/16.prim_async_alert.729567277 | May 16 01:49:37 PM PDT 24 | May 16 01:49:38 PM PDT 24 | 10480175 ps | ||
| T45 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.93379175 | May 16 12:24:42 PM PDT 24 | May 16 12:25:01 PM PDT 24 | 29015810 ps | ||
| T4 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.118565231 | May 16 12:24:32 PM PDT 24 | May 16 12:24:50 PM PDT 24 | 30462103 ps | ||
| T23 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3271247476 | May 16 12:24:42 PM PDT 24 | May 16 12:25:02 PM PDT 24 | 30116055 ps | ||
| T24 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2146625604 | May 16 12:24:15 PM PDT 24 | May 16 12:24:29 PM PDT 24 | 30092446 ps | ||
| T46 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1303359405 | May 16 12:20:57 PM PDT 24 | May 16 12:20:58 PM PDT 24 | 31600805 ps | ||
| T13 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2621926390 | May 16 12:22:25 PM PDT 24 | May 16 12:22:26 PM PDT 24 | 29734969 ps | ||
| T47 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3862588346 | May 16 12:19:31 PM PDT 24 | May 16 12:19:33 PM PDT 24 | 28439207 ps | ||
| T42 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1613274616 | May 16 12:24:14 PM PDT 24 | May 16 12:24:28 PM PDT 24 | 30368761 ps | ||
| T25 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.291048585 | May 16 12:23:22 PM PDT 24 | May 16 12:23:28 PM PDT 24 | 29247172 ps | ||
| T48 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1644532090 | May 16 12:19:17 PM PDT 24 | May 16 12:19:19 PM PDT 24 | 28798079 ps | ||
| T50 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2217372642 | May 16 12:19:17 PM PDT 24 | May 16 12:19:19 PM PDT 24 | 30676279 ps | ||
| T51 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4196890611 | May 16 12:24:19 PM PDT 24 | May 16 12:24:35 PM PDT 24 | 30633367 ps | ||
| T52 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.356601075 | May 16 12:24:33 PM PDT 24 | May 16 12:24:53 PM PDT 24 | 28428080 ps | ||
| T5 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.611136981 | May 16 12:20:45 PM PDT 24 | May 16 12:20:46 PM PDT 24 | 30558321 ps | ||
| T53 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1474509497 | May 16 12:24:01 PM PDT 24 | May 16 12:24:05 PM PDT 24 | 29009487 ps | ||
| T54 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3189639433 | May 16 12:24:06 PM PDT 24 | May 16 12:24:17 PM PDT 24 | 28188155 ps | ||
| T43 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.753348429 | May 16 12:24:48 PM PDT 24 | May 16 12:25:06 PM PDT 24 | 29995590 ps | ||
| T55 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3251172840 | May 16 12:23:04 PM PDT 24 | May 16 12:23:06 PM PDT 24 | 29545787 ps | ||
| T35 | /workspace/coverage/sync_alert/18.prim_sync_alert.96888207 | May 16 01:49:47 PM PDT 24 | May 16 01:49:49 PM PDT 24 | 9288259 ps | ||
| T26 | /workspace/coverage/sync_alert/3.prim_sync_alert.1176276646 | May 16 01:49:49 PM PDT 24 | May 16 01:49:51 PM PDT 24 | 10431014 ps | ||
| T36 | /workspace/coverage/sync_alert/15.prim_sync_alert.1353692839 | May 16 01:49:47 PM PDT 24 | May 16 01:49:49 PM PDT 24 | 8768407 ps | ||
| T37 | /workspace/coverage/sync_alert/19.prim_sync_alert.1135339289 | May 16 01:49:50 PM PDT 24 | May 16 01:49:52 PM PDT 24 | 9106301 ps | ||
| T38 | /workspace/coverage/sync_alert/1.prim_sync_alert.4043507416 | May 16 01:49:37 PM PDT 24 | May 16 01:49:39 PM PDT 24 | 9444865 ps | ||
| T27 | /workspace/coverage/sync_alert/4.prim_sync_alert.1380109754 | May 16 01:49:48 PM PDT 24 | May 16 01:49:49 PM PDT 24 | 8927582 ps | ||
| T39 | /workspace/coverage/sync_alert/17.prim_sync_alert.4234146563 | May 16 01:49:48 PM PDT 24 | May 16 01:49:51 PM PDT 24 | 9204785 ps | ||
| T40 | /workspace/coverage/sync_alert/6.prim_sync_alert.4190114678 | May 16 01:49:48 PM PDT 24 | May 16 01:49:50 PM PDT 24 | 7749038 ps | ||
| T28 | /workspace/coverage/sync_alert/9.prim_sync_alert.810201055 | May 16 01:49:52 PM PDT 24 | May 16 01:49:53 PM PDT 24 | 9610329 ps | ||
| T29 | /workspace/coverage/sync_alert/13.prim_sync_alert.1817231762 | May 16 01:49:47 PM PDT 24 | May 16 01:49:48 PM PDT 24 | 9313768 ps | ||
| T56 | /workspace/coverage/sync_alert/10.prim_sync_alert.2591874193 | May 16 01:49:48 PM PDT 24 | May 16 01:49:49 PM PDT 24 | 9837971 ps | ||
| T30 | /workspace/coverage/sync_alert/14.prim_sync_alert.2340196891 | May 16 01:49:49 PM PDT 24 | May 16 01:49:51 PM PDT 24 | 9933513 ps | ||
| T31 | /workspace/coverage/sync_alert/2.prim_sync_alert.1194702152 | May 16 01:49:37 PM PDT 24 | May 16 01:49:40 PM PDT 24 | 9442876 ps | ||
| T32 | /workspace/coverage/sync_alert/11.prim_sync_alert.1159500363 | May 16 01:49:48 PM PDT 24 | May 16 01:49:49 PM PDT 24 | 8891014 ps | ||
| T33 | /workspace/coverage/sync_alert/0.prim_sync_alert.1658380438 | May 16 01:49:36 PM PDT 24 | May 16 01:49:38 PM PDT 24 | 9389110 ps | ||
| T34 | /workspace/coverage/sync_alert/12.prim_sync_alert.2269500788 | May 16 01:49:50 PM PDT 24 | May 16 01:49:51 PM PDT 24 | 10538188 ps | ||
| T57 | /workspace/coverage/sync_alert/7.prim_sync_alert.1740846808 | May 16 01:49:48 PM PDT 24 | May 16 01:49:51 PM PDT 24 | 11084948 ps | ||
| T8 | /workspace/coverage/sync_alert/8.prim_sync_alert.1989777780 | May 16 01:49:48 PM PDT 24 | May 16 01:49:50 PM PDT 24 | 9614269 ps | ||
| T58 | /workspace/coverage/sync_alert/16.prim_sync_alert.2929334277 | May 16 01:49:47 PM PDT 24 | May 16 01:49:49 PM PDT 24 | 9030867 ps | ||
| T9 | /workspace/coverage/sync_alert/5.prim_sync_alert.1251923412 | May 16 01:49:48 PM PDT 24 | May 16 01:49:50 PM PDT 24 | 9549911 ps | ||
| T59 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.943009180 | May 16 01:50:00 PM PDT 24 | May 16 01:50:02 PM PDT 24 | 28327625 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.332827903 | May 16 01:50:01 PM PDT 24 | May 16 01:50:03 PM PDT 24 | 28526099 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1415987437 | May 16 01:49:58 PM PDT 24 | May 16 01:50:00 PM PDT 24 | 28393087 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.622029299 | May 16 01:50:00 PM PDT 24 | May 16 01:50:02 PM PDT 24 | 27771561 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4169378860 | May 16 01:50:01 PM PDT 24 | May 16 01:50:03 PM PDT 24 | 29321646 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3550712479 | May 16 01:49:58 PM PDT 24 | May 16 01:49:59 PM PDT 24 | 27665680 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2202383054 | May 16 01:50:22 PM PDT 24 | May 16 01:50:26 PM PDT 24 | 25992364 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3507171449 | May 16 01:50:00 PM PDT 24 | May 16 01:50:02 PM PDT 24 | 26371831 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.69149805 | May 16 01:50:00 PM PDT 24 | May 16 01:50:02 PM PDT 24 | 26183178 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1508141780 | May 16 01:50:10 PM PDT 24 | May 16 01:50:11 PM PDT 24 | 27490018 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2559512870 | May 16 01:50:00 PM PDT 24 | May 16 01:50:01 PM PDT 24 | 27572203 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.662888463 | May 16 01:50:11 PM PDT 24 | May 16 01:50:12 PM PDT 24 | 28614576 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3827430820 | May 16 01:50:00 PM PDT 24 | May 16 01:50:01 PM PDT 24 | 28245345 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3240845451 | May 16 01:50:20 PM PDT 24 | May 16 01:50:23 PM PDT 24 | 29487794 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.415220205 | May 16 01:49:58 PM PDT 24 | May 16 01:50:00 PM PDT 24 | 27891559 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3993776200 | May 16 01:50:00 PM PDT 24 | May 16 01:50:02 PM PDT 24 | 27154208 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4214288742 | May 16 01:50:00 PM PDT 24 | May 16 01:50:01 PM PDT 24 | 26619822 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3283326254 | May 16 01:50:21 PM PDT 24 | May 16 01:50:25 PM PDT 24 | 27967249 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2138134826 | May 16 01:50:00 PM PDT 24 | May 16 01:50:02 PM PDT 24 | 27384289 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3228187523 | May 16 01:50:00 PM PDT 24 | May 16 01:50:02 PM PDT 24 | 25823261 ps |
| Test location | /workspace/coverage/default/8.prim_async_alert.1783997160 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10873326 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:38 PM PDT 24 |
| Finished | May 16 01:49:40 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-291ac491-24d0-4b46-84c0-01ec381c0b23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783997160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1783997160 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.1135339289 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9106301 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:50 PM PDT 24 |
| Finished | May 16 01:49:52 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-877fcdb0-d11b-48cd-962f-e0cf34125896 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1135339289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1135339289 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2621926390 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 29734969 ps |
| CPU time | 0.4 seconds |
| Started | May 16 12:22:25 PM PDT 24 |
| Finished | May 16 12:22:26 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-4030215e-119a-43a5-a441-1b467af5a5de |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2621926390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2621926390 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.1732700872 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11193466 ps |
| CPU time | 0.4 seconds |
| Started | May 16 01:49:37 PM PDT 24 |
| Finished | May 16 01:49:39 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-dec7238a-8c7e-4ee8-9427-9625424cfbb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1732700872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1732700872 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.118565231 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30462103 ps |
| CPU time | 0.42 seconds |
| Started | May 16 12:24:32 PM PDT 24 |
| Finished | May 16 12:24:50 PM PDT 24 |
| Peak memory | 144548 kb |
| Host | smart-d9d9b787-10d1-4e80-998e-a4ea506a8a51 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=118565231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.118565231 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1251923412 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9549911 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:48 PM PDT 24 |
| Finished | May 16 01:49:50 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-a2c17558-367a-4106-abda-3adc843af901 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1251923412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1251923412 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.2098110461 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11749868 ps |
| CPU time | 0.4 seconds |
| Started | May 16 01:49:38 PM PDT 24 |
| Finished | May 16 01:49:41 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-ab7e51a6-6db0-444e-b76d-85208e110ac8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2098110461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2098110461 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1527795650 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10644850 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:38 PM PDT 24 |
| Finished | May 16 01:49:40 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-87176bfa-09f9-4930-9546-5108f5da3dcc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527795650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1527795650 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.330497936 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11870746 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:40 PM PDT 24 |
| Finished | May 16 01:49:42 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-7b7a09bd-73b2-4ecc-bac5-292582a3274a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330497936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.330497936 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.4053031355 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11948774 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:37 PM PDT 24 |
| Finished | May 16 01:49:39 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-8ead8e75-13bd-46b9-9d65-160742130dd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4053031355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4053031355 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3040034060 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11404910 ps |
| CPU time | 0.4 seconds |
| Started | May 16 01:49:36 PM PDT 24 |
| Finished | May 16 01:49:38 PM PDT 24 |
| Peak memory | 145840 kb |
| Host | smart-6f82084b-9132-42ca-abdb-dc09168a2872 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040034060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3040034060 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1567539238 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11258121 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:38 PM PDT 24 |
| Finished | May 16 01:49:40 PM PDT 24 |
| Peak memory | 145832 kb |
| Host | smart-5f0c6b14-ee28-443f-8cc0-dd138322cf7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1567539238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1567539238 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.742781178 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10829132 ps |
| CPU time | 0.4 seconds |
| Started | May 16 01:49:36 PM PDT 24 |
| Finished | May 16 01:49:37 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-211496a0-3f43-4cce-a6e3-5031c8a2e2f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742781178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.742781178 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.729567277 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10480175 ps |
| CPU time | 0.42 seconds |
| Started | May 16 01:49:37 PM PDT 24 |
| Finished | May 16 01:49:38 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-48a7435e-6999-42f3-9128-7835e95589d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729567277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.729567277 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.90163340 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11248779 ps |
| CPU time | 0.4 seconds |
| Started | May 16 01:49:39 PM PDT 24 |
| Finished | May 16 01:49:41 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-9d14af35-b4e3-4981-b5fb-81ec575fb7f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90163340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.90163340 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.4145505106 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11435886 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:36 PM PDT 24 |
| Finished | May 16 01:49:38 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-34535836-6d8b-48fb-878c-88b7f3722fe0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4145505106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.4145505106 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3466613634 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12304533 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:36 PM PDT 24 |
| Finished | May 16 01:49:38 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-81635623-2293-4058-b6b1-89fc5f114b63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466613634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3466613634 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3679825326 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10922118 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:35 PM PDT 24 |
| Finished | May 16 01:49:37 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-7bb20931-208a-4dfa-a93e-0e0859ccc68f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679825326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3679825326 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.2646456965 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10815845 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:37 PM PDT 24 |
| Finished | May 16 01:49:39 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-83cc09fb-18a7-44c2-8dc7-4921862e099c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2646456965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2646456965 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.187539197 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12131395 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:37 PM PDT 24 |
| Finished | May 16 01:49:40 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-3aa7db7d-36af-41d8-809d-5796c63cd6a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187539197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.187539197 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2245966180 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11377009 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:36 PM PDT 24 |
| Finished | May 16 01:49:38 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-d75a164a-a123-4ba1-a393-dfab35db9cc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2245966180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2245966180 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.3066970680 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11776258 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:39 PM PDT 24 |
| Finished | May 16 01:49:41 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-437358bf-e032-4795-bd81-210f906c72fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066970680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3066970680 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.3437134179 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12407319 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:36 PM PDT 24 |
| Finished | May 16 01:49:37 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-936b03dc-43eb-4d96-bcb0-281a12e20bc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437134179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3437134179 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.93379175 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29015810 ps |
| CPU time | 0.38 seconds |
| Started | May 16 12:24:42 PM PDT 24 |
| Finished | May 16 12:25:01 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-32f4059d-1360-4f96-a2e3-f4852f2c54db |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=93379175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.93379175 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.356601075 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 28428080 ps |
| CPU time | 0.43 seconds |
| Started | May 16 12:24:33 PM PDT 24 |
| Finished | May 16 12:24:53 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-55130e25-f27e-45c3-ae29-1e5c4e83cf00 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=356601075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.356601075 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1644532090 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 28798079 ps |
| CPU time | 0.39 seconds |
| Started | May 16 12:19:17 PM PDT 24 |
| Finished | May 16 12:19:19 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-6e5f439e-6d58-4b56-9562-62e5d499f691 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1644532090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1644532090 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1613274616 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30368761 ps |
| CPU time | 0.46 seconds |
| Started | May 16 12:24:14 PM PDT 24 |
| Finished | May 16 12:24:28 PM PDT 24 |
| Peak memory | 144304 kb |
| Host | smart-1c414fc7-e24d-49e1-9f4e-1d7e87cbe371 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1613274616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1613274616 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.291048585 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 29247172 ps |
| CPU time | 0.45 seconds |
| Started | May 16 12:23:22 PM PDT 24 |
| Finished | May 16 12:23:28 PM PDT 24 |
| Peak memory | 144176 kb |
| Host | smart-0d98904e-dfc9-4421-9a17-7327393693ab |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=291048585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.291048585 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.753348429 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 29995590 ps |
| CPU time | 0.39 seconds |
| Started | May 16 12:24:48 PM PDT 24 |
| Finished | May 16 12:25:06 PM PDT 24 |
| Peak memory | 145356 kb |
| Host | smart-73faa623-4e6a-401d-b9c9-961a3bde4ed1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=753348429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.753348429 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3189639433 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 28188155 ps |
| CPU time | 0.4 seconds |
| Started | May 16 12:24:06 PM PDT 24 |
| Finished | May 16 12:24:17 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-89c2c8ee-5e46-4cf6-bbe3-61f86e4c4653 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3189639433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3189639433 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3251172840 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29545787 ps |
| CPU time | 0.4 seconds |
| Started | May 16 12:23:04 PM PDT 24 |
| Finished | May 16 12:23:06 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-05b80f1a-df86-49dc-a34b-0dbd78c91f2f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3251172840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3251172840 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1303359405 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 31600805 ps |
| CPU time | 0.44 seconds |
| Started | May 16 12:20:57 PM PDT 24 |
| Finished | May 16 12:20:58 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-ebdae2bd-ee3c-490a-949a-4f6ef8902d69 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1303359405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1303359405 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1474509497 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29009487 ps |
| CPU time | 0.41 seconds |
| Started | May 16 12:24:01 PM PDT 24 |
| Finished | May 16 12:24:05 PM PDT 24 |
| Peak memory | 144744 kb |
| Host | smart-1b9de524-1281-493e-968a-447bc5c8dad9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1474509497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1474509497 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3862588346 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 28439207 ps |
| CPU time | 0.43 seconds |
| Started | May 16 12:19:31 PM PDT 24 |
| Finished | May 16 12:19:33 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-997ec533-beb1-41a6-8755-3d150caea21a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3862588346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3862588346 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3271247476 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 30116055 ps |
| CPU time | 0.39 seconds |
| Started | May 16 12:24:42 PM PDT 24 |
| Finished | May 16 12:25:02 PM PDT 24 |
| Peak memory | 145376 kb |
| Host | smart-d9e95769-3323-4724-bd9a-abdc110fff2a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3271247476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3271247476 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4196890611 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30633367 ps |
| CPU time | 0.45 seconds |
| Started | May 16 12:24:19 PM PDT 24 |
| Finished | May 16 12:24:35 PM PDT 24 |
| Peak memory | 145240 kb |
| Host | smart-7db5a19b-f0f9-4858-b3d5-3a6abc70fb2b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4196890611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.4196890611 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2146625604 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 30092446 ps |
| CPU time | 0.42 seconds |
| Started | May 16 12:24:15 PM PDT 24 |
| Finished | May 16 12:24:29 PM PDT 24 |
| Peak memory | 144456 kb |
| Host | smart-724fe33c-30ef-43b0-ae61-4e51025f5ff3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2146625604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2146625604 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.611136981 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30558321 ps |
| CPU time | 0.41 seconds |
| Started | May 16 12:20:45 PM PDT 24 |
| Finished | May 16 12:20:46 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-470e255f-d109-4038-b38d-ad312b0de8d6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=611136981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.611136981 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2217372642 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30676279 ps |
| CPU time | 0.39 seconds |
| Started | May 16 12:19:17 PM PDT 24 |
| Finished | May 16 12:19:19 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-2cac6ee8-22bf-4e5d-8a77-5ff19b041201 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2217372642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2217372642 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.1658380438 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9389110 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:36 PM PDT 24 |
| Finished | May 16 01:49:38 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-f6ea488a-03fb-4cc4-a1b2-9c17c609bdbd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1658380438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1658380438 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.4043507416 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9444865 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:37 PM PDT 24 |
| Finished | May 16 01:49:39 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-90fbc8d3-a272-447c-8229-659552570d95 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4043507416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.4043507416 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.2591874193 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9837971 ps |
| CPU time | 0.41 seconds |
| Started | May 16 01:49:48 PM PDT 24 |
| Finished | May 16 01:49:49 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-4f34de50-d91a-4f05-bc0a-ed5e8bc0b406 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2591874193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2591874193 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1159500363 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8891014 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:48 PM PDT 24 |
| Finished | May 16 01:49:49 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-9b150084-9f33-45e6-8c00-fc3c83c79abd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1159500363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1159500363 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.2269500788 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10538188 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:50 PM PDT 24 |
| Finished | May 16 01:49:51 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-b2eabac6-7b21-4138-b14f-ee86cd09b98c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2269500788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2269500788 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1817231762 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9313768 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:47 PM PDT 24 |
| Finished | May 16 01:49:48 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-ec270e05-7b7a-42f3-9dc5-543352bd1f6b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1817231762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1817231762 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.2340196891 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9933513 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:49 PM PDT 24 |
| Finished | May 16 01:49:51 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-d0178447-af27-4bad-a920-e1d9fa3d361c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2340196891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2340196891 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.1353692839 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8768407 ps |
| CPU time | 0.41 seconds |
| Started | May 16 01:49:47 PM PDT 24 |
| Finished | May 16 01:49:49 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-21d0ff43-3bbc-4554-a13e-4aec3e1713c6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1353692839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1353692839 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.2929334277 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9030867 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:47 PM PDT 24 |
| Finished | May 16 01:49:49 PM PDT 24 |
| Peak memory | 145680 kb |
| Host | smart-12d8b34f-1baf-434d-b59a-7633e183699b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2929334277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2929334277 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.4234146563 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9204785 ps |
| CPU time | 0.43 seconds |
| Started | May 16 01:49:48 PM PDT 24 |
| Finished | May 16 01:49:51 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-a7bb39a8-4319-433c-8c6d-06b91e59f3ab |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4234146563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.4234146563 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.96888207 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9288259 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:47 PM PDT 24 |
| Finished | May 16 01:49:49 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-5b8f9ee5-cb7d-48bc-a3ea-7e21d9d845d3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=96888207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.96888207 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.1194702152 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9442876 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:37 PM PDT 24 |
| Finished | May 16 01:49:40 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-7d97780b-d47e-466e-b0b6-b0d8bf8d4836 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1194702152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1194702152 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.1176276646 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10431014 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:49 PM PDT 24 |
| Finished | May 16 01:49:51 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-a67cf39a-99a4-44d7-a4f3-04f4ec141f18 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1176276646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1176276646 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.1380109754 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8927582 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:48 PM PDT 24 |
| Finished | May 16 01:49:49 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-f34f166b-4e76-4279-88a8-c864ea376192 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1380109754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1380109754 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.4190114678 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 7749038 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:48 PM PDT 24 |
| Finished | May 16 01:49:50 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-754fdcd4-ecde-4043-a2e6-25e3a63ae265 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4190114678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.4190114678 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1740846808 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 11084948 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:48 PM PDT 24 |
| Finished | May 16 01:49:51 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-9480738f-aa1b-464c-af0a-49198d7499bc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1740846808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1740846808 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1989777780 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9614269 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:48 PM PDT 24 |
| Finished | May 16 01:49:50 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-e5348258-055f-4373-9e4a-07448c134d54 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1989777780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1989777780 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.810201055 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9610329 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:52 PM PDT 24 |
| Finished | May 16 01:49:53 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-72d5130b-cce8-4fce-8648-e2171aae090b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=810201055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.810201055 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.332827903 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 28526099 ps |
| CPU time | 0.41 seconds |
| Started | May 16 01:50:01 PM PDT 24 |
| Finished | May 16 01:50:03 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-a645f2b4-d4f1-4582-8c22-5d50b33cd6a3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=332827903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.332827903 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1415987437 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 28393087 ps |
| CPU time | 0.4 seconds |
| Started | May 16 01:49:58 PM PDT 24 |
| Finished | May 16 01:50:00 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-7415627f-a36f-4da2-b789-43a355f364a8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1415987437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1415987437 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2559512870 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27572203 ps |
| CPU time | 0.41 seconds |
| Started | May 16 01:50:00 PM PDT 24 |
| Finished | May 16 01:50:01 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-0b23bfe0-cbd1-48ea-bdcf-409c6d39e694 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2559512870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2559512870 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3507171449 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26371831 ps |
| CPU time | 0.42 seconds |
| Started | May 16 01:50:00 PM PDT 24 |
| Finished | May 16 01:50:02 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-7a000b69-a055-4d8e-ad15-1220184a039c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3507171449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3507171449 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.622029299 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27771561 ps |
| CPU time | 0.41 seconds |
| Started | May 16 01:50:00 PM PDT 24 |
| Finished | May 16 01:50:02 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-406991b8-9873-40a9-8355-49ec7cc14554 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=622029299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.622029299 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4214288742 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26619822 ps |
| CPU time | 0.41 seconds |
| Started | May 16 01:50:00 PM PDT 24 |
| Finished | May 16 01:50:01 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-79fbf03b-131d-409a-be35-c52eb9b8ba71 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4214288742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.4214288742 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3228187523 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 25823261 ps |
| CPU time | 0.41 seconds |
| Started | May 16 01:50:00 PM PDT 24 |
| Finished | May 16 01:50:02 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-4348df47-0df9-4c10-9d80-a6898ec2a61e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3228187523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3228187523 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.662888463 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 28614576 ps |
| CPU time | 0.4 seconds |
| Started | May 16 01:50:11 PM PDT 24 |
| Finished | May 16 01:50:12 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-441725ba-bdd6-4634-ae85-9df5965858ba |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=662888463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.662888463 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1508141780 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27490018 ps |
| CPU time | 0.4 seconds |
| Started | May 16 01:50:10 PM PDT 24 |
| Finished | May 16 01:50:11 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-3b86f13f-93c1-4b7b-8e48-432bd95451c6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1508141780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1508141780 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2202383054 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 25992364 ps |
| CPU time | 0.43 seconds |
| Started | May 16 01:50:22 PM PDT 24 |
| Finished | May 16 01:50:26 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-87a7f3ac-1e3b-4dad-8f98-a9d1138ac2e5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2202383054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2202383054 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3240845451 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 29487794 ps |
| CPU time | 0.4 seconds |
| Started | May 16 01:50:20 PM PDT 24 |
| Finished | May 16 01:50:23 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-6162b397-e789-4324-b633-85a586e4a9a5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3240845451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3240845451 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3283326254 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27967249 ps |
| CPU time | 0.41 seconds |
| Started | May 16 01:50:21 PM PDT 24 |
| Finished | May 16 01:50:25 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-2c96c3ce-f0bf-4a42-bc7b-a0eed70330f1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3283326254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3283326254 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4169378860 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 29321646 ps |
| CPU time | 0.41 seconds |
| Started | May 16 01:50:01 PM PDT 24 |
| Finished | May 16 01:50:03 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-d474f3b1-3bdc-40c8-90b2-9e0c2a8d6f90 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4169378860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.4169378860 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.943009180 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 28327625 ps |
| CPU time | 0.4 seconds |
| Started | May 16 01:50:00 PM PDT 24 |
| Finished | May 16 01:50:02 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-26c3c7bb-31af-401f-a991-978fe8cd9e19 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=943009180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.943009180 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2138134826 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27384289 ps |
| CPU time | 0.41 seconds |
| Started | May 16 01:50:00 PM PDT 24 |
| Finished | May 16 01:50:02 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-ef1c971a-18b9-44ec-b57a-4382941b3140 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2138134826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2138134826 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3993776200 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27154208 ps |
| CPU time | 0.4 seconds |
| Started | May 16 01:50:00 PM PDT 24 |
| Finished | May 16 01:50:02 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-1dd174d2-0023-43c0-a798-7824ee52bb26 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3993776200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3993776200 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.415220205 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27891559 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:49:58 PM PDT 24 |
| Finished | May 16 01:50:00 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-d2607994-6bc7-4b04-a106-99cb76a94ae0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=415220205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.415220205 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.69149805 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26183178 ps |
| CPU time | 0.39 seconds |
| Started | May 16 01:50:00 PM PDT 24 |
| Finished | May 16 01:50:02 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-33879e17-3c65-4063-9013-fd7dc2da08c3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=69149805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.69149805 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3827430820 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28245345 ps |
| CPU time | 0.4 seconds |
| Started | May 16 01:50:00 PM PDT 24 |
| Finished | May 16 01:50:01 PM PDT 24 |
| Peak memory | 145516 kb |
| Host | smart-9299e357-1fcc-4d25-b7db-6c3f10e7bd88 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3827430820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3827430820 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3550712479 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27665680 ps |
| CPU time | 0.38 seconds |
| Started | May 16 01:49:58 PM PDT 24 |
| Finished | May 16 01:49:59 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-b085f6f8-ec0e-4e0c-b8ae-3e4b367f57d7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3550712479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3550712479 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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