| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.53 | 88.53 | 100.00 | 100.00 | 91.67 | 91.67 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/4.prim_async_alert.2488242797 |
| 92.60 | 4.07 | 100.00 | 0.00 | 93.75 | 2.08 | 100.00 | 0.00 | 89.29 | 10.71 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/3.prim_sync_alert.2809698828 |
| 94.50 | 1.90 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 9.30 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3373860360 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/10.prim_async_alert.991748072 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2806403464 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.2772230602 |
| /workspace/coverage/default/1.prim_async_alert.2813113534 |
| /workspace/coverage/default/11.prim_async_alert.4007568815 |
| /workspace/coverage/default/12.prim_async_alert.2393114770 |
| /workspace/coverage/default/13.prim_async_alert.1872787703 |
| /workspace/coverage/default/14.prim_async_alert.1484849408 |
| /workspace/coverage/default/15.prim_async_alert.3555128124 |
| /workspace/coverage/default/16.prim_async_alert.1966713624 |
| /workspace/coverage/default/17.prim_async_alert.3053569446 |
| /workspace/coverage/default/18.prim_async_alert.3758625505 |
| /workspace/coverage/default/19.prim_async_alert.3243538974 |
| /workspace/coverage/default/2.prim_async_alert.3562259108 |
| /workspace/coverage/default/3.prim_async_alert.3400954710 |
| /workspace/coverage/default/5.prim_async_alert.631615779 |
| /workspace/coverage/default/6.prim_async_alert.467956643 |
| /workspace/coverage/default/7.prim_async_alert.456761241 |
| /workspace/coverage/default/8.prim_async_alert.3196068141 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1257837859 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.959456646 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.68097816 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3368862101 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.4142646286 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3923207569 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1226144258 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1216866525 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3788846407 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.47626658 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1309509180 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.208147870 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.206227073 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1100418853 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.285878236 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.243278445 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3315981399 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2634424365 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3849418517 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.3336069865 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.4192892200 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3799876680 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.4063137863 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3922918798 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.994816543 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1218857423 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.941120911 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.3540884311 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.853753446 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.1688964555 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.228905818 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2873755707 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.2117465219 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.3153654643 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.863078367 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.207492179 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.3402335056 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1927693162 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.6680313 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2229210484 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1116084744 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.933143168 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2276831465 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2257364509 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4218296948 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.730540966 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2452515197 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3051167329 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2715984539 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.530306055 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3792876799 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.842969836 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.823982717 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1517598021 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2454401328 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.741591395 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2836701076 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/8.prim_async_alert.3196068141 | May 19 01:28:44 PM PDT 24 | May 19 01:28:48 PM PDT 24 | 12063904 ps | ||
| T2 | /workspace/coverage/default/11.prim_async_alert.4007568815 | May 19 01:28:41 PM PDT 24 | May 19 01:28:43 PM PDT 24 | 10980462 ps | ||
| T3 | /workspace/coverage/default/4.prim_async_alert.2488242797 | May 19 01:28:44 PM PDT 24 | May 19 01:28:48 PM PDT 24 | 12106396 ps | ||
| T7 | /workspace/coverage/default/18.prim_async_alert.3758625505 | May 19 01:28:43 PM PDT 24 | May 19 01:28:47 PM PDT 24 | 11436504 ps | ||
| T21 | /workspace/coverage/default/13.prim_async_alert.1872787703 | May 19 01:28:42 PM PDT 24 | May 19 01:28:45 PM PDT 24 | 11082735 ps | ||
| T22 | /workspace/coverage/default/17.prim_async_alert.3053569446 | May 19 01:28:45 PM PDT 24 | May 19 01:28:50 PM PDT 24 | 11270724 ps | ||
| T9 | /workspace/coverage/default/3.prim_async_alert.3400954710 | May 19 01:28:48 PM PDT 24 | May 19 01:28:53 PM PDT 24 | 10236105 ps | ||
| T15 | /workspace/coverage/default/12.prim_async_alert.2393114770 | May 19 01:28:48 PM PDT 24 | May 19 01:28:53 PM PDT 24 | 12153099 ps | ||
| T23 | /workspace/coverage/default/0.prim_async_alert.2772230602 | May 19 01:28:44 PM PDT 24 | May 19 01:28:48 PM PDT 24 | 10799862 ps | ||
| T10 | /workspace/coverage/default/5.prim_async_alert.631615779 | May 19 01:28:42 PM PDT 24 | May 19 01:28:46 PM PDT 24 | 11673497 ps | ||
| T11 | /workspace/coverage/default/6.prim_async_alert.467956643 | May 19 01:28:41 PM PDT 24 | May 19 01:28:43 PM PDT 24 | 10694501 ps | ||
| T8 | /workspace/coverage/default/14.prim_async_alert.1484849408 | May 19 01:28:43 PM PDT 24 | May 19 01:28:47 PM PDT 24 | 11164115 ps | ||
| T24 | /workspace/coverage/default/19.prim_async_alert.3243538974 | May 19 01:28:43 PM PDT 24 | May 19 01:28:47 PM PDT 24 | 12359932 ps | ||
| T25 | /workspace/coverage/default/16.prim_async_alert.1966713624 | May 19 01:28:42 PM PDT 24 | May 19 01:28:45 PM PDT 24 | 11376842 ps | ||
| T49 | /workspace/coverage/default/10.prim_async_alert.991748072 | May 19 01:28:43 PM PDT 24 | May 19 01:28:47 PM PDT 24 | 10306751 ps | ||
| T41 | /workspace/coverage/default/15.prim_async_alert.3555128124 | May 19 01:28:42 PM PDT 24 | May 19 01:28:45 PM PDT 24 | 10569287 ps | ||
| T16 | /workspace/coverage/default/2.prim_async_alert.3562259108 | May 19 01:28:41 PM PDT 24 | May 19 01:28:43 PM PDT 24 | 11724488 ps | ||
| T50 | /workspace/coverage/default/7.prim_async_alert.456761241 | May 19 01:28:39 PM PDT 24 | May 19 01:28:41 PM PDT 24 | 11872008 ps | ||
| T51 | /workspace/coverage/default/1.prim_async_alert.2813113534 | May 19 01:28:41 PM PDT 24 | May 19 01:28:44 PM PDT 24 | 11673537 ps | ||
| T26 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.68097816 | May 19 01:29:19 PM PDT 24 | May 19 01:29:21 PM PDT 24 | 31363494 ps | ||
| T43 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.206227073 | May 19 01:29:17 PM PDT 24 | May 19 01:29:19 PM PDT 24 | 30268160 ps | ||
| T44 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.243278445 | May 19 01:29:18 PM PDT 24 | May 19 01:29:21 PM PDT 24 | 31093681 ps | ||
| T17 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3373860360 | May 19 01:29:21 PM PDT 24 | May 19 01:29:23 PM PDT 24 | 30875765 ps | ||
| T19 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3315981399 | May 19 01:29:18 PM PDT 24 | May 19 01:29:20 PM PDT 24 | 28644339 ps | ||
| T18 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1100418853 | May 19 01:29:21 PM PDT 24 | May 19 01:29:23 PM PDT 24 | 29791694 ps | ||
| T45 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1257837859 | May 19 01:29:17 PM PDT 24 | May 19 01:29:19 PM PDT 24 | 29643989 ps | ||
| T46 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1216866525 | May 19 01:29:18 PM PDT 24 | May 19 01:29:20 PM PDT 24 | 29516934 ps | ||
| T47 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.959456646 | May 19 01:29:17 PM PDT 24 | May 19 01:29:20 PM PDT 24 | 30656782 ps | ||
| T48 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1309509180 | May 19 01:29:21 PM PDT 24 | May 19 01:29:23 PM PDT 24 | 31566012 ps | ||
| T52 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3788846407 | May 19 01:29:19 PM PDT 24 | May 19 01:29:22 PM PDT 24 | 30886405 ps | ||
| T53 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.47626658 | May 19 01:29:19 PM PDT 24 | May 19 01:29:21 PM PDT 24 | 29824932 ps | ||
| T54 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3368862101 | May 19 01:29:17 PM PDT 24 | May 19 01:29:19 PM PDT 24 | 31394453 ps | ||
| T55 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3923207569 | May 19 01:29:19 PM PDT 24 | May 19 01:29:21 PM PDT 24 | 31168765 ps | ||
| T42 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3849418517 | May 19 01:29:19 PM PDT 24 | May 19 01:29:21 PM PDT 24 | 29008780 ps | ||
| T56 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2634424365 | May 19 01:29:19 PM PDT 24 | May 19 01:29:21 PM PDT 24 | 31429311 ps | ||
| T57 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.208147870 | May 19 01:29:19 PM PDT 24 | May 19 01:29:21 PM PDT 24 | 30318801 ps | ||
| T58 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1226144258 | May 19 01:29:19 PM PDT 24 | May 19 01:29:21 PM PDT 24 | 30497880 ps | ||
| T59 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.4142646286 | May 19 01:29:21 PM PDT 24 | May 19 01:29:23 PM PDT 24 | 29952581 ps | ||
| T20 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.285878236 | May 19 01:29:17 PM PDT 24 | May 19 01:29:20 PM PDT 24 | 30109539 ps | ||
| T27 | /workspace/coverage/sync_alert/12.prim_sync_alert.3922918798 | May 19 01:25:40 PM PDT 24 | May 19 01:25:42 PM PDT 24 | 9606882 ps | ||
| T36 | /workspace/coverage/sync_alert/2.prim_sync_alert.2873755707 | May 19 01:25:39 PM PDT 24 | May 19 01:25:40 PM PDT 24 | 9251945 ps | ||
| T37 | /workspace/coverage/sync_alert/19.prim_sync_alert.228905818 | May 19 01:25:40 PM PDT 24 | May 19 01:25:42 PM PDT 24 | 9460228 ps | ||
| T38 | /workspace/coverage/sync_alert/17.prim_sync_alert.853753446 | May 19 01:25:43 PM PDT 24 | May 19 01:25:44 PM PDT 24 | 9274822 ps | ||
| T39 | /workspace/coverage/sync_alert/11.prim_sync_alert.4063137863 | May 19 01:25:39 PM PDT 24 | May 19 01:25:40 PM PDT 24 | 10099932 ps | ||
| T40 | /workspace/coverage/sync_alert/1.prim_sync_alert.4192892200 | May 19 01:25:43 PM PDT 24 | May 19 01:25:45 PM PDT 24 | 9640604 ps | ||
| T12 | /workspace/coverage/sync_alert/9.prim_sync_alert.1927693162 | May 19 01:25:42 PM PDT 24 | May 19 01:25:43 PM PDT 24 | 10166136 ps | ||
| T13 | /workspace/coverage/sync_alert/0.prim_sync_alert.3336069865 | May 19 01:25:40 PM PDT 24 | May 19 01:25:41 PM PDT 24 | 9287072 ps | ||
| T14 | /workspace/coverage/sync_alert/3.prim_sync_alert.2809698828 | May 19 01:25:44 PM PDT 24 | May 19 01:25:46 PM PDT 24 | 10421771 ps | ||
| T28 | /workspace/coverage/sync_alert/16.prim_sync_alert.3540884311 | May 19 01:25:40 PM PDT 24 | May 19 01:25:41 PM PDT 24 | 9144977 ps | ||
| T60 | /workspace/coverage/sync_alert/13.prim_sync_alert.994816543 | May 19 01:25:43 PM PDT 24 | May 19 01:25:45 PM PDT 24 | 8420545 ps | ||
| T61 | /workspace/coverage/sync_alert/18.prim_sync_alert.1688964555 | May 19 01:25:43 PM PDT 24 | May 19 01:25:45 PM PDT 24 | 9356640 ps | ||
| T62 | /workspace/coverage/sync_alert/15.prim_sync_alert.941120911 | May 19 01:25:45 PM PDT 24 | May 19 01:25:46 PM PDT 24 | 9707066 ps | ||
| T29 | /workspace/coverage/sync_alert/7.prim_sync_alert.207492179 | May 19 01:25:41 PM PDT 24 | May 19 01:25:42 PM PDT 24 | 8779565 ps | ||
| T30 | /workspace/coverage/sync_alert/5.prim_sync_alert.3153654643 | May 19 01:25:41 PM PDT 24 | May 19 01:25:43 PM PDT 24 | 9158746 ps | ||
| T31 | /workspace/coverage/sync_alert/4.prim_sync_alert.2117465219 | May 19 01:25:42 PM PDT 24 | May 19 01:25:43 PM PDT 24 | 8062171 ps | ||
| T32 | /workspace/coverage/sync_alert/8.prim_sync_alert.3402335056 | May 19 01:25:45 PM PDT 24 | May 19 01:25:47 PM PDT 24 | 8885634 ps | ||
| T33 | /workspace/coverage/sync_alert/14.prim_sync_alert.1218857423 | May 19 01:25:43 PM PDT 24 | May 19 01:25:45 PM PDT 24 | 8809952 ps | ||
| T34 | /workspace/coverage/sync_alert/6.prim_sync_alert.863078367 | May 19 01:25:40 PM PDT 24 | May 19 01:25:41 PM PDT 24 | 9343332 ps | ||
| T35 | /workspace/coverage/sync_alert/10.prim_sync_alert.3799876680 | May 19 01:25:40 PM PDT 24 | May 19 01:25:42 PM PDT 24 | 9879708 ps | ||
| T4 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.741591395 | May 19 01:25:43 PM PDT 24 | May 19 01:25:45 PM PDT 24 | 25926843 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2257364509 | May 19 01:25:43 PM PDT 24 | May 19 01:25:45 PM PDT 24 | 26675354 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2276831465 | May 19 01:25:43 PM PDT 24 | May 19 01:25:46 PM PDT 24 | 28704142 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.730540966 | May 19 01:25:46 PM PDT 24 | May 19 01:25:48 PM PDT 24 | 26899434 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1517598021 | May 19 01:25:43 PM PDT 24 | May 19 01:25:46 PM PDT 24 | 26601722 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.530306055 | May 19 01:25:41 PM PDT 24 | May 19 01:25:43 PM PDT 24 | 26459887 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2836701076 | May 19 01:25:45 PM PDT 24 | May 19 01:25:46 PM PDT 24 | 27129544 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2715984539 | May 19 01:25:45 PM PDT 24 | May 19 01:25:46 PM PDT 24 | 28457084 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2806403464 | May 19 01:25:46 PM PDT 24 | May 19 01:25:47 PM PDT 24 | 27896386 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2454401328 | May 19 01:25:43 PM PDT 24 | May 19 01:25:45 PM PDT 24 | 27620766 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4218296948 | May 19 01:25:49 PM PDT 24 | May 19 01:25:50 PM PDT 24 | 27660221 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.933143168 | May 19 01:25:43 PM PDT 24 | May 19 01:25:45 PM PDT 24 | 29093728 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.823982717 | May 19 01:25:41 PM PDT 24 | May 19 01:25:42 PM PDT 24 | 25003961 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3051167329 | May 19 01:25:45 PM PDT 24 | May 19 01:25:46 PM PDT 24 | 26660065 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.6680313 | May 19 01:25:43 PM PDT 24 | May 19 01:25:45 PM PDT 24 | 28521746 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1116084744 | May 19 01:25:49 PM PDT 24 | May 19 01:25:50 PM PDT 24 | 24481414 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2452515197 | May 19 01:25:44 PM PDT 24 | May 19 01:25:46 PM PDT 24 | 27391332 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2229210484 | May 19 01:25:43 PM PDT 24 | May 19 01:25:45 PM PDT 24 | 27040339 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3792876799 | May 19 01:25:40 PM PDT 24 | May 19 01:25:42 PM PDT 24 | 26642273 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.842969836 | May 19 01:25:43 PM PDT 24 | May 19 01:25:46 PM PDT 24 | 27565166 ps |
| Test location | /workspace/coverage/default/4.prim_async_alert.2488242797 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12106396 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:28:44 PM PDT 24 |
| Finished | May 19 01:28:48 PM PDT 24 |
| Peak memory | 145748 kb |
| Host | smart-b8bcc7c1-6f2d-4c52-9052-c656ae75d1bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488242797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2488242797 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.2809698828 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10421771 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:25:44 PM PDT 24 |
| Finished | May 19 01:25:46 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-6e1d44e8-3807-4273-a151-eb0a1dba31c2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2809698828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2809698828 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3373860360 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 30875765 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:29:21 PM PDT 24 |
| Finished | May 19 01:29:23 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-92ee0f93-b72a-4dba-b19d-8c7aa76b2a49 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3373860360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3373860360 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.991748072 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10306751 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:28:43 PM PDT 24 |
| Finished | May 19 01:28:47 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-2eb21dde-a4f3-4907-bfff-ce6b2b7934de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=991748072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.991748072 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2806403464 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27896386 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:25:46 PM PDT 24 |
| Finished | May 19 01:25:47 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-da14554d-b5a4-4b3d-a418-e50fd18df50b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2806403464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2806403464 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.2772230602 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10799862 ps |
| CPU time | 0.38 seconds |
| Started | May 19 01:28:44 PM PDT 24 |
| Finished | May 19 01:28:48 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-04490837-4111-4328-b0f8-b15e6c55ae0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772230602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2772230602 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.2813113534 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 11673537 ps |
| CPU time | 0.42 seconds |
| Started | May 19 01:28:41 PM PDT 24 |
| Finished | May 19 01:28:44 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-871c998f-b25d-45e0-bfdb-8082815544a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2813113534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2813113534 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.4007568815 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10980462 ps |
| CPU time | 0.42 seconds |
| Started | May 19 01:28:41 PM PDT 24 |
| Finished | May 19 01:28:43 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-ae58c0d6-6bdf-4e13-ab61-b6c7a5657c94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4007568815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4007568815 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.2393114770 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12153099 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:28:48 PM PDT 24 |
| Finished | May 19 01:28:53 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-c37b1607-c498-4897-bc33-c1cd3fef4938 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2393114770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2393114770 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1872787703 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11082735 ps |
| CPU time | 0.38 seconds |
| Started | May 19 01:28:42 PM PDT 24 |
| Finished | May 19 01:28:45 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-9694bb58-c472-429e-8e1f-3be9341d87fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1872787703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1872787703 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.1484849408 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11164115 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:28:43 PM PDT 24 |
| Finished | May 19 01:28:47 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-082cd734-c779-4540-9b0a-6cc0c6ce1e2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1484849408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1484849408 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3555128124 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10569287 ps |
| CPU time | 0.43 seconds |
| Started | May 19 01:28:42 PM PDT 24 |
| Finished | May 19 01:28:45 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-d17c581e-e45d-44ba-a638-2dd1655598d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3555128124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3555128124 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.1966713624 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11376842 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:28:42 PM PDT 24 |
| Finished | May 19 01:28:45 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-f4382b6c-162c-4c7f-8111-fa838b0d1d4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1966713624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1966713624 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.3053569446 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11270724 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:28:45 PM PDT 24 |
| Finished | May 19 01:28:50 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-66dcf3a4-a61e-4ec2-92df-a65381c32f83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053569446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3053569446 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.3758625505 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11436504 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:28:43 PM PDT 24 |
| Finished | May 19 01:28:47 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-e2f1c0b7-381d-45d1-81ec-90cd147e3d2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3758625505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3758625505 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3243538974 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12359932 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:28:43 PM PDT 24 |
| Finished | May 19 01:28:47 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-9c65ff2d-f2b8-43fa-a8a2-5087db61a6e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3243538974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3243538974 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3562259108 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11724488 ps |
| CPU time | 0.38 seconds |
| Started | May 19 01:28:41 PM PDT 24 |
| Finished | May 19 01:28:43 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-91c5895c-b9c0-4862-b1dd-d6a07afd3b30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3562259108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3562259108 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.3400954710 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10236105 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:28:48 PM PDT 24 |
| Finished | May 19 01:28:53 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-190da30f-bfe8-45aa-9ad0-6db05b479448 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400954710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3400954710 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.631615779 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11673497 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:28:42 PM PDT 24 |
| Finished | May 19 01:28:46 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-751e228c-b534-470f-a41f-c5287f500a44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631615779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.631615779 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.467956643 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10694501 ps |
| CPU time | 0.38 seconds |
| Started | May 19 01:28:41 PM PDT 24 |
| Finished | May 19 01:28:43 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-be03dce1-3652-448f-b069-b39099e9777e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=467956643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.467956643 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.456761241 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11872008 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:28:39 PM PDT 24 |
| Finished | May 19 01:28:41 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-4644e717-7b51-445c-a049-20ea8af43ec6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=456761241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.456761241 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.3196068141 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12063904 ps |
| CPU time | 0.38 seconds |
| Started | May 19 01:28:44 PM PDT 24 |
| Finished | May 19 01:28:48 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-51e39eda-49c5-4086-8286-3ef0b4ed7756 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196068141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3196068141 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1257837859 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29643989 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:29:17 PM PDT 24 |
| Finished | May 19 01:29:19 PM PDT 24 |
| Peak memory | 145752 kb |
| Host | smart-3e1f2d6f-1d5a-4fb8-8790-8ab278137cae |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1257837859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1257837859 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.959456646 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 30656782 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:29:17 PM PDT 24 |
| Finished | May 19 01:29:20 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-876f6f97-5c51-4c2c-92c2-d2cf70592992 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=959456646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.959456646 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.68097816 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 31363494 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:29:19 PM PDT 24 |
| Finished | May 19 01:29:21 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-3b081105-1fd2-4ae6-9afb-f9f5153f1f3f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=68097816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.68097816 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3368862101 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 31394453 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:29:17 PM PDT 24 |
| Finished | May 19 01:29:19 PM PDT 24 |
| Peak memory | 145756 kb |
| Host | smart-fb87e7a3-6fee-40be-a16a-b52ff574ead5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3368862101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3368862101 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.4142646286 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 29952581 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:29:21 PM PDT 24 |
| Finished | May 19 01:29:23 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-a887ee67-0107-49ae-bbd1-c97dcf7e5e0a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4142646286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.4142646286 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3923207569 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 31168765 ps |
| CPU time | 0.44 seconds |
| Started | May 19 01:29:19 PM PDT 24 |
| Finished | May 19 01:29:21 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-109b0a59-af0f-414c-bc5a-d7faf5862fe6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3923207569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3923207569 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1226144258 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 30497880 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:29:19 PM PDT 24 |
| Finished | May 19 01:29:21 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-f99390e7-70b3-4c9e-a758-9029cef7dd40 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1226144258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1226144258 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1216866525 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29516934 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:29:18 PM PDT 24 |
| Finished | May 19 01:29:20 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-e4ecc91a-4106-4631-b3f0-0b7e0c15c129 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1216866525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1216866525 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3788846407 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30886405 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:29:19 PM PDT 24 |
| Finished | May 19 01:29:22 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-2e5c477f-128e-40b2-9325-e97b50876285 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3788846407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3788846407 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.47626658 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29824932 ps |
| CPU time | 0.47 seconds |
| Started | May 19 01:29:19 PM PDT 24 |
| Finished | May 19 01:29:21 PM PDT 24 |
| Peak memory | 145680 kb |
| Host | smart-dde4cdc4-2c30-4f18-a21a-a2a4b67fb116 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=47626658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.47626658 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1309509180 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 31566012 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:29:21 PM PDT 24 |
| Finished | May 19 01:29:23 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-3de6333c-165e-4be8-9e41-d94557ab9d7c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1309509180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1309509180 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.208147870 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 30318801 ps |
| CPU time | 0.42 seconds |
| Started | May 19 01:29:19 PM PDT 24 |
| Finished | May 19 01:29:21 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-ca302224-7c9c-4cdb-8192-6f9d98467122 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=208147870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.208147870 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.206227073 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30268160 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:29:17 PM PDT 24 |
| Finished | May 19 01:29:19 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-37f6f849-4836-4844-9456-5cf1425ac44f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=206227073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.206227073 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1100418853 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 29791694 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:29:21 PM PDT 24 |
| Finished | May 19 01:29:23 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-e8dd5b6d-6542-4c3c-8b68-d0d4ed1a2cba |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1100418853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1100418853 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.285878236 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 30109539 ps |
| CPU time | 0.42 seconds |
| Started | May 19 01:29:17 PM PDT 24 |
| Finished | May 19 01:29:20 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-6dcef194-328d-46f2-9153-585696cc7f78 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=285878236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.285878236 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.243278445 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 31093681 ps |
| CPU time | 0.44 seconds |
| Started | May 19 01:29:18 PM PDT 24 |
| Finished | May 19 01:29:21 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-807b4f2e-8726-41bb-ae51-e71ed5eac6e0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=243278445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.243278445 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3315981399 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 28644339 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:29:18 PM PDT 24 |
| Finished | May 19 01:29:20 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-dd9321fa-ef8f-4b86-869a-79a606f3065a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3315981399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3315981399 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2634424365 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 31429311 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:29:19 PM PDT 24 |
| Finished | May 19 01:29:21 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-d31c2a15-c9e3-4c83-b3b5-30c2ed134a07 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2634424365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2634424365 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3849418517 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29008780 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:29:19 PM PDT 24 |
| Finished | May 19 01:29:21 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-a95c3f66-3c15-4a35-94a8-95610014d943 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3849418517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3849418517 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.3336069865 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 9287072 ps |
| CPU time | 0.38 seconds |
| Started | May 19 01:25:40 PM PDT 24 |
| Finished | May 19 01:25:41 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-7d86412a-c1d1-44db-a625-a21ad8872ab0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3336069865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3336069865 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.4192892200 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9640604 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:45 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-d53e6129-53ca-400b-919d-c95cb5899217 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4192892200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.4192892200 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3799876680 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9879708 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:25:40 PM PDT 24 |
| Finished | May 19 01:25:42 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-0a9c5012-8aa1-448e-b9a1-c31271c5add7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3799876680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3799876680 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.4063137863 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10099932 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:25:39 PM PDT 24 |
| Finished | May 19 01:25:40 PM PDT 24 |
| Peak memory | 145692 kb |
| Host | smart-371bb5a4-9239-49a8-ad43-34eaf56f6b66 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4063137863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.4063137863 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3922918798 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9606882 ps |
| CPU time | 0.38 seconds |
| Started | May 19 01:25:40 PM PDT 24 |
| Finished | May 19 01:25:42 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-4ae810fa-dbf2-4bd9-b047-54ce3271680e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3922918798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3922918798 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.994816543 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8420545 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:45 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-ffabb054-6e71-4bf1-abee-fe47e809b06e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=994816543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.994816543 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1218857423 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8809952 ps |
| CPU time | 0.38 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:45 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-7b97c297-1afa-4413-a2b2-58a4505505a4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1218857423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1218857423 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.941120911 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 9707066 ps |
| CPU time | 0.38 seconds |
| Started | May 19 01:25:45 PM PDT 24 |
| Finished | May 19 01:25:46 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-583a5175-f0d9-41e6-9146-9e6c52405ac2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=941120911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.941120911 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.3540884311 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9144977 ps |
| CPU time | 0.37 seconds |
| Started | May 19 01:25:40 PM PDT 24 |
| Finished | May 19 01:25:41 PM PDT 24 |
| Peak memory | 145524 kb |
| Host | smart-7f7889ff-1131-4c0a-a24e-1c8dfcb4621b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3540884311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3540884311 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.853753446 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9274822 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:44 PM PDT 24 |
| Peak memory | 145516 kb |
| Host | smart-1c7c17f0-155e-4336-b677-a426eb332062 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=853753446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.853753446 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.1688964555 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9356640 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:45 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-94f3d3c9-a07e-48ac-9b98-5a6911f5f4ae |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1688964555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1688964555 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.228905818 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9460228 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:25:40 PM PDT 24 |
| Finished | May 19 01:25:42 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-16e7d236-221d-49e2-88bf-6a02d2ae2d9a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=228905818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.228905818 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2873755707 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9251945 ps |
| CPU time | 0.38 seconds |
| Started | May 19 01:25:39 PM PDT 24 |
| Finished | May 19 01:25:40 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-ea64d725-ba10-48ed-a08e-736939d8e44d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2873755707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2873755707 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.2117465219 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8062171 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:25:42 PM PDT 24 |
| Finished | May 19 01:25:43 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-6d94aa4c-ec78-48b1-a32b-5b46b442e345 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2117465219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2117465219 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.3153654643 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9158746 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:25:41 PM PDT 24 |
| Finished | May 19 01:25:43 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-d58e080e-7a52-406b-afde-7d66b19f1d94 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3153654643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3153654643 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.863078367 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9343332 ps |
| CPU time | 0.37 seconds |
| Started | May 19 01:25:40 PM PDT 24 |
| Finished | May 19 01:25:41 PM PDT 24 |
| Peak memory | 145516 kb |
| Host | smart-b6f19bb1-0514-44d1-ba5d-50565c3d44b0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=863078367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.863078367 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.207492179 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8779565 ps |
| CPU time | 0.38 seconds |
| Started | May 19 01:25:41 PM PDT 24 |
| Finished | May 19 01:25:42 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-736c390f-9cca-492f-838d-8d4ab6b2c696 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=207492179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.207492179 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.3402335056 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8885634 ps |
| CPU time | 0.42 seconds |
| Started | May 19 01:25:45 PM PDT 24 |
| Finished | May 19 01:25:47 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-70efed15-530f-4680-925f-d381205b8dd9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3402335056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3402335056 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1927693162 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10166136 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:25:42 PM PDT 24 |
| Finished | May 19 01:25:43 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-da7c1ce3-e883-405d-925d-29adc33696b5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1927693162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1927693162 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.6680313 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28521746 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:45 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-c06fe12a-aee4-4f55-99df-1f003195a798 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=6680313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.6680313 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2229210484 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27040339 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:45 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-74f1bdd8-3a71-469c-b537-b3026d6b14af |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2229210484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2229210484 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1116084744 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 24481414 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:25:49 PM PDT 24 |
| Finished | May 19 01:25:50 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-603acdf8-141a-48f1-ad5e-c48c5bd72828 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1116084744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1116084744 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.933143168 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 29093728 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:45 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-3dcf135d-ae5f-4334-83df-0d5f401a4a1b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=933143168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.933143168 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2276831465 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 28704142 ps |
| CPU time | 0.44 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:46 PM PDT 24 |
| Peak memory | 145536 kb |
| Host | smart-2f73cd0f-51ad-4165-9525-1a596b4b66d2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2276831465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2276831465 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2257364509 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 26675354 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:45 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-ac322e59-e766-403f-8fb8-576a7674ede4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2257364509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2257364509 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.4218296948 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27660221 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:25:49 PM PDT 24 |
| Finished | May 19 01:25:50 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-30d873c7-839f-453f-9d32-edbe8d9088b3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4218296948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.4218296948 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.730540966 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 26899434 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:25:46 PM PDT 24 |
| Finished | May 19 01:25:48 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-ad6f211f-0754-431c-bced-720f3d937110 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=730540966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.730540966 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2452515197 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27391332 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:25:44 PM PDT 24 |
| Finished | May 19 01:25:46 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-3a88bf24-5a97-4800-8d1a-e7b7dbd09768 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2452515197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2452515197 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3051167329 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26660065 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:25:45 PM PDT 24 |
| Finished | May 19 01:25:46 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-c8780a97-8177-450e-b4d4-43e9aaeec953 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3051167329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3051167329 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2715984539 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28457084 ps |
| CPU time | 0.42 seconds |
| Started | May 19 01:25:45 PM PDT 24 |
| Finished | May 19 01:25:46 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-cbab94c1-9ad3-49c7-9cc7-b48bd0111086 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2715984539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2715984539 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.530306055 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26459887 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:25:41 PM PDT 24 |
| Finished | May 19 01:25:43 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-13616ea4-96a5-46ce-9e21-0eab3cb335c5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=530306055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.530306055 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3792876799 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26642273 ps |
| CPU time | 0.42 seconds |
| Started | May 19 01:25:40 PM PDT 24 |
| Finished | May 19 01:25:42 PM PDT 24 |
| Peak memory | 145732 kb |
| Host | smart-d93efe5e-a89b-49e9-8fd0-37e18ba2c942 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3792876799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3792876799 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.842969836 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 27565166 ps |
| CPU time | 0.4 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:46 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-a5cd97ba-370a-4b24-8310-ae4d3e2dcaf9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=842969836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.842969836 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.823982717 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 25003961 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:25:41 PM PDT 24 |
| Finished | May 19 01:25:42 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-c602ad2d-0ffe-4ee0-a2ee-3c53579a04bd |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=823982717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.823982717 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1517598021 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26601722 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:46 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-6f64fd8b-9234-4738-b9ee-5cd2471269b5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1517598021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1517598021 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2454401328 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27620766 ps |
| CPU time | 0.41 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:45 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-b800d76a-c1ab-4596-b797-4600dbc68b4b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2454401328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2454401328 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.741591395 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 25926843 ps |
| CPU time | 0.38 seconds |
| Started | May 19 01:25:43 PM PDT 24 |
| Finished | May 19 01:25:45 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-d43a5732-10c9-4520-838e-0445b60d950c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=741591395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.741591395 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2836701076 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 27129544 ps |
| CPU time | 0.39 seconds |
| Started | May 19 01:25:45 PM PDT 24 |
| Finished | May 19 01:25:46 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-df50c26b-84ba-401e-9a25-c1ed79287365 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2836701076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2836701076 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |