| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.42 | 88.42 | 100.00 | 100.00 | 95.83 | 95.83 | 96.43 | 96.43 | 75.00 | 75.00 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/7.prim_async_alert.3561555248 |
| 91.55 | 3.13 | 100.00 | 0.00 | 95.83 | 0.00 | 96.43 | 0.00 | 82.14 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/15.prim_sync_alert.3600274535 |
| 93.90 | 2.35 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 3.57 | 85.71 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1344884954 |
| 94.50 | 0.60 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.278935826 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3166473701 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.2400525159 |
| /workspace/coverage/default/1.prim_async_alert.382919881 |
| /workspace/coverage/default/10.prim_async_alert.3530896760 |
| /workspace/coverage/default/11.prim_async_alert.2707221481 |
| /workspace/coverage/default/12.prim_async_alert.1638677337 |
| /workspace/coverage/default/13.prim_async_alert.1368199321 |
| /workspace/coverage/default/14.prim_async_alert.326720399 |
| /workspace/coverage/default/16.prim_async_alert.1898466319 |
| /workspace/coverage/default/17.prim_async_alert.3924120179 |
| /workspace/coverage/default/18.prim_async_alert.1452704278 |
| /workspace/coverage/default/19.prim_async_alert.3534188285 |
| /workspace/coverage/default/2.prim_async_alert.3439871683 |
| /workspace/coverage/default/3.prim_async_alert.2569376051 |
| /workspace/coverage/default/4.prim_async_alert.983745682 |
| /workspace/coverage/default/5.prim_async_alert.2681521723 |
| /workspace/coverage/default/6.prim_async_alert.3845041421 |
| /workspace/coverage/default/8.prim_async_alert.3870114282 |
| /workspace/coverage/default/9.prim_async_alert.1530183816 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3372035230 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1250319053 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.833081365 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2314842027 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.573585182 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1947337249 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2089143020 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2794389772 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1164935346 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.261619031 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.440224995 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.541826222 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3528088807 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2992182773 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.763622659 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2669607293 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.3822149346 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.3809691601 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3209317543 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.158586338 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3260033155 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.2462238066 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.2252191657 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.2331562273 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.461152552 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.1661444419 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.3672329958 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2748225307 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3058477352 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.2024102764 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.2055722303 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.3929738138 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.4278644827 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.2826029857 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.3965004613 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1091110960 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2296084960 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3703744288 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.410327168 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.610772725 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1918403679 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.715082981 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2197410955 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.118303535 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2964203743 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2572011716 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1233862053 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3617200273 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.936812140 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2483359980 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4285712885 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2091712126 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2222826558 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3420496567 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3673373934 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_async_alert.1530183816 | May 21 12:50:24 PM PDT 24 | May 21 12:50:34 PM PDT 24 | 10150909 ps | ||
| T2 | /workspace/coverage/default/8.prim_async_alert.3870114282 | May 21 12:50:30 PM PDT 24 | May 21 12:50:40 PM PDT 24 | 11029404 ps | ||
| T3 | /workspace/coverage/default/1.prim_async_alert.382919881 | May 21 12:50:25 PM PDT 24 | May 21 12:50:36 PM PDT 24 | 10756362 ps | ||
| T10 | /workspace/coverage/default/2.prim_async_alert.3439871683 | May 21 12:50:29 PM PDT 24 | May 21 12:50:39 PM PDT 24 | 12153191 ps | ||
| T12 | /workspace/coverage/default/18.prim_async_alert.1452704278 | May 21 12:50:30 PM PDT 24 | May 21 12:50:40 PM PDT 24 | 10958987 ps | ||
| T7 | /workspace/coverage/default/7.prim_async_alert.3561555248 | May 21 12:50:25 PM PDT 24 | May 21 12:50:35 PM PDT 24 | 10761811 ps | ||
| T8 | /workspace/coverage/default/13.prim_async_alert.1368199321 | May 21 12:50:40 PM PDT 24 | May 21 12:50:47 PM PDT 24 | 12406289 ps | ||
| T9 | /workspace/coverage/default/12.prim_async_alert.1638677337 | May 21 12:50:29 PM PDT 24 | May 21 12:50:40 PM PDT 24 | 10901078 ps | ||
| T19 | /workspace/coverage/default/17.prim_async_alert.3924120179 | May 21 12:50:20 PM PDT 24 | May 21 12:50:30 PM PDT 24 | 10590050 ps | ||
| T20 | /workspace/coverage/default/4.prim_async_alert.983745682 | May 21 12:50:27 PM PDT 24 | May 21 12:50:38 PM PDT 24 | 10707341 ps | ||
| T18 | /workspace/coverage/default/5.prim_async_alert.2681521723 | May 21 12:50:31 PM PDT 24 | May 21 12:50:40 PM PDT 24 | 10896295 ps | ||
| T42 | /workspace/coverage/default/14.prim_async_alert.326720399 | May 21 12:50:27 PM PDT 24 | May 21 12:50:38 PM PDT 24 | 11762635 ps | ||
| T21 | /workspace/coverage/default/16.prim_async_alert.1898466319 | May 21 12:50:24 PM PDT 24 | May 21 12:50:34 PM PDT 24 | 10925132 ps | ||
| T43 | /workspace/coverage/default/10.prim_async_alert.3530896760 | May 21 12:50:21 PM PDT 24 | May 21 12:50:32 PM PDT 24 | 10722522 ps | ||
| T11 | /workspace/coverage/default/19.prim_async_alert.3534188285 | May 21 12:50:22 PM PDT 24 | May 21 12:50:33 PM PDT 24 | 11194707 ps | ||
| T44 | /workspace/coverage/default/11.prim_async_alert.2707221481 | May 21 12:50:26 PM PDT 24 | May 21 12:50:36 PM PDT 24 | 11367394 ps | ||
| T45 | /workspace/coverage/default/6.prim_async_alert.3845041421 | May 21 12:50:22 PM PDT 24 | May 21 12:50:32 PM PDT 24 | 11287602 ps | ||
| T46 | /workspace/coverage/default/3.prim_async_alert.2569376051 | May 21 12:50:20 PM PDT 24 | May 21 12:50:30 PM PDT 24 | 10776624 ps | ||
| T47 | /workspace/coverage/default/0.prim_async_alert.2400525159 | May 21 12:50:20 PM PDT 24 | May 21 12:50:30 PM PDT 24 | 10937702 ps | ||
| T4 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3166473701 | May 21 01:03:31 PM PDT 24 | May 21 01:03:32 PM PDT 24 | 28689124 ps | ||
| T13 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.261619031 | May 21 01:03:33 PM PDT 24 | May 21 01:03:35 PM PDT 24 | 31079683 ps | ||
| T39 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1947337249 | May 21 01:03:33 PM PDT 24 | May 21 01:03:35 PM PDT 24 | 29135978 ps | ||
| T22 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1164935346 | May 21 01:03:34 PM PDT 24 | May 21 01:03:36 PM PDT 24 | 28515790 ps | ||
| T23 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1344884954 | May 21 01:03:33 PM PDT 24 | May 21 01:03:35 PM PDT 24 | 30993171 ps | ||
| T40 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2992182773 | May 21 01:03:31 PM PDT 24 | May 21 01:03:33 PM PDT 24 | 29635403 ps | ||
| T41 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.573585182 | May 21 01:03:34 PM PDT 24 | May 21 01:03:36 PM PDT 24 | 30775752 ps | ||
| T24 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3372035230 | May 21 01:03:26 PM PDT 24 | May 21 01:03:28 PM PDT 24 | 29332447 ps | ||
| T25 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2089143020 | May 21 01:03:33 PM PDT 24 | May 21 01:03:34 PM PDT 24 | 30472080 ps | ||
| T16 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2669607293 | May 21 01:03:34 PM PDT 24 | May 21 01:03:36 PM PDT 24 | 29825487 ps | ||
| T48 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.440224995 | May 21 01:03:32 PM PDT 24 | May 21 01:03:33 PM PDT 24 | 30721594 ps | ||
| T49 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3528088807 | May 21 01:03:32 PM PDT 24 | May 21 01:03:34 PM PDT 24 | 30554134 ps | ||
| T50 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2314842027 | May 21 01:03:33 PM PDT 24 | May 21 01:03:34 PM PDT 24 | 28685826 ps | ||
| T51 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.541826222 | May 21 01:03:33 PM PDT 24 | May 21 01:03:35 PM PDT 24 | 30828584 ps | ||
| T52 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.763622659 | May 21 01:03:32 PM PDT 24 | May 21 01:03:33 PM PDT 24 | 29528017 ps | ||
| T14 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.278935826 | May 21 01:03:26 PM PDT 24 | May 21 01:03:27 PM PDT 24 | 28061448 ps | ||
| T53 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2794389772 | May 21 01:03:34 PM PDT 24 | May 21 01:03:36 PM PDT 24 | 31916917 ps | ||
| T54 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.833081365 | May 21 01:03:34 PM PDT 24 | May 21 01:03:36 PM PDT 24 | 31138017 ps | ||
| T55 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1250319053 | May 21 01:03:31 PM PDT 24 | May 21 01:03:32 PM PDT 24 | 32352813 ps | ||
| T35 | /workspace/coverage/sync_alert/10.prim_sync_alert.3209317543 | May 21 01:03:39 PM PDT 24 | May 21 01:03:40 PM PDT 24 | 9936348 ps | ||
| T36 | /workspace/coverage/sync_alert/3.prim_sync_alert.3058477352 | May 21 01:03:33 PM PDT 24 | May 21 01:03:35 PM PDT 24 | 9590645 ps | ||
| T26 | /workspace/coverage/sync_alert/0.prim_sync_alert.3822149346 | May 21 01:03:32 PM PDT 24 | May 21 01:03:34 PM PDT 24 | 9894451 ps | ||
| T37 | /workspace/coverage/sync_alert/8.prim_sync_alert.2826029857 | May 21 01:03:38 PM PDT 24 | May 21 01:03:39 PM PDT 24 | 10340405 ps | ||
| T27 | /workspace/coverage/sync_alert/17.prim_sync_alert.461152552 | May 21 01:03:45 PM PDT 24 | May 21 01:03:46 PM PDT 24 | 9226151 ps | ||
| T17 | /workspace/coverage/sync_alert/2.prim_sync_alert.2748225307 | May 21 01:03:33 PM PDT 24 | May 21 01:03:34 PM PDT 24 | 8821283 ps | ||
| T28 | /workspace/coverage/sync_alert/19.prim_sync_alert.3672329958 | May 21 01:03:44 PM PDT 24 | May 21 01:03:45 PM PDT 24 | 9132452 ps | ||
| T29 | /workspace/coverage/sync_alert/7.prim_sync_alert.4278644827 | May 21 01:03:39 PM PDT 24 | May 21 01:03:39 PM PDT 24 | 8477539 ps | ||
| T30 | /workspace/coverage/sync_alert/15.prim_sync_alert.3600274535 | May 21 01:03:45 PM PDT 24 | May 21 01:03:47 PM PDT 24 | 9216146 ps | ||
| T38 | /workspace/coverage/sync_alert/4.prim_sync_alert.2024102764 | May 21 01:03:39 PM PDT 24 | May 21 01:03:40 PM PDT 24 | 8623447 ps | ||
| T15 | /workspace/coverage/sync_alert/5.prim_sync_alert.2055722303 | May 21 01:03:39 PM PDT 24 | May 21 01:03:40 PM PDT 24 | 9670904 ps | ||
| T56 | /workspace/coverage/sync_alert/11.prim_sync_alert.158586338 | May 21 01:03:39 PM PDT 24 | May 21 01:03:39 PM PDT 24 | 8533591 ps | ||
| T31 | /workspace/coverage/sync_alert/1.prim_sync_alert.3809691601 | May 21 01:03:35 PM PDT 24 | May 21 01:03:36 PM PDT 24 | 7833056 ps | ||
| T57 | /workspace/coverage/sync_alert/18.prim_sync_alert.1661444419 | May 21 01:03:45 PM PDT 24 | May 21 01:03:47 PM PDT 24 | 9713008 ps | ||
| T32 | /workspace/coverage/sync_alert/13.prim_sync_alert.2462238066 | May 21 01:03:44 PM PDT 24 | May 21 01:03:45 PM PDT 24 | 8855875 ps | ||
| T58 | /workspace/coverage/sync_alert/14.prim_sync_alert.2252191657 | May 21 01:03:44 PM PDT 24 | May 21 01:03:45 PM PDT 24 | 10154712 ps | ||
| T59 | /workspace/coverage/sync_alert/12.prim_sync_alert.3260033155 | May 21 01:03:44 PM PDT 24 | May 21 01:03:46 PM PDT 24 | 9169524 ps | ||
| T60 | /workspace/coverage/sync_alert/6.prim_sync_alert.3929738138 | May 21 01:03:40 PM PDT 24 | May 21 01:03:41 PM PDT 24 | 8813432 ps | ||
| T33 | /workspace/coverage/sync_alert/9.prim_sync_alert.3965004613 | May 21 01:03:38 PM PDT 24 | May 21 01:03:39 PM PDT 24 | 9162945 ps | ||
| T61 | /workspace/coverage/sync_alert/16.prim_sync_alert.2331562273 | May 21 01:03:44 PM PDT 24 | May 21 01:03:45 PM PDT 24 | 9293505 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2572011716 | May 21 12:50:32 PM PDT 24 | May 21 12:50:41 PM PDT 24 | 27481126 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2091712126 | May 21 12:50:26 PM PDT 24 | May 21 12:50:37 PM PDT 24 | 27285451 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.715082981 | May 21 12:50:34 PM PDT 24 | May 21 12:50:43 PM PDT 24 | 27817191 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1233862053 | May 21 12:50:26 PM PDT 24 | May 21 12:50:36 PM PDT 24 | 29340703 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1091110960 | May 21 12:50:25 PM PDT 24 | May 21 12:50:35 PM PDT 24 | 27771799 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3673373934 | May 21 12:50:26 PM PDT 24 | May 21 12:50:36 PM PDT 24 | 26262164 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2964203743 | May 21 12:50:28 PM PDT 24 | May 21 12:50:38 PM PDT 24 | 28904667 ps | ||
| T34 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4285712885 | May 21 12:50:21 PM PDT 24 | May 21 12:50:31 PM PDT 24 | 27482496 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2483359980 | May 21 12:50:28 PM PDT 24 | May 21 12:50:38 PM PDT 24 | 26206172 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.118303535 | May 21 12:50:26 PM PDT 24 | May 21 12:50:37 PM PDT 24 | 27860410 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.936812140 | May 21 12:50:21 PM PDT 24 | May 21 12:50:32 PM PDT 24 | 27634376 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3617200273 | May 21 12:50:39 PM PDT 24 | May 21 12:50:46 PM PDT 24 | 27248536 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2222826558 | May 21 12:50:33 PM PDT 24 | May 21 12:50:42 PM PDT 24 | 28283661 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3703744288 | May 21 12:50:27 PM PDT 24 | May 21 12:50:38 PM PDT 24 | 25398405 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2197410955 | May 21 12:50:20 PM PDT 24 | May 21 12:50:31 PM PDT 24 | 26919825 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1918403679 | May 21 12:50:27 PM PDT 24 | May 21 12:50:38 PM PDT 24 | 29038607 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3420496567 | May 21 12:50:30 PM PDT 24 | May 21 12:50:40 PM PDT 24 | 29464292 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2296084960 | May 21 12:50:33 PM PDT 24 | May 21 12:50:43 PM PDT 24 | 26831476 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.410327168 | May 21 12:50:20 PM PDT 24 | May 21 12:50:30 PM PDT 24 | 26431882 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.610772725 | May 21 12:50:23 PM PDT 24 | May 21 12:50:34 PM PDT 24 | 27033734 ps |
| Test location | /workspace/coverage/default/7.prim_async_alert.3561555248 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10761811 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:25 PM PDT 24 |
| Finished | May 21 12:50:35 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-2eac9236-3723-44d7-8ecd-55bf43a1946c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3561555248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3561555248 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3600274535 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9216146 ps |
| CPU time | 0.39 seconds |
| Started | May 21 01:03:45 PM PDT 24 |
| Finished | May 21 01:03:47 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-3485e041-7729-4161-826a-05c837f61a2f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3600274535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3600274535 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1344884954 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 30993171 ps |
| CPU time | 0.4 seconds |
| Started | May 21 01:03:33 PM PDT 24 |
| Finished | May 21 01:03:35 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-129a6289-967f-4808-b4fe-3d53ae37a4dd |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1344884954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1344884954 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.278935826 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 28061448 ps |
| CPU time | 0.42 seconds |
| Started | May 21 01:03:26 PM PDT 24 |
| Finished | May 21 01:03:27 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-d4314101-a217-473d-91b1-35c5864a33ec |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=278935826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.278935826 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3166473701 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28689124 ps |
| CPU time | 0.39 seconds |
| Started | May 21 01:03:31 PM PDT 24 |
| Finished | May 21 01:03:32 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-e8bc3e9e-11e5-4f7a-adcb-560b56287b5a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3166473701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3166473701 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.2400525159 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10937702 ps |
| CPU time | 0.38 seconds |
| Started | May 21 12:50:20 PM PDT 24 |
| Finished | May 21 12:50:30 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-260c0fe7-e032-4887-8718-686597a98820 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2400525159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2400525159 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.382919881 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10756362 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:25 PM PDT 24 |
| Finished | May 21 12:50:36 PM PDT 24 |
| Peak memory | 145952 kb |
| Host | smart-366780bb-bd15-40da-ad4d-4aa60fabdaed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=382919881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.382919881 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.3530896760 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 10722522 ps |
| CPU time | 0.37 seconds |
| Started | May 21 12:50:21 PM PDT 24 |
| Finished | May 21 12:50:32 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-b140c541-df4c-47bd-ae55-fd5e62acfe61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3530896760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3530896760 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.2707221481 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11367394 ps |
| CPU time | 0.4 seconds |
| Started | May 21 12:50:26 PM PDT 24 |
| Finished | May 21 12:50:36 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-34edd5d5-8bd4-431a-8b5c-e772ed66c730 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2707221481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2707221481 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.1638677337 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10901078 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:29 PM PDT 24 |
| Finished | May 21 12:50:40 PM PDT 24 |
| Peak memory | 145864 kb |
| Host | smart-ecec8686-26fe-4070-9bfc-219118fbea3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638677337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1638677337 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1368199321 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12406289 ps |
| CPU time | 0.38 seconds |
| Started | May 21 12:50:40 PM PDT 24 |
| Finished | May 21 12:50:47 PM PDT 24 |
| Peak memory | 145864 kb |
| Host | smart-434e95b0-0e8e-4ae9-a933-06a7ce9acdd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1368199321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1368199321 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.326720399 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11762635 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:27 PM PDT 24 |
| Finished | May 21 12:50:38 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-68f1ba63-b28c-491c-9b3c-6d4d636c4dee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326720399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.326720399 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.1898466319 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10925132 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:24 PM PDT 24 |
| Finished | May 21 12:50:34 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-41fac623-43c6-43dd-898c-61918102701d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898466319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1898466319 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.3924120179 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10590050 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:20 PM PDT 24 |
| Finished | May 21 12:50:30 PM PDT 24 |
| Peak memory | 145848 kb |
| Host | smart-e71133bd-65d5-45e0-b69b-8ab13eafe502 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924120179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3924120179 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.1452704278 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10958987 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:30 PM PDT 24 |
| Finished | May 21 12:50:40 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-4bc87b21-339c-43a6-b192-5e45477ca5f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452704278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1452704278 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3534188285 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11194707 ps |
| CPU time | 0.38 seconds |
| Started | May 21 12:50:22 PM PDT 24 |
| Finished | May 21 12:50:33 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-d45aeb2a-7783-4292-a023-e3655d977548 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3534188285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3534188285 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3439871683 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12153191 ps |
| CPU time | 0.4 seconds |
| Started | May 21 12:50:29 PM PDT 24 |
| Finished | May 21 12:50:39 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-6843859d-2d9b-4a88-86e4-6cf969291cb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3439871683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3439871683 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.2569376051 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10776624 ps |
| CPU time | 0.38 seconds |
| Started | May 21 12:50:20 PM PDT 24 |
| Finished | May 21 12:50:30 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-a9d5fe2a-b01e-4496-bdcc-8887961272ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569376051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2569376051 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.983745682 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10707341 ps |
| CPU time | 0.37 seconds |
| Started | May 21 12:50:27 PM PDT 24 |
| Finished | May 21 12:50:38 PM PDT 24 |
| Peak memory | 145872 kb |
| Host | smart-bf3589e3-0803-4037-9382-533d0ddb9be8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983745682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.983745682 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.2681521723 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10896295 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:31 PM PDT 24 |
| Finished | May 21 12:50:40 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-4b297c8b-0b8c-4290-ae3a-00ac3cbfdcca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2681521723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2681521723 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.3845041421 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11287602 ps |
| CPU time | 0.38 seconds |
| Started | May 21 12:50:22 PM PDT 24 |
| Finished | May 21 12:50:32 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-3307fd82-1e02-47ea-a3bc-aaa642c46034 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3845041421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3845041421 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.3870114282 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11029404 ps |
| CPU time | 0.38 seconds |
| Started | May 21 12:50:30 PM PDT 24 |
| Finished | May 21 12:50:40 PM PDT 24 |
| Peak memory | 145860 kb |
| Host | smart-f5d7bae2-41ff-4022-a36c-4e4c79ab17dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3870114282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3870114282 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1530183816 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10150909 ps |
| CPU time | 0.4 seconds |
| Started | May 21 12:50:24 PM PDT 24 |
| Finished | May 21 12:50:34 PM PDT 24 |
| Peak memory | 145884 kb |
| Host | smart-291b0038-bdbb-47d9-b20d-34602a0c16e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530183816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1530183816 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3372035230 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 29332447 ps |
| CPU time | 0.41 seconds |
| Started | May 21 01:03:26 PM PDT 24 |
| Finished | May 21 01:03:28 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-7070e38a-e153-4ed3-9ef7-2ee27c8bb017 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3372035230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3372035230 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1250319053 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 32352813 ps |
| CPU time | 0.4 seconds |
| Started | May 21 01:03:31 PM PDT 24 |
| Finished | May 21 01:03:32 PM PDT 24 |
| Peak memory | 145852 kb |
| Host | smart-6588be17-3c36-48ef-9c8a-49443fb49cea |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1250319053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1250319053 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.833081365 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 31138017 ps |
| CPU time | 0.4 seconds |
| Started | May 21 01:03:34 PM PDT 24 |
| Finished | May 21 01:03:36 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-8c19ea80-4635-4f7b-859f-2c9037048578 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=833081365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.833081365 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2314842027 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 28685826 ps |
| CPU time | 0.4 seconds |
| Started | May 21 01:03:33 PM PDT 24 |
| Finished | May 21 01:03:34 PM PDT 24 |
| Peak memory | 145832 kb |
| Host | smart-5c2db0f3-df2a-447e-8cbd-babd28656345 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2314842027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2314842027 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.573585182 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30775752 ps |
| CPU time | 0.42 seconds |
| Started | May 21 01:03:34 PM PDT 24 |
| Finished | May 21 01:03:36 PM PDT 24 |
| Peak memory | 145860 kb |
| Host | smart-6bcb0a0c-932b-4838-b6ab-9a82a8e3337c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=573585182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.573585182 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1947337249 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 29135978 ps |
| CPU time | 0.41 seconds |
| Started | May 21 01:03:33 PM PDT 24 |
| Finished | May 21 01:03:35 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-32bf3189-7e96-4853-9f27-81a5443ea188 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1947337249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1947337249 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2089143020 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 30472080 ps |
| CPU time | 0.41 seconds |
| Started | May 21 01:03:33 PM PDT 24 |
| Finished | May 21 01:03:34 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-435b104b-4f14-435d-a8c4-2f19784da854 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2089143020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2089143020 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2794389772 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 31916917 ps |
| CPU time | 0.41 seconds |
| Started | May 21 01:03:34 PM PDT 24 |
| Finished | May 21 01:03:36 PM PDT 24 |
| Peak memory | 145832 kb |
| Host | smart-ff50870f-f48d-4d61-8c52-f0867d1859bd |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2794389772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2794389772 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1164935346 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 28515790 ps |
| CPU time | 0.4 seconds |
| Started | May 21 01:03:34 PM PDT 24 |
| Finished | May 21 01:03:36 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-5170894c-8d40-4030-9408-14274f1bf52b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1164935346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1164935346 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.261619031 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 31079683 ps |
| CPU time | 0.4 seconds |
| Started | May 21 01:03:33 PM PDT 24 |
| Finished | May 21 01:03:35 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-2c795b61-04a6-4da1-a328-980bd43f05cc |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=261619031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.261619031 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.440224995 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30721594 ps |
| CPU time | 0.4 seconds |
| Started | May 21 01:03:32 PM PDT 24 |
| Finished | May 21 01:03:33 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-2102e4fd-6708-4b7e-9158-9010e7bc16ec |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=440224995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.440224995 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.541826222 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30828584 ps |
| CPU time | 0.41 seconds |
| Started | May 21 01:03:33 PM PDT 24 |
| Finished | May 21 01:03:35 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-dbb24e4c-ea63-45f5-af16-4f22788b4388 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=541826222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.541826222 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3528088807 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 30554134 ps |
| CPU time | 0.39 seconds |
| Started | May 21 01:03:32 PM PDT 24 |
| Finished | May 21 01:03:34 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-42f7077c-a26f-47cb-82a3-04908f1d8190 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3528088807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3528088807 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2992182773 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29635403 ps |
| CPU time | 0.4 seconds |
| Started | May 21 01:03:31 PM PDT 24 |
| Finished | May 21 01:03:33 PM PDT 24 |
| Peak memory | 145840 kb |
| Host | smart-41b81ecd-5b31-4a78-9d7c-cf94b44b0d98 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2992182773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2992182773 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.763622659 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 29528017 ps |
| CPU time | 0.41 seconds |
| Started | May 21 01:03:32 PM PDT 24 |
| Finished | May 21 01:03:33 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-375d2ae4-c48a-430f-917a-e59580ca83e3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=763622659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.763622659 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2669607293 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 29825487 ps |
| CPU time | 0.42 seconds |
| Started | May 21 01:03:34 PM PDT 24 |
| Finished | May 21 01:03:36 PM PDT 24 |
| Peak memory | 145832 kb |
| Host | smart-73dff4ce-479d-4dec-b562-d5d7b732cb2c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2669607293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2669607293 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.3822149346 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9894451 ps |
| CPU time | 0.38 seconds |
| Started | May 21 01:03:32 PM PDT 24 |
| Finished | May 21 01:03:34 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-1d270c56-e206-4d6f-a4b9-69b250a8aefc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3822149346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3822149346 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.3809691601 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7833056 ps |
| CPU time | 0.38 seconds |
| Started | May 21 01:03:35 PM PDT 24 |
| Finished | May 21 01:03:36 PM PDT 24 |
| Peak memory | 145476 kb |
| Host | smart-afc176ef-c807-450f-9f1d-3defbf99ece0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3809691601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3809691601 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3209317543 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9936348 ps |
| CPU time | 0.38 seconds |
| Started | May 21 01:03:39 PM PDT 24 |
| Finished | May 21 01:03:40 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-aaddb8fa-4687-4aae-a6f6-d6fdf765ee62 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3209317543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3209317543 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.158586338 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8533591 ps |
| CPU time | 0.38 seconds |
| Started | May 21 01:03:39 PM PDT 24 |
| Finished | May 21 01:03:39 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-705c9869-0c51-4a13-9732-088f8485c7b0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=158586338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.158586338 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3260033155 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9169524 ps |
| CPU time | 0.37 seconds |
| Started | May 21 01:03:44 PM PDT 24 |
| Finished | May 21 01:03:46 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-bc77d10d-bf1a-47e2-a5af-fe9e6cb40bf7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3260033155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3260033155 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.2462238066 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8855875 ps |
| CPU time | 0.38 seconds |
| Started | May 21 01:03:44 PM PDT 24 |
| Finished | May 21 01:03:45 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-524dab0b-c3d4-48b1-b879-25b673a6a606 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2462238066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2462238066 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.2252191657 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 10154712 ps |
| CPU time | 0.39 seconds |
| Started | May 21 01:03:44 PM PDT 24 |
| Finished | May 21 01:03:45 PM PDT 24 |
| Peak memory | 145476 kb |
| Host | smart-da9117d9-19b7-4516-a88f-914e094a9775 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2252191657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2252191657 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.2331562273 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9293505 ps |
| CPU time | 0.38 seconds |
| Started | May 21 01:03:44 PM PDT 24 |
| Finished | May 21 01:03:45 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-fbc8687c-fc2d-4992-8de0-c11e72cc5f29 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2331562273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2331562273 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.461152552 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9226151 ps |
| CPU time | 0.4 seconds |
| Started | May 21 01:03:45 PM PDT 24 |
| Finished | May 21 01:03:46 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-bad777ec-8394-43b3-b17d-ad87ff236480 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=461152552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.461152552 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.1661444419 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9713008 ps |
| CPU time | 0.37 seconds |
| Started | May 21 01:03:45 PM PDT 24 |
| Finished | May 21 01:03:47 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-1d622314-1836-446e-85d8-76e64d78051c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1661444419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1661444419 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.3672329958 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9132452 ps |
| CPU time | 0.41 seconds |
| Started | May 21 01:03:44 PM PDT 24 |
| Finished | May 21 01:03:45 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-c319a9b5-c79e-48db-8dbd-ac961812c5dc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3672329958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3672329958 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2748225307 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8821283 ps |
| CPU time | 0.38 seconds |
| Started | May 21 01:03:33 PM PDT 24 |
| Finished | May 21 01:03:34 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-a7989384-c09b-48e2-826a-c7c099405351 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2748225307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2748225307 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3058477352 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9590645 ps |
| CPU time | 0.38 seconds |
| Started | May 21 01:03:33 PM PDT 24 |
| Finished | May 21 01:03:35 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-0ecc6b28-4678-4e67-ba2e-d286fb9cca60 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3058477352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3058477352 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.2024102764 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8623447 ps |
| CPU time | 0.4 seconds |
| Started | May 21 01:03:39 PM PDT 24 |
| Finished | May 21 01:03:40 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-cc9d1db8-5527-4394-a372-4996fdac688e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2024102764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2024102764 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.2055722303 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9670904 ps |
| CPU time | 0.44 seconds |
| Started | May 21 01:03:39 PM PDT 24 |
| Finished | May 21 01:03:40 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-96ce0c9d-5598-4b5b-af9b-5839888e97fd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2055722303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2055722303 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.3929738138 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8813432 ps |
| CPU time | 0.39 seconds |
| Started | May 21 01:03:40 PM PDT 24 |
| Finished | May 21 01:03:41 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-a632fd2b-c1f3-4330-9dda-570bba15493b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3929738138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3929738138 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.4278644827 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8477539 ps |
| CPU time | 0.39 seconds |
| Started | May 21 01:03:39 PM PDT 24 |
| Finished | May 21 01:03:39 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-0883158d-ffc5-42a0-9fd6-0f06f68fc8a1 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4278644827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.4278644827 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.2826029857 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10340405 ps |
| CPU time | 0.37 seconds |
| Started | May 21 01:03:38 PM PDT 24 |
| Finished | May 21 01:03:39 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-2050afd4-0300-495f-9a74-73e4bf1df9d5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2826029857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2826029857 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.3965004613 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9162945 ps |
| CPU time | 0.39 seconds |
| Started | May 21 01:03:38 PM PDT 24 |
| Finished | May 21 01:03:39 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-2c5d92ab-9fc6-479b-adea-ad02048e0362 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3965004613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3965004613 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1091110960 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27771799 ps |
| CPU time | 0.38 seconds |
| Started | May 21 12:50:25 PM PDT 24 |
| Finished | May 21 12:50:35 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-27707e43-7789-42ab-88fb-d9337399e639 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1091110960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1091110960 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2296084960 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 26831476 ps |
| CPU time | 0.42 seconds |
| Started | May 21 12:50:33 PM PDT 24 |
| Finished | May 21 12:50:43 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-1b313aef-8d03-465c-95d7-29bf6718e763 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2296084960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2296084960 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3703744288 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 25398405 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:27 PM PDT 24 |
| Finished | May 21 12:50:38 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-9e802420-0e0b-4ade-a7d1-e207e2b2b6f7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3703744288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3703744288 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.410327168 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26431882 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:20 PM PDT 24 |
| Finished | May 21 12:50:30 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-eddd56cf-0dae-4f17-b9ab-307ac0c7978b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=410327168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.410327168 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.610772725 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27033734 ps |
| CPU time | 0.37 seconds |
| Started | May 21 12:50:23 PM PDT 24 |
| Finished | May 21 12:50:34 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-7de86977-1db6-4251-a000-c61df3d5faf2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=610772725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.610772725 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1918403679 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 29038607 ps |
| CPU time | 0.4 seconds |
| Started | May 21 12:50:27 PM PDT 24 |
| Finished | May 21 12:50:38 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-63f701b5-01e5-40be-b213-06c00190a638 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1918403679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1918403679 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.715082981 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27817191 ps |
| CPU time | 0.38 seconds |
| Started | May 21 12:50:34 PM PDT 24 |
| Finished | May 21 12:50:43 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-d928c61a-0462-410d-a56b-a048c1e09114 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=715082981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.715082981 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2197410955 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26919825 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:20 PM PDT 24 |
| Finished | May 21 12:50:31 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-7a7b87a9-be93-4471-adf5-8300cb0289d7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2197410955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2197410955 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.118303535 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27860410 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:26 PM PDT 24 |
| Finished | May 21 12:50:37 PM PDT 24 |
| Peak memory | 145660 kb |
| Host | smart-b975fdab-87e7-4fd0-8aba-a1729ed06199 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=118303535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.118303535 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2964203743 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28904667 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:28 PM PDT 24 |
| Finished | May 21 12:50:38 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-298fafda-0d48-4067-ab37-138543f74512 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2964203743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2964203743 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2572011716 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 27481126 ps |
| CPU time | 0.4 seconds |
| Started | May 21 12:50:32 PM PDT 24 |
| Finished | May 21 12:50:41 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-b0f0a8c0-0bec-4d9e-b1c3-77081a3ee397 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2572011716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2572011716 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1233862053 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 29340703 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:26 PM PDT 24 |
| Finished | May 21 12:50:36 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-d60214b2-8252-499e-ae8e-4623d58726b5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1233862053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1233862053 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3617200273 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27248536 ps |
| CPU time | 0.4 seconds |
| Started | May 21 12:50:39 PM PDT 24 |
| Finished | May 21 12:50:46 PM PDT 24 |
| Peak memory | 145660 kb |
| Host | smart-57f2474e-77e2-4ec6-9a68-5a747a875924 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3617200273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3617200273 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.936812140 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27634376 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:21 PM PDT 24 |
| Finished | May 21 12:50:32 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-df3ccf3d-1286-4130-9086-8ce918dfb7ae |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=936812140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.936812140 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2483359980 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26206172 ps |
| CPU time | 0.4 seconds |
| Started | May 21 12:50:28 PM PDT 24 |
| Finished | May 21 12:50:38 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-b0d80ead-21e0-454d-a5cf-e502e651acbb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2483359980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2483359980 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4285712885 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 27482496 ps |
| CPU time | 0.41 seconds |
| Started | May 21 12:50:21 PM PDT 24 |
| Finished | May 21 12:50:31 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-d8b36212-00b4-4bcc-8372-d9b62952cab6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4285712885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.4285712885 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2091712126 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27285451 ps |
| CPU time | 0.4 seconds |
| Started | May 21 12:50:26 PM PDT 24 |
| Finished | May 21 12:50:37 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-47116e31-8bee-4587-8a43-49058c047d8b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2091712126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2091712126 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2222826558 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28283661 ps |
| CPU time | 0.4 seconds |
| Started | May 21 12:50:33 PM PDT 24 |
| Finished | May 21 12:50:42 PM PDT 24 |
| Peak memory | 145660 kb |
| Host | smart-7ae0af28-b629-44af-825c-dd789d218357 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2222826558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2222826558 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3420496567 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 29464292 ps |
| CPU time | 0.4 seconds |
| Started | May 21 12:50:30 PM PDT 24 |
| Finished | May 21 12:50:40 PM PDT 24 |
| Peak memory | 145660 kb |
| Host | smart-7ee22839-720e-4c9f-8859-1a194aa0e6b2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3420496567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3420496567 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3673373934 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26262164 ps |
| CPU time | 0.39 seconds |
| Started | May 21 12:50:26 PM PDT 24 |
| Finished | May 21 12:50:36 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-739b470c-2d27-4c73-9144-c5579dc92bbc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3673373934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3673373934 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |