| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.67 | 88.67 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 75.00 | 75.00 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/3.prim_async_alert.783289325 |
| 91.80 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/6.prim_sync_alert.1153008968 |
| 93.31 | 1.51 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 82.14 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3845877942 |
| 93.90 | 0.60 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 85.71 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/0.prim_async_alert.1904964853 |
| 94.50 | 0.60 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1827528444 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1648388116 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2697572037 |
| Name |
|---|
| /workspace/coverage/default/1.prim_async_alert.2553804571 |
| /workspace/coverage/default/10.prim_async_alert.1209587416 |
| /workspace/coverage/default/11.prim_async_alert.512899147 |
| /workspace/coverage/default/12.prim_async_alert.1145333216 |
| /workspace/coverage/default/13.prim_async_alert.1599862410 |
| /workspace/coverage/default/14.prim_async_alert.878138482 |
| /workspace/coverage/default/15.prim_async_alert.3415841103 |
| /workspace/coverage/default/16.prim_async_alert.2838182758 |
| /workspace/coverage/default/17.prim_async_alert.2222062207 |
| /workspace/coverage/default/18.prim_async_alert.3021678261 |
| /workspace/coverage/default/19.prim_async_alert.2567283749 |
| /workspace/coverage/default/2.prim_async_alert.3896027825 |
| /workspace/coverage/default/4.prim_async_alert.2304863927 |
| /workspace/coverage/default/5.prim_async_alert.744190767 |
| /workspace/coverage/default/6.prim_async_alert.834340046 |
| /workspace/coverage/default/7.prim_async_alert.3365410320 |
| /workspace/coverage/default/8.prim_async_alert.851662450 |
| /workspace/coverage/default/9.prim_async_alert.6589795 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1931333876 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1792024313 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2241974154 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2214857246 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3190866453 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3289529478 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3021202670 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3188687694 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3550180985 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3990494547 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.102207207 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3431295248 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.164747796 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2492229833 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.378702882 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.2560623583 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.1565628334 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.1724474020 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.4242951104 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3976494682 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1921039199 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.2690771831 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.1304507904 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.3527869126 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.1769388050 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.3920366418 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.3177693812 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.3807958122 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3349813774 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.3737264853 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.2781012112 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.3127222598 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.1145194735 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.3608837466 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2463861053 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2464860223 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.129937931 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1402005665 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.681138061 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1621980775 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3405338959 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3571293274 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2613768827 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.856859663 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1527440164 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3716380459 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2058746200 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.790187755 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.588789270 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3475211542 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2412482592 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2911470672 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3175211019 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/0.prim_async_alert.1904964853 | May 23 01:11:30 PM PDT 24 | May 23 01:11:32 PM PDT 24 | 11564455 ps | ||
| T2 | /workspace/coverage/default/12.prim_async_alert.1145333216 | May 23 01:11:39 PM PDT 24 | May 23 01:11:40 PM PDT 24 | 11177155 ps | ||
| T3 | /workspace/coverage/default/15.prim_async_alert.3415841103 | May 23 01:11:44 PM PDT 24 | May 23 01:11:45 PM PDT 24 | 11777842 ps | ||
| T7 | /workspace/coverage/default/3.prim_async_alert.783289325 | May 23 01:11:37 PM PDT 24 | May 23 01:11:38 PM PDT 24 | 11897541 ps | ||
| T12 | /workspace/coverage/default/1.prim_async_alert.2553804571 | May 23 01:11:30 PM PDT 24 | May 23 01:11:31 PM PDT 24 | 11087110 ps | ||
| T15 | /workspace/coverage/default/18.prim_async_alert.3021678261 | May 23 01:11:43 PM PDT 24 | May 23 01:11:44 PM PDT 24 | 10737669 ps | ||
| T16 | /workspace/coverage/default/16.prim_async_alert.2838182758 | May 23 01:11:44 PM PDT 24 | May 23 01:11:45 PM PDT 24 | 11158509 ps | ||
| T8 | /workspace/coverage/default/2.prim_async_alert.3896027825 | May 23 01:11:29 PM PDT 24 | May 23 01:11:30 PM PDT 24 | 11310796 ps | ||
| T17 | /workspace/coverage/default/7.prim_async_alert.3365410320 | May 23 01:11:28 PM PDT 24 | May 23 01:11:29 PM PDT 24 | 11402589 ps | ||
| T9 | /workspace/coverage/default/13.prim_async_alert.1599862410 | May 23 01:11:37 PM PDT 24 | May 23 01:11:39 PM PDT 24 | 11321732 ps | ||
| T18 | /workspace/coverage/default/5.prim_async_alert.744190767 | May 23 01:11:38 PM PDT 24 | May 23 01:11:39 PM PDT 24 | 10888165 ps | ||
| T10 | /workspace/coverage/default/10.prim_async_alert.1209587416 | May 23 01:11:32 PM PDT 24 | May 23 01:11:34 PM PDT 24 | 10901765 ps | ||
| T39 | /workspace/coverage/default/11.prim_async_alert.512899147 | May 23 01:11:37 PM PDT 24 | May 23 01:11:39 PM PDT 24 | 11836716 ps | ||
| T19 | /workspace/coverage/default/4.prim_async_alert.2304863927 | May 23 01:11:37 PM PDT 24 | May 23 01:11:38 PM PDT 24 | 10973316 ps | ||
| T20 | /workspace/coverage/default/14.prim_async_alert.878138482 | May 23 01:11:39 PM PDT 24 | May 23 01:11:40 PM PDT 24 | 11297843 ps | ||
| T14 | /workspace/coverage/default/6.prim_async_alert.834340046 | May 23 01:11:30 PM PDT 24 | May 23 01:11:31 PM PDT 24 | 11516214 ps | ||
| T48 | /workspace/coverage/default/19.prim_async_alert.2567283749 | May 23 01:11:43 PM PDT 24 | May 23 01:11:45 PM PDT 24 | 11068250 ps | ||
| T21 | /workspace/coverage/default/8.prim_async_alert.851662450 | May 23 01:11:28 PM PDT 24 | May 23 01:11:29 PM PDT 24 | 10914312 ps | ||
| T22 | /workspace/coverage/default/9.prim_async_alert.6589795 | May 23 01:11:37 PM PDT 24 | May 23 01:11:38 PM PDT 24 | 11321631 ps | ||
| T49 | /workspace/coverage/default/17.prim_async_alert.2222062207 | May 23 01:11:44 PM PDT 24 | May 23 01:11:45 PM PDT 24 | 10351828 ps | ||
| T41 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3990494547 | May 23 12:23:20 PM PDT 24 | May 23 12:23:22 PM PDT 24 | 29907701 ps | ||
| T42 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.102207207 | May 23 12:22:46 PM PDT 24 | May 23 12:22:48 PM PDT 24 | 31035621 ps | ||
| T43 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3845877942 | May 23 12:25:51 PM PDT 24 | May 23 12:25:54 PM PDT 24 | 30724877 ps | ||
| T44 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.164747796 | May 23 12:24:04 PM PDT 24 | May 23 12:24:05 PM PDT 24 | 31419787 ps | ||
| T40 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3431295248 | May 23 12:25:11 PM PDT 24 | May 23 12:25:13 PM PDT 24 | 30752478 ps | ||
| T45 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1792024313 | May 23 12:26:46 PM PDT 24 | May 23 12:26:48 PM PDT 24 | 27905609 ps | ||
| T4 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1648388116 | May 23 12:25:29 PM PDT 24 | May 23 12:25:30 PM PDT 24 | 29814302 ps | ||
| T46 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2241974154 | May 23 12:21:41 PM PDT 24 | May 23 12:21:43 PM PDT 24 | 28682812 ps | ||
| T47 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3289529478 | May 23 12:22:07 PM PDT 24 | May 23 12:22:09 PM PDT 24 | 28655145 ps | ||
| T5 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.378702882 | May 23 12:25:27 PM PDT 24 | May 23 12:25:28 PM PDT 24 | 29665910 ps | ||
| T50 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3190866453 | May 23 12:26:28 PM PDT 24 | May 23 12:26:31 PM PDT 24 | 29909647 ps | ||
| T51 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1931333876 | May 23 12:25:35 PM PDT 24 | May 23 12:25:37 PM PDT 24 | 29642937 ps | ||
| T52 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3021202670 | May 23 12:26:16 PM PDT 24 | May 23 12:26:17 PM PDT 24 | 31216967 ps | ||
| T53 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2492229833 | May 23 12:24:19 PM PDT 24 | May 23 12:24:21 PM PDT 24 | 29030463 ps | ||
| T13 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1827528444 | May 23 12:25:48 PM PDT 24 | May 23 12:25:51 PM PDT 24 | 29495175 ps | ||
| T54 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3188687694 | May 23 12:21:42 PM PDT 24 | May 23 12:21:44 PM PDT 24 | 30771508 ps | ||
| T55 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3550180985 | May 23 12:21:27 PM PDT 24 | May 23 12:21:28 PM PDT 24 | 29571948 ps | ||
| T56 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2214857246 | May 23 12:25:51 PM PDT 24 | May 23 12:25:54 PM PDT 24 | 30680525 ps | ||
| T23 | /workspace/coverage/sync_alert/14.prim_sync_alert.2690771831 | May 23 01:14:29 PM PDT 24 | May 23 01:14:32 PM PDT 24 | 9058602 ps | ||
| T33 | /workspace/coverage/sync_alert/15.prim_sync_alert.1304507904 | May 23 01:14:31 PM PDT 24 | May 23 01:14:34 PM PDT 24 | 9850249 ps | ||
| T24 | /workspace/coverage/sync_alert/9.prim_sync_alert.3608837466 | May 23 01:14:47 PM PDT 24 | May 23 01:14:50 PM PDT 24 | 10130614 ps | ||
| T34 | /workspace/coverage/sync_alert/4.prim_sync_alert.3737264853 | May 23 01:14:42 PM PDT 24 | May 23 01:14:45 PM PDT 24 | 9511962 ps | ||
| T25 | /workspace/coverage/sync_alert/7.prim_sync_alert.3127222598 | May 23 01:14:33 PM PDT 24 | May 23 01:14:35 PM PDT 24 | 9573885 ps | ||
| T35 | /workspace/coverage/sync_alert/1.prim_sync_alert.1565628334 | May 23 01:14:34 PM PDT 24 | May 23 01:14:36 PM PDT 24 | 9368251 ps | ||
| T26 | /workspace/coverage/sync_alert/2.prim_sync_alert.3807958122 | May 23 01:14:30 PM PDT 24 | May 23 01:14:33 PM PDT 24 | 9273630 ps | ||
| T36 | /workspace/coverage/sync_alert/11.prim_sync_alert.4242951104 | May 23 01:14:34 PM PDT 24 | May 23 01:14:36 PM PDT 24 | 9217664 ps | ||
| T37 | /workspace/coverage/sync_alert/10.prim_sync_alert.1724474020 | May 23 01:14:31 PM PDT 24 | May 23 01:14:34 PM PDT 24 | 9378857 ps | ||
| T38 | /workspace/coverage/sync_alert/6.prim_sync_alert.1153008968 | May 23 01:14:39 PM PDT 24 | May 23 01:14:40 PM PDT 24 | 9695209 ps | ||
| T27 | /workspace/coverage/sync_alert/8.prim_sync_alert.1145194735 | May 23 01:14:30 PM PDT 24 | May 23 01:14:33 PM PDT 24 | 9467755 ps | ||
| T28 | /workspace/coverage/sync_alert/16.prim_sync_alert.3527869126 | May 23 01:14:37 PM PDT 24 | May 23 01:14:38 PM PDT 24 | 8367506 ps | ||
| T57 | /workspace/coverage/sync_alert/3.prim_sync_alert.3349813774 | May 23 01:14:30 PM PDT 24 | May 23 01:14:33 PM PDT 24 | 9647843 ps | ||
| T29 | /workspace/coverage/sync_alert/13.prim_sync_alert.1921039199 | May 23 01:14:47 PM PDT 24 | May 23 01:14:50 PM PDT 24 | 8628902 ps | ||
| T30 | /workspace/coverage/sync_alert/12.prim_sync_alert.3976494682 | May 23 01:14:47 PM PDT 24 | May 23 01:14:50 PM PDT 24 | 10849170 ps | ||
| T31 | /workspace/coverage/sync_alert/0.prim_sync_alert.2560623583 | May 23 01:14:42 PM PDT 24 | May 23 01:14:45 PM PDT 24 | 9675352 ps | ||
| T58 | /workspace/coverage/sync_alert/19.prim_sync_alert.3177693812 | May 23 01:14:44 PM PDT 24 | May 23 01:14:47 PM PDT 24 | 9132057 ps | ||
| T59 | /workspace/coverage/sync_alert/5.prim_sync_alert.2781012112 | May 23 01:14:47 PM PDT 24 | May 23 01:14:50 PM PDT 24 | 10443889 ps | ||
| T60 | /workspace/coverage/sync_alert/17.prim_sync_alert.1769388050 | May 23 01:14:31 PM PDT 24 | May 23 01:14:35 PM PDT 24 | 8811970 ps | ||
| T32 | /workspace/coverage/sync_alert/18.prim_sync_alert.3920366418 | May 23 01:14:37 PM PDT 24 | May 23 01:14:39 PM PDT 24 | 9287675 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.129937931 | May 23 01:14:44 PM PDT 24 | May 23 01:14:47 PM PDT 24 | 27189897 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.790187755 | May 23 01:14:47 PM PDT 24 | May 23 01:14:50 PM PDT 24 | 26975338 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2463861053 | May 23 01:14:37 PM PDT 24 | May 23 01:14:38 PM PDT 24 | 27702745 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3571293274 | May 23 01:14:42 PM PDT 24 | May 23 01:14:45 PM PDT 24 | 28135721 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2058746200 | May 23 01:14:48 PM PDT 24 | May 23 01:14:50 PM PDT 24 | 30645242 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1621980775 | May 23 01:14:44 PM PDT 24 | May 23 01:14:48 PM PDT 24 | 28995073 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3175211019 | May 23 01:14:44 PM PDT 24 | May 23 01:14:47 PM PDT 24 | 27477317 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2464860223 | May 23 01:14:31 PM PDT 24 | May 23 01:14:35 PM PDT 24 | 26895989 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1527440164 | May 23 01:14:42 PM PDT 24 | May 23 01:14:45 PM PDT 24 | 27530516 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2613768827 | May 23 01:14:46 PM PDT 24 | May 23 01:14:49 PM PDT 24 | 28389451 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2412482592 | May 23 01:14:44 PM PDT 24 | May 23 01:14:47 PM PDT 24 | 28840191 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.588789270 | May 23 01:14:43 PM PDT 24 | May 23 01:14:46 PM PDT 24 | 27470866 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3716380459 | May 23 01:14:31 PM PDT 24 | May 23 01:14:35 PM PDT 24 | 28567846 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3475211542 | May 23 01:14:43 PM PDT 24 | May 23 01:14:46 PM PDT 24 | 26333647 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2911470672 | May 23 01:14:48 PM PDT 24 | May 23 01:14:51 PM PDT 24 | 26200002 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1402005665 | May 23 01:14:44 PM PDT 24 | May 23 01:14:47 PM PDT 24 | 28145695 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.856859663 | May 23 01:14:44 PM PDT 24 | May 23 01:14:47 PM PDT 24 | 27691330 ps | ||
| T11 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2697572037 | May 23 01:14:42 PM PDT 24 | May 23 01:14:44 PM PDT 24 | 28542210 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3405338959 | May 23 01:14:46 PM PDT 24 | May 23 01:14:49 PM PDT 24 | 26978309 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.681138061 | May 23 01:14:44 PM PDT 24 | May 23 01:14:46 PM PDT 24 | 26220061 ps |
| Test location | /workspace/coverage/default/3.prim_async_alert.783289325 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11897541 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:11:37 PM PDT 24 |
| Finished | May 23 01:11:38 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-7b492c38-1e72-43b7-a6de-717935af5e8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=783289325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.783289325 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1153008968 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9695209 ps |
| CPU time | 0.39 seconds |
| Started | May 23 01:14:39 PM PDT 24 |
| Finished | May 23 01:14:40 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-a2756948-860b-4993-a31c-398dd0c247f4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1153008968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1153008968 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3845877942 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30724877 ps |
| CPU time | 0.46 seconds |
| Started | May 23 12:25:51 PM PDT 24 |
| Finished | May 23 12:25:54 PM PDT 24 |
| Peak memory | 145752 kb |
| Host | smart-f93018fa-6064-449e-8450-cce3aeefe74e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3845877942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3845877942 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.1904964853 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11564455 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:11:30 PM PDT 24 |
| Finished | May 23 01:11:32 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-2bf15459-735a-4125-809b-b82fd0dd122a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904964853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1904964853 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1827528444 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 29495175 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:25:48 PM PDT 24 |
| Finished | May 23 12:25:51 PM PDT 24 |
| Peak memory | 145260 kb |
| Host | smart-fc2edda8-b7e2-4594-8dc9-5b9fae787baf |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1827528444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1827528444 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1648388116 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 29814302 ps |
| CPU time | 0.44 seconds |
| Started | May 23 12:25:29 PM PDT 24 |
| Finished | May 23 12:25:30 PM PDT 24 |
| Peak memory | 145908 kb |
| Host | smart-f763c68d-0485-4652-8de8-cfd90e45feb7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1648388116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1648388116 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2697572037 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 28542210 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:14:44 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-433790e3-abff-4383-bcb9-121b1d5168cc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2697572037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2697572037 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.2553804571 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11087110 ps |
| CPU time | 0.41 seconds |
| Started | May 23 01:11:30 PM PDT 24 |
| Finished | May 23 01:11:31 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-228a2c94-65c5-40cf-a2f8-d244d14b3db8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2553804571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2553804571 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.1209587416 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10901765 ps |
| CPU time | 0.39 seconds |
| Started | May 23 01:11:32 PM PDT 24 |
| Finished | May 23 01:11:34 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-658018fc-39f7-4fe6-870d-fee9c0d4b229 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209587416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1209587416 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.512899147 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11836716 ps |
| CPU time | 0.39 seconds |
| Started | May 23 01:11:37 PM PDT 24 |
| Finished | May 23 01:11:39 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-44ba2791-1d8e-4e74-9c42-2519acb043de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512899147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.512899147 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.1145333216 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11177155 ps |
| CPU time | 0.43 seconds |
| Started | May 23 01:11:39 PM PDT 24 |
| Finished | May 23 01:11:40 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-1346347f-a6cc-4286-9729-da0d22f07cf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145333216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1145333216 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.1599862410 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11321732 ps |
| CPU time | 0.37 seconds |
| Started | May 23 01:11:37 PM PDT 24 |
| Finished | May 23 01:11:39 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-f43ef7ed-0863-4fc2-a8a7-1f5f511605a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1599862410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1599862410 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.878138482 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11297843 ps |
| CPU time | 0.45 seconds |
| Started | May 23 01:11:39 PM PDT 24 |
| Finished | May 23 01:11:40 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-6626eaa8-fd23-40ca-bcc0-340df0136842 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=878138482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.878138482 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3415841103 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11777842 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:11:44 PM PDT 24 |
| Finished | May 23 01:11:45 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-e946766b-0a81-4f42-8fad-f00d25c5ffab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3415841103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3415841103 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.2838182758 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11158509 ps |
| CPU time | 0.41 seconds |
| Started | May 23 01:11:44 PM PDT 24 |
| Finished | May 23 01:11:45 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-2df8265c-db9b-4885-9ea3-e24a95272e0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838182758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2838182758 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.2222062207 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10351828 ps |
| CPU time | 0.37 seconds |
| Started | May 23 01:11:44 PM PDT 24 |
| Finished | May 23 01:11:45 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-29ff86d0-7d7c-4e4c-bafc-8e42919becf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222062207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2222062207 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.3021678261 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10737669 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:11:43 PM PDT 24 |
| Finished | May 23 01:11:44 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-2d031133-50cc-4c6d-8a2d-703f1b8f3119 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021678261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3021678261 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.2567283749 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11068250 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:11:43 PM PDT 24 |
| Finished | May 23 01:11:45 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-3dd76cd1-c46c-478d-92ce-4bc97ea6e6d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567283749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2567283749 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3896027825 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11310796 ps |
| CPU time | 0.39 seconds |
| Started | May 23 01:11:29 PM PDT 24 |
| Finished | May 23 01:11:30 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-a16e7e37-1757-454c-9233-bcac1a17f17a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896027825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3896027825 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.2304863927 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10973316 ps |
| CPU time | 0.39 seconds |
| Started | May 23 01:11:37 PM PDT 24 |
| Finished | May 23 01:11:38 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-f85ff548-3ca3-485c-81fa-26dae6b34a22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2304863927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2304863927 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.744190767 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10888165 ps |
| CPU time | 0.39 seconds |
| Started | May 23 01:11:38 PM PDT 24 |
| Finished | May 23 01:11:39 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-d7eb6687-fcb0-4190-8c28-1477c0328392 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744190767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.744190767 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.834340046 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11516214 ps |
| CPU time | 0.42 seconds |
| Started | May 23 01:11:30 PM PDT 24 |
| Finished | May 23 01:11:31 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-ce4cca5d-d82d-408d-a8e1-49e61f072934 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834340046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.834340046 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.3365410320 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11402589 ps |
| CPU time | 0.42 seconds |
| Started | May 23 01:11:28 PM PDT 24 |
| Finished | May 23 01:11:29 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-2f7838fd-f9f8-4647-9568-db6dc64c4ed5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3365410320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3365410320 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.851662450 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10914312 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:11:28 PM PDT 24 |
| Finished | May 23 01:11:29 PM PDT 24 |
| Peak memory | 145864 kb |
| Host | smart-76e4d7ee-0c28-4df2-9cb4-d0534f0615ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851662450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.851662450 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.6589795 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11321631 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:11:37 PM PDT 24 |
| Finished | May 23 01:11:38 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-cb7d0b94-d367-4cb5-bf2e-459e6c15825f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6589795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.6589795 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1931333876 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29642937 ps |
| CPU time | 0.44 seconds |
| Started | May 23 12:25:35 PM PDT 24 |
| Finished | May 23 12:25:37 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-ea366b93-b7dc-46a6-9b6b-d58f1c19cead |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1931333876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1931333876 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1792024313 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 27905609 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:26:46 PM PDT 24 |
| Finished | May 23 12:26:48 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-40fae0fa-d082-4cb3-986b-5f0374abc5ef |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1792024313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1792024313 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2241974154 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 28682812 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:21:41 PM PDT 24 |
| Finished | May 23 12:21:43 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-5d1c3c6e-ed91-4227-b680-9cc98cfbfdd7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2241974154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2241974154 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2214857246 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 30680525 ps |
| CPU time | 0.41 seconds |
| Started | May 23 12:25:51 PM PDT 24 |
| Finished | May 23 12:25:54 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-e1c958c9-f6e6-45c4-ba2c-ccda4e8c3c78 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2214857246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2214857246 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3190866453 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 29909647 ps |
| CPU time | 0.44 seconds |
| Started | May 23 12:26:28 PM PDT 24 |
| Finished | May 23 12:26:31 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-c08f0962-0ea3-468f-aeca-8c31992284f6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3190866453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3190866453 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3289529478 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 28655145 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:22:07 PM PDT 24 |
| Finished | May 23 12:22:09 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-71494df5-5ebb-440d-a46f-94ea4496e658 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3289529478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3289529478 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3021202670 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 31216967 ps |
| CPU time | 0.45 seconds |
| Started | May 23 12:26:16 PM PDT 24 |
| Finished | May 23 12:26:17 PM PDT 24 |
| Peak memory | 145260 kb |
| Host | smart-ef77bb79-6be1-4daa-a9ac-6a3197d95785 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3021202670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3021202670 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3188687694 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30771508 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:21:42 PM PDT 24 |
| Finished | May 23 12:21:44 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-9724d3c8-d14e-4964-bad8-9da20e502ad6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3188687694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3188687694 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3550180985 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29571948 ps |
| CPU time | 0.39 seconds |
| Started | May 23 12:21:27 PM PDT 24 |
| Finished | May 23 12:21:28 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-93654743-a54a-45f9-9538-a8b9a29f65ef |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3550180985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3550180985 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3990494547 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29907701 ps |
| CPU time | 0.42 seconds |
| Started | May 23 12:23:20 PM PDT 24 |
| Finished | May 23 12:23:22 PM PDT 24 |
| Peak memory | 145536 kb |
| Host | smart-94923b1b-c8e0-4919-bdb8-65c872cba9ec |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3990494547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3990494547 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.102207207 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 31035621 ps |
| CPU time | 0.42 seconds |
| Started | May 23 12:22:46 PM PDT 24 |
| Finished | May 23 12:22:48 PM PDT 24 |
| Peak memory | 145700 kb |
| Host | smart-072be1a6-84fa-4ed2-9f70-d4635f15b243 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=102207207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.102207207 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3431295248 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 30752478 ps |
| CPU time | 0.44 seconds |
| Started | May 23 12:25:11 PM PDT 24 |
| Finished | May 23 12:25:13 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-32942c52-60eb-4b0f-a1a6-893ec3de6e93 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3431295248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3431295248 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.164747796 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 31419787 ps |
| CPU time | 0.43 seconds |
| Started | May 23 12:24:04 PM PDT 24 |
| Finished | May 23 12:24:05 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-cfb5b42c-3cd8-4cb3-b8c2-bfecb5f8d1c5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=164747796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.164747796 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2492229833 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29030463 ps |
| CPU time | 0.46 seconds |
| Started | May 23 12:24:19 PM PDT 24 |
| Finished | May 23 12:24:21 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-a1f2d7fc-64b3-4c0a-b2d0-37abd2b6418d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2492229833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2492229833 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.378702882 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 29665910 ps |
| CPU time | 0.4 seconds |
| Started | May 23 12:25:27 PM PDT 24 |
| Finished | May 23 12:25:28 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-d47be7f5-9eda-461e-adac-fd0cbfec2cf2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=378702882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.378702882 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.2560623583 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9675352 ps |
| CPU time | 0.37 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:14:45 PM PDT 24 |
| Peak memory | 145456 kb |
| Host | smart-8d68b026-f4c9-45e9-858b-881546a6df2f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2560623583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2560623583 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.1565628334 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9368251 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:14:34 PM PDT 24 |
| Finished | May 23 01:14:36 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-cf56c5ec-648c-4d86-8c94-263f19c6d278 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1565628334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1565628334 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.1724474020 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9378857 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:14:31 PM PDT 24 |
| Finished | May 23 01:14:34 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-97ab6bb0-c3e2-4117-9ff7-901258b848b4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1724474020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1724474020 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.4242951104 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9217664 ps |
| CPU time | 0.37 seconds |
| Started | May 23 01:14:34 PM PDT 24 |
| Finished | May 23 01:14:36 PM PDT 24 |
| Peak memory | 145448 kb |
| Host | smart-b64f5513-7512-4f9a-8b1c-245a4173ac15 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4242951104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.4242951104 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3976494682 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10849170 ps |
| CPU time | 0.39 seconds |
| Started | May 23 01:14:47 PM PDT 24 |
| Finished | May 23 01:14:50 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-80513835-2656-4ede-8b4a-fe7a351fe795 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3976494682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3976494682 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1921039199 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8628902 ps |
| CPU time | 0.39 seconds |
| Started | May 23 01:14:47 PM PDT 24 |
| Finished | May 23 01:14:50 PM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-41875889-68db-451c-9f1d-0c3c46f675b5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1921039199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1921039199 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.2690771831 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9058602 ps |
| CPU time | 0.37 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:14:32 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-fca10184-5df4-42d0-99ff-8af9dbb8bed8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2690771831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2690771831 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.1304507904 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9850249 ps |
| CPU time | 0.37 seconds |
| Started | May 23 01:14:31 PM PDT 24 |
| Finished | May 23 01:14:34 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-415025e8-ca55-4bfe-98a9-9e8d80d58631 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1304507904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1304507904 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.3527869126 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8367506 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:14:37 PM PDT 24 |
| Finished | May 23 01:14:38 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-69fdcbae-9c76-41ae-b2fd-0d5571f8f8f3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3527869126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3527869126 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.1769388050 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8811970 ps |
| CPU time | 0.39 seconds |
| Started | May 23 01:14:31 PM PDT 24 |
| Finished | May 23 01:14:35 PM PDT 24 |
| Peak memory | 145520 kb |
| Host | smart-415752da-ab14-42ef-947b-78111fdc0fcc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1769388050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1769388050 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.3920366418 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9287675 ps |
| CPU time | 0.41 seconds |
| Started | May 23 01:14:37 PM PDT 24 |
| Finished | May 23 01:14:39 PM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-5bc1d4ad-a7d4-4aa6-88e5-1d2a097a7868 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3920366418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3920366418 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.3177693812 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9132057 ps |
| CPU time | 0.42 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:14:47 PM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-6a324aea-8fe3-447f-8570-f041a5e07435 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3177693812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3177693812 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3807958122 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9273630 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:14:30 PM PDT 24 |
| Finished | May 23 01:14:33 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-2d4cba33-7851-4ed1-9fad-5f93d8bf1f1b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3807958122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3807958122 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3349813774 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9647843 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:14:30 PM PDT 24 |
| Finished | May 23 01:14:33 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-699b03d5-0f91-45b3-b30d-565f90ba3714 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3349813774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3349813774 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.3737264853 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9511962 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:14:45 PM PDT 24 |
| Peak memory | 145456 kb |
| Host | smart-e280856c-e4bb-480e-8ae2-d80cf55dc9e7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3737264853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3737264853 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.2781012112 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 10443889 ps |
| CPU time | 0.39 seconds |
| Started | May 23 01:14:47 PM PDT 24 |
| Finished | May 23 01:14:50 PM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-808e787a-9b40-4673-aec4-59cbd0a4d7ac |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2781012112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2781012112 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.3127222598 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9573885 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:14:33 PM PDT 24 |
| Finished | May 23 01:14:35 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-4823b8ae-525e-46e1-ac43-339a1b90b2d2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3127222598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3127222598 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1145194735 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9467755 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:14:30 PM PDT 24 |
| Finished | May 23 01:14:33 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-355bef55-5fca-4e91-aac3-d885c8ae7678 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1145194735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1145194735 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.3608837466 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10130614 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:14:47 PM PDT 24 |
| Finished | May 23 01:14:50 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-f631967e-08c2-405c-a8a7-5e73a4957407 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3608837466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3608837466 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2463861053 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27702745 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:14:37 PM PDT 24 |
| Finished | May 23 01:14:38 PM PDT 24 |
| Peak memory | 145532 kb |
| Host | smart-cace3abc-a522-447f-9730-a7bd733a022f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2463861053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2463861053 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2464860223 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26895989 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:14:31 PM PDT 24 |
| Finished | May 23 01:14:35 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-c051eced-c01c-422d-a6de-97f1c8936df8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2464860223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2464860223 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.129937931 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27189897 ps |
| CPU time | 0.42 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:14:47 PM PDT 24 |
| Peak memory | 145504 kb |
| Host | smart-52a6526b-14d6-4019-b96a-cdf776b02ad2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=129937931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.129937931 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1402005665 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 28145695 ps |
| CPU time | 0.41 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:14:47 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-a6bba9e3-c853-49c2-afbb-b30604f8ea78 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1402005665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1402005665 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.681138061 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26220061 ps |
| CPU time | 0.41 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:14:46 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-73c98529-e3e3-4d5d-8e51-33d8342b017a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=681138061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.681138061 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1621980775 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28995073 ps |
| CPU time | 0.41 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:14:48 PM PDT 24 |
| Peak memory | 145476 kb |
| Host | smart-c69770c4-6003-45bd-9572-ec998d26d1de |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1621980775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1621980775 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3405338959 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 26978309 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:14:46 PM PDT 24 |
| Finished | May 23 01:14:49 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-f0c9dc90-9658-43b8-8e83-d56f10796599 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3405338959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3405338959 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3571293274 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 28135721 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:14:45 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-908688ca-dba5-4ed6-acdb-0821046d8059 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3571293274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3571293274 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2613768827 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28389451 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:14:46 PM PDT 24 |
| Finished | May 23 01:14:49 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-d66a8510-8351-4472-9132-71f7d594c5df |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2613768827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2613768827 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.856859663 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27691330 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:14:47 PM PDT 24 |
| Peak memory | 145504 kb |
| Host | smart-6173d817-9857-4356-93d6-d8c2082a1a8c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=856859663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.856859663 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1527440164 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27530516 ps |
| CPU time | 0.42 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:14:45 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-4fd05eb2-05cb-4d95-a9fb-a4700e431d25 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1527440164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1527440164 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3716380459 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28567846 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:14:31 PM PDT 24 |
| Finished | May 23 01:14:35 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-7efd752e-5e44-4fed-b137-6626bd49b796 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3716380459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3716380459 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2058746200 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 30645242 ps |
| CPU time | 0.41 seconds |
| Started | May 23 01:14:48 PM PDT 24 |
| Finished | May 23 01:14:50 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-ff98c330-dbcf-48e0-b6c8-ea19641342f2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2058746200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2058746200 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.790187755 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 26975338 ps |
| CPU time | 0.41 seconds |
| Started | May 23 01:14:47 PM PDT 24 |
| Finished | May 23 01:14:50 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-ddcaed60-e3ac-4e1f-93a7-45ca205a11a3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=790187755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.790187755 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.588789270 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27470866 ps |
| CPU time | 0.47 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:14:46 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-d833aa19-7ad5-4411-844a-b0c297e3de75 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=588789270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.588789270 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3475211542 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26333647 ps |
| CPU time | 0.38 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:14:46 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-1b3f2b03-4e60-42c3-822e-838d688d667c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3475211542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3475211542 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2412482592 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28840191 ps |
| CPU time | 0.4 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:14:47 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-475fd771-69b4-40cf-abf4-2dff4cad938c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2412482592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2412482592 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2911470672 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26200002 ps |
| CPU time | 0.42 seconds |
| Started | May 23 01:14:48 PM PDT 24 |
| Finished | May 23 01:14:51 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-3da797be-ef3f-4c3d-814c-8c5b00395768 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2911470672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2911470672 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3175211019 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27477317 ps |
| CPU time | 0.42 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:14:47 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-f57b2501-d601-4ea0-ab2b-6a7a82701445 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3175211019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3175211019 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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