| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.32 | 88.32 | 100.00 | 100.00 | 91.67 | 91.67 | 96.43 | 96.43 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/14.prim_async_alert.2298512856 |
| 90.86 | 2.53 | 100.00 | 0.00 | 91.67 | 0.00 | 96.43 | 0.00 | 82.14 | 3.57 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/2.prim_sync_alert.3654841362 |
| 92.96 | 2.11 | 100.00 | 0.00 | 93.75 | 2.08 | 100.00 | 3.57 | 82.14 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1095056813 |
| 93.90 | 0.94 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 85.71 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/15.prim_async_alert.1945832658 |
| 94.50 | 0.60 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1078186839 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1703108904 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2509502715 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.170796189 |
| /workspace/coverage/default/10.prim_async_alert.538304026 |
| /workspace/coverage/default/11.prim_async_alert.1430600044 |
| /workspace/coverage/default/12.prim_async_alert.3865149100 |
| /workspace/coverage/default/13.prim_async_alert.547074591 |
| /workspace/coverage/default/16.prim_async_alert.2704286377 |
| /workspace/coverage/default/17.prim_async_alert.1655456539 |
| /workspace/coverage/default/18.prim_async_alert.2808084093 |
| /workspace/coverage/default/19.prim_async_alert.2349519131 |
| /workspace/coverage/default/2.prim_async_alert.2289294997 |
| /workspace/coverage/default/3.prim_async_alert.452456104 |
| /workspace/coverage/default/4.prim_async_alert.3278345090 |
| /workspace/coverage/default/5.prim_async_alert.2604584897 |
| /workspace/coverage/default/6.prim_async_alert.1429211965 |
| /workspace/coverage/default/7.prim_async_alert.3846990245 |
| /workspace/coverage/default/8.prim_async_alert.1986251540 |
| /workspace/coverage/default/9.prim_async_alert.1800270582 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3132181275 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.561220071 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.350104251 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.538591985 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3190673158 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3218881855 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3859037439 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2639627516 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.688298625 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.253572410 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2984922195 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.931399712 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1836432637 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.622517542 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1066826405 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2808230849 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1728924197 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.196811538 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.1465241396 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3579994870 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.3554584817 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.4239412705 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.3917631489 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1671045268 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.2535353676 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.334925680 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.2161541658 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.592826950 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.3272683472 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.1342172514 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.4215871787 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.110450900 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1866523632 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1090835413 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.409257465 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.3149416049 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.488798425 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3384266823 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1708708514 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3850575743 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.582735738 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3956538431 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1525129348 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3295930422 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1239507128 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1663572562 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.829194766 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3644598032 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1892269332 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2318335683 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3344700008 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1352295553 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.141867334 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.915497650 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/11.prim_async_alert.1430600044 | May 26 01:48:20 PM PDT 24 | May 26 01:48:21 PM PDT 24 | 10840967 ps | ||
| T2 | /workspace/coverage/default/4.prim_async_alert.3278345090 | May 26 01:48:17 PM PDT 24 | May 26 01:48:19 PM PDT 24 | 11059200 ps | ||
| T3 | /workspace/coverage/default/18.prim_async_alert.2808084093 | May 26 01:48:20 PM PDT 24 | May 26 01:48:21 PM PDT 24 | 11386414 ps | ||
| T10 | /workspace/coverage/default/2.prim_async_alert.2289294997 | May 26 01:48:21 PM PDT 24 | May 26 01:48:22 PM PDT 24 | 10565935 ps | ||
| T19 | /workspace/coverage/default/14.prim_async_alert.2298512856 | May 26 01:48:19 PM PDT 24 | May 26 01:48:21 PM PDT 24 | 11770818 ps | ||
| T7 | /workspace/coverage/default/0.prim_async_alert.170796189 | May 26 01:48:18 PM PDT 24 | May 26 01:48:20 PM PDT 24 | 10588081 ps | ||
| T23 | /workspace/coverage/default/15.prim_async_alert.1945832658 | May 26 01:48:17 PM PDT 24 | May 26 01:48:18 PM PDT 24 | 11203161 ps | ||
| T8 | /workspace/coverage/default/9.prim_async_alert.1800270582 | May 26 01:48:19 PM PDT 24 | May 26 01:48:20 PM PDT 24 | 11050712 ps | ||
| T9 | /workspace/coverage/default/5.prim_async_alert.2604584897 | May 26 01:48:18 PM PDT 24 | May 26 01:48:19 PM PDT 24 | 11242644 ps | ||
| T24 | /workspace/coverage/default/19.prim_async_alert.2349519131 | May 26 01:48:18 PM PDT 24 | May 26 01:48:19 PM PDT 24 | 11839703 ps | ||
| T20 | /workspace/coverage/default/8.prim_async_alert.1986251540 | May 26 01:48:16 PM PDT 24 | May 26 01:48:17 PM PDT 24 | 10861340 ps | ||
| T26 | /workspace/coverage/default/17.prim_async_alert.1655456539 | May 26 01:48:19 PM PDT 24 | May 26 01:48:20 PM PDT 24 | 10627353 ps | ||
| T50 | /workspace/coverage/default/7.prim_async_alert.3846990245 | May 26 01:48:19 PM PDT 24 | May 26 01:48:20 PM PDT 24 | 11036751 ps | ||
| T25 | /workspace/coverage/default/6.prim_async_alert.1429211965 | May 26 01:48:17 PM PDT 24 | May 26 01:48:18 PM PDT 24 | 11103631 ps | ||
| T51 | /workspace/coverage/default/10.prim_async_alert.538304026 | May 26 01:48:17 PM PDT 24 | May 26 01:48:19 PM PDT 24 | 11242022 ps | ||
| T21 | /workspace/coverage/default/13.prim_async_alert.547074591 | May 26 01:48:19 PM PDT 24 | May 26 01:48:20 PM PDT 24 | 11452775 ps | ||
| T22 | /workspace/coverage/default/12.prim_async_alert.3865149100 | May 26 01:48:17 PM PDT 24 | May 26 01:48:18 PM PDT 24 | 11094246 ps | ||
| T52 | /workspace/coverage/default/16.prim_async_alert.2704286377 | May 26 01:48:20 PM PDT 24 | May 26 01:48:21 PM PDT 24 | 11717320 ps | ||
| T13 | /workspace/coverage/default/3.prim_async_alert.452456104 | May 26 01:48:20 PM PDT 24 | May 26 01:48:21 PM PDT 24 | 12187926 ps | ||
| T14 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.688298625 | May 26 01:48:27 PM PDT 24 | May 26 01:48:29 PM PDT 24 | 30866107 ps | ||
| T15 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2808230849 | May 26 01:48:28 PM PDT 24 | May 26 01:48:30 PM PDT 24 | 28860468 ps | ||
| T42 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1095056813 | May 26 01:48:26 PM PDT 24 | May 26 01:48:27 PM PDT 24 | 29472169 ps | ||
| T43 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2639627516 | May 26 01:48:30 PM PDT 24 | May 26 01:48:31 PM PDT 24 | 31736020 ps | ||
| T44 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3132181275 | May 26 01:48:17 PM PDT 24 | May 26 01:48:18 PM PDT 24 | 28246317 ps | ||
| T45 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2984922195 | May 26 01:48:19 PM PDT 24 | May 26 01:48:21 PM PDT 24 | 30520637 ps | ||
| T46 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.253572410 | May 26 01:48:28 PM PDT 24 | May 26 01:48:30 PM PDT 24 | 29028291 ps | ||
| T47 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.561220071 | May 26 01:48:20 PM PDT 24 | May 26 01:48:21 PM PDT 24 | 31081192 ps | ||
| T48 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3218881855 | May 26 01:48:26 PM PDT 24 | May 26 01:48:27 PM PDT 24 | 29312650 ps | ||
| T49 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.538591985 | May 26 01:48:28 PM PDT 24 | May 26 01:48:30 PM PDT 24 | 29990064 ps | ||
| T53 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.350104251 | May 26 01:48:28 PM PDT 24 | May 26 01:48:30 PM PDT 24 | 31298028 ps | ||
| T54 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.931399712 | May 26 01:48:27 PM PDT 24 | May 26 01:48:29 PM PDT 24 | 30882452 ps | ||
| T16 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1078186839 | May 26 01:48:31 PM PDT 24 | May 26 01:48:32 PM PDT 24 | 33335526 ps | ||
| T55 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1836432637 | May 26 01:48:27 PM PDT 24 | May 26 01:48:29 PM PDT 24 | 30744544 ps | ||
| T56 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1066826405 | May 26 01:48:28 PM PDT 24 | May 26 01:48:29 PM PDT 24 | 32276191 ps | ||
| T57 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.622517542 | May 26 01:48:28 PM PDT 24 | May 26 01:48:30 PM PDT 24 | 30980550 ps | ||
| T17 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1728924197 | May 26 01:48:26 PM PDT 24 | May 26 01:48:27 PM PDT 24 | 31029687 ps | ||
| T58 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3190673158 | May 26 01:48:29 PM PDT 24 | May 26 01:48:30 PM PDT 24 | 28260865 ps | ||
| T59 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3859037439 | May 26 01:48:28 PM PDT 24 | May 26 01:48:29 PM PDT 24 | 30531223 ps | ||
| T34 | /workspace/coverage/sync_alert/8.prim_sync_alert.409257465 | May 26 01:48:37 PM PDT 24 | May 26 01:48:38 PM PDT 24 | 9472617 ps | ||
| T27 | /workspace/coverage/sync_alert/11.prim_sync_alert.3554584817 | May 26 01:48:37 PM PDT 24 | May 26 01:48:37 PM PDT 24 | 8422018 ps | ||
| T28 | /workspace/coverage/sync_alert/17.prim_sync_alert.2161541658 | May 26 01:48:43 PM PDT 24 | May 26 01:48:45 PM PDT 24 | 8764948 ps | ||
| T35 | /workspace/coverage/sync_alert/14.prim_sync_alert.1671045268 | May 26 01:48:43 PM PDT 24 | May 26 01:48:45 PM PDT 24 | 9739134 ps | ||
| T36 | /workspace/coverage/sync_alert/1.prim_sync_alert.1465241396 | May 26 01:48:28 PM PDT 24 | May 26 01:48:30 PM PDT 24 | 8887172 ps | ||
| T37 | /workspace/coverage/sync_alert/19.prim_sync_alert.3272683472 | May 26 01:48:35 PM PDT 24 | May 26 01:48:36 PM PDT 24 | 9122525 ps | ||
| T38 | /workspace/coverage/sync_alert/2.prim_sync_alert.3654841362 | May 26 01:48:28 PM PDT 24 | May 26 01:48:30 PM PDT 24 | 9059322 ps | ||
| T39 | /workspace/coverage/sync_alert/4.prim_sync_alert.4215871787 | May 26 01:48:43 PM PDT 24 | May 26 01:48:44 PM PDT 24 | 9158351 ps | ||
| T40 | /workspace/coverage/sync_alert/12.prim_sync_alert.4239412705 | May 26 01:48:42 PM PDT 24 | May 26 01:48:43 PM PDT 24 | 9298414 ps | ||
| T41 | /workspace/coverage/sync_alert/9.prim_sync_alert.3149416049 | May 26 01:48:34 PM PDT 24 | May 26 01:48:35 PM PDT 24 | 9132751 ps | ||
| T60 | /workspace/coverage/sync_alert/13.prim_sync_alert.3917631489 | May 26 01:48:34 PM PDT 24 | May 26 01:48:36 PM PDT 24 | 8982327 ps | ||
| T61 | /workspace/coverage/sync_alert/18.prim_sync_alert.592826950 | May 26 01:48:36 PM PDT 24 | May 26 01:48:37 PM PDT 24 | 9836304 ps | ||
| T29 | /workspace/coverage/sync_alert/7.prim_sync_alert.1090835413 | May 26 01:48:37 PM PDT 24 | May 26 01:48:37 PM PDT 24 | 9337920 ps | ||
| T18 | /workspace/coverage/sync_alert/16.prim_sync_alert.334925680 | May 26 01:48:44 PM PDT 24 | May 26 01:48:45 PM PDT 24 | 9659366 ps | ||
| T62 | /workspace/coverage/sync_alert/5.prim_sync_alert.110450900 | May 26 01:48:34 PM PDT 24 | May 26 01:48:35 PM PDT 24 | 8214002 ps | ||
| T30 | /workspace/coverage/sync_alert/15.prim_sync_alert.2535353676 | May 26 01:48:36 PM PDT 24 | May 26 01:48:37 PM PDT 24 | 9154635 ps | ||
| T63 | /workspace/coverage/sync_alert/3.prim_sync_alert.1342172514 | May 26 01:48:29 PM PDT 24 | May 26 01:48:30 PM PDT 24 | 8696032 ps | ||
| T31 | /workspace/coverage/sync_alert/6.prim_sync_alert.1866523632 | May 26 01:48:43 PM PDT 24 | May 26 01:48:45 PM PDT 24 | 9351058 ps | ||
| T64 | /workspace/coverage/sync_alert/0.prim_sync_alert.196811538 | May 26 01:48:27 PM PDT 24 | May 26 01:48:29 PM PDT 24 | 9663817 ps | ||
| T32 | /workspace/coverage/sync_alert/10.prim_sync_alert.3579994870 | May 26 01:48:35 PM PDT 24 | May 26 01:48:36 PM PDT 24 | 9840066 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2318335683 | May 26 01:48:44 PM PDT 24 | May 26 01:48:46 PM PDT 24 | 27021089 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3295930422 | May 26 01:48:43 PM PDT 24 | May 26 01:48:45 PM PDT 24 | 25850819 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3384266823 | May 26 01:48:42 PM PDT 24 | May 26 01:48:44 PM PDT 24 | 28725806 ps | ||
| T33 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1892269332 | May 26 01:48:38 PM PDT 24 | May 26 01:48:39 PM PDT 24 | 27775770 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1708708514 | May 26 01:48:47 PM PDT 24 | May 26 01:48:48 PM PDT 24 | 26691200 ps | ||
| T4 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3850575743 | May 26 01:48:47 PM PDT 24 | May 26 01:48:48 PM PDT 24 | 25649655 ps | ||
| T11 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2509502715 | May 26 01:48:42 PM PDT 24 | May 26 01:48:43 PM PDT 24 | 27590750 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3956538431 | May 26 01:48:45 PM PDT 24 | May 26 01:48:47 PM PDT 24 | 27399420 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1239507128 | May 26 01:48:43 PM PDT 24 | May 26 01:48:44 PM PDT 24 | 26612526 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1663572562 | May 26 01:48:44 PM PDT 24 | May 26 01:48:45 PM PDT 24 | 26572029 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3344700008 | May 26 01:48:46 PM PDT 24 | May 26 01:48:47 PM PDT 24 | 27608475 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.141867334 | May 26 01:48:44 PM PDT 24 | May 26 01:48:46 PM PDT 24 | 27478197 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.915497650 | May 26 01:48:36 PM PDT 24 | May 26 01:48:37 PM PDT 24 | 27356853 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.829194766 | May 26 01:48:38 PM PDT 24 | May 26 01:48:39 PM PDT 24 | 27004652 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3644598032 | May 26 01:48:43 PM PDT 24 | May 26 01:48:45 PM PDT 24 | 27073793 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.582735738 | May 26 01:48:45 PM PDT 24 | May 26 01:48:47 PM PDT 24 | 25931270 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1703108904 | May 26 01:48:44 PM PDT 24 | May 26 01:48:46 PM PDT 24 | 26764213 ps | ||
| T12 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1352295553 | May 26 01:48:37 PM PDT 24 | May 26 01:48:38 PM PDT 24 | 25649536 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.488798425 | May 26 01:48:36 PM PDT 24 | May 26 01:48:37 PM PDT 24 | 28686381 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1525129348 | May 26 01:48:42 PM PDT 24 | May 26 01:48:43 PM PDT 24 | 26296972 ps |
| Test location | /workspace/coverage/default/14.prim_async_alert.2298512856 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11770818 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:19 PM PDT 24 |
| Finished | May 26 01:48:21 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-6925bf80-71a8-46e8-8317-df1f1035e0e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298512856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2298512856 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.3654841362 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9059322 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:28 PM PDT 24 |
| Finished | May 26 01:48:30 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-dc5460de-a29a-42c6-afec-cbab493fca4c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3654841362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3654841362 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1095056813 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29472169 ps |
| CPU time | 0.44 seconds |
| Started | May 26 01:48:26 PM PDT 24 |
| Finished | May 26 01:48:27 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-b16b9f05-1788-40de-a0fd-608a54b505d9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1095056813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1095056813 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.1945832658 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11203161 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:17 PM PDT 24 |
| Finished | May 26 01:48:18 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-85a0ea3f-4940-4680-94a2-b112c5d7573f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945832658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1945832658 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1078186839 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 33335526 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:48:31 PM PDT 24 |
| Finished | May 26 01:48:32 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-52da46c0-eba8-4372-9e98-016224d54565 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1078186839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1078186839 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1703108904 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 26764213 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:44 PM PDT 24 |
| Finished | May 26 01:48:46 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-be0fc8f3-62ee-441a-b9fd-8f37ff273bd1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1703108904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1703108904 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2509502715 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 27590750 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:42 PM PDT 24 |
| Finished | May 26 01:48:43 PM PDT 24 |
| Peak memory | 145536 kb |
| Host | smart-bb99446d-8cf2-4202-a982-2efd14a4b78e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2509502715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2509502715 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.170796189 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10588081 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:18 PM PDT 24 |
| Finished | May 26 01:48:20 PM PDT 24 |
| Peak memory | 145732 kb |
| Host | smart-baf2a88a-b408-48c8-868b-1ee8c0a7fa87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=170796189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.170796189 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.538304026 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 11242022 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:17 PM PDT 24 |
| Finished | May 26 01:48:19 PM PDT 24 |
| Peak memory | 145896 kb |
| Host | smart-46578a54-a11e-4f89-a286-30370552bf31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=538304026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.538304026 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.1430600044 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10840967 ps |
| CPU time | 0.43 seconds |
| Started | May 26 01:48:20 PM PDT 24 |
| Finished | May 26 01:48:21 PM PDT 24 |
| Peak memory | 145920 kb |
| Host | smart-ccfb8789-6caa-487a-9a74-1a45a3ffe281 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1430600044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1430600044 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3865149100 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11094246 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:17 PM PDT 24 |
| Finished | May 26 01:48:18 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-32707661-0e42-473f-9ca9-d41acf93103b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865149100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3865149100 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.547074591 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11452775 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:19 PM PDT 24 |
| Finished | May 26 01:48:20 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-9955bf87-c47e-4b9d-bce8-535b0482f805 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547074591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.547074591 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.2704286377 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 11717320 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:20 PM PDT 24 |
| Finished | May 26 01:48:21 PM PDT 24 |
| Peak memory | 145852 kb |
| Host | smart-9eac7f15-ee00-40ed-b597-b9fea5ac218b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704286377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2704286377 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1655456539 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10627353 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:19 PM PDT 24 |
| Finished | May 26 01:48:20 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-a93fdd79-324c-49c8-aa8d-3fe6f92bcdb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1655456539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1655456539 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.2808084093 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11386414 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:20 PM PDT 24 |
| Finished | May 26 01:48:21 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-dad23744-be57-445f-9d32-90fd06ad196b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2808084093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2808084093 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.2349519131 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11839703 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:18 PM PDT 24 |
| Finished | May 26 01:48:19 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-51804f22-a61b-4e49-928f-32c93d05e001 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349519131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2349519131 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.2289294997 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10565935 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:21 PM PDT 24 |
| Finished | May 26 01:48:22 PM PDT 24 |
| Peak memory | 145844 kb |
| Host | smart-fd4c2910-238d-4507-8d2c-ce0a58d04e28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289294997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2289294997 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.452456104 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12187926 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:20 PM PDT 24 |
| Finished | May 26 01:48:21 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-572c8d95-b2a7-4aec-99fb-ed0b0efed5f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452456104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.452456104 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.3278345090 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11059200 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:17 PM PDT 24 |
| Finished | May 26 01:48:19 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-c9d2c413-405c-44ab-948d-986a66ebb218 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3278345090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3278345090 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.2604584897 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11242644 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:18 PM PDT 24 |
| Finished | May 26 01:48:19 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-28d7509c-d658-44ed-9164-daf48045b8c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2604584897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2604584897 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.1429211965 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11103631 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:17 PM PDT 24 |
| Finished | May 26 01:48:18 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-ec1250a5-92e4-4274-8ffe-90b30aab7ffa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1429211965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1429211965 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.3846990245 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11036751 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:19 PM PDT 24 |
| Finished | May 26 01:48:20 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-d2719078-4be7-44b6-803b-c60ac2284656 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846990245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3846990245 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.1986251540 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10861340 ps |
| CPU time | 0.37 seconds |
| Started | May 26 01:48:16 PM PDT 24 |
| Finished | May 26 01:48:17 PM PDT 24 |
| Peak memory | 145912 kb |
| Host | smart-9cf79d04-139f-42ae-97a7-2b92ef424533 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986251540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1986251540 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1800270582 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11050712 ps |
| CPU time | 0.37 seconds |
| Started | May 26 01:48:19 PM PDT 24 |
| Finished | May 26 01:48:20 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-16309074-6aca-410e-930d-4c672556cf1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800270582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1800270582 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3132181275 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 28246317 ps |
| CPU time | 0.42 seconds |
| Started | May 26 01:48:17 PM PDT 24 |
| Finished | May 26 01:48:18 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-d50737c5-fe4a-427d-83f8-5efb4aa5250b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3132181275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3132181275 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.561220071 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 31081192 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:20 PM PDT 24 |
| Finished | May 26 01:48:21 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-d6c6c671-eb45-47e6-9290-71abfb49daba |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=561220071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.561220071 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.350104251 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 31298028 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:28 PM PDT 24 |
| Finished | May 26 01:48:30 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-8c299e8d-5e1d-4b89-8758-c5e2744e3240 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=350104251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.350104251 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.538591985 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29990064 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:48:28 PM PDT 24 |
| Finished | May 26 01:48:30 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-62509bb0-fb47-4fac-acbb-74936259775e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=538591985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.538591985 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3190673158 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 28260865 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:29 PM PDT 24 |
| Finished | May 26 01:48:30 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-4dc89131-3ac7-477a-ab8e-acdb2989d9e0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3190673158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3190673158 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3218881855 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29312650 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:26 PM PDT 24 |
| Finished | May 26 01:48:27 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-ad4b2115-3e86-477a-bb08-61ac9b1a5411 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3218881855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3218881855 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3859037439 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 30531223 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:48:28 PM PDT 24 |
| Finished | May 26 01:48:29 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-29ccc7bb-96fd-4a1f-bb89-6f8ae988885f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3859037439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3859037439 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2639627516 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31736020 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:48:30 PM PDT 24 |
| Finished | May 26 01:48:31 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-13cf3e37-eedf-4a18-929b-08f7b98a9898 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2639627516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2639627516 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.688298625 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 30866107 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:27 PM PDT 24 |
| Finished | May 26 01:48:29 PM PDT 24 |
| Peak memory | 145884 kb |
| Host | smart-9aba94b2-eb64-48c6-8d83-a665a5ce2926 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=688298625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.688298625 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.253572410 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29028291 ps |
| CPU time | 0.42 seconds |
| Started | May 26 01:48:28 PM PDT 24 |
| Finished | May 26 01:48:30 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-b74964b6-3377-4ef0-92e9-ad15a99882f8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=253572410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.253572410 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2984922195 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30520637 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:19 PM PDT 24 |
| Finished | May 26 01:48:21 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-63fd27f0-b6d6-47b6-bb6b-50508690bcd1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2984922195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2984922195 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.931399712 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30882452 ps |
| CPU time | 0.45 seconds |
| Started | May 26 01:48:27 PM PDT 24 |
| Finished | May 26 01:48:29 PM PDT 24 |
| Peak memory | 145852 kb |
| Host | smart-c522d766-928c-43f6-b701-98eea3a69330 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=931399712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.931399712 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1836432637 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 30744544 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:48:27 PM PDT 24 |
| Finished | May 26 01:48:29 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-de076d4a-0c86-44d6-9b47-ae7a7349f241 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1836432637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1836432637 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.622517542 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 30980550 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:48:28 PM PDT 24 |
| Finished | May 26 01:48:30 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-f74ceda3-b944-418a-9487-f83140463af2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=622517542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.622517542 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1066826405 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 32276191 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:48:28 PM PDT 24 |
| Finished | May 26 01:48:29 PM PDT 24 |
| Peak memory | 145748 kb |
| Host | smart-2478a8fb-17ab-4bf1-8c22-c58a0d60dd0b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1066826405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1066826405 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2808230849 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 28860468 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:28 PM PDT 24 |
| Finished | May 26 01:48:30 PM PDT 24 |
| Peak memory | 145752 kb |
| Host | smart-9cb0a202-26f5-4c72-b0f9-582fcafdb187 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2808230849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2808230849 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1728924197 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 31029687 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:26 PM PDT 24 |
| Finished | May 26 01:48:27 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-51b3b28d-d1cb-4772-95f6-c315c78a1229 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1728924197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1728924197 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.196811538 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 9663817 ps |
| CPU time | 0.37 seconds |
| Started | May 26 01:48:27 PM PDT 24 |
| Finished | May 26 01:48:29 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-12946c9b-ff05-4cce-8532-5512a537695f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=196811538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.196811538 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.1465241396 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8887172 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:28 PM PDT 24 |
| Finished | May 26 01:48:30 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-79b12c38-bfb0-470c-b28e-aabcfc0cea13 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1465241396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1465241396 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3579994870 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9840066 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:35 PM PDT 24 |
| Finished | May 26 01:48:36 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-8030551d-3cbc-4f9c-b81a-1b6a7bc933b8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3579994870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3579994870 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.3554584817 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8422018 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:37 PM PDT 24 |
| Finished | May 26 01:48:37 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-8b32320b-84e5-4acd-a862-f3fc63928143 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3554584817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3554584817 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.4239412705 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9298414 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:42 PM PDT 24 |
| Finished | May 26 01:48:43 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-f08693fc-e091-467b-a4c4-16ce97f5164a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4239412705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.4239412705 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.3917631489 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8982327 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:34 PM PDT 24 |
| Finished | May 26 01:48:36 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-bda9778d-54f0-4f04-af4d-8bacb5648ba0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3917631489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3917631489 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1671045268 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9739134 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:43 PM PDT 24 |
| Finished | May 26 01:48:45 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-8b0db325-ad00-47b7-a523-33a784f00518 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1671045268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1671045268 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.2535353676 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9154635 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:36 PM PDT 24 |
| Finished | May 26 01:48:37 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-fb87953f-c65f-4bb3-92a6-6e5c836b0ed2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2535353676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2535353676 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.334925680 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9659366 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:44 PM PDT 24 |
| Finished | May 26 01:48:45 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-6453e3f7-ba9d-4acc-951a-0c8721320a6d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=334925680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.334925680 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.2161541658 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8764948 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:43 PM PDT 24 |
| Finished | May 26 01:48:45 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-045e7ad9-c59c-4bde-abb6-ea7133e1a82d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2161541658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2161541658 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.592826950 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9836304 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:36 PM PDT 24 |
| Finished | May 26 01:48:37 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-08c83727-c629-453e-b858-028fa6a8d427 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=592826950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.592826950 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.3272683472 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9122525 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:35 PM PDT 24 |
| Finished | May 26 01:48:36 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-a67201c6-6f8c-4a0a-9e8d-5bd9b026c81d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3272683472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3272683472 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.1342172514 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 8696032 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:29 PM PDT 24 |
| Finished | May 26 01:48:30 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-245a7560-48fb-480c-aaba-0e109ad6fe51 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1342172514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1342172514 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.4215871787 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9158351 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:43 PM PDT 24 |
| Finished | May 26 01:48:44 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-391be2c3-1a72-44cb-90c3-6b0b78c16c1b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4215871787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.4215871787 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.110450900 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 8214002 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:48:34 PM PDT 24 |
| Finished | May 26 01:48:35 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-692f51ec-26a9-49f0-a3a9-0ebec5f9c96b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=110450900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.110450900 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1866523632 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9351058 ps |
| CPU time | 0.43 seconds |
| Started | May 26 01:48:43 PM PDT 24 |
| Finished | May 26 01:48:45 PM PDT 24 |
| Peak memory | 145536 kb |
| Host | smart-10175d23-f7ad-44c2-9424-393f8d953c26 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1866523632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1866523632 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1090835413 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9337920 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:37 PM PDT 24 |
| Finished | May 26 01:48:37 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-a66a5c79-7065-4240-8b82-5ad0a7e2b34a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1090835413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1090835413 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.409257465 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9472617 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:48:37 PM PDT 24 |
| Finished | May 26 01:48:38 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-3b6ecd7e-4c47-434e-b5c0-44080aa86b85 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=409257465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.409257465 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.3149416049 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9132751 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:34 PM PDT 24 |
| Finished | May 26 01:48:35 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-813bbe69-169c-4b3a-a192-a1b4e2b4cb20 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3149416049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3149416049 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.488798425 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 28686381 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:48:36 PM PDT 24 |
| Finished | May 26 01:48:37 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-45abd6c1-dd04-44e3-a7c0-8cf13fedb4d4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=488798425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.488798425 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3384266823 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28725806 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:42 PM PDT 24 |
| Finished | May 26 01:48:44 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-a4e74f4d-389c-4ef7-aeb2-f5ea5c8a926f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3384266823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3384266823 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1708708514 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26691200 ps |
| CPU time | 0.44 seconds |
| Started | May 26 01:48:47 PM PDT 24 |
| Finished | May 26 01:48:48 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-835e3667-53e9-4eea-9259-c5b63bf39d51 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1708708514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1708708514 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3850575743 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 25649655 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:48:47 PM PDT 24 |
| Finished | May 26 01:48:48 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-7e8b6112-3a61-4d3f-bd28-198e84682be4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3850575743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3850575743 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.582735738 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 25931270 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:45 PM PDT 24 |
| Finished | May 26 01:48:47 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-5fc2cde6-dd37-4f65-b2c0-760f78235e57 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=582735738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.582735738 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3956538431 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27399420 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:45 PM PDT 24 |
| Finished | May 26 01:48:47 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-8873f6d6-c100-4b75-b14f-1436bdf556fa |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3956538431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3956538431 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1525129348 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26296972 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:42 PM PDT 24 |
| Finished | May 26 01:48:43 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-91a34f97-1647-4300-a3a4-52e69eea23f5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1525129348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1525129348 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3295930422 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 25850819 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:43 PM PDT 24 |
| Finished | May 26 01:48:45 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-97225ebb-9fe3-47bb-8f6a-e8ed5956a4e1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3295930422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3295930422 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1239507128 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 26612526 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:48:43 PM PDT 24 |
| Finished | May 26 01:48:44 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-eb59c4cf-88be-41b5-b4d9-d7d444aef351 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1239507128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1239507128 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1663572562 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26572029 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:44 PM PDT 24 |
| Finished | May 26 01:48:45 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-c28e95b0-bf47-4045-99aa-73ca409ef1a4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1663572562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1663572562 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.829194766 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27004652 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:38 PM PDT 24 |
| Finished | May 26 01:48:39 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-422cf838-d886-4a51-a3aa-5915f40899c9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=829194766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.829194766 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3644598032 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27073793 ps |
| CPU time | 0.42 seconds |
| Started | May 26 01:48:43 PM PDT 24 |
| Finished | May 26 01:48:45 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-2ed19d99-655b-4dfb-a3ed-b545d5d7f4ca |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3644598032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3644598032 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1892269332 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 27775770 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:38 PM PDT 24 |
| Finished | May 26 01:48:39 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-e8b61ecd-d546-4238-b613-5fd3fed4deb3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1892269332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1892269332 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2318335683 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27021089 ps |
| CPU time | 0.44 seconds |
| Started | May 26 01:48:44 PM PDT 24 |
| Finished | May 26 01:48:46 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-4290fd26-67aa-45a3-9779-070eb993e36d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2318335683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2318335683 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3344700008 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27608475 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:46 PM PDT 24 |
| Finished | May 26 01:48:47 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-3b707cad-db82-4fc2-9001-7edf98a0a43d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3344700008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3344700008 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1352295553 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 25649536 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:48:37 PM PDT 24 |
| Finished | May 26 01:48:38 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-4cff54bf-8079-4237-8ad3-fec13b48dfa9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1352295553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1352295553 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.141867334 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27478197 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:48:44 PM PDT 24 |
| Finished | May 26 01:48:46 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-35b58fb0-416e-4bbf-afdd-522b40556262 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=141867334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.141867334 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.915497650 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 27356853 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:48:36 PM PDT 24 |
| Finished | May 26 01:48:37 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-0b937a24-c5fb-4d2b-a529-389148cfc934 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=915497650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.915497650 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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