| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 89.23 | 89.23 | 100.00 | 100.00 | 95.83 | 95.83 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/19.prim_async_alert.2547850102 |
| 92.35 | 3.13 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/17.prim_sync_alert.2426385965 |
| 94.11 | 1.76 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 83.72 | 6.98 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3880453159 |
| 94.50 | 0.39 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 2.33 | /workspace/coverage/default/1.prim_async_alert.2956669643 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4136354184 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.167395738 |
| /workspace/coverage/default/10.prim_async_alert.1139831382 |
| /workspace/coverage/default/11.prim_async_alert.4119088194 |
| /workspace/coverage/default/12.prim_async_alert.2730866514 |
| /workspace/coverage/default/13.prim_async_alert.2746254553 |
| /workspace/coverage/default/14.prim_async_alert.2686746994 |
| /workspace/coverage/default/15.prim_async_alert.2124710897 |
| /workspace/coverage/default/16.prim_async_alert.1525655809 |
| /workspace/coverage/default/17.prim_async_alert.2585496632 |
| /workspace/coverage/default/18.prim_async_alert.2108465870 |
| /workspace/coverage/default/2.prim_async_alert.4242998413 |
| /workspace/coverage/default/3.prim_async_alert.3857451671 |
| /workspace/coverage/default/4.prim_async_alert.463015357 |
| /workspace/coverage/default/5.prim_async_alert.1058094403 |
| /workspace/coverage/default/6.prim_async_alert.1778822907 |
| /workspace/coverage/default/7.prim_async_alert.1100644423 |
| /workspace/coverage/default/8.prim_async_alert.122122572 |
| /workspace/coverage/default/9.prim_async_alert.3660231280 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4269302010 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1260216230 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2778959797 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3999414130 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3418234869 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2902055594 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3038655110 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1077961437 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3791602200 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2626552680 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1940754827 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2383226171 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.792414366 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.386084157 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1915620648 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2068702070 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1579418677 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.765685957 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.3838535186 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.933782370 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.1324449428 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.4191872763 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3034695857 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1258975077 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.3339738987 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.2367930830 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.2273518356 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.244554336 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.1097774727 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2788891324 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.1098434951 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.2444757346 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.1679948195 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.889185573 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1565390292 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.1524970323 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.2017657527 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3845841082 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1179529714 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.585049632 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2004773988 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2860599434 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2950278433 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.732476522 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.991332221 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2977009845 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.617465352 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3606188949 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3835458089 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3432493084 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1337243797 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1458396460 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3700880355 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3558734073 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2226953107 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2750119104 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2500778112 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_async_alert.2108465870 | May 28 01:07:07 PM PDT 24 | May 28 01:07:13 PM PDT 24 | 11555527 ps | ||
| T2 | /workspace/coverage/default/2.prim_async_alert.4242998413 | May 28 01:07:06 PM PDT 24 | May 28 01:07:12 PM PDT 24 | 11443343 ps | ||
| T3 | /workspace/coverage/default/19.prim_async_alert.2547850102 | May 28 01:07:04 PM PDT 24 | May 28 01:07:09 PM PDT 24 | 12318827 ps | ||
| T17 | /workspace/coverage/default/3.prim_async_alert.3857451671 | May 28 01:07:10 PM PDT 24 | May 28 01:07:15 PM PDT 24 | 10589846 ps | ||
| T9 | /workspace/coverage/default/16.prim_async_alert.1525655809 | May 28 01:07:07 PM PDT 24 | May 28 01:07:13 PM PDT 24 | 12341990 ps | ||
| T18 | /workspace/coverage/default/4.prim_async_alert.463015357 | May 28 01:07:02 PM PDT 24 | May 28 01:07:04 PM PDT 24 | 10672594 ps | ||
| T10 | /workspace/coverage/default/15.prim_async_alert.2124710897 | May 28 01:07:03 PM PDT 24 | May 28 01:07:05 PM PDT 24 | 11936960 ps | ||
| T19 | /workspace/coverage/default/12.prim_async_alert.2730866514 | May 28 01:07:04 PM PDT 24 | May 28 01:07:09 PM PDT 24 | 10931799 ps | ||
| T11 | /workspace/coverage/default/9.prim_async_alert.3660231280 | May 28 01:07:06 PM PDT 24 | May 28 01:07:12 PM PDT 24 | 12069507 ps | ||
| T20 | /workspace/coverage/default/5.prim_async_alert.1058094403 | May 28 01:07:09 PM PDT 24 | May 28 01:07:14 PM PDT 24 | 10481824 ps | ||
| T21 | /workspace/coverage/default/0.prim_async_alert.167395738 | May 28 01:07:08 PM PDT 24 | May 28 01:07:14 PM PDT 24 | 10779830 ps | ||
| T7 | /workspace/coverage/default/6.prim_async_alert.1778822907 | May 28 01:07:04 PM PDT 24 | May 28 01:07:09 PM PDT 24 | 10876149 ps | ||
| T8 | /workspace/coverage/default/14.prim_async_alert.2686746994 | May 28 01:07:05 PM PDT 24 | May 28 01:07:10 PM PDT 24 | 12203766 ps | ||
| T22 | /workspace/coverage/default/1.prim_async_alert.2956669643 | May 28 01:07:02 PM PDT 24 | May 28 01:07:04 PM PDT 24 | 11186256 ps | ||
| T23 | /workspace/coverage/default/7.prim_async_alert.1100644423 | May 28 01:07:04 PM PDT 24 | May 28 01:07:09 PM PDT 24 | 11381342 ps | ||
| T24 | /workspace/coverage/default/10.prim_async_alert.1139831382 | May 28 01:07:03 PM PDT 24 | May 28 01:07:08 PM PDT 24 | 10653201 ps | ||
| T12 | /workspace/coverage/default/8.prim_async_alert.122122572 | May 28 01:07:03 PM PDT 24 | May 28 01:07:06 PM PDT 24 | 12263341 ps | ||
| T49 | /workspace/coverage/default/17.prim_async_alert.2585496632 | May 28 01:07:05 PM PDT 24 | May 28 01:07:11 PM PDT 24 | 11028850 ps | ||
| T25 | /workspace/coverage/default/13.prim_async_alert.2746254553 | May 28 01:07:04 PM PDT 24 | May 28 01:07:08 PM PDT 24 | 11246024 ps | ||
| T50 | /workspace/coverage/default/11.prim_async_alert.4119088194 | May 28 01:07:05 PM PDT 24 | May 28 01:07:11 PM PDT 24 | 10890397 ps | ||
| T42 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2068702070 | May 28 01:07:03 PM PDT 24 | May 28 01:07:05 PM PDT 24 | 30364663 ps | ||
| T15 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3880453159 | May 28 01:07:05 PM PDT 24 | May 28 01:07:11 PM PDT 24 | 29925876 ps | ||
| T4 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.792414366 | May 28 01:07:02 PM PDT 24 | May 28 01:07:04 PM PDT 24 | 30500461 ps | ||
| T43 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1579418677 | May 28 01:07:10 PM PDT 24 | May 28 01:07:15 PM PDT 24 | 30073978 ps | ||
| T44 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4269302010 | May 28 01:07:05 PM PDT 24 | May 28 01:07:10 PM PDT 24 | 29316170 ps | ||
| T13 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3418234869 | May 28 01:07:05 PM PDT 24 | May 28 01:07:11 PM PDT 24 | 31350100 ps | ||
| T45 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2383226171 | May 28 01:07:07 PM PDT 24 | May 28 01:07:13 PM PDT 24 | 30416188 ps | ||
| T46 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3038655110 | May 28 01:07:04 PM PDT 24 | May 28 01:07:09 PM PDT 24 | 29507762 ps | ||
| T47 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1077961437 | May 28 01:07:04 PM PDT 24 | May 28 01:07:08 PM PDT 24 | 30705402 ps | ||
| T48 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2902055594 | May 28 01:07:05 PM PDT 24 | May 28 01:07:10 PM PDT 24 | 29747390 ps | ||
| T51 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2626552680 | May 28 01:07:05 PM PDT 24 | May 28 01:07:11 PM PDT 24 | 30304719 ps | ||
| T52 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3791602200 | May 28 01:07:05 PM PDT 24 | May 28 01:07:10 PM PDT 24 | 29953054 ps | ||
| T5 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.765685957 | May 28 01:07:03 PM PDT 24 | May 28 01:07:05 PM PDT 24 | 30096718 ps | ||
| T53 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2778959797 | May 28 01:07:03 PM PDT 24 | May 28 01:07:08 PM PDT 24 | 29834565 ps | ||
| T41 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1940754827 | May 28 01:07:07 PM PDT 24 | May 28 01:07:13 PM PDT 24 | 32033784 ps | ||
| T54 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1915620648 | May 28 01:07:08 PM PDT 24 | May 28 01:07:14 PM PDT 24 | 31289511 ps | ||
| T16 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.386084157 | May 28 01:07:03 PM PDT 24 | May 28 01:07:06 PM PDT 24 | 31628630 ps | ||
| T14 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1260216230 | May 28 01:07:07 PM PDT 24 | May 28 01:07:13 PM PDT 24 | 30601474 ps | ||
| T55 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3999414130 | May 28 01:07:07 PM PDT 24 | May 28 01:07:13 PM PDT 24 | 31280302 ps | ||
| T6 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4136354184 | May 28 01:07:07 PM PDT 24 | May 28 01:07:13 PM PDT 24 | 29142866 ps | ||
| T35 | /workspace/coverage/sync_alert/13.prim_sync_alert.1258975077 | May 28 01:07:57 PM PDT 24 | May 28 01:07:58 PM PDT 24 | 9731172 ps | ||
| T26 | /workspace/coverage/sync_alert/1.prim_sync_alert.933782370 | May 28 01:08:01 PM PDT 24 | May 28 01:08:02 PM PDT 24 | 10248541 ps | ||
| T36 | /workspace/coverage/sync_alert/7.prim_sync_alert.1565390292 | May 28 01:07:50 PM PDT 24 | May 28 01:07:51 PM PDT 24 | 8489413 ps | ||
| T37 | /workspace/coverage/sync_alert/17.prim_sync_alert.2426385965 | May 28 01:07:48 PM PDT 24 | May 28 01:07:49 PM PDT 24 | 8746887 ps | ||
| T38 | /workspace/coverage/sync_alert/5.prim_sync_alert.1679948195 | May 28 01:07:43 PM PDT 24 | May 28 01:07:45 PM PDT 24 | 10087316 ps | ||
| T27 | /workspace/coverage/sync_alert/3.prim_sync_alert.1098434951 | May 28 01:07:55 PM PDT 24 | May 28 01:07:57 PM PDT 24 | 9367897 ps | ||
| T28 | /workspace/coverage/sync_alert/9.prim_sync_alert.2017657527 | May 28 01:07:38 PM PDT 24 | May 28 01:07:49 PM PDT 24 | 8628399 ps | ||
| T39 | /workspace/coverage/sync_alert/2.prim_sync_alert.2788891324 | May 28 01:07:44 PM PDT 24 | May 28 01:07:45 PM PDT 24 | 9066785 ps | ||
| T40 | /workspace/coverage/sync_alert/14.prim_sync_alert.3339738987 | May 28 01:07:55 PM PDT 24 | May 28 01:07:56 PM PDT 24 | 8433474 ps | ||
| T29 | /workspace/coverage/sync_alert/18.prim_sync_alert.244554336 | May 28 01:07:41 PM PDT 24 | May 28 01:07:42 PM PDT 24 | 8973902 ps | ||
| T30 | /workspace/coverage/sync_alert/6.prim_sync_alert.889185573 | May 28 01:07:49 PM PDT 24 | May 28 01:07:51 PM PDT 24 | 9788381 ps | ||
| T56 | /workspace/coverage/sync_alert/19.prim_sync_alert.1097774727 | May 28 01:07:46 PM PDT 24 | May 28 01:07:47 PM PDT 24 | 9657599 ps | ||
| T57 | /workspace/coverage/sync_alert/10.prim_sync_alert.1324449428 | May 28 01:07:42 PM PDT 24 | May 28 01:07:44 PM PDT 24 | 9860413 ps | ||
| T31 | /workspace/coverage/sync_alert/11.prim_sync_alert.4191872763 | May 28 01:07:43 PM PDT 24 | May 28 01:07:45 PM PDT 24 | 8395149 ps | ||
| T32 | /workspace/coverage/sync_alert/4.prim_sync_alert.2444757346 | May 28 01:07:57 PM PDT 24 | May 28 01:07:58 PM PDT 24 | 9567919 ps | ||
| T58 | /workspace/coverage/sync_alert/0.prim_sync_alert.3838535186 | May 28 01:07:46 PM PDT 24 | May 28 01:07:48 PM PDT 24 | 9863637 ps | ||
| T33 | /workspace/coverage/sync_alert/16.prim_sync_alert.2273518356 | May 28 01:07:49 PM PDT 24 | May 28 01:07:51 PM PDT 24 | 9485106 ps | ||
| T34 | /workspace/coverage/sync_alert/15.prim_sync_alert.2367930830 | May 28 01:07:41 PM PDT 24 | May 28 01:07:48 PM PDT 24 | 9576839 ps | ||
| T59 | /workspace/coverage/sync_alert/12.prim_sync_alert.3034695857 | May 28 01:07:59 PM PDT 24 | May 28 01:08:01 PM PDT 24 | 8302586 ps | ||
| T60 | /workspace/coverage/sync_alert/8.prim_sync_alert.1524970323 | May 28 01:07:49 PM PDT 24 | May 28 01:07:50 PM PDT 24 | 9668501 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2750119104 | May 28 01:08:11 PM PDT 24 | May 28 01:08:13 PM PDT 24 | 29284062 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2860599434 | May 28 01:07:43 PM PDT 24 | May 28 01:07:44 PM PDT 24 | 28709673 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.732476522 | May 28 01:07:51 PM PDT 24 | May 28 01:07:52 PM PDT 24 | 26815924 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.585049632 | May 28 01:07:43 PM PDT 24 | May 28 01:07:45 PM PDT 24 | 27636823 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1458396460 | May 28 01:07:57 PM PDT 24 | May 28 01:08:03 PM PDT 24 | 27308684 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2004773988 | May 28 01:07:47 PM PDT 24 | May 28 01:07:49 PM PDT 24 | 28270040 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.617465352 | May 28 01:08:10 PM PDT 24 | May 28 01:08:12 PM PDT 24 | 28207808 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.991332221 | May 28 01:07:49 PM PDT 24 | May 28 01:07:50 PM PDT 24 | 28412882 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1179529714 | May 28 01:07:57 PM PDT 24 | May 28 01:07:59 PM PDT 24 | 26312872 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3700880355 | May 28 01:07:37 PM PDT 24 | May 28 01:07:38 PM PDT 24 | 28404728 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2500778112 | May 28 01:08:03 PM PDT 24 | May 28 01:08:04 PM PDT 24 | 28661835 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3835458089 | May 28 01:07:41 PM PDT 24 | May 28 01:07:42 PM PDT 24 | 29049185 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3845841082 | May 28 01:07:45 PM PDT 24 | May 28 01:07:46 PM PDT 24 | 26771160 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3606188949 | May 28 01:07:57 PM PDT 24 | May 28 01:07:59 PM PDT 24 | 26539373 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1337243797 | May 28 01:07:46 PM PDT 24 | May 28 01:07:48 PM PDT 24 | 26910586 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3558734073 | May 28 01:07:48 PM PDT 24 | May 28 01:07:50 PM PDT 24 | 29793695 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2950278433 | May 28 01:07:53 PM PDT 24 | May 28 01:07:59 PM PDT 24 | 27995971 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3432493084 | May 28 01:07:39 PM PDT 24 | May 28 01:07:40 PM PDT 24 | 29520120 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2977009845 | May 28 01:08:12 PM PDT 24 | May 28 01:08:14 PM PDT 24 | 27679311 ps | ||
| T80 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2226953107 | May 28 01:07:52 PM PDT 24 | May 28 01:07:53 PM PDT 24 | 26854218 ps |
| Test location | /workspace/coverage/default/19.prim_async_alert.2547850102 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12318827 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:04 PM PDT 24 |
| Finished | May 28 01:07:09 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-c71fcdcf-dc64-4ba2-9273-b762438a6701 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547850102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2547850102 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.2426385965 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8746887 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:48 PM PDT 24 |
| Finished | May 28 01:07:49 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-7bc7ea63-78e8-4618-a2bc-41dcdef2ef9b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2426385965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2426385965 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3880453159 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 29925876 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:05 PM PDT 24 |
| Finished | May 28 01:07:11 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-dfd2ae30-d9fa-43e5-bc80-17280eefb754 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3880453159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3880453159 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.2956669643 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11186256 ps |
| CPU time | 0.44 seconds |
| Started | May 28 01:07:02 PM PDT 24 |
| Finished | May 28 01:07:04 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-713fac43-e7bb-486f-b5bc-dccd6a4ec1f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956669643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2956669643 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4136354184 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 29142866 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:07 PM PDT 24 |
| Finished | May 28 01:07:13 PM PDT 24 |
| Peak memory | 145668 kb |
| Host | smart-b245dbc9-918b-48e2-8841-02cf2ecd1787 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4136354184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.4136354184 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.167395738 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10779830 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:08 PM PDT 24 |
| Finished | May 28 01:07:14 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-3cf1d05b-2dbf-44ad-8043-a3c7b2e0bb48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167395738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.167395738 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.1139831382 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10653201 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:03 PM PDT 24 |
| Finished | May 28 01:07:08 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-b46abb30-0b35-418d-b52c-d60a6431d757 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1139831382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1139831382 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.4119088194 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10890397 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:05 PM PDT 24 |
| Finished | May 28 01:07:11 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-64dcc67e-3891-4333-8614-576209e72187 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119088194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4119088194 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.2730866514 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10931799 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:04 PM PDT 24 |
| Finished | May 28 01:07:09 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-b1a03232-6d13-4c5d-88e7-a6c1821988f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730866514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2730866514 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.2746254553 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11246024 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:07:04 PM PDT 24 |
| Finished | May 28 01:07:08 PM PDT 24 |
| Peak memory | 145700 kb |
| Host | smart-ebd19f3d-514a-4ead-8ce8-f0669eea926d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2746254553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2746254553 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.2686746994 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12203766 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:05 PM PDT 24 |
| Finished | May 28 01:07:10 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-bb2b9383-fbc9-4bbc-b24f-f7166b216dc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686746994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2686746994 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.2124710897 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11936960 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:07:03 PM PDT 24 |
| Finished | May 28 01:07:05 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-55a6bd8a-0a70-4ee2-8fb6-827044e847b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2124710897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2124710897 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.1525655809 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12341990 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:07 PM PDT 24 |
| Finished | May 28 01:07:13 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-a9fb4fe5-d8be-4e1c-a3aa-4d0d9d21bdb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525655809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1525655809 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.2585496632 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11028850 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:07:05 PM PDT 24 |
| Finished | May 28 01:07:11 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-277ac4b1-0557-4efe-972b-ecf080b89043 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585496632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2585496632 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.2108465870 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11555527 ps |
| CPU time | 0.44 seconds |
| Started | May 28 01:07:07 PM PDT 24 |
| Finished | May 28 01:07:13 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-0a79564c-0d07-4326-af6e-3aaf423a3cb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2108465870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2108465870 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.4242998413 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11443343 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:06 PM PDT 24 |
| Finished | May 28 01:07:12 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-53aa785f-8ec0-46e1-b578-1150c48399dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4242998413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.4242998413 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.3857451671 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10589846 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:10 PM PDT 24 |
| Finished | May 28 01:07:15 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-f1ff9031-e34f-40d5-b219-ff690abd328d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857451671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3857451671 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.463015357 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10672594 ps |
| CPU time | 0.37 seconds |
| Started | May 28 01:07:02 PM PDT 24 |
| Finished | May 28 01:07:04 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-8db22051-b959-485c-83d0-97ddef983703 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=463015357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.463015357 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1058094403 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10481824 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:09 PM PDT 24 |
| Finished | May 28 01:07:14 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-46dbf251-3260-49c6-b5d6-9b0b3c56cbf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1058094403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1058094403 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.1778822907 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10876149 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:04 PM PDT 24 |
| Finished | May 28 01:07:09 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-73a91e22-fb08-44a2-8040-b2804f808cfd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1778822907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1778822907 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.1100644423 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11381342 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:04 PM PDT 24 |
| Finished | May 28 01:07:09 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-12ce8dac-46dd-4158-92db-374cd11cd030 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1100644423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1100644423 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.122122572 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12263341 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:07:03 PM PDT 24 |
| Finished | May 28 01:07:06 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-88b75ede-f736-4e46-ace4-8a3b6b648fec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=122122572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.122122572 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.3660231280 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12069507 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:07:06 PM PDT 24 |
| Finished | May 28 01:07:12 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-1b861b7a-a223-4aaf-857a-d87ed91bee3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660231280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3660231280 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4269302010 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 29316170 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:05 PM PDT 24 |
| Finished | May 28 01:07:10 PM PDT 24 |
| Peak memory | 145680 kb |
| Host | smart-d569e7de-7501-4af5-b89d-57e810a08228 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4269302010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4269302010 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1260216230 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 30601474 ps |
| CPU time | 0.44 seconds |
| Started | May 28 01:07:07 PM PDT 24 |
| Finished | May 28 01:07:13 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-df5af926-2556-4fbf-ad26-516f50632651 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1260216230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1260216230 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2778959797 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29834565 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:07:03 PM PDT 24 |
| Finished | May 28 01:07:08 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-e76de169-5b2a-45cb-8bec-2e8593fc10e6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2778959797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2778959797 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3999414130 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 31280302 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:07:07 PM PDT 24 |
| Finished | May 28 01:07:13 PM PDT 24 |
| Peak memory | 145668 kb |
| Host | smart-d1554c31-4d64-4402-9548-1dc83781bd16 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3999414130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3999414130 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3418234869 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 31350100 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:07:05 PM PDT 24 |
| Finished | May 28 01:07:11 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-f6713245-dca1-4de8-81f5-5a64af25d5c4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3418234869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3418234869 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2902055594 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29747390 ps |
| CPU time | 0.45 seconds |
| Started | May 28 01:07:05 PM PDT 24 |
| Finished | May 28 01:07:10 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-9371cba0-35d3-4745-a798-4b5781426182 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2902055594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2902055594 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3038655110 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29507762 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:04 PM PDT 24 |
| Finished | May 28 01:07:09 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-52039bc6-e20e-42fa-bbb8-c6eacf98d63f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3038655110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3038655110 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1077961437 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 30705402 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:04 PM PDT 24 |
| Finished | May 28 01:07:08 PM PDT 24 |
| Peak memory | 145704 kb |
| Host | smart-c536f406-4d93-48de-9db3-e39fbe3aaeab |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1077961437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1077961437 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3791602200 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 29953054 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:05 PM PDT 24 |
| Finished | May 28 01:07:10 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-84e27108-9b38-4b0d-99b7-d040630391dd |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3791602200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3791602200 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2626552680 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30304719 ps |
| CPU time | 0.43 seconds |
| Started | May 28 01:07:05 PM PDT 24 |
| Finished | May 28 01:07:11 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-fd0c0191-f203-4d22-926f-75b2603a7245 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2626552680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2626552680 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1940754827 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 32033784 ps |
| CPU time | 0.43 seconds |
| Started | May 28 01:07:07 PM PDT 24 |
| Finished | May 28 01:07:13 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-f93d24d0-6e24-4496-919e-ae87848c99d3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1940754827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1940754827 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2383226171 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30416188 ps |
| CPU time | 0.43 seconds |
| Started | May 28 01:07:07 PM PDT 24 |
| Finished | May 28 01:07:13 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-af87fefd-2304-41cd-b8fb-997924d03020 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2383226171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2383226171 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.792414366 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30500461 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:02 PM PDT 24 |
| Finished | May 28 01:07:04 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-1a3f5915-122c-4aae-ac6c-ab3816625e80 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=792414366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.792414366 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.386084157 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 31628630 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:03 PM PDT 24 |
| Finished | May 28 01:07:06 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-85515383-106a-4448-bad2-60562ce6e336 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=386084157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.386084157 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1915620648 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 31289511 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:08 PM PDT 24 |
| Finished | May 28 01:07:14 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-4ebe1a5b-ce67-45fb-95a9-abc36983282d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1915620648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1915620648 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2068702070 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30364663 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:03 PM PDT 24 |
| Finished | May 28 01:07:05 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-afc7078f-50fa-48bf-b91a-3bda4b5558e1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2068702070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2068702070 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1579418677 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30073978 ps |
| CPU time | 0.44 seconds |
| Started | May 28 01:07:10 PM PDT 24 |
| Finished | May 28 01:07:15 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-fa0eaf68-881a-4602-ad7a-606adad7816b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1579418677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1579418677 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.765685957 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30096718 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:03 PM PDT 24 |
| Finished | May 28 01:07:05 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-9bb07906-7da8-4019-9384-c187ae69b6fc |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=765685957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.765685957 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.3838535186 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9863637 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:46 PM PDT 24 |
| Finished | May 28 01:07:48 PM PDT 24 |
| Peak memory | 145520 kb |
| Host | smart-01aa8310-ce6a-43ef-a56c-42b56e7d296f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3838535186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3838535186 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.933782370 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10248541 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:08:01 PM PDT 24 |
| Finished | May 28 01:08:02 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-5a12ea7d-8fe5-48af-b6c7-e4a81c193c18 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=933782370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.933782370 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.1324449428 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9860413 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:07:42 PM PDT 24 |
| Finished | May 28 01:07:44 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-53c3e320-5b1b-49c2-b062-41d3b0f93bab |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1324449428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1324449428 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.4191872763 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8395149 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:07:43 PM PDT 24 |
| Finished | May 28 01:07:45 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-566679f7-b1a5-406e-96e0-0484f988a54a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4191872763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.4191872763 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3034695857 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8302586 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:07:59 PM PDT 24 |
| Finished | May 28 01:08:01 PM PDT 24 |
| Peak memory | 145476 kb |
| Host | smart-ca398278-29ba-43e5-998a-f64290fe3908 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3034695857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3034695857 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1258975077 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9731172 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:57 PM PDT 24 |
| Finished | May 28 01:07:58 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-3df6c50c-b2c5-4a16-96f5-a95e727d5ae8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1258975077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1258975077 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.3339738987 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8433474 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:55 PM PDT 24 |
| Finished | May 28 01:07:56 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-e1c1332c-fd36-4e26-8811-7fbc9a26f52e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3339738987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3339738987 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.2367930830 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9576839 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:41 PM PDT 24 |
| Finished | May 28 01:07:48 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-92d6612a-feb9-4d35-b125-9900b65d6350 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2367930830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2367930830 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.2273518356 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9485106 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:07:49 PM PDT 24 |
| Finished | May 28 01:07:51 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-88687465-e884-4898-9bee-fddbef7dacfd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2273518356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2273518356 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.244554336 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8973902 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:41 PM PDT 24 |
| Finished | May 28 01:07:42 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-ed689fbe-fe0c-430d-9d28-04ade3e23b6b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=244554336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.244554336 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.1097774727 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9657599 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:46 PM PDT 24 |
| Finished | May 28 01:07:47 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-0f5e4512-4a4b-45bc-a6f2-96da236c97d9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1097774727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1097774727 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2788891324 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9066785 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:44 PM PDT 24 |
| Finished | May 28 01:07:45 PM PDT 24 |
| Peak memory | 145448 kb |
| Host | smart-3918ba6e-f540-4edc-9cc4-5e31ec6694a3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2788891324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2788891324 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.1098434951 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9367897 ps |
| CPU time | 0.37 seconds |
| Started | May 28 01:07:55 PM PDT 24 |
| Finished | May 28 01:07:57 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-b91386af-8203-433e-9165-35cbe65d0e3c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1098434951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1098434951 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.2444757346 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9567919 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:57 PM PDT 24 |
| Finished | May 28 01:07:58 PM PDT 24 |
| Peak memory | 145500 kb |
| Host | smart-84c373ae-1c29-4775-a654-9046689ed48a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2444757346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2444757346 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1679948195 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10087316 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:07:43 PM PDT 24 |
| Finished | May 28 01:07:45 PM PDT 24 |
| Peak memory | 145480 kb |
| Host | smart-714b6761-8197-4c87-b6bf-fcd1294b2a5c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1679948195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1679948195 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.889185573 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9788381 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:49 PM PDT 24 |
| Finished | May 28 01:07:51 PM PDT 24 |
| Peak memory | 145504 kb |
| Host | smart-8a30fc21-c0fc-4540-9e98-69af26fb7756 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=889185573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.889185573 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1565390292 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8489413 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:07:50 PM PDT 24 |
| Finished | May 28 01:07:51 PM PDT 24 |
| Peak memory | 145508 kb |
| Host | smart-5b152e3d-444c-4201-a265-b7b844c2e1ba |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1565390292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1565390292 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1524970323 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9668501 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:49 PM PDT 24 |
| Finished | May 28 01:07:50 PM PDT 24 |
| Peak memory | 145480 kb |
| Host | smart-e667711f-b957-40b5-912c-188073c1b36d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1524970323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1524970323 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.2017657527 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8628399 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:07:38 PM PDT 24 |
| Finished | May 28 01:07:49 PM PDT 24 |
| Peak memory | 145516 kb |
| Host | smart-e01a7dbb-008a-434f-af55-c497481e1e6b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2017657527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2017657527 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3845841082 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26771160 ps |
| CPU time | 0.44 seconds |
| Started | May 28 01:07:45 PM PDT 24 |
| Finished | May 28 01:07:46 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-b3b21007-4e50-4768-8abc-3c59b8a07fd5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3845841082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3845841082 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1179529714 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 26312872 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:07:57 PM PDT 24 |
| Finished | May 28 01:07:59 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-2a767851-efa2-4a0e-acfa-891cb69eb224 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1179529714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1179529714 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.585049632 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27636823 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:07:43 PM PDT 24 |
| Finished | May 28 01:07:45 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-999f52dd-5eac-496a-86bb-026ba77b7e98 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=585049632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.585049632 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2004773988 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 28270040 ps |
| CPU time | 0.43 seconds |
| Started | May 28 01:07:47 PM PDT 24 |
| Finished | May 28 01:07:49 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-e904fc9a-b243-44ec-9342-25b51f37e8a7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2004773988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2004773988 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2860599434 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 28709673 ps |
| CPU time | 0.38 seconds |
| Started | May 28 01:07:43 PM PDT 24 |
| Finished | May 28 01:07:44 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-f19d290a-5abe-486f-927f-96279f5a8762 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2860599434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2860599434 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2950278433 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27995971 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:07:53 PM PDT 24 |
| Finished | May 28 01:07:59 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-ba3785c0-be54-4915-b77f-dd0951443860 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2950278433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2950278433 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.732476522 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 26815924 ps |
| CPU time | 0.45 seconds |
| Started | May 28 01:07:51 PM PDT 24 |
| Finished | May 28 01:07:52 PM PDT 24 |
| Peak memory | 145488 kb |
| Host | smart-e0ce3d70-849b-406d-8955-9099701eef1a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=732476522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.732476522 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.991332221 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28412882 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:07:49 PM PDT 24 |
| Finished | May 28 01:07:50 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-47d68510-c2ba-40aa-be43-82e5724eb2c7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=991332221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.991332221 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2977009845 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 27679311 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:08:12 PM PDT 24 |
| Finished | May 28 01:08:14 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-1d0d4cbe-2bbc-42e2-a53e-29d21c7fe083 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2977009845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2977009845 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.617465352 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28207808 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:08:10 PM PDT 24 |
| Finished | May 28 01:08:12 PM PDT 24 |
| Peak memory | 145488 kb |
| Host | smart-c2d22e8c-7548-47ba-9b0e-912236e06a3d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=617465352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.617465352 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3606188949 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26539373 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:57 PM PDT 24 |
| Finished | May 28 01:07:59 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-06cca9c2-f241-47b9-86f5-19edd7bb8d66 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3606188949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3606188949 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3835458089 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 29049185 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:07:41 PM PDT 24 |
| Finished | May 28 01:07:42 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-299d223e-457b-414f-b2c9-8e87293eefbb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3835458089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3835458089 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3432493084 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 29520120 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:39 PM PDT 24 |
| Finished | May 28 01:07:40 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-c0b1ca7a-5df1-4b2c-ac7f-8ba194a93581 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3432493084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3432493084 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1337243797 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26910586 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:46 PM PDT 24 |
| Finished | May 28 01:07:48 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-0cbabf71-a9b9-4891-9594-0fcbf21865f2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1337243797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1337243797 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1458396460 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27308684 ps |
| CPU time | 0.4 seconds |
| Started | May 28 01:07:57 PM PDT 24 |
| Finished | May 28 01:08:03 PM PDT 24 |
| Peak memory | 145488 kb |
| Host | smart-c3e59127-a1d9-4592-98c9-37c8986ea756 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1458396460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1458396460 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3700880355 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28404728 ps |
| CPU time | 0.41 seconds |
| Started | May 28 01:07:37 PM PDT 24 |
| Finished | May 28 01:07:38 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-541f9951-4866-4144-907e-a781b6a64b35 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3700880355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3700880355 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3558734073 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 29793695 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:48 PM PDT 24 |
| Finished | May 28 01:07:50 PM PDT 24 |
| Peak memory | 145488 kb |
| Host | smart-03c4883e-5710-4131-8b22-4c6f17beec0d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3558734073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3558734073 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2226953107 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 26854218 ps |
| CPU time | 0.39 seconds |
| Started | May 28 01:07:52 PM PDT 24 |
| Finished | May 28 01:07:53 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-505d7860-9f0c-462a-8e65-9341130a8861 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2226953107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2226953107 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2750119104 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 29284062 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:08:11 PM PDT 24 |
| Finished | May 28 01:08:13 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-674767ee-1b8d-4195-b9e8-a0e975ca96a5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2750119104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2750119104 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2500778112 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28661835 ps |
| CPU time | 0.42 seconds |
| Started | May 28 01:08:03 PM PDT 24 |
| Finished | May 28 01:08:04 PM PDT 24 |
| Peak memory | 145660 kb |
| Host | smart-62761e71-d670-43dc-9ece-195e48af836e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2500778112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2500778112 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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