Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	100.00	100.00	89.29	95.83	86.05

Total tests in report: 78

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
88.28	88.28	100.00	100.00	93.75	93.75	100.00	100.00	75.00	75.00	95.83	95.83	65.12	65.12	/workspace/coverage/default/3.prim_async_alert.2378349724
91.41	3.13	100.00	0.00	93.75	0.00	100.00	0.00	82.14	7.14	95.83	0.00	76.74	11.63	/workspace/coverage/sync_alert/13.prim_sync_alert.3157507382
93.90	2.49	100.00	0.00	95.83	2.08	100.00	0.00	85.71	3.57	95.83	0.00	86.05	9.30	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4286722482
94.85	0.94	100.00	0.00	97.92	2.08	100.00	0.00	89.29	3.57	95.83	0.00	86.05	0.00	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1319547988
95.19	0.35	100.00	0.00	100.00	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspace/coverage/sync_alert/17.prim_sync_alert.1654228570

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3791742660
/workspace/coverage/default/1.prim_async_alert.593674803
/workspace/coverage/default/10.prim_async_alert.3070777959
/workspace/coverage/default/11.prim_async_alert.2923117049
/workspace/coverage/default/12.prim_async_alert.4071848857
/workspace/coverage/default/13.prim_async_alert.3171420199
/workspace/coverage/default/14.prim_async_alert.2864896886
/workspace/coverage/default/15.prim_async_alert.897938573
/workspace/coverage/default/17.prim_async_alert.2987731943
/workspace/coverage/default/18.prim_async_alert.899726262
/workspace/coverage/default/19.prim_async_alert.2211295185
/workspace/coverage/default/2.prim_async_alert.2990903719
/workspace/coverage/default/4.prim_async_alert.566332635
/workspace/coverage/default/5.prim_async_alert.3044198807
/workspace/coverage/default/6.prim_async_alert.373565411
/workspace/coverage/default/7.prim_async_alert.1922640005
/workspace/coverage/default/8.prim_async_alert.881672416
/workspace/coverage/default/9.prim_async_alert.40114417
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2596380031
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3633270617
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.667936165
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2499921193
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3117925778
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4113024759
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.618593410
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.495601389
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2250194825
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4223797842
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.733224246
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1102235432
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3235534600
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2381887124
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.455450997
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1489852550
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.709048489
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3460334759
/workspace/coverage/sync_alert/0.prim_sync_alert.3827731199
/workspace/coverage/sync_alert/1.prim_sync_alert.2009683759
/workspace/coverage/sync_alert/10.prim_sync_alert.3987199441
/workspace/coverage/sync_alert/11.prim_sync_alert.723772025
/workspace/coverage/sync_alert/12.prim_sync_alert.1859725649
/workspace/coverage/sync_alert/14.prim_sync_alert.26655679
/workspace/coverage/sync_alert/15.prim_sync_alert.2921555773
/workspace/coverage/sync_alert/16.prim_sync_alert.4222781012
/workspace/coverage/sync_alert/18.prim_sync_alert.2560305015
/workspace/coverage/sync_alert/19.prim_sync_alert.285432048
/workspace/coverage/sync_alert/2.prim_sync_alert.3780881900
/workspace/coverage/sync_alert/3.prim_sync_alert.2643852334
/workspace/coverage/sync_alert/4.prim_sync_alert.3472965051
/workspace/coverage/sync_alert/5.prim_sync_alert.1910488813
/workspace/coverage/sync_alert/6.prim_sync_alert.387136718
/workspace/coverage/sync_alert/7.prim_sync_alert.1287540607
/workspace/coverage/sync_alert/8.prim_sync_alert.2900516593
/workspace/coverage/sync_alert/9.prim_sync_alert.1842170101
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1106661900
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1988723283
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2553604405
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2708214253
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3794535933
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3545148861
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3786921013
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3238009201
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1243218838
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.403800498
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.518107311
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1520768290
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1940858516
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.77238630
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3892345046
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1710468923
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1323841546
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.17953783
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2567056997

Total test records in report: 78

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/12.prim_async_alert.4071848857	May 30 12:23:05 PM PDT 24	May 30 12:23:06 PM PDT 24	12314514 ps
T2	/workspace/coverage/default/9.prim_async_alert.40114417	May 30 12:27:47 PM PDT 24	May 30 12:27:49 PM PDT 24	11354350 ps
T3	/workspace/coverage/default/2.prim_async_alert.2990903719	May 30 12:23:09 PM PDT 24	May 30 12:23:10 PM PDT 24	11199754 ps
T10	/workspace/coverage/default/11.prim_async_alert.2923117049	May 30 12:23:02 PM PDT 24	May 30 12:23:04 PM PDT 24	11655039 ps
T20	/workspace/coverage/default/17.prim_async_alert.2987731943	May 30 12:24:47 PM PDT 24	May 30 12:24:49 PM PDT 24	10849547 ps
T21	/workspace/coverage/default/19.prim_async_alert.2211295185	May 30 12:23:00 PM PDT 24	May 30 12:23:01 PM PDT 24	11000455 ps
T7	/workspace/coverage/default/14.prim_async_alert.2864896886	May 30 12:22:57 PM PDT 24	May 30 12:22:58 PM PDT 24	11918684 ps
T22	/workspace/coverage/default/8.prim_async_alert.881672416	May 30 12:23:02 PM PDT 24	May 30 12:23:04 PM PDT 24	11082020 ps
T8	/workspace/coverage/default/3.prim_async_alert.2378349724	May 30 12:23:02 PM PDT 24	May 30 12:23:04 PM PDT 24	11625332 ps
T23	/workspace/coverage/default/0.prim_async_alert.3791742660	May 30 12:22:57 PM PDT 24	May 30 12:22:58 PM PDT 24	11588829 ps
T24	/workspace/coverage/default/1.prim_async_alert.593674803	May 30 12:23:05 PM PDT 24	May 30 12:23:06 PM PDT 24	10737784 ps
T25	/workspace/coverage/default/6.prim_async_alert.373565411	May 30 12:23:08 PM PDT 24	May 30 12:23:09 PM PDT 24	11536270 ps
T17	/workspace/coverage/default/15.prim_async_alert.897938573	May 30 12:23:02 PM PDT 24	May 30 12:23:04 PM PDT 24	11142020 ps
T48	/workspace/coverage/default/10.prim_async_alert.3070777959	May 30 12:23:05 PM PDT 24	May 30 12:23:06 PM PDT 24	11633875 ps
T49	/workspace/coverage/default/7.prim_async_alert.1922640005	May 30 12:22:57 PM PDT 24	May 30 12:22:58 PM PDT 24	11182669 ps
T50	/workspace/coverage/default/4.prim_async_alert.566332635	May 30 12:23:05 PM PDT 24	May 30 12:23:06 PM PDT 24	10712736 ps
T13	/workspace/coverage/default/18.prim_async_alert.899726262	May 30 12:23:05 PM PDT 24	May 30 12:23:06 PM PDT 24	12100340 ps
T51	/workspace/coverage/default/5.prim_async_alert.3044198807	May 30 12:23:31 PM PDT 24	May 30 12:23:32 PM PDT 24	11661351 ps
T14	/workspace/coverage/default/13.prim_async_alert.3171420199	May 30 12:27:47 PM PDT 24	May 30 12:27:49 PM PDT 24	11608346 ps
T43	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2596380031	May 30 12:22:52 PM PDT 24	May 30 12:22:53 PM PDT 24	30223316 ps
T9	/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3117925778	May 30 12:24:03 PM PDT 24	May 30 12:24:05 PM PDT 24	30016621 ps
T44	/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.667936165	May 30 12:28:21 PM PDT 24	May 30 12:28:23 PM PDT 24	30091513 ps
T4	/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.709048489	May 30 12:23:01 PM PDT 24	May 30 12:23:03 PM PDT 24	31153188 ps
T26	/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2499921193	May 30 12:23:01 PM PDT 24	May 30 12:23:03 PM PDT 24	31370779 ps
T45	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4223797842	May 30 12:28:20 PM PDT 24	May 30 12:28:21 PM PDT 24	29620655 ps
T15	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4286722482	May 30 12:22:57 PM PDT 24	May 30 12:22:58 PM PDT 24	32243268 ps
T46	/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3633270617	May 30 12:27:47 PM PDT 24	May 30 12:27:49 PM PDT 24	30592255 ps
T27	/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3460334759	May 30 12:23:01 PM PDT 24	May 30 12:23:03 PM PDT 24	30587301 ps
T47	/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.733224246	May 30 12:23:31 PM PDT 24	May 30 12:23:33 PM PDT 24	29130516 ps
T52	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2381887124	May 30 12:23:26 PM PDT 24	May 30 12:23:27 PM PDT 24	32544904 ps
T53	/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.495601389	May 30 12:24:03 PM PDT 24	May 30 12:24:05 PM PDT 24	30702308 ps
T54	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1102235432	May 30 12:23:05 PM PDT 24	May 30 12:23:06 PM PDT 24	29608443 ps
T28	/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.618593410	May 30 12:24:03 PM PDT 24	May 30 12:24:05 PM PDT 24	30365786 ps
T55	/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4113024759	May 30 12:26:55 PM PDT 24	May 30 12:26:56 PM PDT 24	29803969 ps
T56	/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2250194825	May 30 12:28:20 PM PDT 24	May 30 12:28:22 PM PDT 24	29658206 ps
T57	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.455450997	May 30 12:24:58 PM PDT 24	May 30 12:24:59 PM PDT 24	28543061 ps
T58	/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3235534600	May 30 12:23:01 PM PDT 24	May 30 12:23:03 PM PDT 24	30790265 ps
T59	/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1489852550	May 30 12:23:01 PM PDT 24	May 30 12:23:02 PM PDT 24	31505044 ps
T35	/workspace/coverage/sync_alert/11.prim_sync_alert.723772025	May 30 12:26:02 PM PDT 24	May 30 12:26:03 PM PDT 24	8540264 ps
T36	/workspace/coverage/sync_alert/6.prim_sync_alert.387136718	May 30 12:24:04 PM PDT 24	May 30 12:24:05 PM PDT 24	8474724 ps
T37	/workspace/coverage/sync_alert/3.prim_sync_alert.2643852334	May 30 12:23:47 PM PDT 24	May 30 12:23:48 PM PDT 24	8826488 ps
T18	/workspace/coverage/sync_alert/0.prim_sync_alert.3827731199	May 30 12:24:04 PM PDT 24	May 30 12:24:05 PM PDT 24	9482220 ps
T19	/workspace/coverage/sync_alert/10.prim_sync_alert.3987199441	May 30 12:28:28 PM PDT 24	May 30 12:28:29 PM PDT 24	9145271 ps
T38	/workspace/coverage/sync_alert/13.prim_sync_alert.3157507382	May 30 12:28:37 PM PDT 24	May 30 12:28:39 PM PDT 24	8240130 ps
T29	/workspace/coverage/sync_alert/9.prim_sync_alert.1842170101	May 30 12:24:03 PM PDT 24	May 30 12:24:05 PM PDT 24	8993593 ps
T39	/workspace/coverage/sync_alert/16.prim_sync_alert.4222781012	May 30 12:25:39 PM PDT 24	May 30 12:25:41 PM PDT 24	9887852 ps
T40	/workspace/coverage/sync_alert/2.prim_sync_alert.3780881900	May 30 12:23:47 PM PDT 24	May 30 12:23:49 PM PDT 24	8395583 ps
T41	/workspace/coverage/sync_alert/7.prim_sync_alert.1287540607	May 30 12:28:20 PM PDT 24	May 30 12:28:21 PM PDT 24	8103814 ps
T42	/workspace/coverage/sync_alert/1.prim_sync_alert.2009683759	May 30 12:28:23 PM PDT 24	May 30 12:28:25 PM PDT 24	8641435 ps
T11	/workspace/coverage/sync_alert/17.prim_sync_alert.1654228570	May 30 12:25:37 PM PDT 24	May 30 12:25:39 PM PDT 24	8831373 ps
T60	/workspace/coverage/sync_alert/14.prim_sync_alert.26655679	May 30 12:29:02 PM PDT 24	May 30 12:29:03 PM PDT 24	10019495 ps
T61	/workspace/coverage/sync_alert/4.prim_sync_alert.3472965051	May 30 12:24:03 PM PDT 24	May 30 12:24:05 PM PDT 24	8794239 ps
T62	/workspace/coverage/sync_alert/12.prim_sync_alert.1859725649	May 30 12:29:10 PM PDT 24	May 30 12:29:12 PM PDT 24	10253799 ps
T63	/workspace/coverage/sync_alert/15.prim_sync_alert.2921555773	May 30 12:23:01 PM PDT 24	May 30 12:23:03 PM PDT 24	9757240 ps
T30	/workspace/coverage/sync_alert/8.prim_sync_alert.2900516593	May 30 12:24:04 PM PDT 24	May 30 12:24:05 PM PDT 24	9345178 ps
T64	/workspace/coverage/sync_alert/19.prim_sync_alert.285432048	May 30 12:29:03 PM PDT 24	May 30 12:29:05 PM PDT 24	8681120 ps
T31	/workspace/coverage/sync_alert/5.prim_sync_alert.1910488813	May 30 12:24:24 PM PDT 24	May 30 12:24:25 PM PDT 24	9022275 ps
T65	/workspace/coverage/sync_alert/18.prim_sync_alert.2560305015	May 30 12:24:38 PM PDT 24	May 30 12:24:39 PM PDT 24	9595359 ps
T32	/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3794535933	May 30 12:28:52 PM PDT 24	May 30 12:28:53 PM PDT 24	26438417 ps
T5	/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.17953783	May 30 12:26:56 PM PDT 24	May 30 12:26:57 PM PDT 24	26944710 ps
T66	/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1520768290	May 30 12:24:03 PM PDT 24	May 30 12:24:05 PM PDT 24	25867813 ps
T33	/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3545148861	May 30 12:23:56 PM PDT 24	May 30 12:23:57 PM PDT 24	26278431 ps
T34	/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3892345046	May 30 12:24:04 PM PDT 24	May 30 12:24:05 PM PDT 24	26844319 ps
T6	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1319547988	May 30 12:28:28 PM PDT 24	May 30 12:28:29 PM PDT 24	28431789 ps
T67	/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.77238630	May 30 12:26:14 PM PDT 24	May 30 12:26:16 PM PDT 24	29136615 ps
T68	/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3786921013	May 30 12:28:52 PM PDT 24	May 30 12:28:53 PM PDT 24	29646882 ps
T69	/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2553604405	May 30 12:28:28 PM PDT 24	May 30 12:28:30 PM PDT 24	26501002 ps
T70	/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3238009201	May 30 12:28:37 PM PDT 24	May 30 12:28:38 PM PDT 24	27574814 ps
T71	/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1710468923	May 30 12:24:37 PM PDT 24	May 30 12:24:38 PM PDT 24	25843941 ps
T12	/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1940858516	May 30 12:24:03 PM PDT 24	May 30 12:24:05 PM PDT 24	27680255 ps
T72	/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1243218838	May 30 12:24:31 PM PDT 24	May 30 12:24:32 PM PDT 24	27064468 ps
T73	/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.403800498	May 30 12:28:37 PM PDT 24	May 30 12:28:39 PM PDT 24	28934968 ps
T74	/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1323841546	May 30 12:28:21 PM PDT 24	May 30 12:28:22 PM PDT 24	27260060 ps
T75	/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1106661900	May 30 12:28:20 PM PDT 24	May 30 12:28:21 PM PDT 24	28811616 ps
T16	/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2567056997	May 30 12:28:21 PM PDT 24	May 30 12:28:23 PM PDT 24	25999749 ps
T76	/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2708214253	May 30 12:28:28 PM PDT 24	May 30 12:28:29 PM PDT 24	27518040 ps
T77	/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1988723283	May 30 12:23:04 PM PDT 24	May 30 12:23:06 PM PDT 24	25437485 ps
T78	/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.518107311	May 30 12:26:01 PM PDT 24	May 30 12:26:03 PM PDT 24	26844868 ps

Test location	/workspace/coverage/default/3.prim_async_alert.2378349724
Short name	T8
Test name
Test status
Simulation time	11625332 ps
CPU time	0.44 seconds
Started	May 30 12:23:02 PM PDT 24
Finished	May 30 12:23:04 PM PDT 24
Peak memory	145248 kb
Host	smart-48bd03bc-e90f-448d-9b6a-30618fbd5874
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2378349724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2378349724
Directory	/workspace/3.prim_async_alert/latest

Test location	/workspace/coverage/sync_alert/13.prim_sync_alert.3157507382
Short name	T38
Test name
Test status
Simulation time	8240130 ps
CPU time	0.4 seconds
Started	May 30 12:28:37 PM PDT 24
Finished	May 30 12:28:39 PM PDT 24
Peak memory	144692 kb
Host	smart-b6d57342-440d-4486-a823-2c1c6299f696
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3157507382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3157507382
Directory	/workspace/13.prim_sync_alert/latest

Test location	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4286722482
Short name	T15
Test name
Test status
Simulation time	32243268 ps
CPU time	0.42 seconds
Started	May 30 12:22:57 PM PDT 24
Finished	May 30 12:22:58 PM PDT 24
Peak memory	145180 kb
Host	smart-ac8869f1-115c-4094-84b4-6a8233cd463e
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4286722482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4286722482
Directory	/workspace/0.prim_async_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1319547988
Short name	T6
Test name
Test status
Simulation time	28431789 ps
CPU time	0.45 seconds
Started	May 30 12:28:28 PM PDT 24
Finished	May 30 12:28:29 PM PDT 24
Peak memory	144128 kb
Host	smart-960369bd-9d11-47bd-85e2-fe7d33034b51
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1319547988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1319547988
Directory	/workspace/10.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_alert/17.prim_sync_alert.1654228570
Short name	T11
Test name
Test status
Simulation time	8831373 ps
CPU time	0.41 seconds
Started	May 30 12:25:37 PM PDT 24
Finished	May 30 12:25:39 PM PDT 24
Peak memory	145408 kb
Host	smart-ac304375-e327-4bc7-998d-86c34e7d561a
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1654228570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1654228570
Directory	/workspace/17.prim_sync_alert/latest

Test location	/workspace/coverage/default/0.prim_async_alert.3791742660
Short name	T23
Test name
Test status
Simulation time	11588829 ps
CPU time	0.4 seconds
Started	May 30 12:22:57 PM PDT 24
Finished	May 30 12:22:58 PM PDT 24
Peak memory	145264 kb
Host	smart-b2de5f35-c9aa-48a2-bf5c-d263faba5710
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3791742660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3791742660
Directory	/workspace/0.prim_async_alert/latest

Test location	/workspace/coverage/default/1.prim_async_alert.593674803
Short name	T24
Test name
Test status
Simulation time	10737784 ps
CPU time	0.48 seconds
Started	May 30 12:23:05 PM PDT 24
Finished	May 30 12:23:06 PM PDT 24
Peak memory	143008 kb
Host	smart-f6e5f749-2743-4c0d-922d-0111fb675000
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=593674803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.593674803
Directory	/workspace/1.prim_async_alert/latest

Test location	/workspace/coverage/default/10.prim_async_alert.3070777959
Short name	T48
Test name
Test status
Simulation time	11633875 ps
CPU time	0.48 seconds
Started	May 30 12:23:05 PM PDT 24
Finished	May 30 12:23:06 PM PDT 24
Peak memory	143524 kb
Host	smart-9004138d-b90e-45eb-9ea2-5c2f81cf52ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3070777959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3070777959
Directory	/workspace/10.prim_async_alert/latest

Test location	/workspace/coverage/default/11.prim_async_alert.2923117049
Short name	T10
Test name
Test status
Simulation time	11655039 ps
CPU time	0.45 seconds
Started	May 30 12:23:02 PM PDT 24
Finished	May 30 12:23:04 PM PDT 24
Peak memory	143612 kb
Host	smart-220fa933-e268-4519-a1d9-f1a885400a8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923117049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2923117049
Directory	/workspace/11.prim_async_alert/latest

Test location	/workspace/coverage/default/12.prim_async_alert.4071848857
Short name	T1
Test name
Test status
Simulation time	12314514 ps
CPU time	0.41 seconds
Started	May 30 12:23:05 PM PDT 24
Finished	May 30 12:23:06 PM PDT 24
Peak memory	144592 kb
Host	smart-37993b6f-8b47-470a-b695-ead85dcbc250
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4071848857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.4071848857
Directory	/workspace/12.prim_async_alert/latest

Test location	/workspace/coverage/default/13.prim_async_alert.3171420199
Short name	T14
Test name
Test status
Simulation time	11608346 ps
CPU time	0.41 seconds
Started	May 30 12:27:47 PM PDT 24
Finished	May 30 12:27:49 PM PDT 24
Peak memory	145000 kb
Host	smart-f3d2ebc1-9b76-419a-99ac-17931fe58d66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3171420199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3171420199
Directory	/workspace/13.prim_async_alert/latest

Test location	/workspace/coverage/default/14.prim_async_alert.2864896886
Short name	T7
Test name
Test status
Simulation time	11918684 ps
CPU time	0.41 seconds
Started	May 30 12:22:57 PM PDT 24
Finished	May 30 12:22:58 PM PDT 24
Peak memory	145476 kb
Host	smart-415b3a0c-e7fa-496b-8d26-5b2a5af676fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2864896886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2864896886
Directory	/workspace/14.prim_async_alert/latest

Test location	/workspace/coverage/default/15.prim_async_alert.897938573
Short name	T17
Test name
Test status
Simulation time	11142020 ps
CPU time	0.43 seconds
Started	May 30 12:23:02 PM PDT 24
Finished	May 30 12:23:04 PM PDT 24
Peak memory	144000 kb
Host	smart-a10cc0ad-49f7-4327-9ae4-1ba37fddc777
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=897938573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.897938573
Directory	/workspace/15.prim_async_alert/latest

Test location	/workspace/coverage/default/17.prim_async_alert.2987731943
Short name	T20
Test name
Test status
Simulation time	10849547 ps
CPU time	0.39 seconds
Started	May 30 12:24:47 PM PDT 24
Finished	May 30 12:24:49 PM PDT 24
Peak memory	145756 kb
Host	smart-a177dc20-9f73-45da-9d7c-ae5a99a358cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987731943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2987731943
Directory	/workspace/17.prim_async_alert/latest

Test location	/workspace/coverage/default/18.prim_async_alert.899726262
Short name	T13
Test name
Test status
Simulation time	12100340 ps
CPU time	0.44 seconds
Started	May 30 12:23:05 PM PDT 24
Finished	May 30 12:23:06 PM PDT 24
Peak memory	143712 kb
Host	smart-8af965a2-5746-4b8c-9d37-6cc01e27a02f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=899726262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.899726262
Directory	/workspace/18.prim_async_alert/latest

Test location	/workspace/coverage/default/19.prim_async_alert.2211295185
Short name	T21
Test name
Test status
Simulation time	11000455 ps
CPU time	0.39 seconds
Started	May 30 12:23:00 PM PDT 24
Finished	May 30 12:23:01 PM PDT 24
Peak memory	145616 kb
Host	smart-9ef0409f-473e-4647-bcf9-1d116eee72bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2211295185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2211295185
Directory	/workspace/19.prim_async_alert/latest

Test location	/workspace/coverage/default/2.prim_async_alert.2990903719
Short name	T3
Test name
Test status
Simulation time	11199754 ps
CPU time	0.39 seconds
Started	May 30 12:23:09 PM PDT 24
Finished	May 30 12:23:10 PM PDT 24
Peak memory	145740 kb
Host	smart-a84d6c10-b296-4c99-9525-265c5ee6170e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990903719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2990903719
Directory	/workspace/2.prim_async_alert/latest

Test location	/workspace/coverage/default/4.prim_async_alert.566332635
Short name	T50
Test name
Test status
Simulation time	10712736 ps
CPU time	0.43 seconds
Started	May 30 12:23:05 PM PDT 24
Finished	May 30 12:23:06 PM PDT 24
Peak memory	143200 kb
Host	smart-4c9ac8b7-a36a-4bc1-a733-e5cf97817d65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=566332635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.566332635
Directory	/workspace/4.prim_async_alert/latest

Test location	/workspace/coverage/default/5.prim_async_alert.3044198807
Short name	T51
Test name
Test status
Simulation time	11661351 ps
CPU time	0.39 seconds
Started	May 30 12:23:31 PM PDT 24
Finished	May 30 12:23:32 PM PDT 24
Peak memory	145776 kb
Host	smart-e1883503-cce3-49cd-a45a-735d88c6072c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044198807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3044198807
Directory	/workspace/5.prim_async_alert/latest

Test location	/workspace/coverage/default/6.prim_async_alert.373565411
Short name	T25
Test name
Test status
Simulation time	11536270 ps
CPU time	0.4 seconds
Started	May 30 12:23:08 PM PDT 24
Finished	May 30 12:23:09 PM PDT 24
Peak memory	145740 kb
Host	smart-3a1ad621-770a-4d52-9052-689a9d915350
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373565411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.373565411
Directory	/workspace/6.prim_async_alert/latest

Test location	/workspace/coverage/default/7.prim_async_alert.1922640005
Short name	T49
Test name
Test status
Simulation time	11182669 ps
CPU time	0.39 seconds
Started	May 30 12:22:57 PM PDT 24
Finished	May 30 12:22:58 PM PDT 24
Peak memory	145776 kb
Host	smart-0794841b-fd33-4c56-ab79-89fb4ad3cf92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1922640005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1922640005
Directory	/workspace/7.prim_async_alert/latest

Test location	/workspace/coverage/default/8.prim_async_alert.881672416
Short name	T22
Test name
Test status
Simulation time	11082020 ps
CPU time	0.39 seconds
Started	May 30 12:23:02 PM PDT 24
Finished	May 30 12:23:04 PM PDT 24
Peak memory	145192 kb
Host	smart-48c54e9d-8309-486e-a942-29d9cea9c05c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=881672416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.881672416
Directory	/workspace/8.prim_async_alert/latest

Test location	/workspace/coverage/default/9.prim_async_alert.40114417
Short name	T2
Test name
Test status
Simulation time	11354350 ps
CPU time	0.42 seconds
Started	May 30 12:27:47 PM PDT 24
Finished	May 30 12:27:49 PM PDT 24
Peak memory	145176 kb
Host	smart-00909345-6238-4256-9dd4-e279945c4039
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40114417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.40114417
Directory	/workspace/9.prim_async_alert/latest

Test location	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2596380031
Short name	T43
Test name
Test status
Simulation time	30223316 ps
CPU time	0.45 seconds
Started	May 30 12:22:52 PM PDT 24
Finished	May 30 12:22:53 PM PDT 24
Peak memory	145596 kb
Host	smart-4a48211a-cb63-403a-82f1-911647e283fd
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2596380031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2596380031
Directory	/workspace/1.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3633270617
Short name	T46
Test name
Test status
Simulation time	30592255 ps
CPU time	0.39 seconds
Started	May 30 12:27:47 PM PDT 24
Finished	May 30 12:27:49 PM PDT 24
Peak memory	146176 kb
Host	smart-8cce1cbb-cbab-4ed1-b963-625ad813d2c1
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3633270617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3633270617
Directory	/workspace/10.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.667936165
Short name	T44
Test name
Test status
Simulation time	30091513 ps
CPU time	0.42 seconds
Started	May 30 12:28:21 PM PDT 24
Finished	May 30 12:28:23 PM PDT 24
Peak memory	145188 kb
Host	smart-620f43de-7798-45ea-8563-d10724a62779
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=667936165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.667936165
Directory	/workspace/11.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2499921193
Short name	T26
Test name
Test status
Simulation time	31370779 ps
CPU time	0.4 seconds
Started	May 30 12:23:01 PM PDT 24
Finished	May 30 12:23:03 PM PDT 24
Peak memory	145608 kb
Host	smart-4bbd9ada-74ea-464b-b56f-1d1a2248849b
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2499921193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2499921193
Directory	/workspace/13.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3117925778
Short name	T9
Test name
Test status
Simulation time	30016621 ps
CPU time	0.49 seconds
Started	May 30 12:24:03 PM PDT 24
Finished	May 30 12:24:05 PM PDT 24
Peak memory	143184 kb
Host	smart-e9f559f1-f5b6-46df-abf3-485fc684d157
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3117925778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3117925778
Directory	/workspace/14.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4113024759
Short name	T55
Test name
Test status
Simulation time	29803969 ps
CPU time	0.41 seconds
Started	May 30 12:26:55 PM PDT 24
Finished	May 30 12:26:56 PM PDT 24
Peak memory	145692 kb
Host	smart-bd4a0dbc-05df-4751-bea1-a73f8d1ca8ea
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4113024759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.4113024759
Directory	/workspace/15.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.618593410
Short name	T28
Test name
Test status
Simulation time	30365786 ps
CPU time	0.54 seconds
Started	May 30 12:24:03 PM PDT 24
Finished	May 30 12:24:05 PM PDT 24
Peak memory	144852 kb
Host	smart-cde5832c-8876-48cd-b103-92fabb51aa11
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=618593410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.618593410
Directory	/workspace/16.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.495601389
Short name	T53
Test name
Test status
Simulation time	30702308 ps
CPU time	0.47 seconds
Started	May 30 12:24:03 PM PDT 24
Finished	May 30 12:24:05 PM PDT 24
Peak memory	143988 kb
Host	smart-2426ae84-05d8-4dbf-8e01-80f11a1d50ec
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=495601389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.495601389
Directory	/workspace/17.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2250194825
Short name	T56
Test name
Test status
Simulation time	29658206 ps
CPU time	0.45 seconds
Started	May 30 12:28:20 PM PDT 24
Finished	May 30 12:28:22 PM PDT 24
Peak memory	145164 kb
Host	smart-2e78cfa6-525b-4cb6-a32b-2ce926cae0c2
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2250194825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2250194825
Directory	/workspace/18.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4223797842
Short name	T45
Test name
Test status
Simulation time	29620655 ps
CPU time	0.45 seconds
Started	May 30 12:28:20 PM PDT 24
Finished	May 30 12:28:21 PM PDT 24
Peak memory	144488 kb
Host	smart-94184436-464d-40f8-b7a4-0851a49f1726
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4223797842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.4223797842
Directory	/workspace/19.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.733224246
Short name	T47
Test name
Test status
Simulation time	29130516 ps
CPU time	0.41 seconds
Started	May 30 12:23:31 PM PDT 24
Finished	May 30 12:23:33 PM PDT 24
Peak memory	145436 kb
Host	smart-e9abfc88-f166-42cd-aa8f-f9923c729fbf
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=733224246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.733224246
Directory	/workspace/2.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1102235432
Short name	T54
Test name
Test status
Simulation time	29608443 ps
CPU time	0.48 seconds
Started	May 30 12:23:05 PM PDT 24
Finished	May 30 12:23:06 PM PDT 24
Peak memory	143300 kb
Host	smart-0ff315a3-4746-468b-b3e6-5b870e0d4270
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1102235432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1102235432
Directory	/workspace/3.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3235534600
Short name	T58
Test name
Test status
Simulation time	30790265 ps
CPU time	0.4 seconds
Started	May 30 12:23:01 PM PDT 24
Finished	May 30 12:23:03 PM PDT 24
Peak memory	145592 kb
Host	smart-9a523073-17eb-4df2-b50b-415bd285ba45
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3235534600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3235534600
Directory	/workspace/4.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2381887124
Short name	T52
Test name
Test status
Simulation time	32544904 ps
CPU time	0.41 seconds
Started	May 30 12:23:26 PM PDT 24
Finished	May 30 12:23:27 PM PDT 24
Peak memory	145432 kb
Host	smart-9c37c815-1086-417c-b422-b8bf6f2d7c10
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2381887124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2381887124
Directory	/workspace/5.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.455450997
Short name	T57
Test name
Test status
Simulation time	28543061 ps
CPU time	0.41 seconds
Started	May 30 12:24:58 PM PDT 24
Finished	May 30 12:24:59 PM PDT 24
Peak memory	145732 kb
Host	smart-d33cb7b9-e3d0-403f-b28a-4203fc1ba6f0
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=455450997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.455450997
Directory	/workspace/6.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1489852550
Short name	T59
Test name
Test status
Simulation time	31505044 ps
CPU time	0.41 seconds
Started	May 30 12:23:01 PM PDT 24
Finished	May 30 12:23:02 PM PDT 24
Peak memory	145736 kb
Host	smart-5f9e87f9-58f7-4eae-a2c5-f96ec05a8b11
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1489852550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1489852550
Directory	/workspace/7.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.709048489
Short name	T4
Test name
Test status
Simulation time	31153188 ps
CPU time	0.41 seconds
Started	May 30 12:23:01 PM PDT 24
Finished	May 30 12:23:03 PM PDT 24
Peak memory	145752 kb
Host	smart-c61dc779-667c-43d1-832f-5a7eb045c282
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=709048489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.709048489
Directory	/workspace/8.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3460334759
Short name	T27
Test name
Test status
Simulation time	30587301 ps
CPU time	0.41 seconds
Started	May 30 12:23:01 PM PDT 24
Finished	May 30 12:23:03 PM PDT 24
Peak memory	145736 kb
Host	smart-87a9709d-d712-42bc-b33b-dab3d3edbf35
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3460334759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3460334759
Directory	/workspace/9.prim_async_fatal_alert/latest

Test location	/workspace/coverage/sync_alert/0.prim_sync_alert.3827731199
Short name	T18
Test name
Test status
Simulation time	9482220 ps
CPU time	0.37 seconds
Started	May 30 12:24:04 PM PDT 24
Finished	May 30 12:24:05 PM PDT 24
Peak memory	144976 kb
Host	smart-cb1bf7ae-ccc1-4222-8be4-a4d48e388953
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3827731199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3827731199
Directory	/workspace/0.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/1.prim_sync_alert.2009683759
Short name	T42
Test name
Test status
Simulation time	8641435 ps
CPU time	0.42 seconds
Started	May 30 12:28:23 PM PDT 24
Finished	May 30 12:28:25 PM PDT 24
Peak memory	145832 kb
Host	smart-f5f69844-a946-4592-ad29-d7cb69970ca6
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2009683759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2009683759
Directory	/workspace/1.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/10.prim_sync_alert.3987199441
Short name	T19
Test name
Test status
Simulation time	9145271 ps
CPU time	0.36 seconds
Started	May 30 12:28:28 PM PDT 24
Finished	May 30 12:28:29 PM PDT 24
Peak memory	144976 kb
Host	smart-ee1eab5c-b7a1-4942-a2d3-bd224b3ce560
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3987199441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3987199441
Directory	/workspace/10.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/11.prim_sync_alert.723772025
Short name	T35
Test name
Test status
Simulation time	8540264 ps
CPU time	0.36 seconds
Started	May 30 12:26:02 PM PDT 24
Finished	May 30 12:26:03 PM PDT 24
Peak memory	145000 kb
Host	smart-7100ca13-cc0a-48f4-986e-b2d0499f62af
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=723772025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.723772025
Directory	/workspace/11.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/12.prim_sync_alert.1859725649
Short name	T62
Test name
Test status
Simulation time	10253799 ps
CPU time	0.45 seconds
Started	May 30 12:29:10 PM PDT 24
Finished	May 30 12:29:12 PM PDT 24
Peak memory	144752 kb
Host	smart-6fed43b7-9d19-4d12-bb5e-7d84299740cf
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1859725649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1859725649
Directory	/workspace/12.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/14.prim_sync_alert.26655679
Short name	T60
Test name
Test status
Simulation time	10019495 ps
CPU time	0.41 seconds
Started	May 30 12:29:02 PM PDT 24
Finished	May 30 12:29:03 PM PDT 24
Peak memory	145836 kb
Host	smart-59d6f781-d55f-485b-adcb-9a8696ac666f
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=26655679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.26655679
Directory	/workspace/14.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/15.prim_sync_alert.2921555773
Short name	T63
Test name
Test status
Simulation time	9757240 ps
CPU time	0.47 seconds
Started	May 30 12:23:01 PM PDT 24
Finished	May 30 12:23:03 PM PDT 24
Peak memory	145844 kb
Host	smart-ef77645f-b1c0-47f2-977d-d2444090f962
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2921555773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2921555773
Directory	/workspace/15.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/16.prim_sync_alert.4222781012
Short name	T39
Test name
Test status
Simulation time	9887852 ps
CPU time	0.4 seconds
Started	May 30 12:25:39 PM PDT 24
Finished	May 30 12:25:41 PM PDT 24
Peak memory	145560 kb
Host	smart-8f6ae21b-54e2-4646-a816-7384b811112a
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4222781012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.4222781012
Directory	/workspace/16.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/18.prim_sync_alert.2560305015
Short name	T65
Test name
Test status
Simulation time	9595359 ps
CPU time	0.4 seconds
Started	May 30 12:24:38 PM PDT 24
Finished	May 30 12:24:39 PM PDT 24
Peak memory	145220 kb
Host	smart-4938a9b8-c604-4979-95aa-ac6d145a99e8
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2560305015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2560305015
Directory	/workspace/18.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/19.prim_sync_alert.285432048
Short name	T64
Test name
Test status
Simulation time	8681120 ps
CPU time	0.41 seconds
Started	May 30 12:29:03 PM PDT 24
Finished	May 30 12:29:05 PM PDT 24
Peak memory	145004 kb
Host	smart-7331d94b-e024-4189-ae18-8b74908ce3fc
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=285432048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.285432048
Directory	/workspace/19.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/2.prim_sync_alert.3780881900
Short name	T40
Test name
Test status
Simulation time	8395583 ps
CPU time	0.39 seconds
Started	May 30 12:23:47 PM PDT 24
Finished	May 30 12:23:49 PM PDT 24
Peak memory	146272 kb
Host	smart-efe3f909-505e-467d-bcc0-9799684a776b
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3780881900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3780881900
Directory	/workspace/2.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/3.prim_sync_alert.2643852334
Short name	T37
Test name
Test status
Simulation time	8826488 ps
CPU time	0.39 seconds
Started	May 30 12:23:47 PM PDT 24
Finished	May 30 12:23:48 PM PDT 24
Peak memory	145176 kb
Host	smart-e66ab8b4-7240-4980-a9e1-6f686fe27a1b
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2643852334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2643852334
Directory	/workspace/3.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/4.prim_sync_alert.3472965051
Short name	T61
Test name
Test status
Simulation time	8794239 ps
CPU time	0.49 seconds
Started	May 30 12:24:03 PM PDT 24
Finished	May 30 12:24:05 PM PDT 24
Peak memory	143692 kb
Host	smart-52c4e9bc-8644-4ad6-8555-362a8e682b49
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3472965051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3472965051
Directory	/workspace/4.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/5.prim_sync_alert.1910488813
Short name	T31
Test name
Test status
Simulation time	9022275 ps
CPU time	0.38 seconds
Started	May 30 12:24:24 PM PDT 24
Finished	May 30 12:24:25 PM PDT 24
Peak memory	145212 kb
Host	smart-e9f4fc3f-ede6-4f64-939b-b8554564df22
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1910488813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1910488813
Directory	/workspace/5.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/6.prim_sync_alert.387136718
Short name	T36
Test name
Test status
Simulation time	8474724 ps
CPU time	0.41 seconds
Started	May 30 12:24:04 PM PDT 24
Finished	May 30 12:24:05 PM PDT 24
Peak memory	144976 kb
Host	smart-800fc6a3-4db1-4148-a374-7c7a7e90113b
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=387136718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.387136718
Directory	/workspace/6.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/7.prim_sync_alert.1287540607
Short name	T41
Test name
Test status
Simulation time	8103814 ps
CPU time	0.42 seconds
Started	May 30 12:28:20 PM PDT 24
Finished	May 30 12:28:21 PM PDT 24
Peak memory	143752 kb
Host	smart-ea3a4bdf-cd5f-44f1-9e2e-23736e9a0eb5
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1287540607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1287540607
Directory	/workspace/7.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/8.prim_sync_alert.2900516593
Short name	T30
Test name
Test status
Simulation time	9345178 ps
CPU time	0.4 seconds
Started	May 30 12:24:04 PM PDT 24
Finished	May 30 12:24:05 PM PDT 24
Peak memory	144952 kb
Host	smart-20087ab1-5b1d-4c34-b147-5e1e1e5095c6
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2900516593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2900516593
Directory	/workspace/8.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/9.prim_sync_alert.1842170101
Short name	T29
Test name
Test status
Simulation time	8993593 ps
CPU time	0.45 seconds
Started	May 30 12:24:03 PM PDT 24
Finished	May 30 12:24:05 PM PDT 24
Peak memory	144304 kb
Host	smart-f11bc4a7-b5c7-4829-9efb-ba6a4ca2b276
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1842170101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1842170101
Directory	/workspace/9.prim_sync_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1106661900
Short name	T75
Test name
Test status
Simulation time	28811616 ps
CPU time	0.44 seconds
Started	May 30 12:28:20 PM PDT 24
Finished	May 30 12:28:21 PM PDT 24
Peak memory	144792 kb
Host	smart-1eb30718-a30c-4336-b2c3-f32a902c1a37
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1106661900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1106661900
Directory	/workspace/0.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1988723283
Short name	T77
Test name
Test status
Simulation time	25437485 ps
CPU time	0.47 seconds
Started	May 30 12:23:04 PM PDT 24
Finished	May 30 12:23:06 PM PDT 24
Peak memory	145856 kb
Host	smart-befc2dc0-3d33-45fc-9a10-ba1e9c158329
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1988723283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1988723283
Directory	/workspace/1.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2553604405
Short name	T69
Test name
Test status
Simulation time	26501002 ps
CPU time	0.38 seconds
Started	May 30 12:28:28 PM PDT 24
Finished	May 30 12:28:30 PM PDT 24
Peak memory	145000 kb
Host	smart-29e6dff8-a5b9-4c0e-b9dd-5ab10cdf53e0
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2553604405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2553604405
Directory	/workspace/11.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2708214253
Short name	T76
Test name
Test status
Simulation time	27518040 ps
CPU time	0.43 seconds
Started	May 30 12:28:28 PM PDT 24
Finished	May 30 12:28:29 PM PDT 24
Peak memory	144352 kb
Host	smart-1969b3c0-31b4-4e25-a3b3-e8cc7e06f798
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2708214253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2708214253
Directory	/workspace/12.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3794535933
Short name	T32
Test name
Test status
Simulation time	26438417 ps
CPU time	0.37 seconds
Started	May 30 12:28:52 PM PDT 24
Finished	May 30 12:28:53 PM PDT 24
Peak memory	145212 kb
Host	smart-b3024710-9444-41ff-a7ac-819f0c5822cd
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3794535933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3794535933
Directory	/workspace/13.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3545148861
Short name	T33
Test name
Test status
Simulation time	26278431 ps
CPU time	0.45 seconds
Started	May 30 12:23:56 PM PDT 24
Finished	May 30 12:23:57 PM PDT 24
Peak memory	145204 kb
Host	smart-47947ffa-252b-43ab-bfde-e908181c1326
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3545148861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3545148861
Directory	/workspace/14.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3786921013
Short name	T68
Test name
Test status
Simulation time	29646882 ps
CPU time	0.38 seconds
Started	May 30 12:28:52 PM PDT 24
Finished	May 30 12:28:53 PM PDT 24
Peak memory	145232 kb
Host	smart-ca2e3ca9-2db1-49f2-bf2b-403331333be5
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3786921013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3786921013
Directory	/workspace/15.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3238009201
Short name	T70
Test name
Test status
Simulation time	27574814 ps
CPU time	0.42 seconds
Started	May 30 12:28:37 PM PDT 24
Finished	May 30 12:28:38 PM PDT 24
Peak memory	145852 kb
Host	smart-eba35795-f930-4fdc-8514-5ae5343c0e52
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3238009201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3238009201
Directory	/workspace/16.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1243218838
Short name	T72
Test name
Test status
Simulation time	27064468 ps
CPU time	0.42 seconds
Started	May 30 12:24:31 PM PDT 24
Finished	May 30 12:24:32 PM PDT 24
Peak memory	145240 kb
Host	smart-5d7af1b3-2853-483e-b6d2-9c6ef43b8f76
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1243218838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1243218838
Directory	/workspace/17.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.403800498
Short name	T73
Test name
Test status
Simulation time	28934968 ps
CPU time	0.42 seconds
Started	May 30 12:28:37 PM PDT 24
Finished	May 30 12:28:39 PM PDT 24
Peak memory	143916 kb
Host	smart-e7357dec-6710-49c7-a22c-754e3668e1af
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=403800498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.403800498
Directory	/workspace/18.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.518107311
Short name	T78
Test name
Test status
Simulation time	26844868 ps
CPU time	0.47 seconds
Started	May 30 12:26:01 PM PDT 24
Finished	May 30 12:26:03 PM PDT 24
Peak memory	145516 kb
Host	smart-7e743af2-f159-44fb-9ba1-7cf93097643f
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=518107311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.518107311
Directory	/workspace/19.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1520768290
Short name	T66
Test name
Test status
Simulation time	25867813 ps
CPU time	0.47 seconds
Started	May 30 12:24:03 PM PDT 24
Finished	May 30 12:24:05 PM PDT 24
Peak memory	142836 kb
Host	smart-61fce148-de8d-4a5a-8511-db4d78329214
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1520768290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1520768290
Directory	/workspace/2.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1940858516
Short name	T12
Test name
Test status
Simulation time	27680255 ps
CPU time	0.4 seconds
Started	May 30 12:24:03 PM PDT 24
Finished	May 30 12:24:05 PM PDT 24
Peak memory	143800 kb
Host	smart-85100bcf-3803-4b1e-be2b-c6d90427f862
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1940858516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1940858516
Directory	/workspace/3.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.77238630
Short name	T67
Test name
Test status
Simulation time	29136615 ps
CPU time	0.42 seconds
Started	May 30 12:26:14 PM PDT 24
Finished	May 30 12:26:16 PM PDT 24
Peak memory	145512 kb
Host	smart-0af757e2-22af-41c9-8907-0694c5365494
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=77238630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.77238630
Directory	/workspace/4.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3892345046
Short name	T34
Test name
Test status
Simulation time	26844319 ps
CPU time	0.39 seconds
Started	May 30 12:24:04 PM PDT 24
Finished	May 30 12:24:05 PM PDT 24
Peak memory	144960 kb
Host	smart-d69797af-5504-4c79-8475-347776bcf458
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3892345046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3892345046
Directory	/workspace/5.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1710468923
Short name	T71
Test name
Test status
Simulation time	25843941 ps
CPU time	0.41 seconds
Started	May 30 12:24:37 PM PDT 24
Finished	May 30 12:24:38 PM PDT 24
Peak memory	145532 kb
Host	smart-1d010b4e-c35c-4295-93d6-115530eb73d4
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1710468923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1710468923
Directory	/workspace/6.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1323841546
Short name	T74
Test name
Test status
Simulation time	27260060 ps
CPU time	0.38 seconds
Started	May 30 12:28:21 PM PDT 24
Finished	May 30 12:28:22 PM PDT 24
Peak memory	144984 kb
Host	smart-ac370e86-2946-43dd-92df-48c869c31476
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1323841546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1323841546
Directory	/workspace/7.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.17953783
Short name	T5
Test name
Test status
Simulation time	26944710 ps
CPU time	0.4 seconds
Started	May 30 12:26:56 PM PDT 24
Finished	May 30 12:26:57 PM PDT 24
Peak memory	145232 kb
Host	smart-e21eaaef-bf49-4ea4-b2a8-29b378200d1e
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=17953783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.17953783
Directory	/workspace/8.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2567056997
Short name	T16
Test name
Test status
Simulation time	25999749 ps
CPU time	0.42 seconds
Started	May 30 12:28:21 PM PDT 24
Finished	May 30 12:28:23 PM PDT 24
Peak memory	145848 kb
Host	smart-1d889e85-8a03-4035-ae50-235d9b0cf813
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2567056997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2567056997
Directory	/workspace/9.prim_sync_fatal_alert/latest