| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.88 | 88.88 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/16.prim_async_alert.1283556850 |
| 92.01 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/17.prim_sync_alert.2827801029 |
| 93.90 | 1.90 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 9.30 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.815570011 |
| 94.50 | 0.60 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/10.prim_async_alert.3204166306 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/7.prim_sync_alert.2589809816 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1690831089 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.3976666283 |
| /workspace/coverage/default/1.prim_async_alert.930016353 |
| /workspace/coverage/default/11.prim_async_alert.3085551332 |
| /workspace/coverage/default/12.prim_async_alert.244395931 |
| /workspace/coverage/default/13.prim_async_alert.490180990 |
| /workspace/coverage/default/14.prim_async_alert.2458594158 |
| /workspace/coverage/default/15.prim_async_alert.3525463512 |
| /workspace/coverage/default/17.prim_async_alert.643793882 |
| /workspace/coverage/default/18.prim_async_alert.4285672942 |
| /workspace/coverage/default/19.prim_async_alert.386521907 |
| /workspace/coverage/default/2.prim_async_alert.3667186798 |
| /workspace/coverage/default/3.prim_async_alert.2769805899 |
| /workspace/coverage/default/4.prim_async_alert.1579855383 |
| /workspace/coverage/default/5.prim_async_alert.3716967508 |
| /workspace/coverage/default/6.prim_async_alert.3442655600 |
| /workspace/coverage/default/7.prim_async_alert.2819289226 |
| /workspace/coverage/default/8.prim_async_alert.4197112362 |
| /workspace/coverage/default/9.prim_async_alert.2878059098 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2927823762 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4050528329 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1167695559 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.833298016 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.301392056 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1043620185 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2742432053 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1692859719 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3720219980 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1448032177 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1735591369 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4148936264 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3836741100 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3905144092 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.871140548 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.354768285 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.89950602 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2577628664 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.1617571193 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.2199716265 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.688510003 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.205722449 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.2386126451 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.3123048713 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.4002113703 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.207693540 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.1331269958 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.1137621789 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.3771973421 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.1622263940 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3614666137 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.514680887 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.3038505939 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.2606404998 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.193210768 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.3147106328 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3479091542 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3927544325 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3852075588 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3866902113 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3194107475 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.58206594 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.665627091 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.302282678 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1198205636 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3079846204 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3164268035 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.839074859 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1832543645 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2422562115 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.979914839 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3911315683 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.820506185 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2023712512 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2212757696 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/6.prim_async_alert.3442655600 | Jun 02 02:00:58 PM PDT 24 | Jun 02 02:00:59 PM PDT 24 | 11021326 ps | ||
| T2 | /workspace/coverage/default/4.prim_async_alert.1579855383 | Jun 02 02:01:00 PM PDT 24 | Jun 02 02:01:01 PM PDT 24 | 11530321 ps | ||
| T3 | /workspace/coverage/default/16.prim_async_alert.1283556850 | Jun 02 02:00:59 PM PDT 24 | Jun 02 02:01:00 PM PDT 24 | 11437954 ps | ||
| T7 | /workspace/coverage/default/8.prim_async_alert.4197112362 | Jun 02 02:01:01 PM PDT 24 | Jun 02 02:01:02 PM PDT 24 | 11456744 ps | ||
| T13 | /workspace/coverage/default/12.prim_async_alert.244395931 | Jun 02 02:00:58 PM PDT 24 | Jun 02 02:00:59 PM PDT 24 | 11934737 ps | ||
| T19 | /workspace/coverage/default/9.prim_async_alert.2878059098 | Jun 02 02:00:57 PM PDT 24 | Jun 02 02:00:58 PM PDT 24 | 10584990 ps | ||
| T15 | /workspace/coverage/default/15.prim_async_alert.3525463512 | Jun 02 02:01:00 PM PDT 24 | Jun 02 02:01:01 PM PDT 24 | 11862717 ps | ||
| T20 | /workspace/coverage/default/5.prim_async_alert.3716967508 | Jun 02 02:00:59 PM PDT 24 | Jun 02 02:01:00 PM PDT 24 | 11015880 ps | ||
| T17 | /workspace/coverage/default/13.prim_async_alert.490180990 | Jun 02 02:01:01 PM PDT 24 | Jun 02 02:01:02 PM PDT 24 | 10474419 ps | ||
| T8 | /workspace/coverage/default/3.prim_async_alert.2769805899 | Jun 02 02:00:59 PM PDT 24 | Jun 02 02:01:00 PM PDT 24 | 12218243 ps | ||
| T21 | /workspace/coverage/default/11.prim_async_alert.3085551332 | Jun 02 02:01:00 PM PDT 24 | Jun 02 02:01:01 PM PDT 24 | 12512006 ps | ||
| T22 | /workspace/coverage/default/19.prim_async_alert.386521907 | Jun 02 02:01:03 PM PDT 24 | Jun 02 02:01:04 PM PDT 24 | 10874640 ps | ||
| T9 | /workspace/coverage/default/2.prim_async_alert.3667186798 | Jun 02 02:00:58 PM PDT 24 | Jun 02 02:00:59 PM PDT 24 | 11089884 ps | ||
| T23 | /workspace/coverage/default/18.prim_async_alert.4285672942 | Jun 02 02:00:57 PM PDT 24 | Jun 02 02:00:57 PM PDT 24 | 10962895 ps | ||
| T18 | /workspace/coverage/default/17.prim_async_alert.643793882 | Jun 02 02:01:00 PM PDT 24 | Jun 02 02:01:01 PM PDT 24 | 11382984 ps | ||
| T10 | /workspace/coverage/default/7.prim_async_alert.2819289226 | Jun 02 02:00:59 PM PDT 24 | Jun 02 02:01:00 PM PDT 24 | 11029274 ps | ||
| T24 | /workspace/coverage/default/14.prim_async_alert.2458594158 | Jun 02 02:01:00 PM PDT 24 | Jun 02 02:01:01 PM PDT 24 | 10506261 ps | ||
| T48 | /workspace/coverage/default/0.prim_async_alert.3976666283 | Jun 02 02:00:58 PM PDT 24 | Jun 02 02:00:59 PM PDT 24 | 10985871 ps | ||
| T14 | /workspace/coverage/default/10.prim_async_alert.3204166306 | Jun 02 02:00:59 PM PDT 24 | Jun 02 02:01:00 PM PDT 24 | 12178992 ps | ||
| T16 | /workspace/coverage/default/1.prim_async_alert.930016353 | Jun 02 02:00:58 PM PDT 24 | Jun 02 02:00:59 PM PDT 24 | 11285989 ps | ||
| T40 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1167695559 | Jun 02 02:01:04 PM PDT 24 | Jun 02 02:01:05 PM PDT 24 | 31547739 ps | ||
| T25 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.815570011 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:06 PM PDT 24 | 31943173 ps | ||
| T26 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.301392056 | Jun 02 02:01:04 PM PDT 24 | Jun 02 02:01:05 PM PDT 24 | 28896920 ps | ||
| T41 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4148936264 | Jun 02 02:01:04 PM PDT 24 | Jun 02 02:01:05 PM PDT 24 | 32043965 ps | ||
| T42 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3720219980 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:07 PM PDT 24 | 28609832 ps | ||
| T43 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1692859719 | Jun 02 02:01:07 PM PDT 24 | Jun 02 02:01:07 PM PDT 24 | 30048514 ps | ||
| T44 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2742432053 | Jun 02 02:01:03 PM PDT 24 | Jun 02 02:01:04 PM PDT 24 | 29816010 ps | ||
| T45 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1043620185 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:06 PM PDT 24 | 29999601 ps | ||
| T46 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.871140548 | Jun 02 02:01:07 PM PDT 24 | Jun 02 02:01:08 PM PDT 24 | 32678761 ps | ||
| T47 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.833298016 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:07 PM PDT 24 | 29407041 ps | ||
| T49 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2927823762 | Jun 02 02:01:07 PM PDT 24 | Jun 02 02:01:08 PM PDT 24 | 29684407 ps | ||
| T50 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1448032177 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:06 PM PDT 24 | 30413632 ps | ||
| T51 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3905144092 | Jun 02 02:01:03 PM PDT 24 | Jun 02 02:01:04 PM PDT 24 | 29674720 ps | ||
| T39 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.89950602 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:06 PM PDT 24 | 32282337 ps | ||
| T52 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1735591369 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:06 PM PDT 24 | 28905965 ps | ||
| T53 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4050528329 | Jun 02 02:01:07 PM PDT 24 | Jun 02 02:01:08 PM PDT 24 | 30790121 ps | ||
| T54 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.354768285 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:06 PM PDT 24 | 32792141 ps | ||
| T55 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3836741100 | Jun 02 02:01:06 PM PDT 24 | Jun 02 02:01:07 PM PDT 24 | 28686649 ps | ||
| T56 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2577628664 | Jun 02 02:01:06 PM PDT 24 | Jun 02 02:01:07 PM PDT 24 | 31328923 ps | ||
| T27 | /workspace/coverage/sync_alert/2.prim_sync_alert.1622263940 | Jun 02 02:01:06 PM PDT 24 | Jun 02 02:01:07 PM PDT 24 | 8373185 ps | ||
| T28 | /workspace/coverage/sync_alert/4.prim_sync_alert.514680887 | Jun 02 02:01:04 PM PDT 24 | Jun 02 02:01:05 PM PDT 24 | 9811737 ps | ||
| T29 | /workspace/coverage/sync_alert/17.prim_sync_alert.2827801029 | Jun 02 02:01:10 PM PDT 24 | Jun 02 02:01:10 PM PDT 24 | 9958922 ps | ||
| T30 | /workspace/coverage/sync_alert/0.prim_sync_alert.1617571193 | Jun 02 02:01:07 PM PDT 24 | Jun 02 02:01:07 PM PDT 24 | 9029675 ps | ||
| T31 | /workspace/coverage/sync_alert/9.prim_sync_alert.3147106328 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:06 PM PDT 24 | 8211788 ps | ||
| T32 | /workspace/coverage/sync_alert/19.prim_sync_alert.3771973421 | Jun 02 02:01:12 PM PDT 24 | Jun 02 02:01:13 PM PDT 24 | 9338226 ps | ||
| T37 | /workspace/coverage/sync_alert/1.prim_sync_alert.2199716265 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:07 PM PDT 24 | 9966665 ps | ||
| T33 | /workspace/coverage/sync_alert/3.prim_sync_alert.3614666137 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:06 PM PDT 24 | 9396997 ps | ||
| T38 | /workspace/coverage/sync_alert/12.prim_sync_alert.2386126451 | Jun 02 02:01:13 PM PDT 24 | Jun 02 02:01:13 PM PDT 24 | 8370644 ps | ||
| T34 | /workspace/coverage/sync_alert/5.prim_sync_alert.3038505939 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:06 PM PDT 24 | 10119130 ps | ||
| T57 | /workspace/coverage/sync_alert/10.prim_sync_alert.688510003 | Jun 02 02:01:10 PM PDT 24 | Jun 02 02:01:11 PM PDT 24 | 9542140 ps | ||
| T58 | /workspace/coverage/sync_alert/15.prim_sync_alert.207693540 | Jun 02 02:01:10 PM PDT 24 | Jun 02 02:01:11 PM PDT 24 | 9597625 ps | ||
| T59 | /workspace/coverage/sync_alert/18.prim_sync_alert.1137621789 | Jun 02 02:01:12 PM PDT 24 | Jun 02 02:01:13 PM PDT 24 | 10319409 ps | ||
| T35 | /workspace/coverage/sync_alert/14.prim_sync_alert.4002113703 | Jun 02 02:01:10 PM PDT 24 | Jun 02 02:01:11 PM PDT 24 | 9714917 ps | ||
| T36 | /workspace/coverage/sync_alert/16.prim_sync_alert.1331269958 | Jun 02 02:01:11 PM PDT 24 | Jun 02 02:01:12 PM PDT 24 | 9149147 ps | ||
| T60 | /workspace/coverage/sync_alert/8.prim_sync_alert.193210768 | Jun 02 02:01:04 PM PDT 24 | Jun 02 02:01:05 PM PDT 24 | 8933207 ps | ||
| T61 | /workspace/coverage/sync_alert/6.prim_sync_alert.2606404998 | Jun 02 02:01:05 PM PDT 24 | Jun 02 02:01:06 PM PDT 24 | 9900194 ps | ||
| T62 | /workspace/coverage/sync_alert/11.prim_sync_alert.205722449 | Jun 02 02:01:10 PM PDT 24 | Jun 02 02:01:11 PM PDT 24 | 10371468 ps | ||
| T11 | /workspace/coverage/sync_alert/7.prim_sync_alert.2589809816 | Jun 02 02:01:03 PM PDT 24 | Jun 02 02:01:04 PM PDT 24 | 8232402 ps | ||
| T63 | /workspace/coverage/sync_alert/13.prim_sync_alert.3123048713 | Jun 02 02:01:11 PM PDT 24 | Jun 02 02:01:12 PM PDT 24 | 9650026 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.979914839 | Jun 02 02:01:13 PM PDT 24 | Jun 02 02:01:14 PM PDT 24 | 27760242 ps | ||
| T4 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2422562115 | Jun 02 02:01:12 PM PDT 24 | Jun 02 02:01:13 PM PDT 24 | 26801582 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.665627091 | Jun 02 02:01:10 PM PDT 24 | Jun 02 02:01:11 PM PDT 24 | 28561848 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2212757696 | Jun 02 02:01:13 PM PDT 24 | Jun 02 02:01:14 PM PDT 24 | 27799877 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1690831089 | Jun 02 02:01:11 PM PDT 24 | Jun 02 02:01:12 PM PDT 24 | 27414460 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3911315683 | Jun 02 02:01:12 PM PDT 24 | Jun 02 02:01:13 PM PDT 24 | 28419892 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2023712512 | Jun 02 02:01:10 PM PDT 24 | Jun 02 02:01:11 PM PDT 24 | 27951181 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3194107475 | Jun 02 02:01:13 PM PDT 24 | Jun 02 02:01:14 PM PDT 24 | 26309649 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3927544325 | Jun 02 02:01:10 PM PDT 24 | Jun 02 02:01:11 PM PDT 24 | 26969545 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3164268035 | Jun 02 02:01:12 PM PDT 24 | Jun 02 02:01:13 PM PDT 24 | 28853926 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3079846204 | Jun 02 02:01:12 PM PDT 24 | Jun 02 02:01:13 PM PDT 24 | 30815600 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1832543645 | Jun 02 02:01:12 PM PDT 24 | Jun 02 02:01:13 PM PDT 24 | 28338603 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3866902113 | Jun 02 02:01:13 PM PDT 24 | Jun 02 02:01:14 PM PDT 24 | 28794981 ps | ||
| T12 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.839074859 | Jun 02 02:01:13 PM PDT 24 | Jun 02 02:01:13 PM PDT 24 | 28065012 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.58206594 | Jun 02 02:01:11 PM PDT 24 | Jun 02 02:01:11 PM PDT 24 | 26996707 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3479091542 | Jun 02 02:01:12 PM PDT 24 | Jun 02 02:01:13 PM PDT 24 | 27339412 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1198205636 | Jun 02 02:01:12 PM PDT 24 | Jun 02 02:01:13 PM PDT 24 | 27182683 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.820506185 | Jun 02 02:01:12 PM PDT 24 | Jun 02 02:01:13 PM PDT 24 | 27689359 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3852075588 | Jun 02 02:01:12 PM PDT 24 | Jun 02 02:01:12 PM PDT 24 | 29278437 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.302282678 | Jun 02 02:01:14 PM PDT 24 | Jun 02 02:01:15 PM PDT 24 | 26623466 ps |
| Test location | /workspace/coverage/default/16.prim_async_alert.1283556850 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11437954 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:00:59 PM PDT 24 |
| Finished | Jun 02 02:01:00 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-0668fb41-3ced-4adf-95a3-0e2eec94ebea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283556850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1283556850 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.2827801029 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9958922 ps |
| CPU time | 0.37 seconds |
| Started | Jun 02 02:01:10 PM PDT 24 |
| Finished | Jun 02 02:01:10 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-0272877a-a409-4e02-a18c-e0b716e23596 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2827801029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2827801029 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.815570011 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 31943173 ps |
| CPU time | 0.42 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:06 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-61ed4ab3-bab8-4722-bf45-41e5f9957df4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=815570011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.815570011 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.3204166306 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12178992 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:00:59 PM PDT 24 |
| Finished | Jun 02 02:01:00 PM PDT 24 |
| Peak memory | 145832 kb |
| Host | smart-82e9df8f-912f-4194-8d45-452042998e61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204166306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3204166306 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.2589809816 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8232402 ps |
| CPU time | 0.38 seconds |
| Started | Jun 02 02:01:03 PM PDT 24 |
| Finished | Jun 02 02:01:04 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-11a863b5-c30f-4853-a1bb-7acba1b63214 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2589809816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2589809816 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1690831089 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 27414460 ps |
| CPU time | 0.44 seconds |
| Started | Jun 02 02:01:11 PM PDT 24 |
| Finished | Jun 02 02:01:12 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-1c792d11-0be0-4417-b007-3195385a651e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1690831089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1690831089 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.3976666283 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10985871 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:00:58 PM PDT 24 |
| Finished | Jun 02 02:00:59 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-10e04f67-3cc8-4ac2-93ac-99b71b078656 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976666283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3976666283 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.930016353 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11285989 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:00:58 PM PDT 24 |
| Finished | Jun 02 02:00:59 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-a75438d5-899b-4677-8042-5d36e01626fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930016353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.930016353 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3085551332 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12512006 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:00 PM PDT 24 |
| Finished | Jun 02 02:01:01 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-52dfa40d-463a-480b-a32f-3c351f992b9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085551332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3085551332 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.244395931 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11934737 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:00:58 PM PDT 24 |
| Finished | Jun 02 02:00:59 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-e596090b-232a-4432-a3b4-4cc7bde6c4e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244395931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.244395931 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.490180990 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10474419 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:01 PM PDT 24 |
| Finished | Jun 02 02:01:02 PM PDT 24 |
| Peak memory | 145892 kb |
| Host | smart-92802e66-6bba-4231-83e8-937036d0b234 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490180990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.490180990 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.2458594158 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10506261 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:00 PM PDT 24 |
| Finished | Jun 02 02:01:01 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-9ca39d6c-5482-4a4e-8e3e-f4714aaf8424 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2458594158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2458594158 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3525463512 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11862717 ps |
| CPU time | 0.45 seconds |
| Started | Jun 02 02:01:00 PM PDT 24 |
| Finished | Jun 02 02:01:01 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-69192599-613e-421b-8026-54913e3e5db7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3525463512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3525463512 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.643793882 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11382984 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:00 PM PDT 24 |
| Finished | Jun 02 02:01:01 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-7fd31a4c-7c76-49f1-93be-790a9c58dda6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643793882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.643793882 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.4285672942 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10962895 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:00:57 PM PDT 24 |
| Finished | Jun 02 02:00:57 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-15af0175-f084-414e-9610-cd2d5cce0641 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4285672942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.4285672942 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.386521907 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10874640 ps |
| CPU time | 0.43 seconds |
| Started | Jun 02 02:01:03 PM PDT 24 |
| Finished | Jun 02 02:01:04 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-8c1bd65b-1a4a-4ff2-b869-a7e122402ed0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386521907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.386521907 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3667186798 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11089884 ps |
| CPU time | 0.38 seconds |
| Started | Jun 02 02:00:58 PM PDT 24 |
| Finished | Jun 02 02:00:59 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-451f7a65-9e81-4c35-840e-ff936444ece9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667186798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3667186798 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.2769805899 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12218243 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:00:59 PM PDT 24 |
| Finished | Jun 02 02:01:00 PM PDT 24 |
| Peak memory | 145908 kb |
| Host | smart-bd35feff-a82f-4142-9765-c0c0408f884a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769805899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2769805899 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.1579855383 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11530321 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:00 PM PDT 24 |
| Finished | Jun 02 02:01:01 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-2cf72bdb-f0f6-45c2-9391-3174ed70be6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1579855383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1579855383 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3716967508 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11015880 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:00:59 PM PDT 24 |
| Finished | Jun 02 02:01:00 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-082ee98d-05b0-4c2f-b88c-8d846f6c9a2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3716967508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3716967508 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.3442655600 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11021326 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:00:58 PM PDT 24 |
| Finished | Jun 02 02:00:59 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-1e527b6b-051b-4e5d-9657-1bc1e3ae70e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442655600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3442655600 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.2819289226 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11029274 ps |
| CPU time | 0.38 seconds |
| Started | Jun 02 02:00:59 PM PDT 24 |
| Finished | Jun 02 02:01:00 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-1bf36a94-d210-4ada-8338-29760a9c31a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819289226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2819289226 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.4197112362 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11456744 ps |
| CPU time | 0.43 seconds |
| Started | Jun 02 02:01:01 PM PDT 24 |
| Finished | Jun 02 02:01:02 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-5cc2fedd-01ed-4667-96fd-8e17677e8112 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4197112362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.4197112362 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.2878059098 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10584990 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:00:57 PM PDT 24 |
| Finished | Jun 02 02:00:58 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-180e0548-944b-4288-8cde-c353d7fb847f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878059098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2878059098 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2927823762 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29684407 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:07 PM PDT 24 |
| Finished | Jun 02 02:01:08 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-0323517c-9a9b-4587-9671-9bdf61beec95 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2927823762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2927823762 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.4050528329 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30790121 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:07 PM PDT 24 |
| Finished | Jun 02 02:01:08 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-f1ff19e6-aa7b-4215-8173-8856f2368581 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4050528329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.4050528329 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1167695559 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 31547739 ps |
| CPU time | 0.45 seconds |
| Started | Jun 02 02:01:04 PM PDT 24 |
| Finished | Jun 02 02:01:05 PM PDT 24 |
| Peak memory | 145868 kb |
| Host | smart-50160227-7e71-44f7-9f78-956978c47b05 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1167695559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1167695559 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.833298016 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 29407041 ps |
| CPU time | 0.41 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:07 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-1b5580c6-f15c-4ca3-a3f1-96fcd32d6b8e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=833298016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.833298016 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.301392056 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 28896920 ps |
| CPU time | 0.44 seconds |
| Started | Jun 02 02:01:04 PM PDT 24 |
| Finished | Jun 02 02:01:05 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-00907103-ba16-40bc-959c-bce85734520c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=301392056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.301392056 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1043620185 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29999601 ps |
| CPU time | 0.41 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:06 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-5a868ccc-e73f-4fea-b5bf-6f56097dec1e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1043620185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1043620185 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2742432053 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 29816010 ps |
| CPU time | 0.45 seconds |
| Started | Jun 02 02:01:03 PM PDT 24 |
| Finished | Jun 02 02:01:04 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-8f6df4be-bcde-4c76-84e4-0f41e16e30b1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2742432053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2742432053 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1692859719 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30048514 ps |
| CPU time | 0.38 seconds |
| Started | Jun 02 02:01:07 PM PDT 24 |
| Finished | Jun 02 02:01:07 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-ea2a63b3-e980-41b3-84fa-d160fadda9eb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1692859719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1692859719 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3720219980 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 28609832 ps |
| CPU time | 0.41 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:07 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-1d1ea1f2-bc6e-4321-b198-e10ebed741c5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3720219980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3720219980 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1448032177 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30413632 ps |
| CPU time | 0.41 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:06 PM PDT 24 |
| Peak memory | 145728 kb |
| Host | smart-5baf1ec6-8229-4d8f-8acb-a40b1f983fac |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1448032177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1448032177 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1735591369 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 28905965 ps |
| CPU time | 0.41 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:06 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-acb84b3b-151f-408e-b41f-0e6140a6cde2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1735591369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1735591369 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4148936264 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 32043965 ps |
| CPU time | 0.45 seconds |
| Started | Jun 02 02:01:04 PM PDT 24 |
| Finished | Jun 02 02:01:05 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-bf86f577-dda4-4304-beab-5d1c55a6b840 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4148936264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4148936264 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3836741100 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 28686649 ps |
| CPU time | 0.41 seconds |
| Started | Jun 02 02:01:06 PM PDT 24 |
| Finished | Jun 02 02:01:07 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-2626ae65-93ed-49c1-8fd9-f89cbec60459 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3836741100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3836741100 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3905144092 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29674720 ps |
| CPU time | 0.41 seconds |
| Started | Jun 02 02:01:03 PM PDT 24 |
| Finished | Jun 02 02:01:04 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-78f0d4bf-551f-48e4-b2ee-f4cab4ed63ae |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3905144092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3905144092 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.871140548 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 32678761 ps |
| CPU time | 0.42 seconds |
| Started | Jun 02 02:01:07 PM PDT 24 |
| Finished | Jun 02 02:01:08 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-08351d87-ebb9-4e3c-bea6-56ec0d866bbe |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=871140548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.871140548 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.354768285 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 32792141 ps |
| CPU time | 0.41 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:06 PM PDT 24 |
| Peak memory | 145748 kb |
| Host | smart-797e2043-b564-4db2-a534-fbd2d3190fe9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=354768285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.354768285 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.89950602 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 32282337 ps |
| CPU time | 0.41 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:06 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-7fc028a0-1a32-42fe-a6f1-67c3cf2fa8eb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=89950602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.89950602 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2577628664 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 31328923 ps |
| CPU time | 0.41 seconds |
| Started | Jun 02 02:01:06 PM PDT 24 |
| Finished | Jun 02 02:01:07 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-98bd77d5-a53c-4557-9129-a5a9541e68f1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2577628664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2577628664 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.1617571193 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9029675 ps |
| CPU time | 0.37 seconds |
| Started | Jun 02 02:01:07 PM PDT 24 |
| Finished | Jun 02 02:01:07 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-67224962-73bd-4f08-8f0f-7fd6535ed503 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1617571193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1617571193 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.2199716265 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9966665 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:07 PM PDT 24 |
| Peak memory | 145540 kb |
| Host | smart-2d403f3a-8187-4f34-99be-cf7ca985bec8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2199716265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2199716265 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.688510003 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9542140 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:10 PM PDT 24 |
| Finished | Jun 02 02:01:11 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-cdef8d0d-f8ea-4800-9eb3-92b705ac597d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=688510003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.688510003 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.205722449 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 10371468 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:10 PM PDT 24 |
| Finished | Jun 02 02:01:11 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-25abffac-c1c0-4498-9cbc-9f3d43afa13c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=205722449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.205722449 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.2386126451 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8370644 ps |
| CPU time | 0.37 seconds |
| Started | Jun 02 02:01:13 PM PDT 24 |
| Finished | Jun 02 02:01:13 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-4e8f991b-1677-4dd5-bd32-1f9994c14165 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2386126451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2386126451 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.3123048713 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 9650026 ps |
| CPU time | 0.37 seconds |
| Started | Jun 02 02:01:11 PM PDT 24 |
| Finished | Jun 02 02:01:12 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-c3989ee6-a038-49c7-aa3c-ea2798ff6bd6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3123048713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3123048713 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.4002113703 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9714917 ps |
| CPU time | 0.38 seconds |
| Started | Jun 02 02:01:10 PM PDT 24 |
| Finished | Jun 02 02:01:11 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-cc8f4f87-49e5-4cdc-978d-8d029e9a9127 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4002113703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.4002113703 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.207693540 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9597625 ps |
| CPU time | 0.42 seconds |
| Started | Jun 02 02:01:10 PM PDT 24 |
| Finished | Jun 02 02:01:11 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-401f9269-f56c-4236-b501-0fe8d72e8022 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=207693540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.207693540 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.1331269958 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9149147 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:11 PM PDT 24 |
| Finished | Jun 02 02:01:12 PM PDT 24 |
| Peak memory | 145484 kb |
| Host | smart-f0e4c00d-d589-43cc-9abb-e1fdd3f6b5a6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1331269958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1331269958 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.1137621789 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 10319409 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:12 PM PDT 24 |
| Finished | Jun 02 02:01:13 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-198f6d87-3753-4c4d-be2d-5aac208c2a27 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1137621789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1137621789 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.3771973421 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9338226 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:12 PM PDT 24 |
| Finished | Jun 02 02:01:13 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-562e452a-910d-4ba3-81a0-730d566414b5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3771973421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3771973421 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.1622263940 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8373185 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:06 PM PDT 24 |
| Finished | Jun 02 02:01:07 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-57e66a35-4d63-4996-a77b-6f79a7a42b00 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1622263940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1622263940 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3614666137 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9396997 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:06 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-fdb8cd58-a6a0-4eee-b78a-85f65568c40c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3614666137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3614666137 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.514680887 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9811737 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:04 PM PDT 24 |
| Finished | Jun 02 02:01:05 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-14baf578-0b44-4f24-b0ce-baa8aacf50fe |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=514680887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.514680887 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.3038505939 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10119130 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:06 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-1dd5638d-6d96-4075-ba0f-e9418d5809b5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3038505939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3038505939 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.2606404998 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9900194 ps |
| CPU time | 0.38 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:06 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-fab90058-f867-445e-8c73-b7a5e0d6b535 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2606404998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2606404998 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.193210768 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8933207 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:04 PM PDT 24 |
| Finished | Jun 02 02:01:05 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-4cfd4d98-3527-495b-95b0-b410b572cefd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=193210768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.193210768 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.3147106328 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8211788 ps |
| CPU time | 0.37 seconds |
| Started | Jun 02 02:01:05 PM PDT 24 |
| Finished | Jun 02 02:01:06 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-77a2bdbc-41a0-4b7e-ba10-6edf3da572a2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3147106328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3147106328 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3479091542 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27339412 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:12 PM PDT 24 |
| Finished | Jun 02 02:01:13 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-9a421127-119e-4f8c-9a8f-76f3c9da496d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3479091542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3479091542 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3927544325 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 26969545 ps |
| CPU time | 0.38 seconds |
| Started | Jun 02 02:01:10 PM PDT 24 |
| Finished | Jun 02 02:01:11 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-c5cbcef0-3666-49a5-8490-63203c592a8c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3927544325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3927544325 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3852075588 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 29278437 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:12 PM PDT 24 |
| Finished | Jun 02 02:01:12 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-096afdb5-77d4-425d-96c4-73b8cb4fd769 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3852075588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3852075588 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3866902113 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 28794981 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:13 PM PDT 24 |
| Finished | Jun 02 02:01:14 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-98589125-476c-4035-bfc1-75fe6bdf2ef1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3866902113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3866902113 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3194107475 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 26309649 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:13 PM PDT 24 |
| Finished | Jun 02 02:01:14 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-36d51aaf-ce41-4c1f-9bb8-08ae4244d0c8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3194107475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3194107475 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.58206594 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26996707 ps |
| CPU time | 0.43 seconds |
| Started | Jun 02 02:01:11 PM PDT 24 |
| Finished | Jun 02 02:01:11 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-b230d4c4-a6a4-4dee-97c0-5815564a5d91 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=58206594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.58206594 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.665627091 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28561848 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:10 PM PDT 24 |
| Finished | Jun 02 02:01:11 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-a188e062-bc8d-45ca-be25-345ac711a6b3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=665627091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.665627091 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.302282678 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 26623466 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:14 PM PDT 24 |
| Finished | Jun 02 02:01:15 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-a1b1c657-10c2-4f0f-92c3-bae233744624 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=302282678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.302282678 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1198205636 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27182683 ps |
| CPU time | 0.41 seconds |
| Started | Jun 02 02:01:12 PM PDT 24 |
| Finished | Jun 02 02:01:13 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-8d4f168d-ac88-4edb-b1b9-e92d62973a3d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1198205636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1198205636 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3079846204 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 30815600 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:12 PM PDT 24 |
| Finished | Jun 02 02:01:13 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-7ec62beb-b80d-4e3c-b6c8-8e15844f0e26 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3079846204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3079846204 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3164268035 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 28853926 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:12 PM PDT 24 |
| Finished | Jun 02 02:01:13 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-abddb775-9562-4151-a0f7-641af72ae244 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3164268035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3164268035 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.839074859 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 28065012 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:13 PM PDT 24 |
| Finished | Jun 02 02:01:13 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-70686c4d-9d9f-4b00-b8ac-12da56114e6f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=839074859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.839074859 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1832543645 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28338603 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:12 PM PDT 24 |
| Finished | Jun 02 02:01:13 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-19297267-b87f-40c1-b597-a1edbf23d3a7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1832543645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1832543645 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2422562115 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 26801582 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:12 PM PDT 24 |
| Finished | Jun 02 02:01:13 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-9c8949e1-734e-4e6b-8f14-8e19082101d7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2422562115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2422562115 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.979914839 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27760242 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:13 PM PDT 24 |
| Finished | Jun 02 02:01:14 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-d561b59c-84bf-4545-aa2c-e2f3b31c8f7e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=979914839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.979914839 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3911315683 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28419892 ps |
| CPU time | 0.41 seconds |
| Started | Jun 02 02:01:12 PM PDT 24 |
| Finished | Jun 02 02:01:13 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-3f5ceb6f-325a-441b-8f71-5a3f262400de |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3911315683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3911315683 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.820506185 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27689359 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:12 PM PDT 24 |
| Finished | Jun 02 02:01:13 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-f8677cfb-139a-4d2a-bcfc-5dd7bde913cb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=820506185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.820506185 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2023712512 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27951181 ps |
| CPU time | 0.4 seconds |
| Started | Jun 02 02:01:10 PM PDT 24 |
| Finished | Jun 02 02:01:11 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-0866d72d-8654-4cef-8fd3-d067160e86ab |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2023712512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2023712512 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2212757696 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27799877 ps |
| CPU time | 0.39 seconds |
| Started | Jun 02 02:01:13 PM PDT 24 |
| Finished | Jun 02 02:01:14 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-76ec332e-af32-444e-b940-86d460348e95 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2212757696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2212757696 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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