Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.53 88.53 100.00 100.00 91.67 91.67 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/13.prim_async_alert.2639237719
92.01 3.48 100.00 0.00 93.75 2.08 100.00 0.00 85.71 7.14 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/2.prim_sync_alert.2631227358
94.11 2.11 100.00 0.00 95.83 2.08 100.00 0.00 89.29 3.57 95.83 0.00 83.72 6.98 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4011223729
94.50 0.39 100.00 0.00 95.83 0.00 100.00 0.00 89.29 0.00 95.83 0.00 86.05 2.33 /workspace/coverage/default/10.prim_async_alert.4174659671
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1970925461
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.120516549

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.4261267540
/workspace/coverage/default/1.prim_async_alert.2186496416
/workspace/coverage/default/11.prim_async_alert.1746871868
/workspace/coverage/default/12.prim_async_alert.4267512952
/workspace/coverage/default/14.prim_async_alert.2257375594
/workspace/coverage/default/15.prim_async_alert.2731093322
/workspace/coverage/default/16.prim_async_alert.4071414437
/workspace/coverage/default/17.prim_async_alert.1977197549
/workspace/coverage/default/18.prim_async_alert.3577752677
/workspace/coverage/default/19.prim_async_alert.4041331800
/workspace/coverage/default/2.prim_async_alert.3345736236
/workspace/coverage/default/3.prim_async_alert.2133570992
/workspace/coverage/default/4.prim_async_alert.3152517630
/workspace/coverage/default/5.prim_async_alert.3002987627
/workspace/coverage/default/6.prim_async_alert.211470563
/workspace/coverage/default/7.prim_async_alert.1372187844
/workspace/coverage/default/8.prim_async_alert.3931727858
/workspace/coverage/default/9.prim_async_alert.2994320907
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4226494668
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1237800783
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1506086954
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3509582598
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.512449140
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.262772728
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1496294360
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.538779204
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2298777531
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.165321126
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2301624310
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2646954228
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3870385455
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1401131440
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4240945728
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3759645862
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1643111771
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.78263942
/workspace/coverage/sync_alert/0.prim_sync_alert.3031340536
/workspace/coverage/sync_alert/1.prim_sync_alert.280509582
/workspace/coverage/sync_alert/10.prim_sync_alert.1434847653
/workspace/coverage/sync_alert/11.prim_sync_alert.3637452267
/workspace/coverage/sync_alert/12.prim_sync_alert.1081016181
/workspace/coverage/sync_alert/13.prim_sync_alert.2495126752
/workspace/coverage/sync_alert/14.prim_sync_alert.2943518603
/workspace/coverage/sync_alert/15.prim_sync_alert.3842870860
/workspace/coverage/sync_alert/16.prim_sync_alert.783909323
/workspace/coverage/sync_alert/17.prim_sync_alert.1821622457
/workspace/coverage/sync_alert/18.prim_sync_alert.3863279984
/workspace/coverage/sync_alert/19.prim_sync_alert.1056873126
/workspace/coverage/sync_alert/3.prim_sync_alert.1817960615
/workspace/coverage/sync_alert/4.prim_sync_alert.1824213540
/workspace/coverage/sync_alert/5.prim_sync_alert.3573391003
/workspace/coverage/sync_alert/6.prim_sync_alert.2528775325
/workspace/coverage/sync_alert/7.prim_sync_alert.1774107326
/workspace/coverage/sync_alert/8.prim_sync_alert.1672201843
/workspace/coverage/sync_alert/9.prim_sync_alert.3119517904
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1834542383
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3530824450
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4290942740
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.223533731
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3097015936
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2051642593
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3529169426
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3213976529
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2908686336
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.671261807
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.410549342
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1812065308
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2603281173
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2530189609
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.110533043
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2951446546
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1601043320
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2408575081



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/3.prim_async_alert.2133570992 Jun 04 12:53:21 PM PDT 24 Jun 04 12:53:22 PM PDT 24 10708371 ps
T2 /workspace/coverage/default/10.prim_async_alert.4174659671 Jun 04 12:53:26 PM PDT 24 Jun 04 12:53:27 PM PDT 24 11947557 ps
T3 /workspace/coverage/default/17.prim_async_alert.1977197549 Jun 04 12:53:27 PM PDT 24 Jun 04 12:53:28 PM PDT 24 10921721 ps
T19 /workspace/coverage/default/14.prim_async_alert.2257375594 Jun 04 12:53:21 PM PDT 24 Jun 04 12:53:23 PM PDT 24 11323785 ps
T18 /workspace/coverage/default/1.prim_async_alert.2186496416 Jun 04 12:53:23 PM PDT 24 Jun 04 12:53:24 PM PDT 24 11169442 ps
T12 /workspace/coverage/default/6.prim_async_alert.211470563 Jun 04 12:53:24 PM PDT 24 Jun 04 12:53:25 PM PDT 24 11970643 ps
T7 /workspace/coverage/default/4.prim_async_alert.3152517630 Jun 04 12:53:23 PM PDT 24 Jun 04 12:53:24 PM PDT 24 10985752 ps
T13 /workspace/coverage/default/13.prim_async_alert.2639237719 Jun 04 12:53:24 PM PDT 24 Jun 04 12:53:25 PM PDT 24 11986913 ps
T10 /workspace/coverage/default/7.prim_async_alert.1372187844 Jun 04 12:53:22 PM PDT 24 Jun 04 12:53:23 PM PDT 24 10898426 ps
T20 /workspace/coverage/default/18.prim_async_alert.3577752677 Jun 04 12:53:23 PM PDT 24 Jun 04 12:53:24 PM PDT 24 11956639 ps
T14 /workspace/coverage/default/9.prim_async_alert.2994320907 Jun 04 12:53:27 PM PDT 24 Jun 04 12:53:29 PM PDT 24 11803702 ps
T8 /workspace/coverage/default/11.prim_async_alert.1746871868 Jun 04 12:53:25 PM PDT 24 Jun 04 12:53:26 PM PDT 24 10723232 ps
T9 /workspace/coverage/default/5.prim_async_alert.3002987627 Jun 04 12:53:26 PM PDT 24 Jun 04 12:53:27 PM PDT 24 12547107 ps
T21 /workspace/coverage/default/15.prim_async_alert.2731093322 Jun 04 12:53:26 PM PDT 24 Jun 04 12:53:27 PM PDT 24 11263591 ps
T22 /workspace/coverage/default/16.prim_async_alert.4071414437 Jun 04 12:53:26 PM PDT 24 Jun 04 12:53:27 PM PDT 24 11482915 ps
T49 /workspace/coverage/default/2.prim_async_alert.3345736236 Jun 04 12:53:23 PM PDT 24 Jun 04 12:53:24 PM PDT 24 11086331 ps
T17 /workspace/coverage/default/8.prim_async_alert.3931727858 Jun 04 12:53:29 PM PDT 24 Jun 04 12:53:30 PM PDT 24 10464368 ps
T23 /workspace/coverage/default/12.prim_async_alert.4267512952 Jun 04 12:53:23 PM PDT 24 Jun 04 12:53:25 PM PDT 24 10983094 ps
T50 /workspace/coverage/default/0.prim_async_alert.4261267540 Jun 04 12:53:22 PM PDT 24 Jun 04 12:53:24 PM PDT 24 10803144 ps
T51 /workspace/coverage/default/19.prim_async_alert.4041331800 Jun 04 12:53:31 PM PDT 24 Jun 04 12:53:32 PM PDT 24 11146777 ps
T45 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.538779204 Jun 04 12:53:36 PM PDT 24 Jun 04 12:53:37 PM PDT 24 31040844 ps
T46 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.262772728 Jun 04 12:53:33 PM PDT 24 Jun 04 12:53:35 PM PDT 24 31181859 ps
T24 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1496294360 Jun 04 12:53:31 PM PDT 24 Jun 04 12:53:33 PM PDT 24 28500146 ps
T47 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2298777531 Jun 04 12:53:33 PM PDT 24 Jun 04 12:53:35 PM PDT 24 31284870 ps
T25 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4226494668 Jun 04 12:53:29 PM PDT 24 Jun 04 12:53:30 PM PDT 24 30167098 ps
T26 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1237800783 Jun 04 12:53:35 PM PDT 24 Jun 04 12:53:37 PM PDT 24 28583232 ps
T48 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.165321126 Jun 04 12:53:39 PM PDT 24 Jun 04 12:53:40 PM PDT 24 28103736 ps
T27 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4240945728 Jun 04 12:53:33 PM PDT 24 Jun 04 12:53:35 PM PDT 24 30522143 ps
T15 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4011223729 Jun 04 12:53:33 PM PDT 24 Jun 04 12:53:35 PM PDT 24 31589871 ps
T16 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2646954228 Jun 04 12:53:31 PM PDT 24 Jun 04 12:53:32 PM PDT 24 30674159 ps
T52 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3509582598 Jun 04 12:53:33 PM PDT 24 Jun 04 12:53:35 PM PDT 24 32333373 ps
T53 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3870385455 Jun 04 12:53:33 PM PDT 24 Jun 04 12:53:35 PM PDT 24 31367838 ps
T54 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2301624310 Jun 04 12:53:33 PM PDT 24 Jun 04 12:53:34 PM PDT 24 29195021 ps
T55 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1401131440 Jun 04 12:53:37 PM PDT 24 Jun 04 12:53:38 PM PDT 24 29186333 ps
T56 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1506086954 Jun 04 12:53:34 PM PDT 24 Jun 04 12:53:35 PM PDT 24 31020276 ps
T43 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.512449140 Jun 04 12:53:34 PM PDT 24 Jun 04 12:53:36 PM PDT 24 30621273 ps
T57 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.78263942 Jun 04 12:53:31 PM PDT 24 Jun 04 12:53:33 PM PDT 24 31070545 ps
T58 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1643111771 Jun 04 12:53:33 PM PDT 24 Jun 04 12:53:35 PM PDT 24 31413470 ps
T44 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3759645862 Jun 04 12:53:36 PM PDT 24 Jun 04 12:53:37 PM PDT 24 28783280 ps
T37 /workspace/coverage/sync_alert/10.prim_sync_alert.1434847653 Jun 04 12:53:31 PM PDT 24 Jun 04 12:53:33 PM PDT 24 9208337 ps
T38 /workspace/coverage/sync_alert/6.prim_sync_alert.2528775325 Jun 04 12:53:34 PM PDT 24 Jun 04 12:53:36 PM PDT 24 8822373 ps
T39 /workspace/coverage/sync_alert/2.prim_sync_alert.2631227358 Jun 04 12:53:35 PM PDT 24 Jun 04 12:53:37 PM PDT 24 8376362 ps
T28 /workspace/coverage/sync_alert/1.prim_sync_alert.280509582 Jun 04 12:53:37 PM PDT 24 Jun 04 12:53:38 PM PDT 24 9460005 ps
T40 /workspace/coverage/sync_alert/5.prim_sync_alert.3573391003 Jun 04 12:53:35 PM PDT 24 Jun 04 12:53:37 PM PDT 24 10808618 ps
T29 /workspace/coverage/sync_alert/13.prim_sync_alert.2495126752 Jun 04 12:53:35 PM PDT 24 Jun 04 12:53:37 PM PDT 24 8911364 ps
T41 /workspace/coverage/sync_alert/7.prim_sync_alert.1774107326 Jun 04 12:53:32 PM PDT 24 Jun 04 12:53:33 PM PDT 24 9810048 ps
T30 /workspace/coverage/sync_alert/17.prim_sync_alert.1821622457 Jun 04 12:53:34 PM PDT 24 Jun 04 12:53:35 PM PDT 24 8431645 ps
T31 /workspace/coverage/sync_alert/9.prim_sync_alert.3119517904 Jun 04 12:53:36 PM PDT 24 Jun 04 12:53:38 PM PDT 24 9603202 ps
T42 /workspace/coverage/sync_alert/19.prim_sync_alert.1056873126 Jun 04 12:53:33 PM PDT 24 Jun 04 12:53:34 PM PDT 24 8997994 ps
T32 /workspace/coverage/sync_alert/4.prim_sync_alert.1824213540 Jun 04 12:53:35 PM PDT 24 Jun 04 12:53:37 PM PDT 24 8648532 ps
T59 /workspace/coverage/sync_alert/18.prim_sync_alert.3863279984 Jun 04 12:53:33 PM PDT 24 Jun 04 12:53:35 PM PDT 24 9124883 ps
T33 /workspace/coverage/sync_alert/3.prim_sync_alert.1817960615 Jun 04 12:53:36 PM PDT 24 Jun 04 12:53:37 PM PDT 24 9430813 ps
T60 /workspace/coverage/sync_alert/8.prim_sync_alert.1672201843 Jun 04 12:53:33 PM PDT 24 Jun 04 12:53:34 PM PDT 24 9400285 ps
T34 /workspace/coverage/sync_alert/0.prim_sync_alert.3031340536 Jun 04 12:53:34 PM PDT 24 Jun 04 12:53:36 PM PDT 24 10097730 ps
T61 /workspace/coverage/sync_alert/14.prim_sync_alert.2943518603 Jun 04 12:53:33 PM PDT 24 Jun 04 12:53:35 PM PDT 24 10178071 ps
T35 /workspace/coverage/sync_alert/12.prim_sync_alert.1081016181 Jun 04 12:53:37 PM PDT 24 Jun 04 12:53:38 PM PDT 24 9425339 ps
T36 /workspace/coverage/sync_alert/15.prim_sync_alert.3842870860 Jun 04 12:53:41 PM PDT 24 Jun 04 12:53:41 PM PDT 24 8174218 ps
T62 /workspace/coverage/sync_alert/16.prim_sync_alert.783909323 Jun 04 12:53:34 PM PDT 24 Jun 04 12:53:36 PM PDT 24 8609480 ps
T63 /workspace/coverage/sync_alert/11.prim_sync_alert.3637452267 Jun 04 12:53:34 PM PDT 24 Jun 04 12:53:36 PM PDT 24 9640613 ps
T4 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.410549342 Jun 04 12:55:13 PM PDT 24 Jun 04 12:55:15 PM PDT 24 27448492 ps
T64 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.110533043 Jun 04 12:55:14 PM PDT 24 Jun 04 12:55:16 PM PDT 24 28623467 ps
T11 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.120516549 Jun 04 12:55:11 PM PDT 24 Jun 04 12:55:13 PM PDT 24 26804710 ps
T65 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3097015936 Jun 04 12:55:10 PM PDT 24 Jun 04 12:55:12 PM PDT 24 29925827 ps
T66 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2408575081 Jun 04 12:55:13 PM PDT 24 Jun 04 12:55:16 PM PDT 24 26594404 ps
T67 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1601043320 Jun 04 12:55:12 PM PDT 24 Jun 04 12:55:15 PM PDT 24 27658600 ps
T68 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3530824450 Jun 04 12:55:13 PM PDT 24 Jun 04 12:55:29 PM PDT 24 25591379 ps
T69 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4290942740 Jun 04 12:55:17 PM PDT 24 Jun 04 12:55:18 PM PDT 24 26107136 ps
T5 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1970925461 Jun 04 12:55:23 PM PDT 24 Jun 04 12:55:24 PM PDT 24 27193987 ps
T70 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.223533731 Jun 04 12:55:16 PM PDT 24 Jun 04 12:55:17 PM PDT 24 26835589 ps
T71 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2908686336 Jun 04 12:55:12 PM PDT 24 Jun 04 12:55:14 PM PDT 24 26739693 ps
T6 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2530189609 Jun 04 12:55:17 PM PDT 24 Jun 04 12:55:18 PM PDT 24 28256566 ps
T72 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.671261807 Jun 04 12:55:10 PM PDT 24 Jun 04 12:55:12 PM PDT 24 27810440 ps
T73 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2951446546 Jun 04 12:55:10 PM PDT 24 Jun 04 12:55:12 PM PDT 24 27462801 ps
T74 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1812065308 Jun 04 12:55:28 PM PDT 24 Jun 04 12:55:29 PM PDT 24 25514310 ps
T75 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1834542383 Jun 04 12:55:14 PM PDT 24 Jun 04 12:55:16 PM PDT 24 28204112 ps
T76 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3529169426 Jun 04 12:55:12 PM PDT 24 Jun 04 12:55:15 PM PDT 24 27615463 ps
T77 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3213976529 Jun 04 12:55:46 PM PDT 24 Jun 04 12:55:46 PM PDT 24 28791891 ps
T78 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2603281173 Jun 04 12:55:12 PM PDT 24 Jun 04 12:55:14 PM PDT 24 27011921 ps
T79 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2051642593 Jun 04 12:55:13 PM PDT 24 Jun 04 12:55:15 PM PDT 24 27530932 ps

Test location /workspace/coverage/default/13.prim_async_alert.2639237719
Short name T13
Test name
Test status
Simulation time 11986913 ps
CPU time 0.38 seconds
Started Jun 04 12:53:24 PM PDT 24
Finished Jun 04 12:53:25 PM PDT 24
Peak memory 145816 kb
Host smart-4acd091e-3774-4fa9-b0c7-18c9909c28d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639237719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2639237719
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2631227358
Short name T39
Test name
Test status
Simulation time 8376362 ps
CPU time 0.38 seconds
Started Jun 04 12:53:35 PM PDT 24
Finished Jun 04 12:53:37 PM PDT 24
Peak memory 145580 kb
Host smart-64fb45a9-56b0-45cb-bb48-81f8cbbdbf81
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2631227358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2631227358
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4011223729
Short name T15
Test name
Test status
Simulation time 31589871 ps
CPU time 0.4 seconds
Started Jun 04 12:53:33 PM PDT 24
Finished Jun 04 12:53:35 PM PDT 24
Peak memory 145788 kb
Host smart-39638c6b-9216-4d0c-b99c-6ff7a06cfdbe
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4011223729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.4011223729
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.4174659671
Short name T2
Test name
Test status
Simulation time 11947557 ps
CPU time 0.4 seconds
Started Jun 04 12:53:26 PM PDT 24
Finished Jun 04 12:53:27 PM PDT 24
Peak memory 145716 kb
Host smart-4f719a45-227f-4a4d-b096-4cd58515b61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174659671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.4174659671
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1970925461
Short name T5
Test name
Test status
Simulation time 27193987 ps
CPU time 0.4 seconds
Started Jun 04 12:55:23 PM PDT 24
Finished Jun 04 12:55:24 PM PDT 24
Peak memory 145584 kb
Host smart-21fb4ad5-27e6-4488-ae40-0663b1686317
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1970925461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1970925461
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.120516549
Short name T11
Test name
Test status
Simulation time 26804710 ps
CPU time 0.39 seconds
Started Jun 04 12:55:11 PM PDT 24
Finished Jun 04 12:55:13 PM PDT 24
Peak memory 145596 kb
Host smart-796ebb65-179a-4f31-9134-f69fe859a2e3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=120516549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.120516549
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.4261267540
Short name T50
Test name
Test status
Simulation time 10803144 ps
CPU time 0.37 seconds
Started Jun 04 12:53:22 PM PDT 24
Finished Jun 04 12:53:24 PM PDT 24
Peak memory 145820 kb
Host smart-4a9fc1de-cef3-4b2a-a60b-83656484ea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261267540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.4261267540
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2186496416
Short name T18
Test name
Test status
Simulation time 11169442 ps
CPU time 0.37 seconds
Started Jun 04 12:53:23 PM PDT 24
Finished Jun 04 12:53:24 PM PDT 24
Peak memory 145676 kb
Host smart-ec9b5ff8-23c5-4b3d-8045-4139c8277b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186496416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2186496416
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1746871868
Short name T8
Test name
Test status
Simulation time 10723232 ps
CPU time 0.38 seconds
Started Jun 04 12:53:25 PM PDT 24
Finished Jun 04 12:53:26 PM PDT 24
Peak memory 145752 kb
Host smart-f146b28d-af3d-43ed-9c22-d19322ebd91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746871868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1746871868
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.4267512952
Short name T23
Test name
Test status
Simulation time 10983094 ps
CPU time 0.39 seconds
Started Jun 04 12:53:23 PM PDT 24
Finished Jun 04 12:53:25 PM PDT 24
Peak memory 145720 kb
Host smart-26753ec9-1943-4aa2-9a41-d19c3cf3642c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267512952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.4267512952
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2257375594
Short name T19
Test name
Test status
Simulation time 11323785 ps
CPU time 0.4 seconds
Started Jun 04 12:53:21 PM PDT 24
Finished Jun 04 12:53:23 PM PDT 24
Peak memory 145820 kb
Host smart-1d914a21-6b10-4e7f-963f-0660a12dbfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257375594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2257375594
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.2731093322
Short name T21
Test name
Test status
Simulation time 11263591 ps
CPU time 0.41 seconds
Started Jun 04 12:53:26 PM PDT 24
Finished Jun 04 12:53:27 PM PDT 24
Peak memory 145780 kb
Host smart-056a0a3e-3c9b-4a02-a526-680c3661cff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731093322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2731093322
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.4071414437
Short name T22
Test name
Test status
Simulation time 11482915 ps
CPU time 0.37 seconds
Started Jun 04 12:53:26 PM PDT 24
Finished Jun 04 12:53:27 PM PDT 24
Peak memory 145824 kb
Host smart-7d1187cc-b4eb-4e55-8c3a-838683a389f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071414437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.4071414437
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1977197549
Short name T3
Test name
Test status
Simulation time 10921721 ps
CPU time 0.4 seconds
Started Jun 04 12:53:27 PM PDT 24
Finished Jun 04 12:53:28 PM PDT 24
Peak memory 145664 kb
Host smart-db371bf1-e97b-4801-adab-27fe0c5573f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977197549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1977197549
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3577752677
Short name T20
Test name
Test status
Simulation time 11956639 ps
CPU time 0.43 seconds
Started Jun 04 12:53:23 PM PDT 24
Finished Jun 04 12:53:24 PM PDT 24
Peak memory 145752 kb
Host smart-e321f806-ec35-4779-9ebb-f94252400076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577752677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3577752677
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.4041331800
Short name T51
Test name
Test status
Simulation time 11146777 ps
CPU time 0.39 seconds
Started Jun 04 12:53:31 PM PDT 24
Finished Jun 04 12:53:32 PM PDT 24
Peak memory 145720 kb
Host smart-7740a4c7-a8c3-46fd-8ea4-857a0c8bf054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041331800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.4041331800
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3345736236
Short name T49
Test name
Test status
Simulation time 11086331 ps
CPU time 0.37 seconds
Started Jun 04 12:53:23 PM PDT 24
Finished Jun 04 12:53:24 PM PDT 24
Peak memory 145712 kb
Host smart-c060f372-3d30-4a8d-9d2f-879d72e2781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345736236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3345736236
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2133570992
Short name T1
Test name
Test status
Simulation time 10708371 ps
CPU time 0.39 seconds
Started Jun 04 12:53:21 PM PDT 24
Finished Jun 04 12:53:22 PM PDT 24
Peak memory 145804 kb
Host smart-6c336ca7-b730-416f-a3bc-55eb8d75751a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133570992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2133570992
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3152517630
Short name T7
Test name
Test status
Simulation time 10985752 ps
CPU time 0.38 seconds
Started Jun 04 12:53:23 PM PDT 24
Finished Jun 04 12:53:24 PM PDT 24
Peak memory 145800 kb
Host smart-6f908830-77dd-4605-aeca-b1e6f79996d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152517630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3152517630
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3002987627
Short name T9
Test name
Test status
Simulation time 12547107 ps
CPU time 0.38 seconds
Started Jun 04 12:53:26 PM PDT 24
Finished Jun 04 12:53:27 PM PDT 24
Peak memory 145816 kb
Host smart-c53c434b-5d94-46ec-acf2-420276b889d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002987627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3002987627
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.211470563
Short name T12
Test name
Test status
Simulation time 11970643 ps
CPU time 0.4 seconds
Started Jun 04 12:53:24 PM PDT 24
Finished Jun 04 12:53:25 PM PDT 24
Peak memory 145792 kb
Host smart-22173b35-5b36-43c7-84ab-72b2708d608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211470563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.211470563
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1372187844
Short name T10
Test name
Test status
Simulation time 10898426 ps
CPU time 0.38 seconds
Started Jun 04 12:53:22 PM PDT 24
Finished Jun 04 12:53:23 PM PDT 24
Peak memory 145828 kb
Host smart-24e05878-5797-4312-b691-a7c067dc23a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372187844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1372187844
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3931727858
Short name T17
Test name
Test status
Simulation time 10464368 ps
CPU time 0.4 seconds
Started Jun 04 12:53:29 PM PDT 24
Finished Jun 04 12:53:30 PM PDT 24
Peak memory 145816 kb
Host smart-1e720697-9f50-4079-8d1e-55cec025996b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931727858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3931727858
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2994320907
Short name T14
Test name
Test status
Simulation time 11803702 ps
CPU time 0.38 seconds
Started Jun 04 12:53:27 PM PDT 24
Finished Jun 04 12:53:29 PM PDT 24
Peak memory 145804 kb
Host smart-b3e09127-87fd-49e2-9c0e-92f32d215560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994320907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2994320907
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4226494668
Short name T25
Test name
Test status
Simulation time 30167098 ps
CPU time 0.4 seconds
Started Jun 04 12:53:29 PM PDT 24
Finished Jun 04 12:53:30 PM PDT 24
Peak memory 145812 kb
Host smart-a830f676-5cbe-4fa3-b1ae-bdd7dd721e15
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4226494668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4226494668
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1237800783
Short name T26
Test name
Test status
Simulation time 28583232 ps
CPU time 0.41 seconds
Started Jun 04 12:53:35 PM PDT 24
Finished Jun 04 12:53:37 PM PDT 24
Peak memory 145752 kb
Host smart-310819d2-4d95-47d1-921b-4b5845c05fdf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1237800783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1237800783
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1506086954
Short name T56
Test name
Test status
Simulation time 31020276 ps
CPU time 0.4 seconds
Started Jun 04 12:53:34 PM PDT 24
Finished Jun 04 12:53:35 PM PDT 24
Peak memory 145676 kb
Host smart-c5acb17d-0391-465a-8c32-f7cdcc6cd1ac
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1506086954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1506086954
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3509582598
Short name T52
Test name
Test status
Simulation time 32333373 ps
CPU time 0.4 seconds
Started Jun 04 12:53:33 PM PDT 24
Finished Jun 04 12:53:35 PM PDT 24
Peak memory 145788 kb
Host smart-6a5c8c6e-6941-42cd-a921-e4a9a53c29bd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3509582598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3509582598
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.512449140
Short name T43
Test name
Test status
Simulation time 30621273 ps
CPU time 0.4 seconds
Started Jun 04 12:53:34 PM PDT 24
Finished Jun 04 12:53:36 PM PDT 24
Peak memory 145792 kb
Host smart-82741cda-8fd7-4e60-8d3f-3ee2ad8987f9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=512449140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.512449140
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.262772728
Short name T46
Test name
Test status
Simulation time 31181859 ps
CPU time 0.44 seconds
Started Jun 04 12:53:33 PM PDT 24
Finished Jun 04 12:53:35 PM PDT 24
Peak memory 145680 kb
Host smart-ffafc706-ecde-4d8a-afb9-cc0b836b8a76
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=262772728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.262772728
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1496294360
Short name T24
Test name
Test status
Simulation time 28500146 ps
CPU time 0.46 seconds
Started Jun 04 12:53:31 PM PDT 24
Finished Jun 04 12:53:33 PM PDT 24
Peak memory 145688 kb
Host smart-f75dfdb0-6b21-423b-b388-6e51f1072e3d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1496294360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1496294360
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.538779204
Short name T45
Test name
Test status
Simulation time 31040844 ps
CPU time 0.41 seconds
Started Jun 04 12:53:36 PM PDT 24
Finished Jun 04 12:53:37 PM PDT 24
Peak memory 145724 kb
Host smart-f03b9e2f-a828-4222-b420-bd00601b4d81
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=538779204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.538779204
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2298777531
Short name T47
Test name
Test status
Simulation time 31284870 ps
CPU time 0.4 seconds
Started Jun 04 12:53:33 PM PDT 24
Finished Jun 04 12:53:35 PM PDT 24
Peak memory 145760 kb
Host smart-3e875531-9b0f-40d9-bb8c-23c57040086c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2298777531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2298777531
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.165321126
Short name T48
Test name
Test status
Simulation time 28103736 ps
CPU time 0.4 seconds
Started Jun 04 12:53:39 PM PDT 24
Finished Jun 04 12:53:40 PM PDT 24
Peak memory 145800 kb
Host smart-48a73494-1680-4f3c-8f3b-07e0938747c4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=165321126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.165321126
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2301624310
Short name T54
Test name
Test status
Simulation time 29195021 ps
CPU time 0.42 seconds
Started Jun 04 12:53:33 PM PDT 24
Finished Jun 04 12:53:34 PM PDT 24
Peak memory 145640 kb
Host smart-a8ccd255-6294-4d65-9a69-49bf5b7eedc0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2301624310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2301624310
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2646954228
Short name T16
Test name
Test status
Simulation time 30674159 ps
CPU time 0.39 seconds
Started Jun 04 12:53:31 PM PDT 24
Finished Jun 04 12:53:32 PM PDT 24
Peak memory 145812 kb
Host smart-3efc793c-a141-4540-abef-cbd4438a3e35
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2646954228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2646954228
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3870385455
Short name T53
Test name
Test status
Simulation time 31367838 ps
CPU time 0.43 seconds
Started Jun 04 12:53:33 PM PDT 24
Finished Jun 04 12:53:35 PM PDT 24
Peak memory 145756 kb
Host smart-40913165-a80c-4ec4-9304-e14b199242c9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3870385455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3870385455
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1401131440
Short name T55
Test name
Test status
Simulation time 29186333 ps
CPU time 0.4 seconds
Started Jun 04 12:53:37 PM PDT 24
Finished Jun 04 12:53:38 PM PDT 24
Peak memory 145756 kb
Host smart-3ea4882c-2547-4ee4-bc3b-05d22c946d3d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1401131440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1401131440
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.4240945728
Short name T27
Test name
Test status
Simulation time 30522143 ps
CPU time 0.42 seconds
Started Jun 04 12:53:33 PM PDT 24
Finished Jun 04 12:53:35 PM PDT 24
Peak memory 145700 kb
Host smart-e6878813-6f7c-4230-a6d1-996d8213e69d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4240945728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.4240945728
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3759645862
Short name T44
Test name
Test status
Simulation time 28783280 ps
CPU time 0.45 seconds
Started Jun 04 12:53:36 PM PDT 24
Finished Jun 04 12:53:37 PM PDT 24
Peak memory 145776 kb
Host smart-ac42f2f6-2c9b-469f-9e71-311f3e26589f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3759645862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3759645862
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1643111771
Short name T58
Test name
Test status
Simulation time 31413470 ps
CPU time 0.4 seconds
Started Jun 04 12:53:33 PM PDT 24
Finished Jun 04 12:53:35 PM PDT 24
Peak memory 145688 kb
Host smart-1638b42f-73ee-4a1a-94c4-56f2d7efe73d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1643111771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1643111771
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.78263942
Short name T57
Test name
Test status
Simulation time 31070545 ps
CPU time 0.41 seconds
Started Jun 04 12:53:31 PM PDT 24
Finished Jun 04 12:53:33 PM PDT 24
Peak memory 145676 kb
Host smart-d4a75114-fb16-4486-877c-80b3059d8f30
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=78263942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.78263942
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3031340536
Short name T34
Test name
Test status
Simulation time 10097730 ps
CPU time 0.38 seconds
Started Jun 04 12:53:34 PM PDT 24
Finished Jun 04 12:53:36 PM PDT 24
Peak memory 145560 kb
Host smart-fc61c31d-c4fb-41c7-b966-bf8408e3672f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3031340536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3031340536
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.280509582
Short name T28
Test name
Test status
Simulation time 9460005 ps
CPU time 0.42 seconds
Started Jun 04 12:53:37 PM PDT 24
Finished Jun 04 12:53:38 PM PDT 24
Peak memory 145568 kb
Host smart-6494769f-fd16-429c-9f27-32d52002a572
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=280509582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.280509582
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1434847653
Short name T37
Test name
Test status
Simulation time 9208337 ps
CPU time 0.38 seconds
Started Jun 04 12:53:31 PM PDT 24
Finished Jun 04 12:53:33 PM PDT 24
Peak memory 145544 kb
Host smart-47822d14-d2ab-40d8-9f69-67a53ca358e6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1434847653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1434847653
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3637452267
Short name T63
Test name
Test status
Simulation time 9640613 ps
CPU time 0.4 seconds
Started Jun 04 12:53:34 PM PDT 24
Finished Jun 04 12:53:36 PM PDT 24
Peak memory 145556 kb
Host smart-2b02d739-7051-4b5f-a112-0e7c625abbf6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3637452267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3637452267
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1081016181
Short name T35
Test name
Test status
Simulation time 9425339 ps
CPU time 0.38 seconds
Started Jun 04 12:53:37 PM PDT 24
Finished Jun 04 12:53:38 PM PDT 24
Peak memory 145552 kb
Host smart-21e8ecaa-f928-41aa-a6c3-ad810527a6e9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1081016181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1081016181
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2495126752
Short name T29
Test name
Test status
Simulation time 8911364 ps
CPU time 0.39 seconds
Started Jun 04 12:53:35 PM PDT 24
Finished Jun 04 12:53:37 PM PDT 24
Peak memory 145560 kb
Host smart-05786738-2fa8-407b-bc86-dda4156821d9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2495126752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2495126752
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2943518603
Short name T61
Test name
Test status
Simulation time 10178071 ps
CPU time 0.39 seconds
Started Jun 04 12:53:33 PM PDT 24
Finished Jun 04 12:53:35 PM PDT 24
Peak memory 145564 kb
Host smart-c88d3329-db9d-4edd-bb47-ab8c46570c05
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2943518603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2943518603
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3842870860
Short name T36
Test name
Test status
Simulation time 8174218 ps
CPU time 0.39 seconds
Started Jun 04 12:53:41 PM PDT 24
Finished Jun 04 12:53:41 PM PDT 24
Peak memory 145468 kb
Host smart-3cad8065-8d8c-42da-ade3-bc8ae20b195f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3842870860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3842870860
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.783909323
Short name T62
Test name
Test status
Simulation time 8609480 ps
CPU time 0.38 seconds
Started Jun 04 12:53:34 PM PDT 24
Finished Jun 04 12:53:36 PM PDT 24
Peak memory 145484 kb
Host smart-c21cb155-e6dc-4bdc-9bcc-f212a7c557d8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=783909323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.783909323
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1821622457
Short name T30
Test name
Test status
Simulation time 8431645 ps
CPU time 0.38 seconds
Started Jun 04 12:53:34 PM PDT 24
Finished Jun 04 12:53:35 PM PDT 24
Peak memory 145576 kb
Host smart-7de5f4cc-68bf-4a23-ba7e-89bd6b18249f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1821622457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1821622457
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3863279984
Short name T59
Test name
Test status
Simulation time 9124883 ps
CPU time 0.4 seconds
Started Jun 04 12:53:33 PM PDT 24
Finished Jun 04 12:53:35 PM PDT 24
Peak memory 145540 kb
Host smart-8ddb3309-430a-4992-bb2f-5e05f5882149
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3863279984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3863279984
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1056873126
Short name T42
Test name
Test status
Simulation time 8997994 ps
CPU time 0.38 seconds
Started Jun 04 12:53:33 PM PDT 24
Finished Jun 04 12:53:34 PM PDT 24
Peak memory 145564 kb
Host smart-f30b45af-7956-4d9b-bb89-30c37624a29c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1056873126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1056873126
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1817960615
Short name T33
Test name
Test status
Simulation time 9430813 ps
CPU time 0.42 seconds
Started Jun 04 12:53:36 PM PDT 24
Finished Jun 04 12:53:37 PM PDT 24
Peak memory 145556 kb
Host smart-2ffabc40-e4a8-496c-92c6-72d0c247b581
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1817960615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1817960615
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1824213540
Short name T32
Test name
Test status
Simulation time 8648532 ps
CPU time 0.4 seconds
Started Jun 04 12:53:35 PM PDT 24
Finished Jun 04 12:53:37 PM PDT 24
Peak memory 145564 kb
Host smart-9fe98a67-3c79-46b8-ba72-46d88fa05474
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1824213540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1824213540
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3573391003
Short name T40
Test name
Test status
Simulation time 10808618 ps
CPU time 0.43 seconds
Started Jun 04 12:53:35 PM PDT 24
Finished Jun 04 12:53:37 PM PDT 24
Peak memory 145484 kb
Host smart-899c184d-28ba-4c6a-8b33-f5f3bc0a387d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3573391003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3573391003
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2528775325
Short name T38
Test name
Test status
Simulation time 8822373 ps
CPU time 0.37 seconds
Started Jun 04 12:53:34 PM PDT 24
Finished Jun 04 12:53:36 PM PDT 24
Peak memory 145572 kb
Host smart-d816f4d6-31fb-42bb-948b-9e08d17ff7de
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2528775325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2528775325
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1774107326
Short name T41
Test name
Test status
Simulation time 9810048 ps
CPU time 0.39 seconds
Started Jun 04 12:53:32 PM PDT 24
Finished Jun 04 12:53:33 PM PDT 24
Peak memory 145452 kb
Host smart-7f377181-0a22-4d2a-8acd-fd2ea7b095a0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1774107326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1774107326
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1672201843
Short name T60
Test name
Test status
Simulation time 9400285 ps
CPU time 0.39 seconds
Started Jun 04 12:53:33 PM PDT 24
Finished Jun 04 12:53:34 PM PDT 24
Peak memory 145544 kb
Host smart-d381f19c-a1af-4e20-8250-1352dd4299ef
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1672201843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1672201843
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3119517904
Short name T31
Test name
Test status
Simulation time 9603202 ps
CPU time 0.38 seconds
Started Jun 04 12:53:36 PM PDT 24
Finished Jun 04 12:53:38 PM PDT 24
Peak memory 145584 kb
Host smart-2cac4920-30e0-45b1-9bda-a79a4ce0340a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3119517904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3119517904
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1834542383
Short name T75
Test name
Test status
Simulation time 28204112 ps
CPU time 0.39 seconds
Started Jun 04 12:55:14 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 145596 kb
Host smart-9b31c3e6-3a88-4328-82df-447ff3f7c959
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1834542383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1834542383
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3530824450
Short name T68
Test name
Test status
Simulation time 25591379 ps
CPU time 0.39 seconds
Started Jun 04 12:55:13 PM PDT 24
Finished Jun 04 12:55:29 PM PDT 24
Peak memory 145584 kb
Host smart-99b1404a-670f-41c5-b7b4-b1077de747f8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3530824450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3530824450
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4290942740
Short name T69
Test name
Test status
Simulation time 26107136 ps
CPU time 0.39 seconds
Started Jun 04 12:55:17 PM PDT 24
Finished Jun 04 12:55:18 PM PDT 24
Peak memory 145576 kb
Host smart-4da45171-2545-42bb-beb6-7b9849cad529
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4290942740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4290942740
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.223533731
Short name T70
Test name
Test status
Simulation time 26835589 ps
CPU time 0.38 seconds
Started Jun 04 12:55:16 PM PDT 24
Finished Jun 04 12:55:17 PM PDT 24
Peak memory 145572 kb
Host smart-a9cfeae4-5c7a-4a87-b8ca-ef636157ca17
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=223533731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.223533731
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3097015936
Short name T65
Test name
Test status
Simulation time 29925827 ps
CPU time 0.4 seconds
Started Jun 04 12:55:10 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 145596 kb
Host smart-1ce9c39f-7dc5-484e-8744-2dd483625963
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3097015936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3097015936
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2051642593
Short name T79
Test name
Test status
Simulation time 27530932 ps
CPU time 0.38 seconds
Started Jun 04 12:55:13 PM PDT 24
Finished Jun 04 12:55:15 PM PDT 24
Peak memory 145600 kb
Host smart-f903826f-cd5a-451a-8706-37e1816c46b0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2051642593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2051642593
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3529169426
Short name T76
Test name
Test status
Simulation time 27615463 ps
CPU time 0.39 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:15 PM PDT 24
Peak memory 145608 kb
Host smart-c1fabc89-e782-4211-80a0-cdad560c9e9c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3529169426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3529169426
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3213976529
Short name T77
Test name
Test status
Simulation time 28791891 ps
CPU time 0.41 seconds
Started Jun 04 12:55:46 PM PDT 24
Finished Jun 04 12:55:46 PM PDT 24
Peak memory 145608 kb
Host smart-fda778fc-4dd4-44d4-9d63-c9a27ef945de
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3213976529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3213976529
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2908686336
Short name T71
Test name
Test status
Simulation time 26739693 ps
CPU time 0.39 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:14 PM PDT 24
Peak memory 145600 kb
Host smart-5fd703b1-1538-47e5-ab9e-be30e96a311a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2908686336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2908686336
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.671261807
Short name T72
Test name
Test status
Simulation time 27810440 ps
CPU time 0.4 seconds
Started Jun 04 12:55:10 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 145600 kb
Host smart-af486f85-05a5-49a1-b37b-f3e06a04871b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=671261807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.671261807
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.410549342
Short name T4
Test name
Test status
Simulation time 27448492 ps
CPU time 0.4 seconds
Started Jun 04 12:55:13 PM PDT 24
Finished Jun 04 12:55:15 PM PDT 24
Peak memory 145592 kb
Host smart-f1111160-de39-49a8-8a4b-a650cd1b51e0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=410549342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.410549342
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1812065308
Short name T74
Test name
Test status
Simulation time 25514310 ps
CPU time 0.45 seconds
Started Jun 04 12:55:28 PM PDT 24
Finished Jun 04 12:55:29 PM PDT 24
Peak memory 145560 kb
Host smart-719656d8-bc45-49cc-84b1-4f6b6399acc1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1812065308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1812065308
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2603281173
Short name T78
Test name
Test status
Simulation time 27011921 ps
CPU time 0.39 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:14 PM PDT 24
Peak memory 145544 kb
Host smart-5346b820-0270-4ffc-ac81-2c1e3e11b88f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2603281173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2603281173
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2530189609
Short name T6
Test name
Test status
Simulation time 28256566 ps
CPU time 0.42 seconds
Started Jun 04 12:55:17 PM PDT 24
Finished Jun 04 12:55:18 PM PDT 24
Peak memory 145564 kb
Host smart-477e0a4d-9665-4931-a7bc-800d0a66f346
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2530189609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2530189609
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.110533043
Short name T64
Test name
Test status
Simulation time 28623467 ps
CPU time 0.39 seconds
Started Jun 04 12:55:14 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 145544 kb
Host smart-821c01d4-3075-4b14-b5d5-4c24afe86322
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=110533043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.110533043
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2951446546
Short name T73
Test name
Test status
Simulation time 27462801 ps
CPU time 0.39 seconds
Started Jun 04 12:55:10 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 145568 kb
Host smart-10a988af-6c64-4678-ac26-29f80df3975e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2951446546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2951446546
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1601043320
Short name T67
Test name
Test status
Simulation time 27658600 ps
CPU time 0.39 seconds
Started Jun 04 12:55:12 PM PDT 24
Finished Jun 04 12:55:15 PM PDT 24
Peak memory 145576 kb
Host smart-c020f58b-0f88-48ab-8976-8c34853a10d1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1601043320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1601043320
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2408575081
Short name T66
Test name
Test status
Simulation time 26594404 ps
CPU time 0.42 seconds
Started Jun 04 12:55:13 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 145464 kb
Host smart-016fad1f-ee4f-4945-be6d-a1a2ade5600e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2408575081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2408575081
Directory /workspace/9.prim_sync_fatal_alert/latest
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