Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.27 89.27 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 67.44 67.44 /workspace/coverage/default/7.prim_async_alert.3462101835
92.39 3.13 100.00 0.00 93.75 0.00 100.00 0.00 85.71 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/1.prim_sync_alert.3773048607
94.15 1.76 100.00 0.00 93.75 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.48986076
94.50 0.35 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/13.prim_async_alert.3865341829
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/7.prim_sync_alert.2117407373
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.991662392

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2089470632
/workspace/coverage/default/1.prim_async_alert.1594423352
/workspace/coverage/default/10.prim_async_alert.2101907381
/workspace/coverage/default/11.prim_async_alert.50050902
/workspace/coverage/default/12.prim_async_alert.3684205931
/workspace/coverage/default/14.prim_async_alert.4127364255
/workspace/coverage/default/15.prim_async_alert.871155753
/workspace/coverage/default/16.prim_async_alert.2407728421
/workspace/coverage/default/17.prim_async_alert.3604043069
/workspace/coverage/default/18.prim_async_alert.880955729
/workspace/coverage/default/19.prim_async_alert.1731809882
/workspace/coverage/default/2.prim_async_alert.3106714115
/workspace/coverage/default/3.prim_async_alert.2180060011
/workspace/coverage/default/4.prim_async_alert.1518315867
/workspace/coverage/default/5.prim_async_alert.239342888
/workspace/coverage/default/6.prim_async_alert.1391749444
/workspace/coverage/default/8.prim_async_alert.1834516162
/workspace/coverage/default/9.prim_async_alert.3699683155
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4181466311
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.342327692
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2223750015
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.809624536
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2915278193
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.40586473
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2422186480
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3572534341
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3752977334
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2004533239
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.514316220
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1314358820
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.943750112
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2682853943
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.398041037
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2329548389
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.552129536
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3094511056
/workspace/coverage/sync_alert/0.prim_sync_alert.2286515983
/workspace/coverage/sync_alert/10.prim_sync_alert.4089018611
/workspace/coverage/sync_alert/11.prim_sync_alert.3518198089
/workspace/coverage/sync_alert/12.prim_sync_alert.348666391
/workspace/coverage/sync_alert/13.prim_sync_alert.2530919665
/workspace/coverage/sync_alert/14.prim_sync_alert.3564466206
/workspace/coverage/sync_alert/15.prim_sync_alert.1377858338
/workspace/coverage/sync_alert/16.prim_sync_alert.3097533645
/workspace/coverage/sync_alert/17.prim_sync_alert.1045753317
/workspace/coverage/sync_alert/18.prim_sync_alert.3795385369
/workspace/coverage/sync_alert/19.prim_sync_alert.2581785715
/workspace/coverage/sync_alert/2.prim_sync_alert.2162402030
/workspace/coverage/sync_alert/3.prim_sync_alert.4050449048
/workspace/coverage/sync_alert/4.prim_sync_alert.3769752905
/workspace/coverage/sync_alert/5.prim_sync_alert.1867765390
/workspace/coverage/sync_alert/6.prim_sync_alert.1708408109
/workspace/coverage/sync_alert/8.prim_sync_alert.2662872525
/workspace/coverage/sync_alert/9.prim_sync_alert.2332664717
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2699078474
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3302465043
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.954526614
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2120469713
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2475837499
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2478355960
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1960732807
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1348202838
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1521361414
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2276724588
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.415969350
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4140623035
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1817528861
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1185039946
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3401831332
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1212346106
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3985164940
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3780976504
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3979306727



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/18.prim_async_alert.880955729 Jun 05 03:35:55 PM PDT 24 Jun 05 03:35:56 PM PDT 24 10599417 ps
T2 /workspace/coverage/default/7.prim_async_alert.3462101835 Jun 05 03:31:11 PM PDT 24 Jun 05 03:31:13 PM PDT 24 11941536 ps
T3 /workspace/coverage/default/13.prim_async_alert.3865341829 Jun 05 03:35:32 PM PDT 24 Jun 05 03:35:33 PM PDT 24 11970116 ps
T6 /workspace/coverage/default/14.prim_async_alert.4127364255 Jun 05 03:35:01 PM PDT 24 Jun 05 03:35:02 PM PDT 24 11923896 ps
T5 /workspace/coverage/default/4.prim_async_alert.1518315867 Jun 05 03:33:47 PM PDT 24 Jun 05 03:33:48 PM PDT 24 11350433 ps
T13 /workspace/coverage/default/17.prim_async_alert.3604043069 Jun 05 03:35:22 PM PDT 24 Jun 05 03:35:23 PM PDT 24 11161261 ps
T14 /workspace/coverage/default/19.prim_async_alert.1731809882 Jun 05 03:32:43 PM PDT 24 Jun 05 03:32:44 PM PDT 24 11745600 ps
T15 /workspace/coverage/default/0.prim_async_alert.2089470632 Jun 05 03:33:20 PM PDT 24 Jun 05 03:33:21 PM PDT 24 10512984 ps
T16 /workspace/coverage/default/10.prim_async_alert.2101907381 Jun 05 03:35:05 PM PDT 24 Jun 05 03:35:07 PM PDT 24 11414134 ps
T17 /workspace/coverage/default/12.prim_async_alert.3684205931 Jun 05 03:36:08 PM PDT 24 Jun 05 03:36:09 PM PDT 24 11180997 ps
T18 /workspace/coverage/default/2.prim_async_alert.3106714115 Jun 05 03:30:31 PM PDT 24 Jun 05 03:30:32 PM PDT 24 10659959 ps
T19 /workspace/coverage/default/9.prim_async_alert.3699683155 Jun 05 03:35:46 PM PDT 24 Jun 05 03:35:47 PM PDT 24 11618314 ps
T36 /workspace/coverage/default/15.prim_async_alert.871155753 Jun 05 03:36:13 PM PDT 24 Jun 05 03:36:14 PM PDT 24 10744952 ps
T44 /workspace/coverage/default/3.prim_async_alert.2180060011 Jun 05 03:35:02 PM PDT 24 Jun 05 03:35:03 PM PDT 24 11364295 ps
T9 /workspace/coverage/default/6.prim_async_alert.1391749444 Jun 05 03:33:07 PM PDT 24 Jun 05 03:33:08 PM PDT 24 11986507 ps
T12 /workspace/coverage/default/1.prim_async_alert.1594423352 Jun 05 03:31:22 PM PDT 24 Jun 05 03:31:23 PM PDT 24 10954940 ps
T45 /workspace/coverage/default/5.prim_async_alert.239342888 Jun 05 03:34:11 PM PDT 24 Jun 05 03:34:12 PM PDT 24 10822699 ps
T20 /workspace/coverage/default/8.prim_async_alert.1834516162 Jun 05 03:34:57 PM PDT 24 Jun 05 03:34:59 PM PDT 24 11529631 ps
T21 /workspace/coverage/default/16.prim_async_alert.2407728421 Jun 05 03:33:20 PM PDT 24 Jun 05 03:33:21 PM PDT 24 11121199 ps
T10 /workspace/coverage/default/11.prim_async_alert.50050902 Jun 05 03:30:57 PM PDT 24 Jun 05 03:30:58 PM PDT 24 12067329 ps
T22 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3752977334 Jun 05 04:58:40 PM PDT 24 Jun 05 04:58:41 PM PDT 24 28190487 ps
T8 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.48986076 Jun 05 04:58:41 PM PDT 24 Jun 05 04:58:42 PM PDT 24 33520817 ps
T23 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3572534341 Jun 05 04:58:32 PM PDT 24 Jun 05 04:58:33 PM PDT 24 29125028 ps
T37 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2004533239 Jun 05 04:58:40 PM PDT 24 Jun 05 04:58:40 PM PDT 24 30401423 ps
T38 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2915278193 Jun 05 04:58:33 PM PDT 24 Jun 05 04:58:33 PM PDT 24 29845597 ps
T39 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.809624536 Jun 05 04:58:32 PM PDT 24 Jun 05 04:58:33 PM PDT 24 30675966 ps
T40 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1314358820 Jun 05 04:58:24 PM PDT 24 Jun 05 04:58:25 PM PDT 24 29935757 ps
T41 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2329548389 Jun 05 04:58:33 PM PDT 24 Jun 05 04:58:34 PM PDT 24 29142256 ps
T42 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3094511056 Jun 05 04:58:34 PM PDT 24 Jun 05 04:58:35 PM PDT 24 31478039 ps
T43 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.40586473 Jun 05 04:58:34 PM PDT 24 Jun 05 04:58:34 PM PDT 24 29437360 ps
T46 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.514316220 Jun 05 04:58:24 PM PDT 24 Jun 05 04:58:24 PM PDT 24 31458209 ps
T47 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.342327692 Jun 05 04:58:25 PM PDT 24 Jun 05 04:58:25 PM PDT 24 32028377 ps
T48 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.552129536 Jun 05 04:58:34 PM PDT 24 Jun 05 04:58:35 PM PDT 24 30982040 ps
T49 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.943750112 Jun 05 04:58:25 PM PDT 24 Jun 05 04:58:26 PM PDT 24 28085453 ps
T50 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.398041037 Jun 05 04:58:32 PM PDT 24 Jun 05 04:58:33 PM PDT 24 29176672 ps
T51 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2223750015 Jun 05 04:58:31 PM PDT 24 Jun 05 04:58:32 PM PDT 24 29946430 ps
T52 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2682853943 Jun 05 04:58:30 PM PDT 24 Jun 05 04:58:31 PM PDT 24 29768854 ps
T53 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4181466311 Jun 05 04:58:26 PM PDT 24 Jun 05 04:58:27 PM PDT 24 30035090 ps
T54 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2422186480 Jun 05 04:58:31 PM PDT 24 Jun 05 04:58:32 PM PDT 24 28863716 ps
T24 /workspace/coverage/sync_alert/4.prim_sync_alert.3769752905 Jun 05 04:39:27 PM PDT 24 Jun 05 04:39:28 PM PDT 24 9318605 ps
T11 /workspace/coverage/sync_alert/9.prim_sync_alert.2332664717 Jun 05 04:39:26 PM PDT 24 Jun 05 04:39:27 PM PDT 24 9388402 ps
T25 /workspace/coverage/sync_alert/3.prim_sync_alert.4050449048 Jun 05 04:39:19 PM PDT 24 Jun 05 04:39:20 PM PDT 24 8751272 ps
T32 /workspace/coverage/sync_alert/15.prim_sync_alert.1377858338 Jun 05 04:39:29 PM PDT 24 Jun 05 04:39:30 PM PDT 24 9810353 ps
T33 /workspace/coverage/sync_alert/19.prim_sync_alert.2581785715 Jun 05 04:39:26 PM PDT 24 Jun 05 04:39:27 PM PDT 24 8030909 ps
T26 /workspace/coverage/sync_alert/10.prim_sync_alert.4089018611 Jun 05 04:39:28 PM PDT 24 Jun 05 04:39:29 PM PDT 24 10585457 ps
T34 /workspace/coverage/sync_alert/11.prim_sync_alert.3518198089 Jun 05 04:39:26 PM PDT 24 Jun 05 04:39:27 PM PDT 24 8608830 ps
T7 /workspace/coverage/sync_alert/7.prim_sync_alert.2117407373 Jun 05 04:39:25 PM PDT 24 Jun 05 04:39:26 PM PDT 24 9683683 ps
T35 /workspace/coverage/sync_alert/2.prim_sync_alert.2162402030 Jun 05 04:39:21 PM PDT 24 Jun 05 04:39:23 PM PDT 24 8641388 ps
T27 /workspace/coverage/sync_alert/1.prim_sync_alert.3773048607 Jun 05 04:39:21 PM PDT 24 Jun 05 04:39:23 PM PDT 24 9536153 ps
T55 /workspace/coverage/sync_alert/8.prim_sync_alert.2662872525 Jun 05 04:39:29 PM PDT 24 Jun 05 04:39:30 PM PDT 24 8423742 ps
T56 /workspace/coverage/sync_alert/16.prim_sync_alert.3097533645 Jun 05 04:39:27 PM PDT 24 Jun 05 04:39:28 PM PDT 24 9103688 ps
T57 /workspace/coverage/sync_alert/0.prim_sync_alert.2286515983 Jun 05 04:39:18 PM PDT 24 Jun 05 04:39:20 PM PDT 24 9923481 ps
T28 /workspace/coverage/sync_alert/18.prim_sync_alert.3795385369 Jun 05 04:39:26 PM PDT 24 Jun 05 04:39:27 PM PDT 24 9617464 ps
T29 /workspace/coverage/sync_alert/17.prim_sync_alert.1045753317 Jun 05 04:39:29 PM PDT 24 Jun 05 04:39:30 PM PDT 24 8871266 ps
T58 /workspace/coverage/sync_alert/13.prim_sync_alert.2530919665 Jun 05 04:39:28 PM PDT 24 Jun 05 04:39:29 PM PDT 24 9648294 ps
T59 /workspace/coverage/sync_alert/14.prim_sync_alert.3564466206 Jun 05 04:39:29 PM PDT 24 Jun 05 04:39:30 PM PDT 24 8700876 ps
T30 /workspace/coverage/sync_alert/6.prim_sync_alert.1708408109 Jun 05 04:39:30 PM PDT 24 Jun 05 04:39:31 PM PDT 24 9571390 ps
T60 /workspace/coverage/sync_alert/12.prim_sync_alert.348666391 Jun 05 04:39:29 PM PDT 24 Jun 05 04:39:30 PM PDT 24 8623246 ps
T31 /workspace/coverage/sync_alert/5.prim_sync_alert.1867765390 Jun 05 04:39:28 PM PDT 24 Jun 05 04:39:29 PM PDT 24 8427241 ps
T61 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2478355960 Jun 05 04:58:55 PM PDT 24 Jun 05 04:58:56 PM PDT 24 28639578 ps
T62 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2475837499 Jun 05 04:58:54 PM PDT 24 Jun 05 04:58:55 PM PDT 24 26744907 ps
T63 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3780976504 Jun 05 04:58:45 PM PDT 24 Jun 05 04:58:46 PM PDT 24 28336399 ps
T64 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3401831332 Jun 05 04:58:45 PM PDT 24 Jun 05 04:58:46 PM PDT 24 27694308 ps
T65 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4140623035 Jun 05 04:58:40 PM PDT 24 Jun 05 04:58:41 PM PDT 24 27756290 ps
T66 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2699078474 Jun 05 04:58:41 PM PDT 24 Jun 05 04:58:42 PM PDT 24 26205856 ps
T67 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3302465043 Jun 05 04:58:41 PM PDT 24 Jun 05 04:58:42 PM PDT 24 26218180 ps
T68 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1817528861 Jun 05 04:58:40 PM PDT 24 Jun 05 04:58:41 PM PDT 24 27164735 ps
T69 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1960732807 Jun 05 04:58:56 PM PDT 24 Jun 05 04:58:57 PM PDT 24 26565558 ps
T70 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1185039946 Jun 05 04:58:40 PM PDT 24 Jun 05 04:58:41 PM PDT 24 27367550 ps
T71 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2120469713 Jun 05 04:58:46 PM PDT 24 Jun 05 04:58:47 PM PDT 24 28835073 ps
T72 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1348202838 Jun 05 04:58:55 PM PDT 24 Jun 05 04:58:56 PM PDT 24 27887877 ps
T73 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.415969350 Jun 05 04:59:00 PM PDT 24 Jun 05 04:59:01 PM PDT 24 28076986 ps
T74 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3979306727 Jun 05 04:58:47 PM PDT 24 Jun 05 04:58:47 PM PDT 24 28039003 ps
T75 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1521361414 Jun 05 04:58:52 PM PDT 24 Jun 05 04:58:53 PM PDT 24 27819737 ps
T76 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3985164940 Jun 05 04:58:48 PM PDT 24 Jun 05 04:58:48 PM PDT 24 26640738 ps
T77 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.954526614 Jun 05 04:58:49 PM PDT 24 Jun 05 04:58:50 PM PDT 24 28012038 ps
T4 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.991662392 Jun 05 04:58:56 PM PDT 24 Jun 05 04:58:57 PM PDT 24 28212148 ps
T78 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1212346106 Jun 05 04:58:48 PM PDT 24 Jun 05 04:58:49 PM PDT 24 28062338 ps
T79 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2276724588 Jun 05 04:58:55 PM PDT 24 Jun 05 04:58:56 PM PDT 24 29751630 ps

Test location /workspace/coverage/default/7.prim_async_alert.3462101835
Short name T2
Test name
Test status
Simulation time 11941536 ps
CPU time 0.44 seconds
Started Jun 05 03:31:11 PM PDT 24
Finished Jun 05 03:31:13 PM PDT 24
Peak memory 145308 kb
Host smart-2041affc-4eab-414e-b371-99e50720ce47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462101835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3462101835
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3773048607
Short name T27
Test name
Test status
Simulation time 9536153 ps
CPU time 0.4 seconds
Started Jun 05 04:39:21 PM PDT 24
Finished Jun 05 04:39:23 PM PDT 24
Peak memory 145592 kb
Host smart-4d471254-ae9a-4b7b-ae7a-dc2583d82f89
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3773048607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3773048607
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.48986076
Short name T8
Test name
Test status
Simulation time 33520817 ps
CPU time 0.39 seconds
Started Jun 05 04:58:41 PM PDT 24
Finished Jun 05 04:58:42 PM PDT 24
Peak memory 145836 kb
Host smart-39755afa-11fa-4177-a538-fed2b3730bb3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=48986076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.48986076
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3865341829
Short name T3
Test name
Test status
Simulation time 11970116 ps
CPU time 0.42 seconds
Started Jun 05 03:35:32 PM PDT 24
Finished Jun 05 03:35:33 PM PDT 24
Peak memory 145060 kb
Host smart-7e5b18e5-753c-4522-aa3e-c3062f8fff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865341829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3865341829
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2117407373
Short name T7
Test name
Test status
Simulation time 9683683 ps
CPU time 0.39 seconds
Started Jun 05 04:39:25 PM PDT 24
Finished Jun 05 04:39:26 PM PDT 24
Peak memory 145588 kb
Host smart-3995d3f8-a5d5-428b-90b6-5c12ce6f4364
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2117407373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2117407373
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.991662392
Short name T4
Test name
Test status
Simulation time 28212148 ps
CPU time 0.4 seconds
Started Jun 05 04:58:56 PM PDT 24
Finished Jun 05 04:58:57 PM PDT 24
Peak memory 145608 kb
Host smart-fc49930c-f8cc-49af-95c1-deec9232997a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=991662392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.991662392
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2089470632
Short name T15
Test name
Test status
Simulation time 10512984 ps
CPU time 0.4 seconds
Started Jun 05 03:33:20 PM PDT 24
Finished Jun 05 03:33:21 PM PDT 24
Peak memory 145436 kb
Host smart-381ae34c-90ea-4fa0-bd64-8bbab0a53774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089470632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2089470632
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1594423352
Short name T12
Test name
Test status
Simulation time 10954940 ps
CPU time 0.4 seconds
Started Jun 05 03:31:22 PM PDT 24
Finished Jun 05 03:31:23 PM PDT 24
Peak memory 145576 kb
Host smart-711f929c-5260-436c-8dab-e7491ebc40f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594423352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1594423352
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2101907381
Short name T16
Test name
Test status
Simulation time 11414134 ps
CPU time 0.38 seconds
Started Jun 05 03:35:05 PM PDT 24
Finished Jun 05 03:35:07 PM PDT 24
Peak memory 145284 kb
Host smart-35c21efa-3296-46b3-8aaf-43caaed3f646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101907381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2101907381
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.50050902
Short name T10
Test name
Test status
Simulation time 12067329 ps
CPU time 0.39 seconds
Started Jun 05 03:30:57 PM PDT 24
Finished Jun 05 03:30:58 PM PDT 24
Peak memory 145440 kb
Host smart-61452a5f-d5e4-4799-88e2-bdaeccfc0518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50050902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.50050902
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.3684205931
Short name T17
Test name
Test status
Simulation time 11180997 ps
CPU time 0.45 seconds
Started Jun 05 03:36:08 PM PDT 24
Finished Jun 05 03:36:09 PM PDT 24
Peak memory 145208 kb
Host smart-756a76a5-5f75-4acb-a7b2-c3279ff2aa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684205931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3684205931
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.4127364255
Short name T6
Test name
Test status
Simulation time 11923896 ps
CPU time 0.38 seconds
Started Jun 05 03:35:01 PM PDT 24
Finished Jun 05 03:35:02 PM PDT 24
Peak memory 145796 kb
Host smart-fd5721be-31d9-40cd-99b8-4715f35a35c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127364255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.4127364255
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.871155753
Short name T36
Test name
Test status
Simulation time 10744952 ps
CPU time 0.42 seconds
Started Jun 05 03:36:13 PM PDT 24
Finished Jun 05 03:36:14 PM PDT 24
Peak memory 144832 kb
Host smart-0094cff8-4ecf-47a1-9322-f56c0753eea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871155753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.871155753
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2407728421
Short name T21
Test name
Test status
Simulation time 11121199 ps
CPU time 0.53 seconds
Started Jun 05 03:33:20 PM PDT 24
Finished Jun 05 03:33:21 PM PDT 24
Peak memory 145928 kb
Host smart-a110c55c-0a9a-48bc-a8df-c5f4e8c0feb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407728421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2407728421
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3604043069
Short name T13
Test name
Test status
Simulation time 11161261 ps
CPU time 0.38 seconds
Started Jun 05 03:35:22 PM PDT 24
Finished Jun 05 03:35:23 PM PDT 24
Peak memory 145368 kb
Host smart-bed5a185-7f0c-42cd-937c-22b62db6db8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604043069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3604043069
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.880955729
Short name T1
Test name
Test status
Simulation time 10599417 ps
CPU time 0.4 seconds
Started Jun 05 03:35:55 PM PDT 24
Finished Jun 05 03:35:56 PM PDT 24
Peak memory 145212 kb
Host smart-a4f6c0c1-4689-4e52-9a67-3bc4423a777a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880955729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.880955729
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1731809882
Short name T14
Test name
Test status
Simulation time 11745600 ps
CPU time 0.4 seconds
Started Jun 05 03:32:43 PM PDT 24
Finished Jun 05 03:32:44 PM PDT 24
Peak memory 145928 kb
Host smart-504393b8-6295-460c-9cd7-c2297e7f3272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731809882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1731809882
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3106714115
Short name T18
Test name
Test status
Simulation time 10659959 ps
CPU time 0.39 seconds
Started Jun 05 03:30:31 PM PDT 24
Finished Jun 05 03:30:32 PM PDT 24
Peak memory 145444 kb
Host smart-dc6e6fcc-75d8-4afc-8871-3fa022fc8b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106714115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3106714115
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2180060011
Short name T44
Test name
Test status
Simulation time 11364295 ps
CPU time 0.41 seconds
Started Jun 05 03:35:02 PM PDT 24
Finished Jun 05 03:35:03 PM PDT 24
Peak memory 144656 kb
Host smart-cf2cec03-4a5a-444c-a954-f0bbe0939032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180060011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2180060011
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1518315867
Short name T5
Test name
Test status
Simulation time 11350433 ps
CPU time 0.39 seconds
Started Jun 05 03:33:47 PM PDT 24
Finished Jun 05 03:33:48 PM PDT 24
Peak memory 145852 kb
Host smart-a52378c7-7091-449c-a439-2ed9032514dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518315867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1518315867
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.239342888
Short name T45
Test name
Test status
Simulation time 10822699 ps
CPU time 0.4 seconds
Started Jun 05 03:34:11 PM PDT 24
Finished Jun 05 03:34:12 PM PDT 24
Peak memory 145908 kb
Host smart-7b800eaf-3c33-479a-9561-649c823f9548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239342888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.239342888
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1391749444
Short name T9
Test name
Test status
Simulation time 11986507 ps
CPU time 0.4 seconds
Started Jun 05 03:33:07 PM PDT 24
Finished Jun 05 03:33:08 PM PDT 24
Peak memory 145456 kb
Host smart-c4e4c69c-88da-4aa1-a6d8-8630c51d41b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391749444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1391749444
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1834516162
Short name T20
Test name
Test status
Simulation time 11529631 ps
CPU time 0.41 seconds
Started Jun 05 03:34:57 PM PDT 24
Finished Jun 05 03:34:59 PM PDT 24
Peak memory 144788 kb
Host smart-44526214-f7e0-450d-8f74-6b70626f11e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834516162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1834516162
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3699683155
Short name T19
Test name
Test status
Simulation time 11618314 ps
CPU time 0.37 seconds
Started Jun 05 03:35:46 PM PDT 24
Finished Jun 05 03:35:47 PM PDT 24
Peak memory 145596 kb
Host smart-b2cf19f6-41fc-4bd4-8d62-0e60534f324f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699683155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3699683155
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4181466311
Short name T53
Test name
Test status
Simulation time 30035090 ps
CPU time 0.39 seconds
Started Jun 05 04:58:26 PM PDT 24
Finished Jun 05 04:58:27 PM PDT 24
Peak memory 145808 kb
Host smart-cac524bb-4901-4d99-80f6-f4abf96fe5cf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4181466311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4181466311
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.342327692
Short name T47
Test name
Test status
Simulation time 32028377 ps
CPU time 0.4 seconds
Started Jun 05 04:58:25 PM PDT 24
Finished Jun 05 04:58:25 PM PDT 24
Peak memory 145816 kb
Host smart-34651b8b-e185-4c3a-9330-6682f93e4b94
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=342327692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.342327692
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2223750015
Short name T51
Test name
Test status
Simulation time 29946430 ps
CPU time 0.4 seconds
Started Jun 05 04:58:31 PM PDT 24
Finished Jun 05 04:58:32 PM PDT 24
Peak memory 145772 kb
Host smart-c4946ca5-f75d-4c66-a6fa-d138f9893cad
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2223750015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2223750015
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.809624536
Short name T39
Test name
Test status
Simulation time 30675966 ps
CPU time 0.38 seconds
Started Jun 05 04:58:32 PM PDT 24
Finished Jun 05 04:58:33 PM PDT 24
Peak memory 145788 kb
Host smart-ca162a63-dc2d-4752-b354-cce14dd6269b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=809624536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.809624536
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2915278193
Short name T38
Test name
Test status
Simulation time 29845597 ps
CPU time 0.4 seconds
Started Jun 05 04:58:33 PM PDT 24
Finished Jun 05 04:58:33 PM PDT 24
Peak memory 145808 kb
Host smart-2e1ccf97-6a71-4db8-b137-191028aac2e7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2915278193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2915278193
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.40586473
Short name T43
Test name
Test status
Simulation time 29437360 ps
CPU time 0.4 seconds
Started Jun 05 04:58:34 PM PDT 24
Finished Jun 05 04:58:34 PM PDT 24
Peak memory 145904 kb
Host smart-24bcea9c-5b82-494a-be9f-f3c859d1ded6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=40586473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.40586473
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2422186480
Short name T54
Test name
Test status
Simulation time 28863716 ps
CPU time 0.4 seconds
Started Jun 05 04:58:31 PM PDT 24
Finished Jun 05 04:58:32 PM PDT 24
Peak memory 145812 kb
Host smart-f8b60f6a-aee5-4cc8-ab3f-ca1129fff845
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2422186480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2422186480
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3572534341
Short name T23
Test name
Test status
Simulation time 29125028 ps
CPU time 0.41 seconds
Started Jun 05 04:58:32 PM PDT 24
Finished Jun 05 04:58:33 PM PDT 24
Peak memory 145780 kb
Host smart-0556f3a4-50b5-479e-9b16-11242552b7fa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3572534341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3572534341
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3752977334
Short name T22
Test name
Test status
Simulation time 28190487 ps
CPU time 0.4 seconds
Started Jun 05 04:58:40 PM PDT 24
Finished Jun 05 04:58:41 PM PDT 24
Peak memory 145824 kb
Host smart-5c8ff099-8853-4618-bafa-7143315a6c43
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3752977334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3752977334
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2004533239
Short name T37
Test name
Test status
Simulation time 30401423 ps
CPU time 0.4 seconds
Started Jun 05 04:58:40 PM PDT 24
Finished Jun 05 04:58:40 PM PDT 24
Peak memory 145672 kb
Host smart-efaef96c-6639-4567-9f71-c9bdc5e3223f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2004533239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2004533239
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.514316220
Short name T46
Test name
Test status
Simulation time 31458209 ps
CPU time 0.41 seconds
Started Jun 05 04:58:24 PM PDT 24
Finished Jun 05 04:58:24 PM PDT 24
Peak memory 145828 kb
Host smart-64788185-dea4-4e9a-bf70-def58c2ee8f5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=514316220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.514316220
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1314358820
Short name T40
Test name
Test status
Simulation time 29935757 ps
CPU time 0.4 seconds
Started Jun 05 04:58:24 PM PDT 24
Finished Jun 05 04:58:25 PM PDT 24
Peak memory 145812 kb
Host smart-809e3354-bd58-4f88-afaa-5412ca6abecf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1314358820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1314358820
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.943750112
Short name T49
Test name
Test status
Simulation time 28085453 ps
CPU time 0.39 seconds
Started Jun 05 04:58:25 PM PDT 24
Finished Jun 05 04:58:26 PM PDT 24
Peak memory 145812 kb
Host smart-d327aa9b-d425-45f9-bbb9-3ac3964206ce
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=943750112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.943750112
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2682853943
Short name T52
Test name
Test status
Simulation time 29768854 ps
CPU time 0.4 seconds
Started Jun 05 04:58:30 PM PDT 24
Finished Jun 05 04:58:31 PM PDT 24
Peak memory 145784 kb
Host smart-a1093f6c-58bb-4c92-a2a8-557701a6cade
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2682853943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2682853943
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.398041037
Short name T50
Test name
Test status
Simulation time 29176672 ps
CPU time 0.41 seconds
Started Jun 05 04:58:32 PM PDT 24
Finished Jun 05 04:58:33 PM PDT 24
Peak memory 145820 kb
Host smart-f3bc3c64-b568-437c-9dbe-e1baee805472
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=398041037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.398041037
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2329548389
Short name T41
Test name
Test status
Simulation time 29142256 ps
CPU time 0.41 seconds
Started Jun 05 04:58:33 PM PDT 24
Finished Jun 05 04:58:34 PM PDT 24
Peak memory 145928 kb
Host smart-657ea7fb-593e-474b-afa1-f525d4894de9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2329548389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2329548389
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.552129536
Short name T48
Test name
Test status
Simulation time 30982040 ps
CPU time 0.4 seconds
Started Jun 05 04:58:34 PM PDT 24
Finished Jun 05 04:58:35 PM PDT 24
Peak memory 145904 kb
Host smart-1188b052-45fd-4271-a36d-32af660af574
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=552129536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.552129536
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3094511056
Short name T42
Test name
Test status
Simulation time 31478039 ps
CPU time 0.41 seconds
Started Jun 05 04:58:34 PM PDT 24
Finished Jun 05 04:58:35 PM PDT 24
Peak memory 145880 kb
Host smart-b43c7337-c728-457d-8e4b-649a0f15d6ad
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3094511056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3094511056
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2286515983
Short name T57
Test name
Test status
Simulation time 9923481 ps
CPU time 0.39 seconds
Started Jun 05 04:39:18 PM PDT 24
Finished Jun 05 04:39:20 PM PDT 24
Peak memory 145588 kb
Host smart-5ed71beb-ea78-4780-88f9-f18de8d47bd4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2286515983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2286515983
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.4089018611
Short name T26
Test name
Test status
Simulation time 10585457 ps
CPU time 0.39 seconds
Started Jun 05 04:39:28 PM PDT 24
Finished Jun 05 04:39:29 PM PDT 24
Peak memory 145584 kb
Host smart-46d28d65-db98-431a-bdb3-f9d25fe80f52
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4089018611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.4089018611
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3518198089
Short name T34
Test name
Test status
Simulation time 8608830 ps
CPU time 0.4 seconds
Started Jun 05 04:39:26 PM PDT 24
Finished Jun 05 04:39:27 PM PDT 24
Peak memory 145584 kb
Host smart-442bad16-0eae-48e6-a464-d01f029d5115
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3518198089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3518198089
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.348666391
Short name T60
Test name
Test status
Simulation time 8623246 ps
CPU time 0.37 seconds
Started Jun 05 04:39:29 PM PDT 24
Finished Jun 05 04:39:30 PM PDT 24
Peak memory 145596 kb
Host smart-50f0982a-002c-4d88-a891-903d8c187e70
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=348666391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.348666391
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2530919665
Short name T58
Test name
Test status
Simulation time 9648294 ps
CPU time 0.4 seconds
Started Jun 05 04:39:28 PM PDT 24
Finished Jun 05 04:39:29 PM PDT 24
Peak memory 145592 kb
Host smart-4754ea77-db62-428f-b271-33d20025e6a0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2530919665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2530919665
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3564466206
Short name T59
Test name
Test status
Simulation time 8700876 ps
CPU time 0.38 seconds
Started Jun 05 04:39:29 PM PDT 24
Finished Jun 05 04:39:30 PM PDT 24
Peak memory 145576 kb
Host smart-797a0227-6e6f-48c2-a4dc-243c06b08472
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3564466206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3564466206
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1377858338
Short name T32
Test name
Test status
Simulation time 9810353 ps
CPU time 0.39 seconds
Started Jun 05 04:39:29 PM PDT 24
Finished Jun 05 04:39:30 PM PDT 24
Peak memory 145584 kb
Host smart-154fb183-03f6-42ba-9342-3485e9a480d5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1377858338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1377858338
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3097533645
Short name T56
Test name
Test status
Simulation time 9103688 ps
CPU time 0.38 seconds
Started Jun 05 04:39:27 PM PDT 24
Finished Jun 05 04:39:28 PM PDT 24
Peak memory 145584 kb
Host smart-51e0bab2-0d2b-4849-9757-f1653b5be463
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3097533645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3097533645
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1045753317
Short name T29
Test name
Test status
Simulation time 8871266 ps
CPU time 0.4 seconds
Started Jun 05 04:39:29 PM PDT 24
Finished Jun 05 04:39:30 PM PDT 24
Peak memory 145552 kb
Host smart-4ccbdd8a-8f5e-4ccc-afce-ecb37a290299
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1045753317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1045753317
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3795385369
Short name T28
Test name
Test status
Simulation time 9617464 ps
CPU time 0.38 seconds
Started Jun 05 04:39:26 PM PDT 24
Finished Jun 05 04:39:27 PM PDT 24
Peak memory 145580 kb
Host smart-97ee454e-7951-4bfb-8d0e-9dbd17977c43
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3795385369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3795385369
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2581785715
Short name T33
Test name
Test status
Simulation time 8030909 ps
CPU time 0.4 seconds
Started Jun 05 04:39:26 PM PDT 24
Finished Jun 05 04:39:27 PM PDT 24
Peak memory 145572 kb
Host smart-140581f1-9459-4f74-a4c8-b81a61d4e98b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2581785715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2581785715
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2162402030
Short name T35
Test name
Test status
Simulation time 8641388 ps
CPU time 0.4 seconds
Started Jun 05 04:39:21 PM PDT 24
Finished Jun 05 04:39:23 PM PDT 24
Peak memory 145592 kb
Host smart-3b02b499-a83e-4b7b-8c39-4eb930fe3114
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2162402030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2162402030
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.4050449048
Short name T25
Test name
Test status
Simulation time 8751272 ps
CPU time 0.38 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:39:20 PM PDT 24
Peak memory 145588 kb
Host smart-a282ac78-71d1-44d1-9dbc-cfefe026e5a6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4050449048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.4050449048
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3769752905
Short name T24
Test name
Test status
Simulation time 9318605 ps
CPU time 0.39 seconds
Started Jun 05 04:39:27 PM PDT 24
Finished Jun 05 04:39:28 PM PDT 24
Peak memory 145548 kb
Host smart-f37e2760-060a-4def-9766-9ce2536a968b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3769752905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3769752905
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1867765390
Short name T31
Test name
Test status
Simulation time 8427241 ps
CPU time 0.37 seconds
Started Jun 05 04:39:28 PM PDT 24
Finished Jun 05 04:39:29 PM PDT 24
Peak memory 145604 kb
Host smart-70e40713-0106-4b4d-b50b-f4bc1af2b472
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1867765390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1867765390
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1708408109
Short name T30
Test name
Test status
Simulation time 9571390 ps
CPU time 0.4 seconds
Started Jun 05 04:39:30 PM PDT 24
Finished Jun 05 04:39:31 PM PDT 24
Peak memory 145496 kb
Host smart-ce6dd668-b59e-4264-8bd6-04c7908d8996
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1708408109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1708408109
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2662872525
Short name T55
Test name
Test status
Simulation time 8423742 ps
CPU time 0.37 seconds
Started Jun 05 04:39:29 PM PDT 24
Finished Jun 05 04:39:30 PM PDT 24
Peak memory 145588 kb
Host smart-8df1d7a1-5983-4402-add5-6dd46aaa8fc0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2662872525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2662872525
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2332664717
Short name T11
Test name
Test status
Simulation time 9388402 ps
CPU time 0.37 seconds
Started Jun 05 04:39:26 PM PDT 24
Finished Jun 05 04:39:27 PM PDT 24
Peak memory 145584 kb
Host smart-b0e7abdf-ff29-4150-8b57-5f7491f5eea2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2332664717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2332664717
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2699078474
Short name T66
Test name
Test status
Simulation time 26205856 ps
CPU time 0.4 seconds
Started Jun 05 04:58:41 PM PDT 24
Finished Jun 05 04:58:42 PM PDT 24
Peak memory 145584 kb
Host smart-21577fdd-86d5-4b9f-9cbb-958050dd559e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2699078474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2699078474
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3302465043
Short name T67
Test name
Test status
Simulation time 26218180 ps
CPU time 0.42 seconds
Started Jun 05 04:58:41 PM PDT 24
Finished Jun 05 04:58:42 PM PDT 24
Peak memory 145576 kb
Host smart-0f3dadf1-47b8-4aa8-8342-5e709f29aff1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3302465043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3302465043
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.954526614
Short name T77
Test name
Test status
Simulation time 28012038 ps
CPU time 0.41 seconds
Started Jun 05 04:58:49 PM PDT 24
Finished Jun 05 04:58:50 PM PDT 24
Peak memory 145604 kb
Host smart-81bed5cd-9d4a-4cd2-9e9f-a61f875edf02
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=954526614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.954526614
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2120469713
Short name T71
Test name
Test status
Simulation time 28835073 ps
CPU time 0.4 seconds
Started Jun 05 04:58:46 PM PDT 24
Finished Jun 05 04:58:47 PM PDT 24
Peak memory 145608 kb
Host smart-f6b1fc21-238a-4bb6-8012-cd65048b522c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2120469713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2120469713
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2475837499
Short name T62
Test name
Test status
Simulation time 26744907 ps
CPU time 0.43 seconds
Started Jun 05 04:58:54 PM PDT 24
Finished Jun 05 04:58:55 PM PDT 24
Peak memory 145608 kb
Host smart-98ae83bf-c4c2-48af-a76d-c6714979fe1b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2475837499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2475837499
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2478355960
Short name T61
Test name
Test status
Simulation time 28639578 ps
CPU time 0.4 seconds
Started Jun 05 04:58:55 PM PDT 24
Finished Jun 05 04:58:56 PM PDT 24
Peak memory 145592 kb
Host smart-229b6073-e792-452f-9220-a0e62860a8a9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2478355960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2478355960
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1960732807
Short name T69
Test name
Test status
Simulation time 26565558 ps
CPU time 0.4 seconds
Started Jun 05 04:58:56 PM PDT 24
Finished Jun 05 04:58:57 PM PDT 24
Peak memory 145616 kb
Host smart-943c3614-f77c-4341-9a0f-8ae648846043
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1960732807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1960732807
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1348202838
Short name T72
Test name
Test status
Simulation time 27887877 ps
CPU time 0.4 seconds
Started Jun 05 04:58:55 PM PDT 24
Finished Jun 05 04:58:56 PM PDT 24
Peak memory 145616 kb
Host smart-eb3a800e-d116-4dab-9ecd-711c2d1adbee
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1348202838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1348202838
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1521361414
Short name T75
Test name
Test status
Simulation time 27819737 ps
CPU time 0.4 seconds
Started Jun 05 04:58:52 PM PDT 24
Finished Jun 05 04:58:53 PM PDT 24
Peak memory 145604 kb
Host smart-770fa35b-d6a5-4f01-af4f-4f5b0e5b024e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1521361414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1521361414
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2276724588
Short name T79
Test name
Test status
Simulation time 29751630 ps
CPU time 0.43 seconds
Started Jun 05 04:58:55 PM PDT 24
Finished Jun 05 04:58:56 PM PDT 24
Peak memory 145612 kb
Host smart-59700198-13a4-4da1-ac45-0496bce6f30e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2276724588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2276724588
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.415969350
Short name T73
Test name
Test status
Simulation time 28076986 ps
CPU time 0.4 seconds
Started Jun 05 04:59:00 PM PDT 24
Finished Jun 05 04:59:01 PM PDT 24
Peak memory 145604 kb
Host smart-fbb31e65-53a2-484d-92eb-f743ab891685
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=415969350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.415969350
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4140623035
Short name T65
Test name
Test status
Simulation time 27756290 ps
CPU time 0.42 seconds
Started Jun 05 04:58:40 PM PDT 24
Finished Jun 05 04:58:41 PM PDT 24
Peak memory 145576 kb
Host smart-17374b6c-aab1-4eb9-a3d2-02528c27a0a3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4140623035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.4140623035
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1817528861
Short name T68
Test name
Test status
Simulation time 27164735 ps
CPU time 0.4 seconds
Started Jun 05 04:58:40 PM PDT 24
Finished Jun 05 04:58:41 PM PDT 24
Peak memory 145592 kb
Host smart-dc5a0a71-56a4-4b50-828d-4aa1aa4f5cb1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1817528861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1817528861
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1185039946
Short name T70
Test name
Test status
Simulation time 27367550 ps
CPU time 0.4 seconds
Started Jun 05 04:58:40 PM PDT 24
Finished Jun 05 04:58:41 PM PDT 24
Peak memory 145588 kb
Host smart-ded62926-3b2c-4e83-916c-0160ca3b6c8f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1185039946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1185039946
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3401831332
Short name T64
Test name
Test status
Simulation time 27694308 ps
CPU time 0.39 seconds
Started Jun 05 04:58:45 PM PDT 24
Finished Jun 05 04:58:46 PM PDT 24
Peak memory 145600 kb
Host smart-3eb5de0b-5ebd-40a6-bcc5-7344e44154e2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3401831332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3401831332
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1212346106
Short name T78
Test name
Test status
Simulation time 28062338 ps
CPU time 0.46 seconds
Started Jun 05 04:58:48 PM PDT 24
Finished Jun 05 04:58:49 PM PDT 24
Peak memory 145592 kb
Host smart-e215644c-b578-42f3-86bb-e4eaea4fc224
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1212346106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1212346106
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3985164940
Short name T76
Test name
Test status
Simulation time 26640738 ps
CPU time 0.4 seconds
Started Jun 05 04:58:48 PM PDT 24
Finished Jun 05 04:58:48 PM PDT 24
Peak memory 145592 kb
Host smart-7fa514dd-4fe5-4568-a21b-88d829b848c8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3985164940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3985164940
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3780976504
Short name T63
Test name
Test status
Simulation time 28336399 ps
CPU time 0.38 seconds
Started Jun 05 04:58:45 PM PDT 24
Finished Jun 05 04:58:46 PM PDT 24
Peak memory 145600 kb
Host smart-00af5da1-afe4-46b2-9e00-bd241f3437ab
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3780976504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3780976504
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3979306727
Short name T74
Test name
Test status
Simulation time 28039003 ps
CPU time 0.4 seconds
Started Jun 05 04:58:47 PM PDT 24
Finished Jun 05 04:58:47 PM PDT 24
Peak memory 145576 kb
Host smart-e95fcd4b-cf01-4116-ada9-71e98992802d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3979306727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3979306727
Directory /workspace/9.prim_sync_fatal_alert/latest
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