| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.92 | 88.92 | 100.00 | 100.00 | 91.67 | 91.67 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/18.prim_async_alert.2645371112 |
| 92.05 | 3.13 | 100.00 | 0.00 | 91.67 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/1.prim_sync_alert.1123327434 |
| 94.15 | 2.11 | 100.00 | 0.00 | 93.75 | 2.08 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1579231800 |
| 94.50 | 0.35 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/11.prim_async_alert.3652567806 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3268368304 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/0.prim_sync_alert.2128917984 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.158670338 |
| /workspace/coverage/default/1.prim_async_alert.2434550041 |
| /workspace/coverage/default/10.prim_async_alert.359405608 |
| /workspace/coverage/default/12.prim_async_alert.3129079147 |
| /workspace/coverage/default/13.prim_async_alert.719567557 |
| /workspace/coverage/default/15.prim_async_alert.2042783349 |
| /workspace/coverage/default/16.prim_async_alert.830104748 |
| /workspace/coverage/default/17.prim_async_alert.3589077570 |
| /workspace/coverage/default/19.prim_async_alert.540200589 |
| /workspace/coverage/default/2.prim_async_alert.1866162231 |
| /workspace/coverage/default/3.prim_async_alert.1020791784 |
| /workspace/coverage/default/4.prim_async_alert.620453993 |
| /workspace/coverage/default/5.prim_async_alert.494927727 |
| /workspace/coverage/default/6.prim_async_alert.2019670081 |
| /workspace/coverage/default/7.prim_async_alert.1834890425 |
| /workspace/coverage/default/8.prim_async_alert.1289187387 |
| /workspace/coverage/default/9.prim_async_alert.1887240820 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.390356502 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3914932469 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2835351604 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.419344890 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1554295830 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3459897199 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1843683481 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1930221973 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2423618435 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.862672274 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.23681734 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1708525612 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1360843165 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3601688199 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1360194688 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.115963900 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.448401934 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.1525670236 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.366826013 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.2782954298 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.217977196 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1896760113 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.3403735720 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.21883210 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.1866363693 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.1906632815 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.3729084544 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2531340686 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.2605723588 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.495647361 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.2593448010 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1087645516 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.2343983799 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.14015485 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1696529239 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2573570981 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2759435125 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3097325319 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3442104827 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2318928555 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2361491615 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1491813816 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1756630866 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.93647271 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2242542631 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.728301152 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1455591329 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2952415023 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.609236426 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3314529837 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.968798367 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1724321349 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2487285066 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3536970662 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.694105923 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/5.prim_async_alert.494927727 | Jun 06 01:24:01 PM PDT 24 | Jun 06 01:24:03 PM PDT 24 | 10817085 ps | ||
| T2 | /workspace/coverage/default/8.prim_async_alert.1289187387 | Jun 06 01:23:59 PM PDT 24 | Jun 06 01:24:01 PM PDT 24 | 10790520 ps | ||
| T3 | /workspace/coverage/default/18.prim_async_alert.2645371112 | Jun 06 01:24:24 PM PDT 24 | Jun 06 01:24:26 PM PDT 24 | 11594672 ps | ||
| T17 | /workspace/coverage/default/19.prim_async_alert.540200589 | Jun 06 01:24:15 PM PDT 24 | Jun 06 01:24:16 PM PDT 24 | 10947895 ps | ||
| T6 | /workspace/coverage/default/6.prim_async_alert.2019670081 | Jun 06 01:24:16 PM PDT 24 | Jun 06 01:24:17 PM PDT 24 | 11542910 ps | ||
| T8 | /workspace/coverage/default/12.prim_async_alert.3129079147 | Jun 06 01:24:07 PM PDT 24 | Jun 06 01:24:09 PM PDT 24 | 10425484 ps | ||
| T11 | /workspace/coverage/default/9.prim_async_alert.1887240820 | Jun 06 01:24:03 PM PDT 24 | Jun 06 01:24:06 PM PDT 24 | 11469972 ps | ||
| T16 | /workspace/coverage/default/17.prim_async_alert.3589077570 | Jun 06 01:24:21 PM PDT 24 | Jun 06 01:24:23 PM PDT 24 | 10819656 ps | ||
| T7 | /workspace/coverage/default/16.prim_async_alert.830104748 | Jun 06 01:24:12 PM PDT 24 | Jun 06 01:24:13 PM PDT 24 | 11381064 ps | ||
| T18 | /workspace/coverage/default/11.prim_async_alert.3652567806 | Jun 06 01:24:13 PM PDT 24 | Jun 06 01:24:14 PM PDT 24 | 10586591 ps | ||
| T12 | /workspace/coverage/default/1.prim_async_alert.2434550041 | Jun 06 01:24:16 PM PDT 24 | Jun 06 01:24:18 PM PDT 24 | 11534419 ps | ||
| T19 | /workspace/coverage/default/3.prim_async_alert.1020791784 | Jun 06 01:24:19 PM PDT 24 | Jun 06 01:24:20 PM PDT 24 | 10704386 ps | ||
| T20 | /workspace/coverage/default/13.prim_async_alert.719567557 | Jun 06 01:24:23 PM PDT 24 | Jun 06 01:24:25 PM PDT 24 | 10785433 ps | ||
| T13 | /workspace/coverage/default/2.prim_async_alert.1866162231 | Jun 06 01:24:03 PM PDT 24 | Jun 06 01:24:10 PM PDT 24 | 10824200 ps | ||
| T21 | /workspace/coverage/default/15.prim_async_alert.2042783349 | Jun 06 01:24:11 PM PDT 24 | Jun 06 01:24:12 PM PDT 24 | 11420314 ps | ||
| T22 | /workspace/coverage/default/7.prim_async_alert.1834890425 | Jun 06 01:24:16 PM PDT 24 | Jun 06 01:24:17 PM PDT 24 | 10981304 ps | ||
| T45 | /workspace/coverage/default/10.prim_async_alert.359405608 | Jun 06 01:24:12 PM PDT 24 | Jun 06 01:24:13 PM PDT 24 | 11229195 ps | ||
| T14 | /workspace/coverage/default/4.prim_async_alert.620453993 | Jun 06 01:24:05 PM PDT 24 | Jun 06 01:24:07 PM PDT 24 | 12039288 ps | ||
| T46 | /workspace/coverage/default/0.prim_async_alert.158670338 | Jun 06 01:24:28 PM PDT 24 | Jun 06 01:24:30 PM PDT 24 | 10176522 ps | ||
| T38 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1843683481 | Jun 06 01:56:59 PM PDT 24 | Jun 06 01:57:00 PM PDT 24 | 30419342 ps | ||
| T39 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1708525612 | Jun 06 01:57:11 PM PDT 24 | Jun 06 01:57:13 PM PDT 24 | 30328542 ps | ||
| T40 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.419344890 | Jun 06 01:57:01 PM PDT 24 | Jun 06 01:57:03 PM PDT 24 | 29784348 ps | ||
| T41 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1579231800 | Jun 06 01:57:06 PM PDT 24 | Jun 06 01:57:07 PM PDT 24 | 29129890 ps | ||
| T4 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3268368304 | Jun 06 01:57:15 PM PDT 24 | Jun 06 01:57:17 PM PDT 24 | 29485788 ps | ||
| T42 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3914932469 | Jun 06 01:56:54 PM PDT 24 | Jun 06 01:56:55 PM PDT 24 | 31014478 ps | ||
| T43 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.448401934 | Jun 06 01:57:01 PM PDT 24 | Jun 06 01:57:03 PM PDT 24 | 28379774 ps | ||
| T37 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1360843165 | Jun 06 01:57:13 PM PDT 24 | Jun 06 01:57:14 PM PDT 24 | 29913245 ps | ||
| T44 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3601688199 | Jun 06 01:57:04 PM PDT 24 | Jun 06 01:57:05 PM PDT 24 | 27857849 ps | ||
| T15 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1930221973 | Jun 06 01:56:59 PM PDT 24 | Jun 06 01:57:01 PM PDT 24 | 29973445 ps | ||
| T47 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3459897199 | Jun 06 01:56:57 PM PDT 24 | Jun 06 01:56:59 PM PDT 24 | 28911119 ps | ||
| T48 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.115963900 | Jun 06 01:57:09 PM PDT 24 | Jun 06 01:57:11 PM PDT 24 | 30213570 ps | ||
| T49 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.23681734 | Jun 06 01:57:09 PM PDT 24 | Jun 06 01:57:11 PM PDT 24 | 32212920 ps | ||
| T5 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2423618435 | Jun 06 01:57:09 PM PDT 24 | Jun 06 01:57:11 PM PDT 24 | 30872051 ps | ||
| T50 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1360194688 | Jun 06 01:57:04 PM PDT 24 | Jun 06 01:57:05 PM PDT 24 | 30306189 ps | ||
| T51 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.862672274 | Jun 06 01:57:02 PM PDT 24 | Jun 06 01:57:04 PM PDT 24 | 29485802 ps | ||
| T52 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.390356502 | Jun 06 01:56:54 PM PDT 24 | Jun 06 01:56:55 PM PDT 24 | 31059802 ps | ||
| T53 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2835351604 | Jun 06 01:57:07 PM PDT 24 | Jun 06 01:57:08 PM PDT 24 | 28743322 ps | ||
| T54 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1554295830 | Jun 06 01:56:59 PM PDT 24 | Jun 06 01:57:01 PM PDT 24 | 30639215 ps | ||
| T31 | /workspace/coverage/sync_alert/7.prim_sync_alert.2343983799 | Jun 06 02:13:19 PM PDT 24 | Jun 06 02:13:22 PM PDT 24 | 10118033 ps | ||
| T23 | /workspace/coverage/sync_alert/15.prim_sync_alert.3403735720 | Jun 06 02:13:14 PM PDT 24 | Jun 06 02:13:17 PM PDT 24 | 9356006 ps | ||
| T32 | /workspace/coverage/sync_alert/11.prim_sync_alert.366826013 | Jun 06 02:13:19 PM PDT 24 | Jun 06 02:13:22 PM PDT 24 | 8538185 ps | ||
| T33 | /workspace/coverage/sync_alert/13.prim_sync_alert.217977196 | Jun 06 02:13:14 PM PDT 24 | Jun 06 02:13:17 PM PDT 24 | 9685863 ps | ||
| T24 | /workspace/coverage/sync_alert/4.prim_sync_alert.495647361 | Jun 06 02:13:14 PM PDT 24 | Jun 06 02:13:17 PM PDT 24 | 9540817 ps | ||
| T25 | /workspace/coverage/sync_alert/8.prim_sync_alert.14015485 | Jun 06 02:13:17 PM PDT 24 | Jun 06 02:13:21 PM PDT 24 | 9555653 ps | ||
| T34 | /workspace/coverage/sync_alert/5.prim_sync_alert.2593448010 | Jun 06 02:13:16 PM PDT 24 | Jun 06 02:13:19 PM PDT 24 | 9078467 ps | ||
| T35 | /workspace/coverage/sync_alert/1.prim_sync_alert.1123327434 | Jun 06 02:13:13 PM PDT 24 | Jun 06 02:13:15 PM PDT 24 | 11013422 ps | ||
| T36 | /workspace/coverage/sync_alert/14.prim_sync_alert.1896760113 | Jun 06 02:13:14 PM PDT 24 | Jun 06 02:13:17 PM PDT 24 | 9725842 ps | ||
| T26 | /workspace/coverage/sync_alert/2.prim_sync_alert.2531340686 | Jun 06 02:13:11 PM PDT 24 | Jun 06 02:13:14 PM PDT 24 | 9459656 ps | ||
| T55 | /workspace/coverage/sync_alert/9.prim_sync_alert.1696529239 | Jun 06 02:13:15 PM PDT 24 | Jun 06 02:13:18 PM PDT 24 | 9599815 ps | ||
| T56 | /workspace/coverage/sync_alert/18.prim_sync_alert.1906632815 | Jun 06 02:13:13 PM PDT 24 | Jun 06 02:13:15 PM PDT 24 | 9163745 ps | ||
| T27 | /workspace/coverage/sync_alert/19.prim_sync_alert.3729084544 | Jun 06 02:13:16 PM PDT 24 | Jun 06 02:13:19 PM PDT 24 | 8511891 ps | ||
| T9 | /workspace/coverage/sync_alert/0.prim_sync_alert.2128917984 | Jun 06 02:13:13 PM PDT 24 | Jun 06 02:13:16 PM PDT 24 | 8502989 ps | ||
| T57 | /workspace/coverage/sync_alert/16.prim_sync_alert.21883210 | Jun 06 02:13:17 PM PDT 24 | Jun 06 02:13:21 PM PDT 24 | 9077571 ps | ||
| T28 | /workspace/coverage/sync_alert/3.prim_sync_alert.2605723588 | Jun 06 02:13:13 PM PDT 24 | Jun 06 02:13:15 PM PDT 24 | 8037069 ps | ||
| T29 | /workspace/coverage/sync_alert/17.prim_sync_alert.1866363693 | Jun 06 02:13:15 PM PDT 24 | Jun 06 02:13:18 PM PDT 24 | 9184341 ps | ||
| T10 | /workspace/coverage/sync_alert/10.prim_sync_alert.1525670236 | Jun 06 02:13:17 PM PDT 24 | Jun 06 02:13:21 PM PDT 24 | 8807283 ps | ||
| T30 | /workspace/coverage/sync_alert/6.prim_sync_alert.1087645516 | Jun 06 02:13:17 PM PDT 24 | Jun 06 02:13:21 PM PDT 24 | 8602112 ps | ||
| T58 | /workspace/coverage/sync_alert/12.prim_sync_alert.2782954298 | Jun 06 02:13:16 PM PDT 24 | Jun 06 02:13:20 PM PDT 24 | 8110643 ps | ||
| T59 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2573570981 | Jun 06 02:13:18 PM PDT 24 | Jun 06 02:13:22 PM PDT 24 | 27199130 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.694105923 | Jun 06 02:13:16 PM PDT 24 | Jun 06 02:13:20 PM PDT 24 | 26724018 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3536970662 | Jun 06 02:13:21 PM PDT 24 | Jun 06 02:13:24 PM PDT 24 | 27642959 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2242542631 | Jun 06 02:13:20 PM PDT 24 | Jun 06 02:13:22 PM PDT 24 | 29345459 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1455591329 | Jun 06 02:13:22 PM PDT 24 | Jun 06 02:13:24 PM PDT 24 | 27440170 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1756630866 | Jun 06 02:13:16 PM PDT 24 | Jun 06 02:13:19 PM PDT 24 | 26933034 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.93647271 | Jun 06 02:13:21 PM PDT 24 | Jun 06 02:13:23 PM PDT 24 | 27559240 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2759435125 | Jun 06 02:13:12 PM PDT 24 | Jun 06 02:13:15 PM PDT 24 | 25370279 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3314529837 | Jun 06 02:13:21 PM PDT 24 | Jun 06 02:13:24 PM PDT 24 | 28765230 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2487285066 | Jun 06 02:13:21 PM PDT 24 | Jun 06 02:13:23 PM PDT 24 | 25339857 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3442104827 | Jun 06 02:13:15 PM PDT 24 | Jun 06 02:13:17 PM PDT 24 | 27419767 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1491813816 | Jun 06 02:13:17 PM PDT 24 | Jun 06 02:13:21 PM PDT 24 | 27381997 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2952415023 | Jun 06 02:13:18 PM PDT 24 | Jun 06 02:13:21 PM PDT 24 | 25857243 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2318928555 | Jun 06 02:13:22 PM PDT 24 | Jun 06 02:13:24 PM PDT 24 | 26737191 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1724321349 | Jun 06 02:13:16 PM PDT 24 | Jun 06 02:13:19 PM PDT 24 | 26650009 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2361491615 | Jun 06 02:13:16 PM PDT 24 | Jun 06 02:13:19 PM PDT 24 | 29021766 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.968798367 | Jun 06 02:13:20 PM PDT 24 | Jun 06 02:13:23 PM PDT 24 | 27357317 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.609236426 | Jun 06 02:13:13 PM PDT 24 | Jun 06 02:13:16 PM PDT 24 | 27461340 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3097325319 | Jun 06 02:13:18 PM PDT 24 | Jun 06 02:13:22 PM PDT 24 | 27562943 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.728301152 | Jun 06 02:13:14 PM PDT 24 | Jun 06 02:13:17 PM PDT 24 | 26817257 ps |
| Test location | /workspace/coverage/default/18.prim_async_alert.2645371112 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11594672 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 01:24:24 PM PDT 24 |
| Finished | Jun 06 01:24:26 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-3340f9a4-3d36-4896-9cf3-71c50ffeb1d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2645371112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2645371112 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.1123327434 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11013422 ps |
| CPU time | 0.37 seconds |
| Started | Jun 06 02:13:13 PM PDT 24 |
| Finished | Jun 06 02:13:15 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-f02a6e36-7027-4dd2-ae61-645e4e6d6fd9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1123327434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1123327434 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1579231800 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29129890 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:57:06 PM PDT 24 |
| Finished | Jun 06 01:57:07 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-2cf0fb2e-066e-49b9-a36c-1d3a88cfb36c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1579231800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1579231800 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3652567806 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10586591 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:24:13 PM PDT 24 |
| Finished | Jun 06 01:24:14 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-5ac80a7a-1b49-4cfb-b66f-9315338ae6a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652567806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3652567806 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3268368304 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 29485788 ps |
| CPU time | 0.42 seconds |
| Started | Jun 06 01:57:15 PM PDT 24 |
| Finished | Jun 06 01:57:17 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-b6b3593c-90a2-4323-9ba8-e2c1a1760ced |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3268368304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3268368304 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.2128917984 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8502989 ps |
| CPU time | 0.43 seconds |
| Started | Jun 06 02:13:13 PM PDT 24 |
| Finished | Jun 06 02:13:16 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-a364cad9-f96d-4f61-842d-28f38381b972 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2128917984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2128917984 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.158670338 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10176522 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:24:28 PM PDT 24 |
| Finished | Jun 06 01:24:30 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-f09ea03f-6870-45f0-a642-593c1f98d7d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=158670338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.158670338 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.2434550041 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11534419 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:24:16 PM PDT 24 |
| Finished | Jun 06 01:24:18 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-156fb079-051a-44bb-80f0-c198b4d40b25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2434550041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2434550041 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.359405608 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11229195 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:24:12 PM PDT 24 |
| Finished | Jun 06 01:24:13 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-da231eed-faed-44e8-920d-d8560b07f447 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359405608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.359405608 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3129079147 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10425484 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 01:24:07 PM PDT 24 |
| Finished | Jun 06 01:24:09 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-6f572e3d-ccea-4df7-a457-90f319fac42c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3129079147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3129079147 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.719567557 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10785433 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:24:23 PM PDT 24 |
| Finished | Jun 06 01:24:25 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-9dff8f61-a177-4d71-9bdd-6354f037395e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=719567557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.719567557 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.2042783349 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11420314 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:24:11 PM PDT 24 |
| Finished | Jun 06 01:24:12 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-3c1d5ad6-88f1-49d1-ae1b-e8fef9c8f73f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2042783349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2042783349 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.830104748 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11381064 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:24:12 PM PDT 24 |
| Finished | Jun 06 01:24:13 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-b7aaef96-7ed8-4a34-9727-f20509683c46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=830104748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.830104748 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.3589077570 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10819656 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:24:21 PM PDT 24 |
| Finished | Jun 06 01:24:23 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-3416886e-21eb-496b-82aa-0128719767e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3589077570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3589077570 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.540200589 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10947895 ps |
| CPU time | 0.37 seconds |
| Started | Jun 06 01:24:15 PM PDT 24 |
| Finished | Jun 06 01:24:16 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-b4801157-d1b6-4edc-abec-9a09eacd5568 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540200589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.540200589 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.1866162231 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10824200 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:24:03 PM PDT 24 |
| Finished | Jun 06 01:24:10 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-9e2cbeba-69c2-455e-9980-2bb1f19a867c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1866162231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1866162231 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.1020791784 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10704386 ps |
| CPU time | 0.37 seconds |
| Started | Jun 06 01:24:19 PM PDT 24 |
| Finished | Jun 06 01:24:20 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-b13afc13-4449-46ed-803e-0ad525e293dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020791784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1020791784 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.620453993 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12039288 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:24:05 PM PDT 24 |
| Finished | Jun 06 01:24:07 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-7532608d-c4bd-44e1-bad4-8a15e42c95d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620453993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.620453993 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.494927727 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10817085 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:24:01 PM PDT 24 |
| Finished | Jun 06 01:24:03 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-6927981a-3946-4d48-acbc-b749a8aa9e40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494927727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.494927727 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2019670081 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11542910 ps |
| CPU time | 0.42 seconds |
| Started | Jun 06 01:24:16 PM PDT 24 |
| Finished | Jun 06 01:24:17 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-0a5f56d6-1c59-491e-845a-685db38024ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2019670081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2019670081 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.1834890425 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10981304 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:24:16 PM PDT 24 |
| Finished | Jun 06 01:24:17 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-48f7f7e1-d09c-4dd7-9abe-2d54dd573924 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834890425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1834890425 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.1289187387 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10790520 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:23:59 PM PDT 24 |
| Finished | Jun 06 01:24:01 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-ba536849-f06e-4fd1-bc52-cb77e876b6af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1289187387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1289187387 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1887240820 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11469972 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:24:03 PM PDT 24 |
| Finished | Jun 06 01:24:06 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-1d277df7-0402-44ae-99ec-aa6fb04ced52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1887240820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1887240820 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.390356502 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 31059802 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:56:54 PM PDT 24 |
| Finished | Jun 06 01:56:55 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-6ba6ca80-7f43-46c7-ba5b-77d25e835b29 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=390356502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.390356502 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3914932469 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 31014478 ps |
| CPU time | 0.41 seconds |
| Started | Jun 06 01:56:54 PM PDT 24 |
| Finished | Jun 06 01:56:55 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-ddd5798e-b78d-4e68-a5ff-296605eb819e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3914932469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3914932469 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2835351604 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 28743322 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:57:07 PM PDT 24 |
| Finished | Jun 06 01:57:08 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-e6ce9b98-cb47-48b1-b0f3-5557b943b6a8 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2835351604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2835351604 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.419344890 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29784348 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:57:01 PM PDT 24 |
| Finished | Jun 06 01:57:03 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-a98f43b3-620e-43a3-b6f1-e850d243d2ab |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=419344890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.419344890 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1554295830 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30639215 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:56:59 PM PDT 24 |
| Finished | Jun 06 01:57:01 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-cbf590ad-32ee-4ff9-9a82-2480403d4743 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1554295830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1554295830 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3459897199 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 28911119 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:56:57 PM PDT 24 |
| Finished | Jun 06 01:56:59 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-048620e3-08ec-441a-ae05-6dd252b7b6b0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3459897199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3459897199 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1843683481 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 30419342 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:56:59 PM PDT 24 |
| Finished | Jun 06 01:57:00 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-164ea822-f8ba-4138-9c10-59218288707b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1843683481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1843683481 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1930221973 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 29973445 ps |
| CPU time | 0.43 seconds |
| Started | Jun 06 01:56:59 PM PDT 24 |
| Finished | Jun 06 01:57:01 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-92a14ac8-d3d5-4bd4-ad91-14ac7d320841 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1930221973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1930221973 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2423618435 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30872051 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:57:09 PM PDT 24 |
| Finished | Jun 06 01:57:11 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-dc4a184e-9edd-4a2a-9598-13f38a077045 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2423618435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2423618435 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.862672274 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29485802 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:57:02 PM PDT 24 |
| Finished | Jun 06 01:57:04 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-22b733b1-6bdd-4254-9c57-11a3dbc0ec1a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=862672274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.862672274 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.23681734 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 32212920 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:57:09 PM PDT 24 |
| Finished | Jun 06 01:57:11 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-bda831ed-b366-4e6e-a12c-10f4fd140f64 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=23681734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.23681734 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1708525612 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 30328542 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:57:11 PM PDT 24 |
| Finished | Jun 06 01:57:13 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-3d09c13b-9618-4afb-861d-f70874a25dc4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1708525612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1708525612 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1360843165 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 29913245 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 01:57:13 PM PDT 24 |
| Finished | Jun 06 01:57:14 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-95e6efdb-e38b-4206-b27a-50ee4cd2d231 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1360843165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1360843165 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3601688199 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 27857849 ps |
| CPU time | 0.42 seconds |
| Started | Jun 06 01:57:04 PM PDT 24 |
| Finished | Jun 06 01:57:05 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-2a23d0be-c671-48bd-8fbf-70999d36143a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3601688199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3601688199 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1360194688 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30306189 ps |
| CPU time | 0.41 seconds |
| Started | Jun 06 01:57:04 PM PDT 24 |
| Finished | Jun 06 01:57:05 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-551a5f03-9ea4-45fd-8066-4507b5e2e61f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1360194688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1360194688 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.115963900 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30213570 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:57:09 PM PDT 24 |
| Finished | Jun 06 01:57:11 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-0037abea-690a-4fa3-88f9-c1f722e9480f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=115963900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.115963900 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.448401934 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 28379774 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 01:57:01 PM PDT 24 |
| Finished | Jun 06 01:57:03 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-c50a63e0-e891-43cf-acb2-0f2165ddcb79 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=448401934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.448401934 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.1525670236 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8807283 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:17 PM PDT 24 |
| Finished | Jun 06 02:13:21 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-9e7c2b1e-6a63-4297-a6d8-63b2d148d0de |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1525670236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1525670236 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.366826013 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8538185 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:19 PM PDT 24 |
| Finished | Jun 06 02:13:22 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-2826491f-69df-4bae-8184-3ae6d4b77a34 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=366826013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.366826013 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.2782954298 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8110643 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:16 PM PDT 24 |
| Finished | Jun 06 02:13:20 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-d7da1ce9-7f39-4a3b-b5b0-3f667c232e77 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2782954298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2782954298 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.217977196 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9685863 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 02:13:14 PM PDT 24 |
| Finished | Jun 06 02:13:17 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-4ae5b274-1a83-41d4-abaf-e8e20efe26cc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=217977196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.217977196 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1896760113 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9725842 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:14 PM PDT 24 |
| Finished | Jun 06 02:13:17 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-dcaf3695-f22d-486e-b05d-9373d1f8f7dc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1896760113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1896760113 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3403735720 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9356006 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:14 PM PDT 24 |
| Finished | Jun 06 02:13:17 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-93b4b67f-c8e4-4d20-8390-f863979cd24d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3403735720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3403735720 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.21883210 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9077571 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:17 PM PDT 24 |
| Finished | Jun 06 02:13:21 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-aaf9a0bd-b2b8-4eeb-bc10-92bda5d6e5b6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=21883210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.21883210 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.1866363693 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9184341 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:15 PM PDT 24 |
| Finished | Jun 06 02:13:18 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-25e60465-8a9d-4a84-a53a-a57edd3dac34 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1866363693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1866363693 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.1906632815 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9163745 ps |
| CPU time | 0.37 seconds |
| Started | Jun 06 02:13:13 PM PDT 24 |
| Finished | Jun 06 02:13:15 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-7b653975-e6ac-4ebe-b151-2ac8f2a70fee |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1906632815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1906632815 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.3729084544 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8511891 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:16 PM PDT 24 |
| Finished | Jun 06 02:13:19 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-5bb668fd-3c3a-42d8-8d24-4937497e3301 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3729084544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3729084544 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2531340686 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9459656 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:11 PM PDT 24 |
| Finished | Jun 06 02:13:14 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-045b8f98-1aa5-4e2b-be46-0b93b071e2ab |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2531340686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2531340686 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.2605723588 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8037069 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:13 PM PDT 24 |
| Finished | Jun 06 02:13:15 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-f5e176dc-950e-4396-b280-9ffe7b2cdcb6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2605723588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2605723588 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.495647361 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9540817 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 02:13:14 PM PDT 24 |
| Finished | Jun 06 02:13:17 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-8d2431ff-3e0c-4f95-aef9-1f167b25097f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=495647361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.495647361 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.2593448010 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9078467 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:16 PM PDT 24 |
| Finished | Jun 06 02:13:19 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-2b7a866a-1861-4190-a676-3de1c6700a2e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2593448010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2593448010 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1087645516 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8602112 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:17 PM PDT 24 |
| Finished | Jun 06 02:13:21 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-a248bc0a-93ee-4a72-bd3a-0f8c0cd1f9bb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1087645516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1087645516 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.2343983799 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10118033 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:19 PM PDT 24 |
| Finished | Jun 06 02:13:22 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-dbbfde5c-20fd-4057-943d-ac953f716350 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2343983799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2343983799 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.14015485 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9555653 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 02:13:17 PM PDT 24 |
| Finished | Jun 06 02:13:21 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-1f14d8fd-3358-4aa5-85a7-76733a1a95ce |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=14015485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.14015485 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1696529239 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9599815 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:15 PM PDT 24 |
| Finished | Jun 06 02:13:18 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-cac9ab51-26dd-4fbd-ba2c-cfdb48f2f674 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1696529239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1696529239 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2573570981 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 27199130 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 02:13:18 PM PDT 24 |
| Finished | Jun 06 02:13:22 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-b8324d68-eed6-4f99-b1e8-f63406dfae04 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2573570981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2573570981 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2759435125 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 25370279 ps |
| CPU time | 0.38 seconds |
| Started | Jun 06 02:13:12 PM PDT 24 |
| Finished | Jun 06 02:13:15 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-9ae197e0-11fb-414d-b3c4-f1899d7662da |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2759435125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2759435125 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3097325319 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27562943 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:18 PM PDT 24 |
| Finished | Jun 06 02:13:22 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-81e2a460-8d98-4b89-8524-ef5d53b68bcf |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3097325319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3097325319 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3442104827 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27419767 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:15 PM PDT 24 |
| Finished | Jun 06 02:13:17 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-0a41be2b-bbb8-4827-94f6-250083ac4155 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3442104827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3442104827 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2318928555 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26737191 ps |
| CPU time | 0.41 seconds |
| Started | Jun 06 02:13:22 PM PDT 24 |
| Finished | Jun 06 02:13:24 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-a30386ff-5dbd-46d5-98b0-753ccf9e82c4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2318928555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2318928555 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2361491615 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 29021766 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 02:13:16 PM PDT 24 |
| Finished | Jun 06 02:13:19 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-b46d674a-1e57-4715-90f1-a5e2af547295 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2361491615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2361491615 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1491813816 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27381997 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 02:13:17 PM PDT 24 |
| Finished | Jun 06 02:13:21 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-9e7b3c8b-68c8-422e-82c1-06cf3a89aeaf |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1491813816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1491813816 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1756630866 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26933034 ps |
| CPU time | 0.42 seconds |
| Started | Jun 06 02:13:16 PM PDT 24 |
| Finished | Jun 06 02:13:19 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-9fecf7d1-a67f-4c15-a00d-32edcda2be74 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1756630866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1756630866 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.93647271 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27559240 ps |
| CPU time | 0.42 seconds |
| Started | Jun 06 02:13:21 PM PDT 24 |
| Finished | Jun 06 02:13:23 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-9e114916-bb05-4874-87d6-c50a7a8e3d0d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=93647271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.93647271 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2242542631 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 29345459 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:20 PM PDT 24 |
| Finished | Jun 06 02:13:22 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-1074ddb0-d563-4baf-90d8-56badd5dff58 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2242542631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2242542631 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.728301152 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26817257 ps |
| CPU time | 0.41 seconds |
| Started | Jun 06 02:13:14 PM PDT 24 |
| Finished | Jun 06 02:13:17 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-147dd1f7-c40b-428a-9aae-af547591540e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=728301152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.728301152 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1455591329 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27440170 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 02:13:22 PM PDT 24 |
| Finished | Jun 06 02:13:24 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-1efccb4b-5830-45b9-b0ee-0c4a0d2d86af |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1455591329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1455591329 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2952415023 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 25857243 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:18 PM PDT 24 |
| Finished | Jun 06 02:13:21 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-04f2535f-aaee-4f56-941c-63d4a1b9372b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2952415023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2952415023 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.609236426 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27461340 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:13 PM PDT 24 |
| Finished | Jun 06 02:13:16 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-428eb1e4-0eba-4740-869f-c694d0ed0d4e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=609236426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.609236426 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3314529837 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28765230 ps |
| CPU time | 0.42 seconds |
| Started | Jun 06 02:13:21 PM PDT 24 |
| Finished | Jun 06 02:13:24 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-53168290-3f55-49c0-bdf5-a9c052209c57 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3314529837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3314529837 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.968798367 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27357317 ps |
| CPU time | 0.39 seconds |
| Started | Jun 06 02:13:20 PM PDT 24 |
| Finished | Jun 06 02:13:23 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-30ac1d0f-007a-4468-84c1-18fa247554bb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=968798367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.968798367 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1724321349 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26650009 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 02:13:16 PM PDT 24 |
| Finished | Jun 06 02:13:19 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-22a2efcf-ba7c-4ba8-961b-1b797f157e2a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1724321349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1724321349 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2487285066 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 25339857 ps |
| CPU time | 0.4 seconds |
| Started | Jun 06 02:13:21 PM PDT 24 |
| Finished | Jun 06 02:13:23 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-b808d87a-6330-46f4-bb44-8ae410cb288f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2487285066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2487285066 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3536970662 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 27642959 ps |
| CPU time | 0.42 seconds |
| Started | Jun 06 02:13:21 PM PDT 24 |
| Finished | Jun 06 02:13:24 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-93de098b-7325-4429-9061-de3fbf31b4a5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3536970662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3536970662 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.694105923 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 26724018 ps |
| CPU time | 0.44 seconds |
| Started | Jun 06 02:13:16 PM PDT 24 |
| Finished | Jun 06 02:13:20 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-0e2fa9a1-4cfb-41bf-8275-a13d01f4416c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=694105923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.694105923 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |