Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/19.prim_async_alert.3043382739
91.80 3.13 100.00 0.00 93.75 0.00 100.00 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/12.prim_sync_alert.1771385475
93.90 2.11 100.00 0.00 95.83 2.08 100.00 0.00 85.71 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2126766265
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/0.prim_async_alert.3438244043
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.209450734

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.1749425134
/workspace/coverage/default/10.prim_async_alert.1885621569
/workspace/coverage/default/11.prim_async_alert.1710781074
/workspace/coverage/default/12.prim_async_alert.463623881
/workspace/coverage/default/13.prim_async_alert.3397347791
/workspace/coverage/default/14.prim_async_alert.81101122
/workspace/coverage/default/15.prim_async_alert.2720247823
/workspace/coverage/default/16.prim_async_alert.4077925228
/workspace/coverage/default/17.prim_async_alert.3974386446
/workspace/coverage/default/18.prim_async_alert.2659745701
/workspace/coverage/default/2.prim_async_alert.2267535359
/workspace/coverage/default/3.prim_async_alert.3248058324
/workspace/coverage/default/4.prim_async_alert.1194955074
/workspace/coverage/default/5.prim_async_alert.607350002
/workspace/coverage/default/6.prim_async_alert.214757874
/workspace/coverage/default/7.prim_async_alert.1735404021
/workspace/coverage/default/8.prim_async_alert.1852741078
/workspace/coverage/default/9.prim_async_alert.3731396031
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1989640371
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2120931232
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3167929332
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1911547692
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1356255064
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.486890622
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2975282030
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.719609766
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3472511708
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1725440644
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3017135523
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3171307854
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3890815263
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1415551299
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1419256381
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.854043562
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4075413103
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3126920667
/workspace/coverage/sync_alert/0.prim_sync_alert.916394754
/workspace/coverage/sync_alert/1.prim_sync_alert.2206372643
/workspace/coverage/sync_alert/10.prim_sync_alert.4252102265
/workspace/coverage/sync_alert/11.prim_sync_alert.1694199453
/workspace/coverage/sync_alert/13.prim_sync_alert.2257788275
/workspace/coverage/sync_alert/14.prim_sync_alert.471237376
/workspace/coverage/sync_alert/15.prim_sync_alert.695881763
/workspace/coverage/sync_alert/16.prim_sync_alert.1969012457
/workspace/coverage/sync_alert/17.prim_sync_alert.4056078806
/workspace/coverage/sync_alert/18.prim_sync_alert.3476341674
/workspace/coverage/sync_alert/19.prim_sync_alert.387156462
/workspace/coverage/sync_alert/2.prim_sync_alert.2789469689
/workspace/coverage/sync_alert/3.prim_sync_alert.688089527
/workspace/coverage/sync_alert/4.prim_sync_alert.3928653058
/workspace/coverage/sync_alert/5.prim_sync_alert.506610857
/workspace/coverage/sync_alert/6.prim_sync_alert.2181064325
/workspace/coverage/sync_alert/7.prim_sync_alert.2599010394
/workspace/coverage/sync_alert/8.prim_sync_alert.4080940308
/workspace/coverage/sync_alert/9.prim_sync_alert.1210061040
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3262005175
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1001012019
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1454759140
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1712203414
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3376767981
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.594242170
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3643975266
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.455553800
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1306360996
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3634668439
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3734284781
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2323048868
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1671213899
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3803978857
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2675678831
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.417598994
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3726699302
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3671889306
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4117333204



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/7.prim_async_alert.1735404021 Jun 07 07:49:14 PM PDT 24 Jun 07 07:49:15 PM PDT 24 12135667 ps
T2 /workspace/coverage/default/0.prim_async_alert.3438244043 Jun 07 07:49:09 PM PDT 24 Jun 07 07:49:10 PM PDT 24 11354062 ps
T3 /workspace/coverage/default/19.prim_async_alert.3043382739 Jun 07 07:49:23 PM PDT 24 Jun 07 07:49:25 PM PDT 24 12607883 ps
T9 /workspace/coverage/default/12.prim_async_alert.463623881 Jun 07 07:49:23 PM PDT 24 Jun 07 07:49:24 PM PDT 24 12253711 ps
T12 /workspace/coverage/default/2.prim_async_alert.2267535359 Jun 07 07:49:14 PM PDT 24 Jun 07 07:49:16 PM PDT 24 11431972 ps
T6 /workspace/coverage/default/18.prim_async_alert.2659745701 Jun 07 07:49:24 PM PDT 24 Jun 07 07:49:26 PM PDT 24 11501602 ps
T15 /workspace/coverage/default/4.prim_async_alert.1194955074 Jun 07 07:49:15 PM PDT 24 Jun 07 07:49:17 PM PDT 24 11538764 ps
T8 /workspace/coverage/default/11.prim_async_alert.1710781074 Jun 07 07:49:22 PM PDT 24 Jun 07 07:49:23 PM PDT 24 11078409 ps
T13 /workspace/coverage/default/1.prim_async_alert.1749425134 Jun 07 07:49:16 PM PDT 24 Jun 07 07:49:17 PM PDT 24 10815899 ps
T16 /workspace/coverage/default/6.prim_async_alert.214757874 Jun 07 07:49:14 PM PDT 24 Jun 07 07:49:15 PM PDT 24 11450909 ps
T17 /workspace/coverage/default/5.prim_async_alert.607350002 Jun 07 07:49:14 PM PDT 24 Jun 07 07:49:15 PM PDT 24 10990904 ps
T21 /workspace/coverage/default/16.prim_async_alert.4077925228 Jun 07 07:49:23 PM PDT 24 Jun 07 07:49:25 PM PDT 24 10893289 ps
T14 /workspace/coverage/default/14.prim_async_alert.81101122 Jun 07 07:49:24 PM PDT 24 Jun 07 07:49:26 PM PDT 24 10787231 ps
T10 /workspace/coverage/default/15.prim_async_alert.2720247823 Jun 07 07:49:23 PM PDT 24 Jun 07 07:49:25 PM PDT 24 12107533 ps
T11 /workspace/coverage/default/17.prim_async_alert.3974386446 Jun 07 07:49:23 PM PDT 24 Jun 07 07:49:25 PM PDT 24 12041457 ps
T18 /workspace/coverage/default/10.prim_async_alert.1885621569 Jun 07 07:49:22 PM PDT 24 Jun 07 07:49:23 PM PDT 24 11562148 ps
T19 /workspace/coverage/default/3.prim_async_alert.3248058324 Jun 07 07:49:15 PM PDT 24 Jun 07 07:49:17 PM PDT 24 11580500 ps
T20 /workspace/coverage/default/13.prim_async_alert.3397347791 Jun 07 07:49:23 PM PDT 24 Jun 07 07:49:24 PM PDT 24 11234179 ps
T7 /workspace/coverage/default/8.prim_async_alert.1852741078 Jun 07 07:49:24 PM PDT 24 Jun 07 07:49:25 PM PDT 24 10652378 ps
T49 /workspace/coverage/default/9.prim_async_alert.3731396031 Jun 07 07:49:23 PM PDT 24 Jun 07 07:49:25 PM PDT 24 10789315 ps
T39 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.719609766 Jun 07 06:06:09 PM PDT 24 Jun 07 06:06:10 PM PDT 24 28325950 ps
T40 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2126766265 Jun 07 06:06:15 PM PDT 24 Jun 07 06:06:15 PM PDT 24 31953765 ps
T41 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1725440644 Jun 07 06:06:13 PM PDT 24 Jun 07 06:06:14 PM PDT 24 29801484 ps
T42 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3472511708 Jun 07 06:06:36 PM PDT 24 Jun 07 06:06:36 PM PDT 24 29852496 ps
T43 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1911547692 Jun 07 06:06:14 PM PDT 24 Jun 07 06:06:14 PM PDT 24 30346860 ps
T44 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1356255064 Jun 07 06:06:14 PM PDT 24 Jun 07 06:06:15 PM PDT 24 29359322 ps
T45 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2120931232 Jun 07 06:06:24 PM PDT 24 Jun 07 06:06:25 PM PDT 24 30515645 ps
T46 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3890815263 Jun 07 06:06:12 PM PDT 24 Jun 07 06:06:13 PM PDT 24 29455684 ps
T47 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3167929332 Jun 07 06:06:18 PM PDT 24 Jun 07 06:06:18 PM PDT 24 30078745 ps
T48 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3171307854 Jun 07 06:06:35 PM PDT 24 Jun 07 06:06:36 PM PDT 24 30508588 ps
T50 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1989640371 Jun 07 06:06:52 PM PDT 24 Jun 07 06:06:52 PM PDT 24 30190347 ps
T51 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.486890622 Jun 07 06:06:12 PM PDT 24 Jun 07 06:06:12 PM PDT 24 31673751 ps
T52 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1415551299 Jun 07 06:06:21 PM PDT 24 Jun 07 06:06:22 PM PDT 24 30884648 ps
T53 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.854043562 Jun 07 06:06:10 PM PDT 24 Jun 07 06:06:11 PM PDT 24 29513826 ps
T54 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4075413103 Jun 07 06:06:13 PM PDT 24 Jun 07 06:06:14 PM PDT 24 28838433 ps
T55 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3126920667 Jun 07 06:06:06 PM PDT 24 Jun 07 06:06:06 PM PDT 24 31793943 ps
T56 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1419256381 Jun 07 06:06:22 PM PDT 24 Jun 07 06:06:23 PM PDT 24 30487570 ps
T57 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2975282030 Jun 07 06:06:13 PM PDT 24 Jun 07 06:06:13 PM PDT 24 30588143 ps
T58 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3017135523 Jun 07 06:06:11 PM PDT 24 Jun 07 06:06:12 PM PDT 24 30323943 ps
T31 /workspace/coverage/sync_alert/15.prim_sync_alert.695881763 Jun 07 07:49:38 PM PDT 24 Jun 07 07:49:40 PM PDT 24 8684617 ps
T32 /workspace/coverage/sync_alert/8.prim_sync_alert.4080940308 Jun 07 07:49:30 PM PDT 24 Jun 07 07:49:32 PM PDT 24 9069430 ps
T33 /workspace/coverage/sync_alert/19.prim_sync_alert.387156462 Jun 07 07:49:38 PM PDT 24 Jun 07 07:49:39 PM PDT 24 8860555 ps
T34 /workspace/coverage/sync_alert/9.prim_sync_alert.1210061040 Jun 07 07:49:30 PM PDT 24 Jun 07 07:49:31 PM PDT 24 10015649 ps
T35 /workspace/coverage/sync_alert/6.prim_sync_alert.2181064325 Jun 07 07:49:33 PM PDT 24 Jun 07 07:49:34 PM PDT 24 7909289 ps
T22 /workspace/coverage/sync_alert/3.prim_sync_alert.688089527 Jun 07 07:49:31 PM PDT 24 Jun 07 07:49:33 PM PDT 24 10766116 ps
T36 /workspace/coverage/sync_alert/13.prim_sync_alert.2257788275 Jun 07 07:49:31 PM PDT 24 Jun 07 07:49:32 PM PDT 24 9194389 ps
T37 /workspace/coverage/sync_alert/12.prim_sync_alert.1771385475 Jun 07 07:49:30 PM PDT 24 Jun 07 07:49:31 PM PDT 24 9200224 ps
T38 /workspace/coverage/sync_alert/5.prim_sync_alert.506610857 Jun 07 07:49:31 PM PDT 24 Jun 07 07:49:32 PM PDT 24 8716836 ps
T23 /workspace/coverage/sync_alert/2.prim_sync_alert.2789469689 Jun 07 07:49:31 PM PDT 24 Jun 07 07:49:33 PM PDT 24 9054873 ps
T59 /workspace/coverage/sync_alert/4.prim_sync_alert.3928653058 Jun 07 07:49:29 PM PDT 24 Jun 07 07:49:31 PM PDT 24 9198007 ps
T24 /workspace/coverage/sync_alert/17.prim_sync_alert.4056078806 Jun 07 07:49:38 PM PDT 24 Jun 07 07:49:39 PM PDT 24 8129274 ps
T25 /workspace/coverage/sync_alert/0.prim_sync_alert.916394754 Jun 07 07:49:24 PM PDT 24 Jun 07 07:49:26 PM PDT 24 8692130 ps
T26 /workspace/coverage/sync_alert/1.prim_sync_alert.2206372643 Jun 07 07:49:22 PM PDT 24 Jun 07 07:49:24 PM PDT 24 9271342 ps
T60 /workspace/coverage/sync_alert/14.prim_sync_alert.471237376 Jun 07 07:49:30 PM PDT 24 Jun 07 07:49:32 PM PDT 24 9649447 ps
T61 /workspace/coverage/sync_alert/11.prim_sync_alert.1694199453 Jun 07 07:49:31 PM PDT 24 Jun 07 07:49:32 PM PDT 24 8044180 ps
T27 /workspace/coverage/sync_alert/10.prim_sync_alert.4252102265 Jun 07 07:49:30 PM PDT 24 Jun 07 07:49:31 PM PDT 24 8561257 ps
T28 /workspace/coverage/sync_alert/7.prim_sync_alert.2599010394 Jun 07 07:49:31 PM PDT 24 Jun 07 07:49:33 PM PDT 24 9486090 ps
T62 /workspace/coverage/sync_alert/18.prim_sync_alert.3476341674 Jun 07 07:49:37 PM PDT 24 Jun 07 07:49:38 PM PDT 24 8386507 ps
T29 /workspace/coverage/sync_alert/16.prim_sync_alert.1969012457 Jun 07 07:49:36 PM PDT 24 Jun 07 07:49:37 PM PDT 24 8725143 ps
T63 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1001012019 Jun 07 06:08:20 PM PDT 24 Jun 07 06:08:21 PM PDT 24 26353101 ps
T30 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3262005175 Jun 07 06:08:30 PM PDT 24 Jun 07 06:08:31 PM PDT 24 26931208 ps
T64 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3734284781 Jun 07 06:08:20 PM PDT 24 Jun 07 06:08:21 PM PDT 24 26109018 ps
T65 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1306360996 Jun 07 06:08:35 PM PDT 24 Jun 07 06:08:35 PM PDT 24 28230360 ps
T66 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2323048868 Jun 07 06:08:06 PM PDT 24 Jun 07 06:08:06 PM PDT 24 27606749 ps
T67 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1454759140 Jun 07 06:08:28 PM PDT 24 Jun 07 06:08:29 PM PDT 24 28534294 ps
T68 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1712203414 Jun 07 06:08:47 PM PDT 24 Jun 07 06:08:48 PM PDT 24 24961782 ps
T69 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3671889306 Jun 07 06:08:48 PM PDT 24 Jun 07 06:08:49 PM PDT 24 27567789 ps
T4 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1671213899 Jun 07 06:08:25 PM PDT 24 Jun 07 06:08:25 PM PDT 24 26081635 ps
T70 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.455553800 Jun 07 06:08:04 PM PDT 24 Jun 07 06:08:05 PM PDT 24 25698466 ps
T71 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3643975266 Jun 07 06:08:28 PM PDT 24 Jun 07 06:08:29 PM PDT 24 26744356 ps
T72 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.594242170 Jun 07 06:08:18 PM PDT 24 Jun 07 06:08:19 PM PDT 24 26211189 ps
T73 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2675678831 Jun 07 06:08:36 PM PDT 24 Jun 07 06:08:36 PM PDT 24 28501249 ps
T74 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3726699302 Jun 07 06:08:18 PM PDT 24 Jun 07 06:08:19 PM PDT 24 27793340 ps
T75 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3803978857 Jun 07 06:08:30 PM PDT 24 Jun 07 06:08:30 PM PDT 24 28625343 ps
T76 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.417598994 Jun 07 06:08:31 PM PDT 24 Jun 07 06:08:31 PM PDT 24 29991310 ps
T77 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4117333204 Jun 07 06:08:05 PM PDT 24 Jun 07 06:08:06 PM PDT 24 27137826 ps
T5 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.209450734 Jun 07 06:08:24 PM PDT 24 Jun 07 06:08:25 PM PDT 24 27764171 ps
T78 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3634668439 Jun 07 06:08:01 PM PDT 24 Jun 07 06:08:01 PM PDT 24 28760776 ps
T79 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3376767981 Jun 07 06:08:33 PM PDT 24 Jun 07 06:08:33 PM PDT 24 28066104 ps

Test location /workspace/coverage/default/19.prim_async_alert.3043382739
Short name T3
Test name
Test status
Simulation time 12607883 ps
CPU time 0.4 seconds
Started Jun 07 07:49:23 PM PDT 24
Finished Jun 07 07:49:25 PM PDT 24
Peak memory 145816 kb
Host smart-f4cad12f-cd63-4221-81ce-049f8e4fe7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043382739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3043382739
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1771385475
Short name T37
Test name
Test status
Simulation time 9200224 ps
CPU time 0.39 seconds
Started Jun 07 07:49:30 PM PDT 24
Finished Jun 07 07:49:31 PM PDT 24
Peak memory 145584 kb
Host smart-8a3bbd70-699f-4ae1-8317-c5810dade4f7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1771385475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1771385475
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2126766265
Short name T40
Test name
Test status
Simulation time 31953765 ps
CPU time 0.39 seconds
Started Jun 07 06:06:15 PM PDT 24
Finished Jun 07 06:06:15 PM PDT 24
Peak memory 145452 kb
Host smart-1dc96369-18ed-4c8d-bca3-de65a8255153
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2126766265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2126766265
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3438244043
Short name T2
Test name
Test status
Simulation time 11354062 ps
CPU time 0.38 seconds
Started Jun 07 07:49:09 PM PDT 24
Finished Jun 07 07:49:10 PM PDT 24
Peak memory 145784 kb
Host smart-a6a816e4-d276-4f7f-862d-ea39d3c89d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438244043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3438244043
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.209450734
Short name T5
Test name
Test status
Simulation time 27764171 ps
CPU time 0.4 seconds
Started Jun 07 06:08:24 PM PDT 24
Finished Jun 07 06:08:25 PM PDT 24
Peak memory 145336 kb
Host smart-2a863d9f-b52f-409b-b560-00a48b27d844
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=209450734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.209450734
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1749425134
Short name T13
Test name
Test status
Simulation time 10815899 ps
CPU time 0.39 seconds
Started Jun 07 07:49:16 PM PDT 24
Finished Jun 07 07:49:17 PM PDT 24
Peak memory 145804 kb
Host smart-bbee6158-819b-4392-89a7-76152481a6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749425134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1749425134
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1885621569
Short name T18
Test name
Test status
Simulation time 11562148 ps
CPU time 0.39 seconds
Started Jun 07 07:49:22 PM PDT 24
Finished Jun 07 07:49:23 PM PDT 24
Peak memory 145796 kb
Host smart-be1d95fe-416c-445c-982c-303ca03f0b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885621569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1885621569
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1710781074
Short name T8
Test name
Test status
Simulation time 11078409 ps
CPU time 0.38 seconds
Started Jun 07 07:49:22 PM PDT 24
Finished Jun 07 07:49:23 PM PDT 24
Peak memory 145744 kb
Host smart-0c72a80d-7d8f-4a85-961c-c78d837303d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710781074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1710781074
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.463623881
Short name T9
Test name
Test status
Simulation time 12253711 ps
CPU time 0.4 seconds
Started Jun 07 07:49:23 PM PDT 24
Finished Jun 07 07:49:24 PM PDT 24
Peak memory 145796 kb
Host smart-d1595bad-7f20-4a2f-9374-7a24a308fe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463623881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.463623881
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3397347791
Short name T20
Test name
Test status
Simulation time 11234179 ps
CPU time 0.4 seconds
Started Jun 07 07:49:23 PM PDT 24
Finished Jun 07 07:49:24 PM PDT 24
Peak memory 145800 kb
Host smart-84942249-25cb-4f0f-910e-bdf623f64838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397347791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3397347791
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.81101122
Short name T14
Test name
Test status
Simulation time 10787231 ps
CPU time 0.39 seconds
Started Jun 07 07:49:24 PM PDT 24
Finished Jun 07 07:49:26 PM PDT 24
Peak memory 145808 kb
Host smart-997769bd-cb11-4ee5-a504-c17fd65634c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81101122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.81101122
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.2720247823
Short name T10
Test name
Test status
Simulation time 12107533 ps
CPU time 0.4 seconds
Started Jun 07 07:49:23 PM PDT 24
Finished Jun 07 07:49:25 PM PDT 24
Peak memory 145764 kb
Host smart-df9f3d6f-0fd9-4c84-8299-6d7330e66a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720247823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2720247823
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.4077925228
Short name T21
Test name
Test status
Simulation time 10893289 ps
CPU time 0.39 seconds
Started Jun 07 07:49:23 PM PDT 24
Finished Jun 07 07:49:25 PM PDT 24
Peak memory 145828 kb
Host smart-06ba4b6e-c402-4de9-be0e-d60822cc12e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077925228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.4077925228
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3974386446
Short name T11
Test name
Test status
Simulation time 12041457 ps
CPU time 0.38 seconds
Started Jun 07 07:49:23 PM PDT 24
Finished Jun 07 07:49:25 PM PDT 24
Peak memory 145804 kb
Host smart-048b8ac1-03c8-4996-85ac-b78db8530e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974386446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3974386446
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.2659745701
Short name T6
Test name
Test status
Simulation time 11501602 ps
CPU time 0.38 seconds
Started Jun 07 07:49:24 PM PDT 24
Finished Jun 07 07:49:26 PM PDT 24
Peak memory 145740 kb
Host smart-05623fc5-0389-4e42-90b4-fa6dc6720421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659745701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2659745701
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2267535359
Short name T12
Test name
Test status
Simulation time 11431972 ps
CPU time 0.39 seconds
Started Jun 07 07:49:14 PM PDT 24
Finished Jun 07 07:49:16 PM PDT 24
Peak memory 145796 kb
Host smart-8297b9c2-2751-45b3-8b69-765a1e284f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267535359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2267535359
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3248058324
Short name T19
Test name
Test status
Simulation time 11580500 ps
CPU time 0.4 seconds
Started Jun 07 07:49:15 PM PDT 24
Finished Jun 07 07:49:17 PM PDT 24
Peak memory 145804 kb
Host smart-71eeda15-48c6-43ad-aad5-ffe5874f2f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248058324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3248058324
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1194955074
Short name T15
Test name
Test status
Simulation time 11538764 ps
CPU time 0.38 seconds
Started Jun 07 07:49:15 PM PDT 24
Finished Jun 07 07:49:17 PM PDT 24
Peak memory 145808 kb
Host smart-7856c005-a36d-4ce5-b09c-f81d12112ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194955074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1194955074
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.607350002
Short name T17
Test name
Test status
Simulation time 10990904 ps
CPU time 0.39 seconds
Started Jun 07 07:49:14 PM PDT 24
Finished Jun 07 07:49:15 PM PDT 24
Peak memory 145732 kb
Host smart-d661a677-e72b-4907-95de-fcc707a1a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607350002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.607350002
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.214757874
Short name T16
Test name
Test status
Simulation time 11450909 ps
CPU time 0.39 seconds
Started Jun 07 07:49:14 PM PDT 24
Finished Jun 07 07:49:15 PM PDT 24
Peak memory 145804 kb
Host smart-cfb09a20-9957-4c95-9cfb-cbdf775d740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214757874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.214757874
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1735404021
Short name T1
Test name
Test status
Simulation time 12135667 ps
CPU time 0.39 seconds
Started Jun 07 07:49:14 PM PDT 24
Finished Jun 07 07:49:15 PM PDT 24
Peak memory 145748 kb
Host smart-8f9772af-9fdc-43b2-9e10-3fc38804624f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735404021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1735404021
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1852741078
Short name T7
Test name
Test status
Simulation time 10652378 ps
CPU time 0.38 seconds
Started Jun 07 07:49:24 PM PDT 24
Finished Jun 07 07:49:25 PM PDT 24
Peak memory 145732 kb
Host smart-2fcca175-431e-4417-b065-afd9b2bd94ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852741078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1852741078
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3731396031
Short name T49
Test name
Test status
Simulation time 10789315 ps
CPU time 0.39 seconds
Started Jun 07 07:49:23 PM PDT 24
Finished Jun 07 07:49:25 PM PDT 24
Peak memory 145784 kb
Host smart-c996ab6e-d397-49b4-aa21-1d455dfa0c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731396031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3731396031
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1989640371
Short name T50
Test name
Test status
Simulation time 30190347 ps
CPU time 0.41 seconds
Started Jun 07 06:06:52 PM PDT 24
Finished Jun 07 06:06:52 PM PDT 24
Peak memory 145160 kb
Host smart-1c392f4f-513a-446e-a6aa-0d5f0f68dade
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1989640371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1989640371
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2120931232
Short name T45
Test name
Test status
Simulation time 30515645 ps
CPU time 0.4 seconds
Started Jun 07 06:06:24 PM PDT 24
Finished Jun 07 06:06:25 PM PDT 24
Peak memory 145156 kb
Host smart-e3bedf2a-19e9-4208-a196-ba1b268e05bb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2120931232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2120931232
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3167929332
Short name T47
Test name
Test status
Simulation time 30078745 ps
CPU time 0.4 seconds
Started Jun 07 06:06:18 PM PDT 24
Finished Jun 07 06:06:18 PM PDT 24
Peak memory 145120 kb
Host smart-284a5386-6bd4-485b-bb86-6175f35aeceb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3167929332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3167929332
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1911547692
Short name T43
Test name
Test status
Simulation time 30346860 ps
CPU time 0.39 seconds
Started Jun 07 06:06:14 PM PDT 24
Finished Jun 07 06:06:14 PM PDT 24
Peak memory 145172 kb
Host smart-fb0a8ac1-a2ff-405c-81b1-325daa2207d1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1911547692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1911547692
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1356255064
Short name T44
Test name
Test status
Simulation time 29359322 ps
CPU time 0.39 seconds
Started Jun 07 06:06:14 PM PDT 24
Finished Jun 07 06:06:15 PM PDT 24
Peak memory 145048 kb
Host smart-4f47132e-3170-46c2-8c7f-46a9db86f5ad
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1356255064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1356255064
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.486890622
Short name T51
Test name
Test status
Simulation time 31673751 ps
CPU time 0.4 seconds
Started Jun 07 06:06:12 PM PDT 24
Finished Jun 07 06:06:12 PM PDT 24
Peak memory 145092 kb
Host smart-df802f15-7e1f-4dcd-822a-3ce49d3a2c8b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=486890622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.486890622
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2975282030
Short name T57
Test name
Test status
Simulation time 30588143 ps
CPU time 0.41 seconds
Started Jun 07 06:06:13 PM PDT 24
Finished Jun 07 06:06:13 PM PDT 24
Peak memory 145112 kb
Host smart-39dd44ba-72dc-4c0b-abaf-fd3d3586a1c7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2975282030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2975282030
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.719609766
Short name T39
Test name
Test status
Simulation time 28325950 ps
CPU time 0.4 seconds
Started Jun 07 06:06:09 PM PDT 24
Finished Jun 07 06:06:10 PM PDT 24
Peak memory 145048 kb
Host smart-677d3888-3c69-4390-b2f2-b6b4a132686f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=719609766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.719609766
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3472511708
Short name T42
Test name
Test status
Simulation time 29852496 ps
CPU time 0.4 seconds
Started Jun 07 06:06:36 PM PDT 24
Finished Jun 07 06:06:36 PM PDT 24
Peak memory 145124 kb
Host smart-ae186bdb-1d14-4797-b917-09d1a2aebe18
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3472511708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3472511708
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1725440644
Short name T41
Test name
Test status
Simulation time 29801484 ps
CPU time 0.4 seconds
Started Jun 07 06:06:13 PM PDT 24
Finished Jun 07 06:06:14 PM PDT 24
Peak memory 145112 kb
Host smart-f8eef726-03af-4ec2-8ab6-8bc2271505b3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1725440644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1725440644
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3017135523
Short name T58
Test name
Test status
Simulation time 30323943 ps
CPU time 0.4 seconds
Started Jun 07 06:06:11 PM PDT 24
Finished Jun 07 06:06:12 PM PDT 24
Peak memory 145128 kb
Host smart-5bc4e129-076d-47c5-88f7-a2c7ba0d54ff
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3017135523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3017135523
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3171307854
Short name T48
Test name
Test status
Simulation time 30508588 ps
CPU time 0.4 seconds
Started Jun 07 06:06:35 PM PDT 24
Finished Jun 07 06:06:36 PM PDT 24
Peak memory 145160 kb
Host smart-c55b2669-536c-41b8-92f6-6ebbd132b325
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3171307854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3171307854
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3890815263
Short name T46
Test name
Test status
Simulation time 29455684 ps
CPU time 0.39 seconds
Started Jun 07 06:06:12 PM PDT 24
Finished Jun 07 06:06:13 PM PDT 24
Peak memory 145176 kb
Host smart-c13310a9-b2e2-4921-a53b-1780f95a0555
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3890815263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3890815263
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1415551299
Short name T52
Test name
Test status
Simulation time 30884648 ps
CPU time 0.4 seconds
Started Jun 07 06:06:21 PM PDT 24
Finished Jun 07 06:06:22 PM PDT 24
Peak memory 145140 kb
Host smart-7302a8f9-ae00-4dac-87e0-de47f83145a6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1415551299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1415551299
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1419256381
Short name T56
Test name
Test status
Simulation time 30487570 ps
CPU time 0.39 seconds
Started Jun 07 06:06:22 PM PDT 24
Finished Jun 07 06:06:23 PM PDT 24
Peak memory 145100 kb
Host smart-a54bbc66-1599-4cfe-a1b0-824e567feb26
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1419256381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1419256381
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.854043562
Short name T53
Test name
Test status
Simulation time 29513826 ps
CPU time 0.4 seconds
Started Jun 07 06:06:10 PM PDT 24
Finished Jun 07 06:06:11 PM PDT 24
Peak memory 145112 kb
Host smart-26f4d0f1-242e-43ec-97f0-dbea3e5980b1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=854043562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.854043562
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4075413103
Short name T54
Test name
Test status
Simulation time 28838433 ps
CPU time 0.41 seconds
Started Jun 07 06:06:13 PM PDT 24
Finished Jun 07 06:06:14 PM PDT 24
Peak memory 145112 kb
Host smart-7acc1472-d73c-457e-ae5d-d79496baa6f1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4075413103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.4075413103
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3126920667
Short name T55
Test name
Test status
Simulation time 31793943 ps
CPU time 0.41 seconds
Started Jun 07 06:06:06 PM PDT 24
Finished Jun 07 06:06:06 PM PDT 24
Peak memory 145136 kb
Host smart-4031b62e-bc3d-429d-ad20-8a8733a65490
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3126920667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3126920667
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.916394754
Short name T25
Test name
Test status
Simulation time 8692130 ps
CPU time 0.43 seconds
Started Jun 07 07:49:24 PM PDT 24
Finished Jun 07 07:49:26 PM PDT 24
Peak memory 145620 kb
Host smart-ea8fc5b3-a6ec-49e4-b5f7-312bf83e6565
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=916394754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.916394754
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2206372643
Short name T26
Test name
Test status
Simulation time 9271342 ps
CPU time 0.37 seconds
Started Jun 07 07:49:22 PM PDT 24
Finished Jun 07 07:49:24 PM PDT 24
Peak memory 145592 kb
Host smart-e5fe24f0-c915-4717-b0b7-259b5f03ad7a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2206372643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2206372643
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.4252102265
Short name T27
Test name
Test status
Simulation time 8561257 ps
CPU time 0.38 seconds
Started Jun 07 07:49:30 PM PDT 24
Finished Jun 07 07:49:31 PM PDT 24
Peak memory 145572 kb
Host smart-2975a661-3d7c-4b3a-bfa0-a06ccabc6581
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4252102265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.4252102265
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1694199453
Short name T61
Test name
Test status
Simulation time 8044180 ps
CPU time 0.38 seconds
Started Jun 07 07:49:31 PM PDT 24
Finished Jun 07 07:49:32 PM PDT 24
Peak memory 145584 kb
Host smart-1012e634-ee65-4007-b737-a7b3714a0548
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1694199453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1694199453
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2257788275
Short name T36
Test name
Test status
Simulation time 9194389 ps
CPU time 0.39 seconds
Started Jun 07 07:49:31 PM PDT 24
Finished Jun 07 07:49:32 PM PDT 24
Peak memory 145592 kb
Host smart-a1f4d9f9-08bb-42e7-ba05-e10b75738325
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2257788275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2257788275
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.471237376
Short name T60
Test name
Test status
Simulation time 9649447 ps
CPU time 0.39 seconds
Started Jun 07 07:49:30 PM PDT 24
Finished Jun 07 07:49:32 PM PDT 24
Peak memory 145592 kb
Host smart-ef0fb059-60b4-4891-b8f9-249bbec9c0db
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=471237376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.471237376
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.695881763
Short name T31
Test name
Test status
Simulation time 8684617 ps
CPU time 0.39 seconds
Started Jun 07 07:49:38 PM PDT 24
Finished Jun 07 07:49:40 PM PDT 24
Peak memory 145468 kb
Host smart-27e8c4e9-3bd6-4e8d-b82c-6c8a23e7779c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=695881763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.695881763
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1969012457
Short name T29
Test name
Test status
Simulation time 8725143 ps
CPU time 0.39 seconds
Started Jun 07 07:49:36 PM PDT 24
Finished Jun 07 07:49:37 PM PDT 24
Peak memory 145568 kb
Host smart-a8091bc1-c350-433f-85ed-4eca03db7745
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1969012457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1969012457
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.4056078806
Short name T24
Test name
Test status
Simulation time 8129274 ps
CPU time 0.38 seconds
Started Jun 07 07:49:38 PM PDT 24
Finished Jun 07 07:49:39 PM PDT 24
Peak memory 145576 kb
Host smart-3122f2ee-36f4-453e-b733-1a747014b7b5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4056078806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.4056078806
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3476341674
Short name T62
Test name
Test status
Simulation time 8386507 ps
CPU time 0.39 seconds
Started Jun 07 07:49:37 PM PDT 24
Finished Jun 07 07:49:38 PM PDT 24
Peak memory 145552 kb
Host smart-26785e49-038b-4438-9b3b-c9915d0cc727
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3476341674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3476341674
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.387156462
Short name T33
Test name
Test status
Simulation time 8860555 ps
CPU time 0.38 seconds
Started Jun 07 07:49:38 PM PDT 24
Finished Jun 07 07:49:39 PM PDT 24
Peak memory 145584 kb
Host smart-78509bab-2a0f-47be-bd60-2429e91104a1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=387156462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.387156462
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2789469689
Short name T23
Test name
Test status
Simulation time 9054873 ps
CPU time 0.39 seconds
Started Jun 07 07:49:31 PM PDT 24
Finished Jun 07 07:49:33 PM PDT 24
Peak memory 145596 kb
Host smart-e66b78c9-41f3-4b05-9141-569b44c48b7c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2789469689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2789469689
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.688089527
Short name T22
Test name
Test status
Simulation time 10766116 ps
CPU time 0.43 seconds
Started Jun 07 07:49:31 PM PDT 24
Finished Jun 07 07:49:33 PM PDT 24
Peak memory 145624 kb
Host smart-677bca6f-5e8f-4c3e-87b2-83045fecb525
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=688089527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.688089527
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3928653058
Short name T59
Test name
Test status
Simulation time 9198007 ps
CPU time 0.4 seconds
Started Jun 07 07:49:29 PM PDT 24
Finished Jun 07 07:49:31 PM PDT 24
Peak memory 145592 kb
Host smart-9cf35184-48df-4d57-ba8d-8f99326c16fb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3928653058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3928653058
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.506610857
Short name T38
Test name
Test status
Simulation time 8716836 ps
CPU time 0.39 seconds
Started Jun 07 07:49:31 PM PDT 24
Finished Jun 07 07:49:32 PM PDT 24
Peak memory 145584 kb
Host smart-958bf64b-5123-40ad-9c4b-3a205fceb677
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=506610857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.506610857
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2181064325
Short name T35
Test name
Test status
Simulation time 7909289 ps
CPU time 0.38 seconds
Started Jun 07 07:49:33 PM PDT 24
Finished Jun 07 07:49:34 PM PDT 24
Peak memory 145560 kb
Host smart-50d585a3-787a-44a6-8f3c-40bf0a0466b5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2181064325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2181064325
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2599010394
Short name T28
Test name
Test status
Simulation time 9486090 ps
CPU time 0.39 seconds
Started Jun 07 07:49:31 PM PDT 24
Finished Jun 07 07:49:33 PM PDT 24
Peak memory 145540 kb
Host smart-8e8d56b0-6f5f-43db-952a-67e3745b5a0a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2599010394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2599010394
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.4080940308
Short name T32
Test name
Test status
Simulation time 9069430 ps
CPU time 0.38 seconds
Started Jun 07 07:49:30 PM PDT 24
Finished Jun 07 07:49:32 PM PDT 24
Peak memory 145592 kb
Host smart-037faec2-1c38-4928-a60a-07104401ab6b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4080940308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.4080940308
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1210061040
Short name T34
Test name
Test status
Simulation time 10015649 ps
CPU time 0.39 seconds
Started Jun 07 07:49:30 PM PDT 24
Finished Jun 07 07:49:31 PM PDT 24
Peak memory 145580 kb
Host smart-9acde33a-efb2-44fc-84bb-1420a89d8511
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1210061040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1210061040
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3262005175
Short name T30
Test name
Test status
Simulation time 26931208 ps
CPU time 0.4 seconds
Started Jun 07 06:08:30 PM PDT 24
Finished Jun 07 06:08:31 PM PDT 24
Peak memory 145444 kb
Host smart-7c0ae25c-74b9-4830-b84b-8861800e522e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3262005175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3262005175
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1001012019
Short name T63
Test name
Test status
Simulation time 26353101 ps
CPU time 0.43 seconds
Started Jun 07 06:08:20 PM PDT 24
Finished Jun 07 06:08:21 PM PDT 24
Peak memory 145848 kb
Host smart-40f06b4e-5846-4912-8752-f8897c398619
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1001012019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1001012019
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1454759140
Short name T67
Test name
Test status
Simulation time 28534294 ps
CPU time 0.46 seconds
Started Jun 07 06:08:28 PM PDT 24
Finished Jun 07 06:08:29 PM PDT 24
Peak memory 145848 kb
Host smart-937b32c2-bebb-4f9e-8229-8b2c238e6c44
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1454759140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1454759140
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1712203414
Short name T68
Test name
Test status
Simulation time 24961782 ps
CPU time 0.39 seconds
Started Jun 07 06:08:47 PM PDT 24
Finished Jun 07 06:08:48 PM PDT 24
Peak memory 145428 kb
Host smart-95b49399-2fb7-4587-8092-d6c810bb64fb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1712203414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1712203414
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3376767981
Short name T79
Test name
Test status
Simulation time 28066104 ps
CPU time 0.43 seconds
Started Jun 07 06:08:33 PM PDT 24
Finished Jun 07 06:08:33 PM PDT 24
Peak memory 145448 kb
Host smart-7d61d4c5-ce95-4fa9-8e76-475be833df22
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3376767981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3376767981
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.594242170
Short name T72
Test name
Test status
Simulation time 26211189 ps
CPU time 0.39 seconds
Started Jun 07 06:08:18 PM PDT 24
Finished Jun 07 06:08:19 PM PDT 24
Peak memory 145440 kb
Host smart-66143132-0284-4ae6-b98b-f816177f1c97
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=594242170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.594242170
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3643975266
Short name T71
Test name
Test status
Simulation time 26744356 ps
CPU time 0.41 seconds
Started Jun 07 06:08:28 PM PDT 24
Finished Jun 07 06:08:29 PM PDT 24
Peak memory 145576 kb
Host smart-029851f5-0b69-432a-9cbd-ad3cbab2e2fc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3643975266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3643975266
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.455553800
Short name T70
Test name
Test status
Simulation time 25698466 ps
CPU time 0.39 seconds
Started Jun 07 06:08:04 PM PDT 24
Finished Jun 07 06:08:05 PM PDT 24
Peak memory 145380 kb
Host smart-a8d2e808-d78e-46e4-8e32-46a227071af3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=455553800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.455553800
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1306360996
Short name T65
Test name
Test status
Simulation time 28230360 ps
CPU time 0.4 seconds
Started Jun 07 06:08:35 PM PDT 24
Finished Jun 07 06:08:35 PM PDT 24
Peak memory 145452 kb
Host smart-8a4e727a-18fe-48f4-b837-1b75bfe719f7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1306360996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1306360996
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3634668439
Short name T78
Test name
Test status
Simulation time 28760776 ps
CPU time 0.39 seconds
Started Jun 07 06:08:01 PM PDT 24
Finished Jun 07 06:08:01 PM PDT 24
Peak memory 145440 kb
Host smart-f63c3d71-fdcb-4298-bade-911011cfb6f6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3634668439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3634668439
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3734284781
Short name T64
Test name
Test status
Simulation time 26109018 ps
CPU time 0.4 seconds
Started Jun 07 06:08:20 PM PDT 24
Finished Jun 07 06:08:21 PM PDT 24
Peak memory 145268 kb
Host smart-0fbbb609-4117-4538-85e5-8a93cb1fc133
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3734284781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3734284781
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2323048868
Short name T66
Test name
Test status
Simulation time 27606749 ps
CPU time 0.39 seconds
Started Jun 07 06:08:06 PM PDT 24
Finished Jun 07 06:08:06 PM PDT 24
Peak memory 145440 kb
Host smart-86e11a31-a49e-4221-8bb3-1af3ec3a6256
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2323048868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2323048868
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1671213899
Short name T4
Test name
Test status
Simulation time 26081635 ps
CPU time 0.4 seconds
Started Jun 07 06:08:25 PM PDT 24
Finished Jun 07 06:08:25 PM PDT 24
Peak memory 145424 kb
Host smart-d6f54288-a6aa-4b3b-95e7-12762a3dc14d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1671213899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1671213899
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3803978857
Short name T75
Test name
Test status
Simulation time 28625343 ps
CPU time 0.39 seconds
Started Jun 07 06:08:30 PM PDT 24
Finished Jun 07 06:08:30 PM PDT 24
Peak memory 145424 kb
Host smart-92f5abed-23b7-4524-b52e-e1281e7e7339
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3803978857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3803978857
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2675678831
Short name T73
Test name
Test status
Simulation time 28501249 ps
CPU time 0.4 seconds
Started Jun 07 06:08:36 PM PDT 24
Finished Jun 07 06:08:36 PM PDT 24
Peak memory 145416 kb
Host smart-b1c943c3-3650-4512-9f4e-f29b96a8cc23
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2675678831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2675678831
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.417598994
Short name T76
Test name
Test status
Simulation time 29991310 ps
CPU time 0.39 seconds
Started Jun 07 06:08:31 PM PDT 24
Finished Jun 07 06:08:31 PM PDT 24
Peak memory 145324 kb
Host smart-8433b9e3-74a9-485c-a227-676e086c8596
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=417598994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.417598994
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3726699302
Short name T74
Test name
Test status
Simulation time 27793340 ps
CPU time 0.4 seconds
Started Jun 07 06:08:18 PM PDT 24
Finished Jun 07 06:08:19 PM PDT 24
Peak memory 145576 kb
Host smart-b0d97609-14d6-4f7a-85db-93c0f08c3bff
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3726699302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3726699302
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3671889306
Short name T69
Test name
Test status
Simulation time 27567789 ps
CPU time 0.38 seconds
Started Jun 07 06:08:48 PM PDT 24
Finished Jun 07 06:08:49 PM PDT 24
Peak memory 145444 kb
Host smart-a8e289fc-ef43-464a-801a-5917436a48dd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3671889306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3671889306
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4117333204
Short name T77
Test name
Test status
Simulation time 27137826 ps
CPU time 0.4 seconds
Started Jun 07 06:08:05 PM PDT 24
Finished Jun 07 06:08:06 PM PDT 24
Peak memory 145384 kb
Host smart-c41eaf7d-5069-48a8-a652-9bf7621c535c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4117333204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.4117333204
Directory /workspace/9.prim_sync_fatal_alert/latest
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