Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.67 88.67 100.00 100.00 93.75 93.75 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/9.prim_async_alert.2957117124
91.80 3.13 100.00 0.00 93.75 0.00 100.00 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/11.prim_sync_alert.4090003004
93.56 1.76 100.00 0.00 93.75 0.00 100.00 0.00 85.71 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4021683232
94.25 0.69 100.00 0.00 97.92 4.17 100.00 0.00 85.71 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.600563645
94.85 0.60 100.00 0.00 97.92 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/1.prim_async_alert.3972253175
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/default/19.prim_async_alert.3233936326

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1557404283
/workspace/coverage/default/10.prim_async_alert.759958309
/workspace/coverage/default/11.prim_async_alert.1028489220
/workspace/coverage/default/12.prim_async_alert.2196976599
/workspace/coverage/default/13.prim_async_alert.3673749303
/workspace/coverage/default/14.prim_async_alert.4113925119
/workspace/coverage/default/15.prim_async_alert.3636457552
/workspace/coverage/default/16.prim_async_alert.4001328327
/workspace/coverage/default/17.prim_async_alert.290051657
/workspace/coverage/default/18.prim_async_alert.1722564382
/workspace/coverage/default/2.prim_async_alert.3964469413
/workspace/coverage/default/3.prim_async_alert.2111099506
/workspace/coverage/default/4.prim_async_alert.2555753238
/workspace/coverage/default/5.prim_async_alert.3384686904
/workspace/coverage/default/6.prim_async_alert.361083635
/workspace/coverage/default/7.prim_async_alert.3356378802
/workspace/coverage/default/8.prim_async_alert.1592829300
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2177431879
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1347170267
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2789725329
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3861031062
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1305924175
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2734506494
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4179083206
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.485886388
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3812536612
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1112145092
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4198425666
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2759312861
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4084787753
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1550446253
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3935909223
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.631800999
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1782236240
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3193964689
/workspace/coverage/sync_alert/0.prim_sync_alert.2459174953
/workspace/coverage/sync_alert/1.prim_sync_alert.2568557081
/workspace/coverage/sync_alert/10.prim_sync_alert.3141308587
/workspace/coverage/sync_alert/12.prim_sync_alert.4252827195
/workspace/coverage/sync_alert/13.prim_sync_alert.4250654179
/workspace/coverage/sync_alert/14.prim_sync_alert.1679926061
/workspace/coverage/sync_alert/15.prim_sync_alert.1618045105
/workspace/coverage/sync_alert/16.prim_sync_alert.2672535135
/workspace/coverage/sync_alert/17.prim_sync_alert.3086048282
/workspace/coverage/sync_alert/18.prim_sync_alert.2345432369
/workspace/coverage/sync_alert/19.prim_sync_alert.3920417886
/workspace/coverage/sync_alert/2.prim_sync_alert.3314986015
/workspace/coverage/sync_alert/3.prim_sync_alert.3147226322
/workspace/coverage/sync_alert/4.prim_sync_alert.1571876664
/workspace/coverage/sync_alert/5.prim_sync_alert.3117991079
/workspace/coverage/sync_alert/6.prim_sync_alert.1223067413
/workspace/coverage/sync_alert/7.prim_sync_alert.2563157946
/workspace/coverage/sync_alert/8.prim_sync_alert.338585669
/workspace/coverage/sync_alert/9.prim_sync_alert.1726536851
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2645946128
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2814699500
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.848784909
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2622596656
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1562492359
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4060309524
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2398861917
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.584005682
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1818112499
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1212639722
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1191224036
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2860983705
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3415896001
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.637495491
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1431578169
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2124952604
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3999595835
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3938602798
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4287167506



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/14.prim_async_alert.4113925119 Jun 09 12:26:20 PM PDT 24 Jun 09 12:26:21 PM PDT 24 10967128 ps
T2 /workspace/coverage/default/12.prim_async_alert.2196976599 Jun 09 12:26:14 PM PDT 24 Jun 09 12:26:16 PM PDT 24 11361342 ps
T3 /workspace/coverage/default/10.prim_async_alert.759958309 Jun 09 12:26:08 PM PDT 24 Jun 09 12:26:09 PM PDT 24 10340530 ps
T7 /workspace/coverage/default/7.prim_async_alert.3356378802 Jun 09 12:26:14 PM PDT 24 Jun 09 12:26:16 PM PDT 24 10458956 ps
T19 /workspace/coverage/default/13.prim_async_alert.3673749303 Jun 09 12:26:10 PM PDT 24 Jun 09 12:26:11 PM PDT 24 11319019 ps
T13 /workspace/coverage/default/17.prim_async_alert.290051657 Jun 09 12:26:12 PM PDT 24 Jun 09 12:26:14 PM PDT 24 11224995 ps
T8 /workspace/coverage/default/9.prim_async_alert.2957117124 Jun 09 12:26:14 PM PDT 24 Jun 09 12:26:16 PM PDT 24 11465162 ps
T18 /workspace/coverage/default/11.prim_async_alert.1028489220 Jun 09 12:26:11 PM PDT 24 Jun 09 12:26:13 PM PDT 24 11523923 ps
T9 /workspace/coverage/default/15.prim_async_alert.3636457552 Jun 09 12:26:33 PM PDT 24 Jun 09 12:26:33 PM PDT 24 11753027 ps
T14 /workspace/coverage/default/16.prim_async_alert.4001328327 Jun 09 12:26:21 PM PDT 24 Jun 09 12:26:22 PM PDT 24 11525226 ps
T47 /workspace/coverage/default/1.prim_async_alert.3972253175 Jun 09 12:26:54 PM PDT 24 Jun 09 12:26:55 PM PDT 24 12426217 ps
T20 /workspace/coverage/default/6.prim_async_alert.361083635 Jun 09 12:26:13 PM PDT 24 Jun 09 12:26:19 PM PDT 24 11821934 ps
T21 /workspace/coverage/default/5.prim_async_alert.3384686904 Jun 09 12:26:10 PM PDT 24 Jun 09 12:26:11 PM PDT 24 10325235 ps
T10 /workspace/coverage/default/19.prim_async_alert.3233936326 Jun 09 12:26:13 PM PDT 24 Jun 09 12:26:14 PM PDT 24 11986453 ps
T48 /workspace/coverage/default/4.prim_async_alert.2555753238 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:02 PM PDT 24 12080929 ps
T11 /workspace/coverage/default/2.prim_async_alert.3964469413 Jun 09 12:26:55 PM PDT 24 Jun 09 12:26:56 PM PDT 24 10887155 ps
T22 /workspace/coverage/default/0.prim_async_alert.1557404283 Jun 09 12:26:55 PM PDT 24 Jun 09 12:26:56 PM PDT 24 11578535 ps
T23 /workspace/coverage/default/18.prim_async_alert.1722564382 Jun 09 12:26:11 PM PDT 24 Jun 09 12:26:13 PM PDT 24 10836619 ps
T12 /workspace/coverage/default/3.prim_async_alert.2111099506 Jun 09 12:26:16 PM PDT 24 Jun 09 12:26:17 PM PDT 24 11578354 ps
T49 /workspace/coverage/default/8.prim_async_alert.1592829300 Jun 09 12:26:16 PM PDT 24 Jun 09 12:26:17 PM PDT 24 11342166 ps
T16 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.631800999 Jun 09 12:26:10 PM PDT 24 Jun 09 12:26:11 PM PDT 24 30859706 ps
T40 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4084787753 Jun 09 12:26:08 PM PDT 24 Jun 09 12:26:10 PM PDT 24 30082496 ps
T41 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3861031062 Jun 09 12:26:13 PM PDT 24 Jun 09 12:26:15 PM PDT 24 28209220 ps
T17 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1550446253 Jun 09 12:26:11 PM PDT 24 Jun 09 12:26:13 PM PDT 24 30077796 ps
T15 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4021683232 Jun 09 12:26:14 PM PDT 24 Jun 09 12:26:16 PM PDT 24 30949433 ps
T42 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1305924175 Jun 09 12:26:12 PM PDT 24 Jun 09 12:26:14 PM PDT 24 31697237 ps
T43 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2759312861 Jun 09 12:26:11 PM PDT 24 Jun 09 12:26:13 PM PDT 24 29668512 ps
T44 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2177431879 Jun 09 12:26:12 PM PDT 24 Jun 09 12:26:13 PM PDT 24 29847499 ps
T45 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.485886388 Jun 09 12:26:15 PM PDT 24 Jun 09 12:26:16 PM PDT 24 30173635 ps
T46 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2789725329 Jun 09 12:26:18 PM PDT 24 Jun 09 12:26:18 PM PDT 24 32326787 ps
T4 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3935909223 Jun 09 12:26:23 PM PDT 24 Jun 09 12:26:23 PM PDT 24 29747481 ps
T50 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1782236240 Jun 09 12:26:15 PM PDT 24 Jun 09 12:26:17 PM PDT 24 30212886 ps
T51 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1112145092 Jun 09 12:26:13 PM PDT 24 Jun 09 12:26:15 PM PDT 24 30465122 ps
T52 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4179083206 Jun 09 12:26:12 PM PDT 24 Jun 09 12:26:14 PM PDT 24 31591716 ps
T53 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3193964689 Jun 09 12:26:08 PM PDT 24 Jun 09 12:26:09 PM PDT 24 30982379 ps
T54 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4198425666 Jun 09 12:26:11 PM PDT 24 Jun 09 12:26:13 PM PDT 24 31286269 ps
T55 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1347170267 Jun 09 12:26:10 PM PDT 24 Jun 09 12:26:12 PM PDT 24 31153040 ps
T56 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2734506494 Jun 09 12:26:09 PM PDT 24 Jun 09 12:26:20 PM PDT 24 30453741 ps
T57 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3812536612 Jun 09 12:26:08 PM PDT 24 Jun 09 12:26:09 PM PDT 24 31035341 ps
T33 /workspace/coverage/sync_alert/18.prim_sync_alert.2345432369 Jun 09 12:28:31 PM PDT 24 Jun 09 12:28:32 PM PDT 24 8966139 ps
T34 /workspace/coverage/sync_alert/3.prim_sync_alert.3147226322 Jun 09 12:26:54 PM PDT 24 Jun 09 12:26:55 PM PDT 24 10150000 ps
T35 /workspace/coverage/sync_alert/9.prim_sync_alert.1726536851 Jun 09 12:26:52 PM PDT 24 Jun 09 12:26:53 PM PDT 24 8635086 ps
T24 /workspace/coverage/sync_alert/19.prim_sync_alert.3920417886 Jun 09 12:27:03 PM PDT 24 Jun 09 12:27:05 PM PDT 24 9705184 ps
T36 /workspace/coverage/sync_alert/1.prim_sync_alert.2568557081 Jun 09 12:28:16 PM PDT 24 Jun 09 12:28:17 PM PDT 24 8340826 ps
T25 /workspace/coverage/sync_alert/13.prim_sync_alert.4250654179 Jun 09 12:26:57 PM PDT 24 Jun 09 12:26:59 PM PDT 24 9203977 ps
T26 /workspace/coverage/sync_alert/5.prim_sync_alert.3117991079 Jun 09 12:28:19 PM PDT 24 Jun 09 12:28:20 PM PDT 24 9018668 ps
T37 /workspace/coverage/sync_alert/11.prim_sync_alert.4090003004 Jun 09 12:26:56 PM PDT 24 Jun 09 12:26:57 PM PDT 24 8844277 ps
T38 /workspace/coverage/sync_alert/10.prim_sync_alert.3141308587 Jun 09 12:28:21 PM PDT 24 Jun 09 12:28:21 PM PDT 24 8875757 ps
T27 /workspace/coverage/sync_alert/14.prim_sync_alert.1679926061 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:08 PM PDT 24 8908868 ps
T39 /workspace/coverage/sync_alert/16.prim_sync_alert.2672535135 Jun 09 12:27:57 PM PDT 24 Jun 09 12:27:59 PM PDT 24 10213619 ps
T28 /workspace/coverage/sync_alert/0.prim_sync_alert.2459174953 Jun 09 12:27:02 PM PDT 24 Jun 09 12:27:04 PM PDT 24 8839693 ps
T29 /workspace/coverage/sync_alert/7.prim_sync_alert.2563157946 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:02 PM PDT 24 9137456 ps
T58 /workspace/coverage/sync_alert/4.prim_sync_alert.1571876664 Jun 09 12:28:20 PM PDT 24 Jun 09 12:28:21 PM PDT 24 8976547 ps
T59 /workspace/coverage/sync_alert/15.prim_sync_alert.1618045105 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:01 PM PDT 24 10132674 ps
T30 /workspace/coverage/sync_alert/2.prim_sync_alert.3314986015 Jun 09 12:27:37 PM PDT 24 Jun 09 12:27:38 PM PDT 24 9040446 ps
T60 /workspace/coverage/sync_alert/6.prim_sync_alert.1223067413 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:07 PM PDT 24 9348091 ps
T61 /workspace/coverage/sync_alert/17.prim_sync_alert.3086048282 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:07 PM PDT 24 9419833 ps
T62 /workspace/coverage/sync_alert/12.prim_sync_alert.4252827195 Jun 09 12:27:05 PM PDT 24 Jun 09 12:27:15 PM PDT 24 10142164 ps
T63 /workspace/coverage/sync_alert/8.prim_sync_alert.338585669 Jun 09 12:26:54 PM PDT 24 Jun 09 12:26:55 PM PDT 24 8965759 ps
T64 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3938602798 Jun 09 12:26:54 PM PDT 24 Jun 09 12:26:55 PM PDT 24 26004706 ps
T65 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4287167506 Jun 09 12:28:25 PM PDT 24 Jun 09 12:28:26 PM PDT 24 28737078 ps
T66 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2398861917 Jun 09 12:26:58 PM PDT 24 Jun 09 12:26:59 PM PDT 24 27230590 ps
T5 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1562492359 Jun 09 12:26:59 PM PDT 24 Jun 09 12:27:00 PM PDT 24 27690342 ps
T31 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2860983705 Jun 09 12:26:55 PM PDT 24 Jun 09 12:26:56 PM PDT 24 25638934 ps
T32 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1431578169 Jun 09 12:26:57 PM PDT 24 Jun 09 12:26:58 PM PDT 24 26837583 ps
T67 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2645946128 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:01 PM PDT 24 29758154 ps
T68 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1191224036 Jun 09 12:27:11 PM PDT 24 Jun 09 12:27:12 PM PDT 24 25884197 ps
T69 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4060309524 Jun 09 12:26:57 PM PDT 24 Jun 09 12:26:58 PM PDT 24 26182192 ps
T70 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.637495491 Jun 09 12:28:31 PM PDT 24 Jun 09 12:28:33 PM PDT 24 27976116 ps
T71 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3999595835 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:09 PM PDT 24 27264474 ps
T72 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.848784909 Jun 09 12:27:01 PM PDT 24 Jun 09 12:27:02 PM PDT 24 26167196 ps
T73 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2124952604 Jun 09 12:27:07 PM PDT 24 Jun 09 12:27:10 PM PDT 24 27177147 ps
T74 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3415896001 Jun 09 12:26:51 PM PDT 24 Jun 09 12:26:51 PM PDT 24 27416216 ps
T75 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.584005682 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:08 PM PDT 24 29845643 ps
T76 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2622596656 Jun 09 12:26:57 PM PDT 24 Jun 09 12:26:59 PM PDT 24 25754793 ps
T77 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2814699500 Jun 09 12:27:06 PM PDT 24 Jun 09 12:27:09 PM PDT 24 29290745 ps
T78 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1212639722 Jun 09 12:26:52 PM PDT 24 Jun 09 12:26:53 PM PDT 24 28247571 ps
T6 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.600563645 Jun 09 12:26:53 PM PDT 24 Jun 09 12:26:54 PM PDT 24 29916644 ps
T79 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1818112499 Jun 09 12:27:00 PM PDT 24 Jun 09 12:27:00 PM PDT 24 27963476 ps

Test location /workspace/coverage/default/9.prim_async_alert.2957117124
Short name T8
Test name
Test status
Simulation time 11465162 ps
CPU time 0.37 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:26:16 PM PDT 24
Peak memory 145640 kb
Host smart-f80ee60a-5594-45ee-b842-122d3f10a360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957117124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2957117124
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.4090003004
Short name T37
Test name
Test status
Simulation time 8844277 ps
CPU time 0.38 seconds
Started Jun 09 12:26:56 PM PDT 24
Finished Jun 09 12:26:57 PM PDT 24
Peak memory 145460 kb
Host smart-0de0d1f6-4b14-4836-b83a-48cb50372a42
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4090003004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.4090003004
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4021683232
Short name T15
Test name
Test status
Simulation time 30949433 ps
CPU time 0.4 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:26:16 PM PDT 24
Peak memory 145224 kb
Host smart-46276c96-3523-4f9d-9a23-8b11130f7c55
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4021683232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.4021683232
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.600563645
Short name T6
Test name
Test status
Simulation time 29916644 ps
CPU time 0.41 seconds
Started Jun 09 12:26:53 PM PDT 24
Finished Jun 09 12:26:54 PM PDT 24
Peak memory 145428 kb
Host smart-104fbd8a-4e9b-4e9d-9674-51d849bbe716
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=600563645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.600563645
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.3972253175
Short name T47
Test name
Test status
Simulation time 12426217 ps
CPU time 0.39 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:26:55 PM PDT 24
Peak memory 145660 kb
Host smart-d0f637fa-5ba5-486c-996a-262f41eb948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972253175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3972253175
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3233936326
Short name T10
Test name
Test status
Simulation time 11986453 ps
CPU time 0.41 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:26:14 PM PDT 24
Peak memory 145700 kb
Host smart-cd6efa7a-f637-4249-9dc8-43eb55c90556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233936326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3233936326
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1557404283
Short name T22
Test name
Test status
Simulation time 11578535 ps
CPU time 0.39 seconds
Started Jun 09 12:26:55 PM PDT 24
Finished Jun 09 12:26:56 PM PDT 24
Peak memory 145656 kb
Host smart-f2cfdff5-c25c-49a7-b0dc-c96a24027e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557404283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1557404283
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.759958309
Short name T3
Test name
Test status
Simulation time 10340530 ps
CPU time 0.39 seconds
Started Jun 09 12:26:08 PM PDT 24
Finished Jun 09 12:26:09 PM PDT 24
Peak memory 145704 kb
Host smart-c2832520-b481-4323-a483-ae1699a04dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759958309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.759958309
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1028489220
Short name T18
Test name
Test status
Simulation time 11523923 ps
CPU time 0.4 seconds
Started Jun 09 12:26:11 PM PDT 24
Finished Jun 09 12:26:13 PM PDT 24
Peak memory 145692 kb
Host smart-bdb6d284-75d9-403a-9260-a13830a00b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028489220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1028489220
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2196976599
Short name T2
Test name
Test status
Simulation time 11361342 ps
CPU time 0.39 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:26:16 PM PDT 24
Peak memory 145692 kb
Host smart-0399a0c3-d6fa-4dfd-8301-84bfa4e9af47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196976599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2196976599
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3673749303
Short name T19
Test name
Test status
Simulation time 11319019 ps
CPU time 0.38 seconds
Started Jun 09 12:26:10 PM PDT 24
Finished Jun 09 12:26:11 PM PDT 24
Peak memory 145700 kb
Host smart-e24ede16-a6a1-4dff-8c27-4dcb44d856f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673749303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3673749303
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.4113925119
Short name T1
Test name
Test status
Simulation time 10967128 ps
CPU time 0.38 seconds
Started Jun 09 12:26:20 PM PDT 24
Finished Jun 09 12:26:21 PM PDT 24
Peak memory 145700 kb
Host smart-6bf2f48d-791b-4ba2-bfc2-c01068b061c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113925119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.4113925119
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.3636457552
Short name T9
Test name
Test status
Simulation time 11753027 ps
CPU time 0.4 seconds
Started Jun 09 12:26:33 PM PDT 24
Finished Jun 09 12:26:33 PM PDT 24
Peak memory 145700 kb
Host smart-2478bf8c-5981-44ab-a02c-2154a45efa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636457552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3636457552
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.4001328327
Short name T14
Test name
Test status
Simulation time 11525226 ps
CPU time 0.38 seconds
Started Jun 09 12:26:21 PM PDT 24
Finished Jun 09 12:26:22 PM PDT 24
Peak memory 145696 kb
Host smart-ace4a38d-2711-464b-9c5c-26bb93f17392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001328327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.4001328327
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.290051657
Short name T13
Test name
Test status
Simulation time 11224995 ps
CPU time 0.4 seconds
Started Jun 09 12:26:12 PM PDT 24
Finished Jun 09 12:26:14 PM PDT 24
Peak memory 145668 kb
Host smart-9e097f47-3dfd-4212-b449-8dca46d1b702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290051657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.290051657
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1722564382
Short name T23
Test name
Test status
Simulation time 10836619 ps
CPU time 0.39 seconds
Started Jun 09 12:26:11 PM PDT 24
Finished Jun 09 12:26:13 PM PDT 24
Peak memory 145704 kb
Host smart-f2a5dce4-1742-4b43-8e80-d2db0fc4dcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722564382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1722564382
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3964469413
Short name T11
Test name
Test status
Simulation time 10887155 ps
CPU time 0.38 seconds
Started Jun 09 12:26:55 PM PDT 24
Finished Jun 09 12:26:56 PM PDT 24
Peak memory 145616 kb
Host smart-d06978f4-50fb-4242-8679-7cb9fc43d894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964469413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3964469413
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2111099506
Short name T12
Test name
Test status
Simulation time 11578354 ps
CPU time 0.38 seconds
Started Jun 09 12:26:16 PM PDT 24
Finished Jun 09 12:26:17 PM PDT 24
Peak memory 145572 kb
Host smart-6fa17495-cda4-45d7-8cba-64a097719726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111099506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2111099506
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2555753238
Short name T48
Test name
Test status
Simulation time 12080929 ps
CPU time 0.38 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 145676 kb
Host smart-f3c5098a-adb6-481a-9a3b-b2ff42721d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555753238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2555753238
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3384686904
Short name T21
Test name
Test status
Simulation time 10325235 ps
CPU time 0.39 seconds
Started Jun 09 12:26:10 PM PDT 24
Finished Jun 09 12:26:11 PM PDT 24
Peak memory 145644 kb
Host smart-c32e8d48-0f3c-4343-8384-a10b24d079f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384686904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3384686904
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.361083635
Short name T20
Test name
Test status
Simulation time 11821934 ps
CPU time 0.38 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:26:19 PM PDT 24
Peak memory 145684 kb
Host smart-679a2650-7e96-4a92-9eab-9d42ce71c399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361083635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.361083635
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3356378802
Short name T7
Test name
Test status
Simulation time 10458956 ps
CPU time 0.39 seconds
Started Jun 09 12:26:14 PM PDT 24
Finished Jun 09 12:26:16 PM PDT 24
Peak memory 145680 kb
Host smart-882b1285-f385-433b-94fb-1b34d15c69fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356378802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3356378802
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1592829300
Short name T49
Test name
Test status
Simulation time 11342166 ps
CPU time 0.38 seconds
Started Jun 09 12:26:16 PM PDT 24
Finished Jun 09 12:26:17 PM PDT 24
Peak memory 145600 kb
Host smart-b28f66e0-6915-43b7-8530-9e4269219ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592829300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1592829300
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2177431879
Short name T44
Test name
Test status
Simulation time 29847499 ps
CPU time 0.39 seconds
Started Jun 09 12:26:12 PM PDT 24
Finished Jun 09 12:26:13 PM PDT 24
Peak memory 145224 kb
Host smart-2f3d4b3b-7fb7-4060-a6ca-41f9de6415c8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2177431879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2177431879
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1347170267
Short name T55
Test name
Test status
Simulation time 31153040 ps
CPU time 0.41 seconds
Started Jun 09 12:26:10 PM PDT 24
Finished Jun 09 12:26:12 PM PDT 24
Peak memory 145196 kb
Host smart-6f7178e1-7f5e-4463-8b5c-00a8dd937462
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1347170267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1347170267
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2789725329
Short name T46
Test name
Test status
Simulation time 32326787 ps
CPU time 0.4 seconds
Started Jun 09 12:26:18 PM PDT 24
Finished Jun 09 12:26:18 PM PDT 24
Peak memory 145224 kb
Host smart-e1d8b26d-4871-437d-8162-1decfe2dbc5d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2789725329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2789725329
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3861031062
Short name T41
Test name
Test status
Simulation time 28209220 ps
CPU time 0.42 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:26:15 PM PDT 24
Peak memory 145228 kb
Host smart-162fe4a3-b662-4c6a-8a64-7414712b7e3c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3861031062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3861031062
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1305924175
Short name T42
Test name
Test status
Simulation time 31697237 ps
CPU time 0.39 seconds
Started Jun 09 12:26:12 PM PDT 24
Finished Jun 09 12:26:14 PM PDT 24
Peak memory 145224 kb
Host smart-5ea14bb3-27f6-47e0-a6cb-ba4456465df5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1305924175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1305924175
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2734506494
Short name T56
Test name
Test status
Simulation time 30453741 ps
CPU time 0.45 seconds
Started Jun 09 12:26:09 PM PDT 24
Finished Jun 09 12:26:20 PM PDT 24
Peak memory 145208 kb
Host smart-c8200fc3-3366-45fa-9f86-935c6eac733c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2734506494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2734506494
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4179083206
Short name T52
Test name
Test status
Simulation time 31591716 ps
CPU time 0.4 seconds
Started Jun 09 12:26:12 PM PDT 24
Finished Jun 09 12:26:14 PM PDT 24
Peak memory 145224 kb
Host smart-9bccbdf9-293f-4287-bec7-fc0f36fd8c0f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4179083206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.4179083206
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.485886388
Short name T45
Test name
Test status
Simulation time 30173635 ps
CPU time 0.39 seconds
Started Jun 09 12:26:15 PM PDT 24
Finished Jun 09 12:26:16 PM PDT 24
Peak memory 145216 kb
Host smart-359c0082-1f9f-4dc8-9c8d-76720352695d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=485886388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.485886388
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3812536612
Short name T57
Test name
Test status
Simulation time 31035341 ps
CPU time 0.39 seconds
Started Jun 09 12:26:08 PM PDT 24
Finished Jun 09 12:26:09 PM PDT 24
Peak memory 145224 kb
Host smart-1e2524c4-dbba-421d-9101-b9ff205c5c57
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3812536612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3812536612
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1112145092
Short name T51
Test name
Test status
Simulation time 30465122 ps
CPU time 0.39 seconds
Started Jun 09 12:26:13 PM PDT 24
Finished Jun 09 12:26:15 PM PDT 24
Peak memory 145224 kb
Host smart-209427e8-21ab-4e84-901f-277305895897
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1112145092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1112145092
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.4198425666
Short name T54
Test name
Test status
Simulation time 31286269 ps
CPU time 0.47 seconds
Started Jun 09 12:26:11 PM PDT 24
Finished Jun 09 12:26:13 PM PDT 24
Peak memory 145204 kb
Host smart-f34b7077-9cc6-4006-8f73-c7841e5bb94b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4198425666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.4198425666
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2759312861
Short name T43
Test name
Test status
Simulation time 29668512 ps
CPU time 0.41 seconds
Started Jun 09 12:26:11 PM PDT 24
Finished Jun 09 12:26:13 PM PDT 24
Peak memory 145180 kb
Host smart-8c120f10-0a62-4e72-83ee-ba1cba713be9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2759312861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2759312861
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4084787753
Short name T40
Test name
Test status
Simulation time 30082496 ps
CPU time 0.4 seconds
Started Jun 09 12:26:08 PM PDT 24
Finished Jun 09 12:26:10 PM PDT 24
Peak memory 145224 kb
Host smart-3f507992-5572-4bc5-9e78-eb95359f7238
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4084787753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.4084787753
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1550446253
Short name T17
Test name
Test status
Simulation time 30077796 ps
CPU time 0.45 seconds
Started Jun 09 12:26:11 PM PDT 24
Finished Jun 09 12:26:13 PM PDT 24
Peak memory 145224 kb
Host smart-8de89134-6ace-44da-81d2-444616fc51f0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1550446253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1550446253
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3935909223
Short name T4
Test name
Test status
Simulation time 29747481 ps
CPU time 0.38 seconds
Started Jun 09 12:26:23 PM PDT 24
Finished Jun 09 12:26:23 PM PDT 24
Peak memory 145224 kb
Host smart-bab9be4f-d2f5-4b0b-966f-c36e7c6f9d37
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3935909223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3935909223
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.631800999
Short name T16
Test name
Test status
Simulation time 30859706 ps
CPU time 0.4 seconds
Started Jun 09 12:26:10 PM PDT 24
Finished Jun 09 12:26:11 PM PDT 24
Peak memory 145188 kb
Host smart-b0bcbc00-93e7-4730-92dd-d766517fe8b2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=631800999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.631800999
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1782236240
Short name T50
Test name
Test status
Simulation time 30212886 ps
CPU time 0.39 seconds
Started Jun 09 12:26:15 PM PDT 24
Finished Jun 09 12:26:17 PM PDT 24
Peak memory 145224 kb
Host smart-8b9adfae-713c-4e41-b66c-c0caa2509e0f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1782236240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1782236240
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3193964689
Short name T53
Test name
Test status
Simulation time 30982379 ps
CPU time 0.4 seconds
Started Jun 09 12:26:08 PM PDT 24
Finished Jun 09 12:26:09 PM PDT 24
Peak memory 145224 kb
Host smart-d13de1d4-4ed1-4ec9-92a8-5334fc9155c1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3193964689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3193964689
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.2459174953
Short name T28
Test name
Test status
Simulation time 8839693 ps
CPU time 0.37 seconds
Started Jun 09 12:27:02 PM PDT 24
Finished Jun 09 12:27:04 PM PDT 24
Peak memory 145464 kb
Host smart-6b523e24-5708-4da0-bb54-c0fbfaa635c2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2459174953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2459174953
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.2568557081
Short name T36
Test name
Test status
Simulation time 8340826 ps
CPU time 0.36 seconds
Started Jun 09 12:28:16 PM PDT 24
Finished Jun 09 12:28:17 PM PDT 24
Peak memory 145192 kb
Host smart-35424501-9492-4bbd-965d-f4b9c2fed5cb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2568557081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2568557081
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3141308587
Short name T38
Test name
Test status
Simulation time 8875757 ps
CPU time 0.36 seconds
Started Jun 09 12:28:21 PM PDT 24
Finished Jun 09 12:28:21 PM PDT 24
Peak memory 145444 kb
Host smart-4d235412-cdb4-4c3e-9238-12bf1ef967df
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3141308587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3141308587
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.4252827195
Short name T62
Test name
Test status
Simulation time 10142164 ps
CPU time 0.37 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:15 PM PDT 24
Peak memory 145456 kb
Host smart-1eb63b86-ec96-4d96-a804-1bd31a87cf5f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4252827195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.4252827195
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.4250654179
Short name T25
Test name
Test status
Simulation time 9203977 ps
CPU time 0.38 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:26:59 PM PDT 24
Peak memory 145460 kb
Host smart-2c134798-9f36-40f8-b4ba-8757080bb39b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4250654179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.4250654179
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.1679926061
Short name T27
Test name
Test status
Simulation time 8908868 ps
CPU time 0.37 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:08 PM PDT 24
Peak memory 145464 kb
Host smart-f5b10c04-63ed-4a2b-bd45-322a2af49170
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1679926061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1679926061
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1618045105
Short name T59
Test name
Test status
Simulation time 10132674 ps
CPU time 0.38 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:01 PM PDT 24
Peak memory 145464 kb
Host smart-d9e203a1-3455-4307-8252-0fcc062aaa2a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1618045105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1618045105
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2672535135
Short name T39
Test name
Test status
Simulation time 10213619 ps
CPU time 0.42 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:27:59 PM PDT 24
Peak memory 145832 kb
Host smart-ba1efca2-0181-4097-ada8-67e2441d24ba
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2672535135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2672535135
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3086048282
Short name T61
Test name
Test status
Simulation time 9419833 ps
CPU time 0.38 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:07 PM PDT 24
Peak memory 145460 kb
Host smart-6e9f119b-aa9f-41f6-a022-e972f98b712f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3086048282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3086048282
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2345432369
Short name T33
Test name
Test status
Simulation time 8966139 ps
CPU time 0.37 seconds
Started Jun 09 12:28:31 PM PDT 24
Finished Jun 09 12:28:32 PM PDT 24
Peak memory 144724 kb
Host smart-52c1d47d-5c66-4390-a19a-8fb330601318
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2345432369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2345432369
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3920417886
Short name T24
Test name
Test status
Simulation time 9705184 ps
CPU time 0.4 seconds
Started Jun 09 12:27:03 PM PDT 24
Finished Jun 09 12:27:05 PM PDT 24
Peak memory 145460 kb
Host smart-54938b60-6465-4a0a-bec6-5c1fb8c7dc75
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3920417886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3920417886
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3314986015
Short name T30
Test name
Test status
Simulation time 9040446 ps
CPU time 0.37 seconds
Started Jun 09 12:27:37 PM PDT 24
Finished Jun 09 12:27:38 PM PDT 24
Peak memory 145464 kb
Host smart-68f92ba1-7cc4-405e-9e4b-0d4d5c25fe65
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3314986015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3314986015
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3147226322
Short name T34
Test name
Test status
Simulation time 10150000 ps
CPU time 0.38 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:26:55 PM PDT 24
Peak memory 145476 kb
Host smart-08ee1816-87e0-43bf-a925-99ddca7dab8b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3147226322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3147226322
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1571876664
Short name T58
Test name
Test status
Simulation time 8976547 ps
CPU time 0.36 seconds
Started Jun 09 12:28:20 PM PDT 24
Finished Jun 09 12:28:21 PM PDT 24
Peak memory 145456 kb
Host smart-c8f65b5f-e7f9-492a-b76e-d43b07c0b6fd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1571876664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1571876664
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3117991079
Short name T26
Test name
Test status
Simulation time 9018668 ps
CPU time 0.37 seconds
Started Jun 09 12:28:19 PM PDT 24
Finished Jun 09 12:28:20 PM PDT 24
Peak memory 145192 kb
Host smart-2b7b4993-1c18-4056-b9b9-b60f8d57035d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3117991079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3117991079
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1223067413
Short name T60
Test name
Test status
Simulation time 9348091 ps
CPU time 0.38 seconds
Started Jun 09 12:27:05 PM PDT 24
Finished Jun 09 12:27:07 PM PDT 24
Peak memory 145464 kb
Host smart-74ea3439-5649-442f-ad4c-066dd9ff9dd9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1223067413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1223067413
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2563157946
Short name T29
Test name
Test status
Simulation time 9137456 ps
CPU time 0.38 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 145460 kb
Host smart-f82dbf6b-411f-42ab-9019-28014571a018
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2563157946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2563157946
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.338585669
Short name T63
Test name
Test status
Simulation time 8965759 ps
CPU time 0.36 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:26:55 PM PDT 24
Peak memory 145496 kb
Host smart-5a114ab7-8064-4092-ba5f-aafd8138692d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=338585669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.338585669
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1726536851
Short name T35
Test name
Test status
Simulation time 8635086 ps
CPU time 0.37 seconds
Started Jun 09 12:26:52 PM PDT 24
Finished Jun 09 12:26:53 PM PDT 24
Peak memory 145464 kb
Host smart-c1104ded-620b-4d54-8bab-ca6f508a5119
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1726536851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1726536851
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2645946128
Short name T67
Test name
Test status
Simulation time 29758154 ps
CPU time 0.39 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:01 PM PDT 24
Peak memory 145488 kb
Host smart-f9e3cde4-9f1d-4aaa-9a5e-9a614ddad1ea
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2645946128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2645946128
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2814699500
Short name T77
Test name
Test status
Simulation time 29290745 ps
CPU time 0.44 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 145472 kb
Host smart-4406153c-39c4-4bd7-82a8-7b4fa13375a1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2814699500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2814699500
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.848784909
Short name T72
Test name
Test status
Simulation time 26167196 ps
CPU time 0.4 seconds
Started Jun 09 12:27:01 PM PDT 24
Finished Jun 09 12:27:02 PM PDT 24
Peak memory 145476 kb
Host smart-0603e59c-fb89-40bf-86dd-6f17788bfb3f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=848784909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.848784909
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2622596656
Short name T76
Test name
Test status
Simulation time 25754793 ps
CPU time 0.38 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:26:59 PM PDT 24
Peak memory 145484 kb
Host smart-bdbe0bb2-9ba8-498c-a67e-63408199b477
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2622596656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2622596656
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1562492359
Short name T5
Test name
Test status
Simulation time 27690342 ps
CPU time 0.46 seconds
Started Jun 09 12:26:59 PM PDT 24
Finished Jun 09 12:27:00 PM PDT 24
Peak memory 145480 kb
Host smart-5076d5b7-625b-4ed7-b0e5-4fe9928c91c6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1562492359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1562492359
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.4060309524
Short name T69
Test name
Test status
Simulation time 26182192 ps
CPU time 0.38 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:26:58 PM PDT 24
Peak memory 145480 kb
Host smart-1746c1e4-e1dc-4f07-8e64-616ca06398b3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4060309524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.4060309524
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2398861917
Short name T66
Test name
Test status
Simulation time 27230590 ps
CPU time 0.39 seconds
Started Jun 09 12:26:58 PM PDT 24
Finished Jun 09 12:26:59 PM PDT 24
Peak memory 145480 kb
Host smart-d5a3db70-25d2-46bf-9a51-4bd3c874fdab
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2398861917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2398861917
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.584005682
Short name T75
Test name
Test status
Simulation time 29845643 ps
CPU time 0.4 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:08 PM PDT 24
Peak memory 145464 kb
Host smart-13de9afd-c677-422c-829e-dc3f7c03706b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=584005682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.584005682
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1818112499
Short name T79
Test name
Test status
Simulation time 27963476 ps
CPU time 0.4 seconds
Started Jun 09 12:27:00 PM PDT 24
Finished Jun 09 12:27:00 PM PDT 24
Peak memory 145484 kb
Host smart-a47cc9ac-c179-47b0-be71-445a5cd4c7fe
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1818112499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1818112499
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1212639722
Short name T78
Test name
Test status
Simulation time 28247571 ps
CPU time 0.41 seconds
Started Jun 09 12:26:52 PM PDT 24
Finished Jun 09 12:26:53 PM PDT 24
Peak memory 145484 kb
Host smart-ea762d6d-12ac-4149-b126-87dd7b4a4d77
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1212639722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1212639722
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1191224036
Short name T68
Test name
Test status
Simulation time 25884197 ps
CPU time 0.39 seconds
Started Jun 09 12:27:11 PM PDT 24
Finished Jun 09 12:27:12 PM PDT 24
Peak memory 145468 kb
Host smart-6d5e218a-4ac6-4223-9dca-86250ca5ec02
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1191224036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1191224036
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2860983705
Short name T31
Test name
Test status
Simulation time 25638934 ps
CPU time 0.39 seconds
Started Jun 09 12:26:55 PM PDT 24
Finished Jun 09 12:26:56 PM PDT 24
Peak memory 145452 kb
Host smart-5ec91f33-3414-452b-8ddb-6490be2dd334
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2860983705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2860983705
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3415896001
Short name T74
Test name
Test status
Simulation time 27416216 ps
CPU time 0.41 seconds
Started Jun 09 12:26:51 PM PDT 24
Finished Jun 09 12:26:51 PM PDT 24
Peak memory 145480 kb
Host smart-fa8db2c9-5173-4021-bd37-b21c10c73965
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3415896001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3415896001
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.637495491
Short name T70
Test name
Test status
Simulation time 27976116 ps
CPU time 0.44 seconds
Started Jun 09 12:28:31 PM PDT 24
Finished Jun 09 12:28:33 PM PDT 24
Peak memory 145460 kb
Host smart-96c94258-fa8b-439c-8134-f8fea8df8408
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=637495491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.637495491
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1431578169
Short name T32
Test name
Test status
Simulation time 26837583 ps
CPU time 0.39 seconds
Started Jun 09 12:26:57 PM PDT 24
Finished Jun 09 12:26:58 PM PDT 24
Peak memory 145476 kb
Host smart-cc1c249c-6e28-4e4a-aa2a-8d3dc42e2c12
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1431578169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1431578169
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2124952604
Short name T73
Test name
Test status
Simulation time 27177147 ps
CPU time 0.4 seconds
Started Jun 09 12:27:07 PM PDT 24
Finished Jun 09 12:27:10 PM PDT 24
Peak memory 145440 kb
Host smart-85033bb6-0d89-40fe-aea3-23e5804d3e29
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2124952604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2124952604
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3999595835
Short name T71
Test name
Test status
Simulation time 27264474 ps
CPU time 0.39 seconds
Started Jun 09 12:27:06 PM PDT 24
Finished Jun 09 12:27:09 PM PDT 24
Peak memory 145480 kb
Host smart-07bc5f2e-c7d2-4391-8ba7-7c4cf4071178
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3999595835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3999595835
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3938602798
Short name T64
Test name
Test status
Simulation time 26004706 ps
CPU time 0.38 seconds
Started Jun 09 12:26:54 PM PDT 24
Finished Jun 09 12:26:55 PM PDT 24
Peak memory 145464 kb
Host smart-a3734788-e083-4825-8bd7-7d9ca22644a7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3938602798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3938602798
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4287167506
Short name T65
Test name
Test status
Simulation time 28737078 ps
CPU time 0.38 seconds
Started Jun 09 12:28:25 PM PDT 24
Finished Jun 09 12:28:26 PM PDT 24
Peak memory 145468 kb
Host smart-c4f5b5c3-8e54-43d7-b94c-f9adf2c29828
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4287167506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.4287167506
Directory /workspace/9.prim_sync_fatal_alert/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%