Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 78
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.88 88.88 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/8.prim_async_alert.3782355586
92.01 3.13 100.00 0.00 93.75 0.00 100.00 0.00 85.71 7.14 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/0.prim_sync_alert.720410835
94.15 2.15 100.00 0.00 93.75 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 9.30 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1034473303
94.85 0.69 100.00 0.00 97.92 4.17 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.721159161
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3979093045

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3873534108
/workspace/coverage/default/1.prim_async_alert.2440041895
/workspace/coverage/default/10.prim_async_alert.1571718557
/workspace/coverage/default/11.prim_async_alert.2394770736
/workspace/coverage/default/12.prim_async_alert.457549754
/workspace/coverage/default/13.prim_async_alert.775859614
/workspace/coverage/default/14.prim_async_alert.649193095
/workspace/coverage/default/15.prim_async_alert.277502667
/workspace/coverage/default/16.prim_async_alert.1541054106
/workspace/coverage/default/17.prim_async_alert.3378959040
/workspace/coverage/default/18.prim_async_alert.1206269974
/workspace/coverage/default/19.prim_async_alert.969873332
/workspace/coverage/default/2.prim_async_alert.2596527371
/workspace/coverage/default/3.prim_async_alert.4196425565
/workspace/coverage/default/4.prim_async_alert.4194540191
/workspace/coverage/default/5.prim_async_alert.1018078372
/workspace/coverage/default/6.prim_async_alert.1749350403
/workspace/coverage/default/7.prim_async_alert.1302931292
/workspace/coverage/default/9.prim_async_alert.3435542563
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4148939535
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.309309692
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2703037648
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1773728948
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.458786101
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4162989569
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1298416712
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3861634540
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3964100017
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2748075915
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.726604173
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.339366754
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3128236578
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2095083706
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.968374225
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1599252124
/workspace/coverage/sync_alert/1.prim_sync_alert.4269520567
/workspace/coverage/sync_alert/10.prim_sync_alert.1076946488
/workspace/coverage/sync_alert/11.prim_sync_alert.3194833983
/workspace/coverage/sync_alert/12.prim_sync_alert.1562903721
/workspace/coverage/sync_alert/13.prim_sync_alert.163381956
/workspace/coverage/sync_alert/14.prim_sync_alert.559369600
/workspace/coverage/sync_alert/15.prim_sync_alert.3126177170
/workspace/coverage/sync_alert/16.prim_sync_alert.2322776469
/workspace/coverage/sync_alert/17.prim_sync_alert.1700913726
/workspace/coverage/sync_alert/18.prim_sync_alert.3099550333
/workspace/coverage/sync_alert/19.prim_sync_alert.447906983
/workspace/coverage/sync_alert/2.prim_sync_alert.3208796719
/workspace/coverage/sync_alert/3.prim_sync_alert.1365261946
/workspace/coverage/sync_alert/4.prim_sync_alert.2798856917
/workspace/coverage/sync_alert/5.prim_sync_alert.2429141944
/workspace/coverage/sync_alert/6.prim_sync_alert.1484882459
/workspace/coverage/sync_alert/7.prim_sync_alert.3867745750
/workspace/coverage/sync_alert/8.prim_sync_alert.2905200014
/workspace/coverage/sync_alert/9.prim_sync_alert.997414233
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1693126512
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2710342296
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3309328363
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.581454840
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3118835056
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.478599693
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1979360262
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2970956716
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1627160279
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.544835723
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.617173899
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2276616607
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.244701345
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1491489903
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4243883573
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1399684716
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.824077290
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3703820421
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3801027477



Total test records in report: 78
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/13.prim_async_alert.775859614 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:19 PM PDT 24 10637999 ps
T2 /workspace/coverage/default/6.prim_async_alert.1749350403 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:17 PM PDT 24 10676143 ps
T3 /workspace/coverage/default/8.prim_async_alert.3782355586 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:19 PM PDT 24 11235532 ps
T9 /workspace/coverage/default/18.prim_async_alert.1206269974 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:19 PM PDT 24 10782800 ps
T7 /workspace/coverage/default/2.prim_async_alert.2596527371 Jun 10 04:42:35 PM PDT 24 Jun 10 04:42:36 PM PDT 24 10984705 ps
T20 /workspace/coverage/default/10.prim_async_alert.1571718557 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:18 PM PDT 24 10494649 ps
T8 /workspace/coverage/default/7.prim_async_alert.1302931292 Jun 10 04:42:19 PM PDT 24 Jun 10 04:42:21 PM PDT 24 11131644 ps
T10 /workspace/coverage/default/14.prim_async_alert.649193095 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:18 PM PDT 24 10774631 ps
T21 /workspace/coverage/default/11.prim_async_alert.2394770736 Jun 10 04:42:14 PM PDT 24 Jun 10 04:42:16 PM PDT 24 11801485 ps
T17 /workspace/coverage/default/12.prim_async_alert.457549754 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:20 PM PDT 24 11787255 ps
T22 /workspace/coverage/default/1.prim_async_alert.2440041895 Jun 10 04:42:21 PM PDT 24 Jun 10 04:42:22 PM PDT 24 11064046 ps
T11 /workspace/coverage/default/19.prim_async_alert.969873332 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:18 PM PDT 24 11654598 ps
T13 /workspace/coverage/default/15.prim_async_alert.277502667 Jun 10 04:42:19 PM PDT 24 Jun 10 04:42:21 PM PDT 24 11658898 ps
T50 /workspace/coverage/default/5.prim_async_alert.1018078372 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:16 PM PDT 24 11557166 ps
T14 /workspace/coverage/default/0.prim_async_alert.3873534108 Jun 10 04:42:22 PM PDT 24 Jun 10 04:42:23 PM PDT 24 11400742 ps
T51 /workspace/coverage/default/3.prim_async_alert.4196425565 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:20 PM PDT 24 11719599 ps
T15 /workspace/coverage/default/4.prim_async_alert.4194540191 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:18 PM PDT 24 12201530 ps
T23 /workspace/coverage/default/17.prim_async_alert.3378959040 Jun 10 04:42:19 PM PDT 24 Jun 10 04:42:21 PM PDT 24 10294595 ps
T18 /workspace/coverage/default/9.prim_async_alert.3435542563 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 11429230 ps
T52 /workspace/coverage/default/16.prim_async_alert.1541054106 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 10965827 ps
T44 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2748075915 Jun 10 07:33:42 PM PDT 24 Jun 10 07:33:46 PM PDT 24 30066451 ps
T19 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.339366754 Jun 10 07:33:38 PM PDT 24 Jun 10 07:33:40 PM PDT 24 28634444 ps
T24 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1034473303 Jun 10 07:33:39 PM PDT 24 Jun 10 07:33:42 PM PDT 24 29056619 ps
T45 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3128236578 Jun 10 07:33:43 PM PDT 24 Jun 10 07:33:46 PM PDT 24 28987089 ps
T43 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1298416712 Jun 10 07:33:43 PM PDT 24 Jun 10 07:33:46 PM PDT 24 27587191 ps
T46 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1599252124 Jun 10 07:33:41 PM PDT 24 Jun 10 07:33:45 PM PDT 24 29716347 ps
T47 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4162989569 Jun 10 07:33:37 PM PDT 24 Jun 10 07:33:38 PM PDT 24 31272803 ps
T4 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.721159161 Jun 10 07:33:37 PM PDT 24 Jun 10 07:33:38 PM PDT 24 31580670 ps
T48 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3964100017 Jun 10 07:33:39 PM PDT 24 Jun 10 07:33:42 PM PDT 24 30076421 ps
T49 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4148939535 Jun 10 07:33:40 PM PDT 24 Jun 10 07:33:43 PM PDT 24 31372137 ps
T53 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1773728948 Jun 10 07:33:39 PM PDT 24 Jun 10 07:33:41 PM PDT 24 29564757 ps
T42 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.726604173 Jun 10 07:33:39 PM PDT 24 Jun 10 07:33:41 PM PDT 24 30521826 ps
T54 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.309309692 Jun 10 07:33:45 PM PDT 24 Jun 10 07:33:48 PM PDT 24 30828497 ps
T16 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2095083706 Jun 10 07:33:40 PM PDT 24 Jun 10 07:33:43 PM PDT 24 30350061 ps
T5 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.968374225 Jun 10 07:33:41 PM PDT 24 Jun 10 07:33:44 PM PDT 24 27200212 ps
T55 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.458786101 Jun 10 07:33:41 PM PDT 24 Jun 10 07:33:45 PM PDT 24 30393627 ps
T6 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3861634540 Jun 10 07:33:43 PM PDT 24 Jun 10 07:33:46 PM PDT 24 31755506 ps
T56 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2703037648 Jun 10 07:33:39 PM PDT 24 Jun 10 07:33:41 PM PDT 24 30916439 ps
T25 /workspace/coverage/sync_alert/3.prim_sync_alert.1365261946 Jun 10 07:30:32 PM PDT 24 Jun 10 07:30:38 PM PDT 24 9792787 ps
T26 /workspace/coverage/sync_alert/17.prim_sync_alert.1700913726 Jun 10 07:30:44 PM PDT 24 Jun 10 07:30:48 PM PDT 24 9331058 ps
T35 /workspace/coverage/sync_alert/14.prim_sync_alert.559369600 Jun 10 07:30:45 PM PDT 24 Jun 10 07:30:50 PM PDT 24 9209306 ps
T36 /workspace/coverage/sync_alert/10.prim_sync_alert.1076946488 Jun 10 07:30:44 PM PDT 24 Jun 10 07:30:48 PM PDT 24 8149448 ps
T27 /workspace/coverage/sync_alert/16.prim_sync_alert.2322776469 Jun 10 07:30:44 PM PDT 24 Jun 10 07:30:49 PM PDT 24 8911952 ps
T37 /workspace/coverage/sync_alert/5.prim_sync_alert.2429141944 Jun 10 07:30:30 PM PDT 24 Jun 10 07:30:36 PM PDT 24 9011433 ps
T38 /workspace/coverage/sync_alert/6.prim_sync_alert.1484882459 Jun 10 07:30:30 PM PDT 24 Jun 10 07:30:36 PM PDT 24 10244846 ps
T39 /workspace/coverage/sync_alert/2.prim_sync_alert.3208796719 Jun 10 07:30:29 PM PDT 24 Jun 10 07:30:35 PM PDT 24 9450266 ps
T40 /workspace/coverage/sync_alert/0.prim_sync_alert.720410835 Jun 10 07:30:31 PM PDT 24 Jun 10 07:30:37 PM PDT 24 9656080 ps
T41 /workspace/coverage/sync_alert/12.prim_sync_alert.1562903721 Jun 10 07:30:45 PM PDT 24 Jun 10 07:30:51 PM PDT 24 9928403 ps
T57 /workspace/coverage/sync_alert/8.prim_sync_alert.2905200014 Jun 10 07:30:32 PM PDT 24 Jun 10 07:30:37 PM PDT 24 8235837 ps
T28 /workspace/coverage/sync_alert/1.prim_sync_alert.4269520567 Jun 10 07:30:29 PM PDT 24 Jun 10 07:30:36 PM PDT 24 10208065 ps
T58 /workspace/coverage/sync_alert/4.prim_sync_alert.2798856917 Jun 10 07:30:32 PM PDT 24 Jun 10 07:30:37 PM PDT 24 9515085 ps
T29 /workspace/coverage/sync_alert/19.prim_sync_alert.447906983 Jun 10 07:30:43 PM PDT 24 Jun 10 07:30:47 PM PDT 24 9198080 ps
T59 /workspace/coverage/sync_alert/11.prim_sync_alert.3194833983 Jun 10 07:30:44 PM PDT 24 Jun 10 07:30:49 PM PDT 24 8333614 ps
T60 /workspace/coverage/sync_alert/9.prim_sync_alert.997414233 Jun 10 07:30:31 PM PDT 24 Jun 10 07:30:37 PM PDT 24 9236868 ps
T30 /workspace/coverage/sync_alert/7.prim_sync_alert.3867745750 Jun 10 07:30:29 PM PDT 24 Jun 10 07:30:36 PM PDT 24 8551608 ps
T61 /workspace/coverage/sync_alert/15.prim_sync_alert.3126177170 Jun 10 07:30:43 PM PDT 24 Jun 10 07:30:46 PM PDT 24 9106677 ps
T31 /workspace/coverage/sync_alert/13.prim_sync_alert.163381956 Jun 10 07:30:42 PM PDT 24 Jun 10 07:30:45 PM PDT 24 8873704 ps
T62 /workspace/coverage/sync_alert/18.prim_sync_alert.3099550333 Jun 10 07:30:43 PM PDT 24 Jun 10 07:30:46 PM PDT 24 8653053 ps
T63 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3309328363 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:18 PM PDT 24 29772106 ps
T32 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1491489903 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:19 PM PDT 24 25014762 ps
T64 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1627160279 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:20 PM PDT 24 29101038 ps
T65 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.617173899 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:19 PM PDT 24 27610949 ps
T33 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.244701345 Jun 10 04:42:18 PM PDT 24 Jun 10 04:42:21 PM PDT 24 30191198 ps
T66 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3703820421 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:18 PM PDT 24 27263210 ps
T34 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1979360262 Jun 10 04:42:15 PM PDT 24 Jun 10 04:42:17 PM PDT 24 28201189 ps
T67 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1693126512 Jun 10 04:42:24 PM PDT 24 Jun 10 04:42:25 PM PDT 24 27392399 ps
T68 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2970956716 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:18 PM PDT 24 29896594 ps
T69 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3118835056 Jun 10 04:42:14 PM PDT 24 Jun 10 04:42:16 PM PDT 24 27901977 ps
T70 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.544835723 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:18 PM PDT 24 29950578 ps
T71 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2276616607 Jun 10 04:42:18 PM PDT 24 Jun 10 04:42:21 PM PDT 24 29848842 ps
T72 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.478599693 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:19 PM PDT 24 30175253 ps
T73 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4243883573 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:18 PM PDT 24 26609453 ps
T74 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.581454840 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:18 PM PDT 24 27418462 ps
T12 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3979093045 Jun 10 04:42:17 PM PDT 24 Jun 10 04:42:19 PM PDT 24 24772432 ps
T75 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.824077290 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 26090824 ps
T76 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3801027477 Jun 10 04:42:14 PM PDT 24 Jun 10 04:42:16 PM PDT 24 28125215 ps
T77 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1399684716 Jun 10 04:42:16 PM PDT 24 Jun 10 04:42:19 PM PDT 24 28692987 ps
T78 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2710342296 Jun 10 04:42:28 PM PDT 24 Jun 10 04:42:29 PM PDT 24 27611811 ps

Test location /workspace/coverage/default/8.prim_async_alert.3782355586
Short name T3
Test name
Test status
Simulation time 11235532 ps
CPU time 0.38 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 145636 kb
Host smart-7e699591-b640-472f-b895-2fedafe28987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782355586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3782355586
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.720410835
Short name T40
Test name
Test status
Simulation time 9656080 ps
CPU time 0.38 seconds
Started Jun 10 07:30:31 PM PDT 24
Finished Jun 10 07:30:37 PM PDT 24
Peak memory 145624 kb
Host smart-9d92f94f-2653-43ca-8c62-834e05a103ab
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=720410835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.720410835
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1034473303
Short name T24
Test name
Test status
Simulation time 29056619 ps
CPU time 0.4 seconds
Started Jun 10 07:33:39 PM PDT 24
Finished Jun 10 07:33:42 PM PDT 24
Peak memory 145320 kb
Host smart-b686691c-a547-4a14-baf0-f808fbfb8a8f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1034473303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1034473303
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.721159161
Short name T4
Test name
Test status
Simulation time 31580670 ps
CPU time 0.4 seconds
Started Jun 10 07:33:37 PM PDT 24
Finished Jun 10 07:33:38 PM PDT 24
Peak memory 145140 kb
Host smart-c4d93a2f-0b53-42a5-b5d0-aaa98cf06ef5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=721159161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.721159161
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3979093045
Short name T12
Test name
Test status
Simulation time 24772432 ps
CPU time 0.38 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 145428 kb
Host smart-45bf908f-01bf-4c8d-996a-cca8463fdfc2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3979093045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3979093045
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3873534108
Short name T14
Test name
Test status
Simulation time 11400742 ps
CPU time 0.39 seconds
Started Jun 10 04:42:22 PM PDT 24
Finished Jun 10 04:42:23 PM PDT 24
Peak memory 145676 kb
Host smart-ecea3d26-7d34-4e86-b9b2-cfc869e9741c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873534108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3873534108
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2440041895
Short name T22
Test name
Test status
Simulation time 11064046 ps
CPU time 0.39 seconds
Started Jun 10 04:42:21 PM PDT 24
Finished Jun 10 04:42:22 PM PDT 24
Peak memory 145424 kb
Host smart-97c52f34-688e-41c1-8bc4-6679502e4b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440041895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2440041895
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1571718557
Short name T20
Test name
Test status
Simulation time 10494649 ps
CPU time 0.36 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 145656 kb
Host smart-d19afea8-e576-42d1-b9ce-aee0f31c19e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571718557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1571718557
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2394770736
Short name T21
Test name
Test status
Simulation time 11801485 ps
CPU time 0.43 seconds
Started Jun 10 04:42:14 PM PDT 24
Finished Jun 10 04:42:16 PM PDT 24
Peak memory 143908 kb
Host smart-0f53785f-cbdb-4c2e-83f1-2fe98b3b4666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394770736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2394770736
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.457549754
Short name T17
Test name
Test status
Simulation time 11787255 ps
CPU time 0.39 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 145656 kb
Host smart-e0787112-de3e-48c2-b895-a0231770ed89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457549754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.457549754
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.775859614
Short name T1
Test name
Test status
Simulation time 10637999 ps
CPU time 0.4 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 144784 kb
Host smart-24bd708c-04e6-4397-b2d2-ae368604e1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775859614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.775859614
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.649193095
Short name T10
Test name
Test status
Simulation time 10774631 ps
CPU time 0.38 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 145664 kb
Host smart-cf5e7fb4-2f76-48b1-b6f4-6b55764d41aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649193095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.649193095
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.277502667
Short name T13
Test name
Test status
Simulation time 11658898 ps
CPU time 0.38 seconds
Started Jun 10 04:42:19 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 145620 kb
Host smart-3cd15252-ed84-44c2-9eb9-bb8af56672a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277502667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.277502667
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1541054106
Short name T52
Test name
Test status
Simulation time 10965827 ps
CPU time 0.4 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 145684 kb
Host smart-8b4362f9-f543-4280-9881-2ff029e565dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541054106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1541054106
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3378959040
Short name T23
Test name
Test status
Simulation time 10294595 ps
CPU time 0.37 seconds
Started Jun 10 04:42:19 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 145632 kb
Host smart-eeae74cf-3265-4ff5-87f2-93a2710f0b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378959040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3378959040
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1206269974
Short name T9
Test name
Test status
Simulation time 10782800 ps
CPU time 0.38 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 145632 kb
Host smart-63d89c82-22dc-4342-bfcf-fce1c332361a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206269974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1206269974
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.969873332
Short name T11
Test name
Test status
Simulation time 11654598 ps
CPU time 0.41 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 145596 kb
Host smart-4820b168-03f8-4d58-8d3f-de4543243fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969873332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.969873332
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2596527371
Short name T7
Test name
Test status
Simulation time 10984705 ps
CPU time 0.39 seconds
Started Jun 10 04:42:35 PM PDT 24
Finished Jun 10 04:42:36 PM PDT 24
Peak memory 145668 kb
Host smart-f3339b7c-f11b-4bf4-b52c-5e21a5916f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596527371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2596527371
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.4196425565
Short name T51
Test name
Test status
Simulation time 11719599 ps
CPU time 0.37 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 145500 kb
Host smart-e16bbfd1-ce07-478a-8ab6-e0ab9c5bd9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196425565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.4196425565
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.4194540191
Short name T15
Test name
Test status
Simulation time 12201530 ps
CPU time 0.38 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 145684 kb
Host smart-d1764da0-0d11-46cb-867b-eb55cd833a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194540191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.4194540191
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1018078372
Short name T50
Test name
Test status
Simulation time 11557166 ps
CPU time 0.38 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:16 PM PDT 24
Peak memory 144708 kb
Host smart-45d5b239-3a31-4580-b9f7-0cd24bb6d242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018078372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1018078372
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1749350403
Short name T2
Test name
Test status
Simulation time 10676143 ps
CPU time 0.38 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:17 PM PDT 24
Peak memory 145480 kb
Host smart-a5874cb8-97e2-42fa-b03d-dd76f30a2c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749350403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1749350403
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1302931292
Short name T8
Test name
Test status
Simulation time 11131644 ps
CPU time 0.45 seconds
Started Jun 10 04:42:19 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 145620 kb
Host smart-211b92be-380f-4636-9fa0-52d2439dc6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302931292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1302931292
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3435542563
Short name T18
Test name
Test status
Simulation time 11429230 ps
CPU time 0.38 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 145524 kb
Host smart-622283c6-8105-4ef6-88f4-58360e1b3b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435542563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3435542563
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4148939535
Short name T49
Test name
Test status
Simulation time 31372137 ps
CPU time 0.39 seconds
Started Jun 10 07:33:40 PM PDT 24
Finished Jun 10 07:33:43 PM PDT 24
Peak memory 145328 kb
Host smart-862cad74-b71b-4c89-a495-f160a4b162b2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4148939535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4148939535
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.309309692
Short name T54
Test name
Test status
Simulation time 30828497 ps
CPU time 0.41 seconds
Started Jun 10 07:33:45 PM PDT 24
Finished Jun 10 07:33:48 PM PDT 24
Peak memory 145336 kb
Host smart-a138e53e-902c-4610-80c0-594c3241efe1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=309309692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.309309692
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2703037648
Short name T56
Test name
Test status
Simulation time 30916439 ps
CPU time 0.39 seconds
Started Jun 10 07:33:39 PM PDT 24
Finished Jun 10 07:33:41 PM PDT 24
Peak memory 145320 kb
Host smart-33ae3080-ad32-4a62-9526-21540231bccd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2703037648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2703037648
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1773728948
Short name T53
Test name
Test status
Simulation time 29564757 ps
CPU time 0.39 seconds
Started Jun 10 07:33:39 PM PDT 24
Finished Jun 10 07:33:41 PM PDT 24
Peak memory 145320 kb
Host smart-df7bd98f-7c57-4d12-b973-0e6c535e569b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1773728948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1773728948
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.458786101
Short name T55
Test name
Test status
Simulation time 30393627 ps
CPU time 0.4 seconds
Started Jun 10 07:33:41 PM PDT 24
Finished Jun 10 07:33:45 PM PDT 24
Peak memory 145320 kb
Host smart-e96f3259-b66f-4bfc-970d-55494e961ef6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=458786101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.458786101
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4162989569
Short name T47
Test name
Test status
Simulation time 31272803 ps
CPU time 0.4 seconds
Started Jun 10 07:33:37 PM PDT 24
Finished Jun 10 07:33:38 PM PDT 24
Peak memory 145312 kb
Host smart-4d55d5cc-44d6-475f-830b-af7f809d063c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4162989569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.4162989569
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1298416712
Short name T43
Test name
Test status
Simulation time 27587191 ps
CPU time 0.39 seconds
Started Jun 10 07:33:43 PM PDT 24
Finished Jun 10 07:33:46 PM PDT 24
Peak memory 145324 kb
Host smart-91c1eeca-f68d-4a49-89c0-8d14b6de2d8a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1298416712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1298416712
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3861634540
Short name T6
Test name
Test status
Simulation time 31755506 ps
CPU time 0.41 seconds
Started Jun 10 07:33:43 PM PDT 24
Finished Jun 10 07:33:46 PM PDT 24
Peak memory 145332 kb
Host smart-d21b9992-050f-4d2c-a5f7-c75d8dea91e7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3861634540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3861634540
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3964100017
Short name T48
Test name
Test status
Simulation time 30076421 ps
CPU time 0.4 seconds
Started Jun 10 07:33:39 PM PDT 24
Finished Jun 10 07:33:42 PM PDT 24
Peak memory 145332 kb
Host smart-ab9ef3ac-952b-4a13-adf5-c3d24cea7802
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3964100017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3964100017
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2748075915
Short name T44
Test name
Test status
Simulation time 30066451 ps
CPU time 0.4 seconds
Started Jun 10 07:33:42 PM PDT 24
Finished Jun 10 07:33:46 PM PDT 24
Peak memory 145328 kb
Host smart-456b8923-06a3-4b58-bfb1-21ff35d68aff
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2748075915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2748075915
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.726604173
Short name T42
Test name
Test status
Simulation time 30521826 ps
CPU time 0.39 seconds
Started Jun 10 07:33:39 PM PDT 24
Finished Jun 10 07:33:41 PM PDT 24
Peak memory 145272 kb
Host smart-694180d7-60e4-42b0-aed1-c8310bdb59ed
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=726604173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.726604173
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.339366754
Short name T19
Test name
Test status
Simulation time 28634444 ps
CPU time 0.38 seconds
Started Jun 10 07:33:38 PM PDT 24
Finished Jun 10 07:33:40 PM PDT 24
Peak memory 145336 kb
Host smart-cc9d8d49-f870-44b0-b48e-07f15b87c380
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=339366754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.339366754
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3128236578
Short name T45
Test name
Test status
Simulation time 28987089 ps
CPU time 0.4 seconds
Started Jun 10 07:33:43 PM PDT 24
Finished Jun 10 07:33:46 PM PDT 24
Peak memory 145324 kb
Host smart-4d9ddd3e-db9a-4c43-9811-627991dfe4ad
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3128236578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3128236578
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2095083706
Short name T16
Test name
Test status
Simulation time 30350061 ps
CPU time 0.39 seconds
Started Jun 10 07:33:40 PM PDT 24
Finished Jun 10 07:33:43 PM PDT 24
Peak memory 145320 kb
Host smart-10cfd582-cb2e-44b1-b32e-7606159eb66c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2095083706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2095083706
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.968374225
Short name T5
Test name
Test status
Simulation time 27200212 ps
CPU time 0.4 seconds
Started Jun 10 07:33:41 PM PDT 24
Finished Jun 10 07:33:44 PM PDT 24
Peak memory 145316 kb
Host smart-4dcf1545-99bb-4995-b8db-491760de2fb0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=968374225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.968374225
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.1599252124
Short name T46
Test name
Test status
Simulation time 29716347 ps
CPU time 0.4 seconds
Started Jun 10 07:33:41 PM PDT 24
Finished Jun 10 07:33:45 PM PDT 24
Peak memory 145332 kb
Host smart-ad532402-9d0c-4e02-9224-f79090c80816
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1599252124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.1599252124
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.4269520567
Short name T28
Test name
Test status
Simulation time 10208065 ps
CPU time 0.38 seconds
Started Jun 10 07:30:29 PM PDT 24
Finished Jun 10 07:30:36 PM PDT 24
Peak memory 145564 kb
Host smart-f13dd01f-5599-4aa2-b608-e71451a9cad5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4269520567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.4269520567
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1076946488
Short name T36
Test name
Test status
Simulation time 8149448 ps
CPU time 0.39 seconds
Started Jun 10 07:30:44 PM PDT 24
Finished Jun 10 07:30:48 PM PDT 24
Peak memory 145580 kb
Host smart-efe2e01a-bef9-476b-a0fc-b3916e1307e5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1076946488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1076946488
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3194833983
Short name T59
Test name
Test status
Simulation time 8333614 ps
CPU time 0.39 seconds
Started Jun 10 07:30:44 PM PDT 24
Finished Jun 10 07:30:49 PM PDT 24
Peak memory 145584 kb
Host smart-652f2259-89ec-4e26-8113-34d85ed71ccb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3194833983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3194833983
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1562903721
Short name T41
Test name
Test status
Simulation time 9928403 ps
CPU time 0.43 seconds
Started Jun 10 07:30:45 PM PDT 24
Finished Jun 10 07:30:51 PM PDT 24
Peak memory 145584 kb
Host smart-e0d69ea7-5901-49b8-94e6-8d3939b68646
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1562903721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1562903721
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.163381956
Short name T31
Test name
Test status
Simulation time 8873704 ps
CPU time 0.41 seconds
Started Jun 10 07:30:42 PM PDT 24
Finished Jun 10 07:30:45 PM PDT 24
Peak memory 145596 kb
Host smart-683037ea-3f42-411e-88a8-cd996d58957b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=163381956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.163381956
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.559369600
Short name T35
Test name
Test status
Simulation time 9209306 ps
CPU time 0.38 seconds
Started Jun 10 07:30:45 PM PDT 24
Finished Jun 10 07:30:50 PM PDT 24
Peak memory 145604 kb
Host smart-dc2faa40-bbcc-4c8b-b1d7-1d729dd22c57
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=559369600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.559369600
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3126177170
Short name T61
Test name
Test status
Simulation time 9106677 ps
CPU time 0.39 seconds
Started Jun 10 07:30:43 PM PDT 24
Finished Jun 10 07:30:46 PM PDT 24
Peak memory 145568 kb
Host smart-5d5ef565-69e1-46b8-b924-f05cc8315fe5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3126177170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3126177170
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2322776469
Short name T27
Test name
Test status
Simulation time 8911952 ps
CPU time 0.38 seconds
Started Jun 10 07:30:44 PM PDT 24
Finished Jun 10 07:30:49 PM PDT 24
Peak memory 145580 kb
Host smart-41fc0c32-4924-4f52-97de-7d8ab8fbef02
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2322776469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2322776469
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1700913726
Short name T26
Test name
Test status
Simulation time 9331058 ps
CPU time 0.39 seconds
Started Jun 10 07:30:44 PM PDT 24
Finished Jun 10 07:30:48 PM PDT 24
Peak memory 145584 kb
Host smart-fd6d0183-f512-4536-a595-5ba8086ba76f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1700913726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1700913726
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3099550333
Short name T62
Test name
Test status
Simulation time 8653053 ps
CPU time 0.39 seconds
Started Jun 10 07:30:43 PM PDT 24
Finished Jun 10 07:30:46 PM PDT 24
Peak memory 145648 kb
Host smart-cdbfe23c-2711-46b8-b458-ed7422e15d28
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3099550333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3099550333
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.447906983
Short name T29
Test name
Test status
Simulation time 9198080 ps
CPU time 0.38 seconds
Started Jun 10 07:30:43 PM PDT 24
Finished Jun 10 07:30:47 PM PDT 24
Peak memory 145648 kb
Host smart-2fa62e16-4d0d-488a-a8b4-9543cd345ec0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=447906983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.447906983
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3208796719
Short name T39
Test name
Test status
Simulation time 9450266 ps
CPU time 0.4 seconds
Started Jun 10 07:30:29 PM PDT 24
Finished Jun 10 07:30:35 PM PDT 24
Peak memory 145564 kb
Host smart-fb53452b-3bd2-425a-b1ef-88b72c3c5021
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3208796719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3208796719
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1365261946
Short name T25
Test name
Test status
Simulation time 9792787 ps
CPU time 0.4 seconds
Started Jun 10 07:30:32 PM PDT 24
Finished Jun 10 07:30:38 PM PDT 24
Peak memory 145584 kb
Host smart-48ccc9f2-f074-4dd8-9e27-726f7d2bff0b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1365261946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1365261946
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2798856917
Short name T58
Test name
Test status
Simulation time 9515085 ps
CPU time 0.39 seconds
Started Jun 10 07:30:32 PM PDT 24
Finished Jun 10 07:30:37 PM PDT 24
Peak memory 145040 kb
Host smart-063f3e5d-0f6a-4b8e-ba89-2f0ea3f2f0b1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2798856917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2798856917
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2429141944
Short name T37
Test name
Test status
Simulation time 9011433 ps
CPU time 0.39 seconds
Started Jun 10 07:30:30 PM PDT 24
Finished Jun 10 07:30:36 PM PDT 24
Peak memory 145584 kb
Host smart-1e0c6ba6-c8ce-4b54-91a7-a2e53b23d265
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2429141944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2429141944
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1484882459
Short name T38
Test name
Test status
Simulation time 10244846 ps
CPU time 0.39 seconds
Started Jun 10 07:30:30 PM PDT 24
Finished Jun 10 07:30:36 PM PDT 24
Peak memory 145572 kb
Host smart-3b858da8-b2bd-4517-9c57-b450c255545b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1484882459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1484882459
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3867745750
Short name T30
Test name
Test status
Simulation time 8551608 ps
CPU time 0.39 seconds
Started Jun 10 07:30:29 PM PDT 24
Finished Jun 10 07:30:36 PM PDT 24
Peak memory 145556 kb
Host smart-29f9a804-7667-4322-9fe5-dba21c1a2a7c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3867745750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3867745750
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2905200014
Short name T57
Test name
Test status
Simulation time 8235837 ps
CPU time 0.39 seconds
Started Jun 10 07:30:32 PM PDT 24
Finished Jun 10 07:30:37 PM PDT 24
Peak memory 145076 kb
Host smart-6867f7b6-d917-4805-a973-0caab13ddf1b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2905200014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2905200014
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.997414233
Short name T60
Test name
Test status
Simulation time 9236868 ps
CPU time 0.4 seconds
Started Jun 10 07:30:31 PM PDT 24
Finished Jun 10 07:30:37 PM PDT 24
Peak memory 145624 kb
Host smart-6450fb4b-dba0-4802-a8ca-bde39231d8ce
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=997414233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.997414233
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1693126512
Short name T67
Test name
Test status
Simulation time 27392399 ps
CPU time 0.38 seconds
Started Jun 10 04:42:24 PM PDT 24
Finished Jun 10 04:42:25 PM PDT 24
Peak memory 145408 kb
Host smart-f141ebb1-7473-4737-bd0b-91d982c09b15
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1693126512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1693126512
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2710342296
Short name T78
Test name
Test status
Simulation time 27611811 ps
CPU time 0.39 seconds
Started Jun 10 04:42:28 PM PDT 24
Finished Jun 10 04:42:29 PM PDT 24
Peak memory 145468 kb
Host smart-2892e9e3-ec93-4bbe-b0aa-9934bac280bf
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2710342296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2710342296
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3309328363
Short name T63
Test name
Test status
Simulation time 29772106 ps
CPU time 0.38 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 145216 kb
Host smart-83fc983e-9c82-41f9-9f4c-d7bd102ad3aa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3309328363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3309328363
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.581454840
Short name T74
Test name
Test status
Simulation time 27418462 ps
CPU time 0.38 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 145228 kb
Host smart-acbd6fb5-3991-4c13-9332-f8a6769238c3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=581454840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.581454840
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3118835056
Short name T69
Test name
Test status
Simulation time 27901977 ps
CPU time 0.41 seconds
Started Jun 10 04:42:14 PM PDT 24
Finished Jun 10 04:42:16 PM PDT 24
Peak memory 144284 kb
Host smart-2ebcb0ae-8a07-42e3-b4a1-60d92e88467a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3118835056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3118835056
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.478599693
Short name T72
Test name
Test status
Simulation time 30175253 ps
CPU time 0.38 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 145424 kb
Host smart-eec049ee-c511-4d01-9765-c0dfd1265c52
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=478599693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.478599693
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1979360262
Short name T34
Test name
Test status
Simulation time 28201189 ps
CPU time 0.38 seconds
Started Jun 10 04:42:15 PM PDT 24
Finished Jun 10 04:42:17 PM PDT 24
Peak memory 144984 kb
Host smart-87dfb161-e0e3-49ea-a14d-54af0174336b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1979360262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1979360262
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2970956716
Short name T68
Test name
Test status
Simulation time 29896594 ps
CPU time 0.39 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 145016 kb
Host smart-54f0d243-dd14-4995-98f7-39aa4c5fa0c1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2970956716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2970956716
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1627160279
Short name T64
Test name
Test status
Simulation time 29101038 ps
CPU time 0.4 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:20 PM PDT 24
Peak memory 145480 kb
Host smart-904861aa-adbe-41ee-927b-0c523300497c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1627160279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1627160279
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.544835723
Short name T70
Test name
Test status
Simulation time 29950578 ps
CPU time 0.38 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 145236 kb
Host smart-46ba1782-f957-4544-95fe-30a126b25a6e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=544835723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.544835723
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.617173899
Short name T65
Test name
Test status
Simulation time 27610949 ps
CPU time 0.38 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 145228 kb
Host smart-ed4bf56a-1b27-4041-a8d8-7e520459232d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=617173899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.617173899
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2276616607
Short name T71
Test name
Test status
Simulation time 29848842 ps
CPU time 0.4 seconds
Started Jun 10 04:42:18 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 145444 kb
Host smart-54eca1b8-b399-40cc-9c0b-5fcb61ceb480
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2276616607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2276616607
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.244701345
Short name T33
Test name
Test status
Simulation time 30191198 ps
CPU time 0.39 seconds
Started Jun 10 04:42:18 PM PDT 24
Finished Jun 10 04:42:21 PM PDT 24
Peak memory 145464 kb
Host smart-b0a221cf-baa5-494d-8a84-e6136f640e46
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=244701345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.244701345
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1491489903
Short name T32
Test name
Test status
Simulation time 25014762 ps
CPU time 0.39 seconds
Started Jun 10 04:42:17 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 145228 kb
Host smart-7758dc67-a696-4581-842c-153ff73f1612
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1491489903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1491489903
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4243883573
Short name T73
Test name
Test status
Simulation time 26609453 ps
CPU time 0.39 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 145064 kb
Host smart-98ce77e1-a8cb-4ea4-a909-ec12789c4660
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4243883573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.4243883573
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1399684716
Short name T77
Test name
Test status
Simulation time 28692987 ps
CPU time 0.39 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 145236 kb
Host smart-9b913014-18a0-4bbb-a28c-2872701eae82
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1399684716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1399684716
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.824077290
Short name T75
Test name
Test status
Simulation time 26090824 ps
CPU time 0.38 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:19 PM PDT 24
Peak memory 145480 kb
Host smart-fed748f0-88d7-43e7-87fa-6d4a1d0ac8b2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=824077290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.824077290
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3703820421
Short name T66
Test name
Test status
Simulation time 27263210 ps
CPU time 0.38 seconds
Started Jun 10 04:42:16 PM PDT 24
Finished Jun 10 04:42:18 PM PDT 24
Peak memory 145236 kb
Host smart-7ee1a550-9611-4fc6-aefa-b7787e6918f5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3703820421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3703820421
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3801027477
Short name T76
Test name
Test status
Simulation time 28125215 ps
CPU time 0.43 seconds
Started Jun 10 04:42:14 PM PDT 24
Finished Jun 10 04:42:16 PM PDT 24
Peak memory 144292 kb
Host smart-1e6c6067-5d0e-469e-92af-2c24072c4b49
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3801027477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3801027477
Directory /workspace/9.prim_sync_fatal_alert/latest
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